Freescale Semiconductor Technical Data Low Voltage 1:20 Differential ECL/PECL/HSTL Clock Fanout Buffer The MC100ES6221 is a bipolar monolithic differential clock fanout buffer. Designed for most demanding clock distribution systems, the MC100ES6221 supports various applications that require the distribution of precisely aligned differential clock signals. Using SiGe technology and a fully differential architecture, the device offers very low skew outputs and superior digital signal characteristics. Target applications for this clock driver is high performance clock distribution in computing, networking and telecommunication systems. MC100ES6221 Rev 5, 04/2005 MC100ES6221 LOW VOLTAGE DUAL 1:20 DIFFERENTIAL ECL/PECL/HSTL CLOCK FANOUT BUFFER Features • • • • • • • • • • • 1:20 differential clock fanout buffer 100 ps maximum device skew SiGe technology Supports DC to 2 GHz operation of clock or data signals ECL/PECL compatible differential clock outputs ECL/PECL/HSTL compatible differential clock inputs Single 3.3 V, –3.3 V, 2.5 V or –2.5 V supply Standard 52 lead LQFP package with exposed pad for enhanced thermal characteristics Supports industrial temperature range Pin and function compatible to the MC100EP221 52-lead Pb-free Package Available Functional Description TB SUFFIX 52-LEAD LQFP PACKAGE EXPOSED PAD CASE 1336A-01 AE SUFFIX 52-LEAD LQFP PACKAGE Pb-FREE PACKAGE CASE 1336A-01 The MC100ES6221 is designed for low skew clock distribution systems and supports clock frequencies up to 2 GHz. The device accepts two clock sources. The CLK0 input can be driven by ECL or PECL compatible signals, the CLK1 input accepts HSTL compatible signals. The selected input signal is distributed to 20 identical, differential ECL/PECL outputs. If VBB is connected to the CLK0 or CLK1 input and bypassed to GND by a 10 nF capacitor, the MC100ES6221 can be driven by single-ended ECL/PECL signals utilizing the VBB bias voltage output. In order to meet the tight skew specification of the device, both outputs of a differential output pair should be terminated, even if only one output is used. In the case where not all ten outputs are used, the output pairs on the same package side as the parts being used on that side should be terminated. The MC100ES6221 can be operated from a single 3.3 V or 2.5 V supply. As most other ECL compatible devices, the MC100ES6221 supports positive (PECL) and negative (ECL) supplies. The MC100ES6221 is pin and function compatible to the MC100EP221. © Freescale Semiconductor, Inc., 2005. All rights reserved. Q19 Q19 CLK_SEL VCC Q11 Q11 Q10 Q9 Q10 Q9 Q8 Q8 Q7 Q7 23 Q13 Q4 44 22 Q14 Q3 45 21 Q14 Q3 46 20 Q15 Q2 47 19 Q15 Q2 48 18 Q16 Q1 49 17 Q16 Q1 50 16 Q17 Q0 51 15 Q17 Q0 52 14 VCC VBB VEE Figure 1. MC100ES6221 Logic Diagram MC100ES6221 1 2 3 4 5 6 7 8 9 10 11 12 13 Q18 Q18 VEE 43 Q19 Q19 Q16 Q16 Q17 Q17 Q18 Q18 Q13 Q4 VEE CLK1 CLK1 • 24 CLK1 • 42 CLK1 VCC Q12 Q5 VBB • 1 Q5 CLK0 • Q12 25 CLK0 VEE • 26 41 CLK_SEL • 0 35 34 33 32 31 30 29 28 27 40 VCC CLK0 CLK0 39 38 37 36 VCC VCC Q1 Q1 Q2 Q2 Q3 Q3 VCC Q6 Q6 Q0 Q0 Figure 2. 52-Lead Package Pinout (Top View) Table 1. Pin Configuration Pin I/O Type Function CLK0, CLK0 Input ECL/PECL Differential reference clock signal input CLK1, CLK1 Input HSTL Alternative differential reference clock signal input CLK_SEL Input ECL/PECL Reference clock input select QA[0–19], QA[0–19] Output ECL/PECL Differential clock outputs VEE(1) Supply Negative power supply VCC Supply Positive power supply. All VCC pins must be connected to the positive power supply for correct DC and AC operation. VBB Output DC Reference voltage output for single ended ECL and PECL operation 1. In ECL mode (negative power supply mode), VEE is either –3.3 V or –2.5 V and VCC is connected to GND (0 V). In PECL mode (positive power supply mode), VEE is connected to GND (0 V) and VCC is either +3.3 V or +2.5 V. In both modes, the input and output levels are referenced to the most positive supply (VCC). Table 2. Function Table Pin CLK_SEL 0 CLK0, CLK0 input pair is the reference clock. CLK0 can be driven by ECL or PECL compatible signals. 1 CLK1, CLK1 input pair is the reference clock. CLK1 can be driven by HSTL compatible signals. MC100ES6221 2 Advanced Clock Drivers Devices Freescale Semiconductor Table 3. Absolute Maximum Ratings(1) Symbol Characteristics Min Max Unit VCC Supply Voltage –0.3 3.6 V VIN DC Input Voltage –0.3 VCC + 0.3 V DC Output Voltage –0.3 VCC + 0.3 V ±20 mA VOUT IIN IOUT TS TFUNC DC Input Current ±50 mA –65 125 °C TA = –40 TJ = +110 °C DC Output Current Storage Temperature Functional Temperature Range Condition 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. Table 4. General Specifications Symbol Characteristics Min Typ Max VCC – 2(1) Unit VTT Output Termination Voltage MM ESD Protection (Machine Model) 200 V HBM ESD Protection (Human Body Model) 4000 V CDM ESD Protection (Charged Device Model) 2000 V LU Latch-Up Immunity 200 mA CIN Input Capacitance θJA, θJB, θJC TJ Thermal Resistance (junction-to-ambient, junction-to-board, junction-to-case) Operating Junction Temperature(2) (continuous operation) 4.0 pF See Table 9. Thermal Resistance °C/W 0 Condition V 110 Inputs °C MTBF = 9.1 years 1. Output termination voltage VTT = 0 V for VCC = 2.5 V operation is supported but the power consumption of the device will increase. 2. Operating junction temperature impacts device life time. Maximum continuous operating junction temperature should be selected according to the application life time requirements (See application note AN1545 for more information). The device AC and DC parameters are specified up to 110°C junction temperature allowing the MC100ES6221 to be used in applications requiring industrial temperature range. It is recommended that users of the MC100ES6221 employ thermal modeling analysis to assist in applying the junction temperature specifications to their particular application. MC100ES6221 Advanced Clock Drivers Devices Freescale Semiconductor 3 Table 5. PECL DC Characteristics (VCC = 2.5 V ± 5% or VCC = 3.3 V ± 5%, VEE = GND, TJ = 0°C to + 110°C) Symbol Characteristics Clock Input Pair CLK0, VPP VCMR IIN Differential Cross Point Input Min Typ Max Unit Condition 0.1 1.3 V Differential operation 1.0 VCC – 0.3 V Differential operation ±100 µA VIN = VIL or VIN = VIH 1.4 V VCC – 0.7 V V (PECL differential signals) Differential Input Voltage(2) Voltage(3) Current(1) Clock Input Pair CLK1, VDIF CLK0(1) CLK1(4) (HSTL differential signals) Differential Input Voltage(5) Voltage(6) 0.2 VX Differential Cross Point VIH Input High Voltage VX + 0.1 VX + 0.7 VIL Input Low Voltage VX – 0.7 VX – 0.1 V IIN Input Current ±100 µA V 0 0.68 - 0.9 VIN = VX ± 0.2 V Clock Inputs (PECL single ended signals) VIH Input Voltage High VCC – 1.165 VCC – 0.880 VIL Input Voltage Low VCC – 1.810 VCC – 1.475 V IIN Input Current(7) ±100 µA VIN = VIL or VIN = VIH PECL Clock Outputs (Q0–19, Q0–19) VOH Output High Voltage VCC – 1.1 VCC – 1.005 VCC – 0.7 V IOH = –30 mA(8) VOL Output Low Voltage VCC – 1.9 VCC – 1.705 VCC – 1.4 V IOL = –5 mA(8) 84 160 mA VCC – 1.20 V Supply current and VBB IEE(9) Maximum Quiescent Supply Current without Output Termination Current VBB Output Reference Voltage (fref < 1.0 GHz)(10) VCC – 1.42 VEE pins IBB = 0.4 mA 1. The input pairs CLK0, CLK1 are compatible to differential signaling standards. CLK0 is compatible to LVPECL signals and CLK1 meets both HSTL differential signal specifications. The difference between CLK0 and CLK1 is the differential input threshold voltage (VCMR). 2. VPP (DC) is the minimum differential input voltage swing required to maintain device functionality. 3. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC) range and the input swing lies within the VPP (DC) specification. 4. Clock inputs driven by differential HSTL compatible signals. Only applicable to CLK1, CLK1. 5. VDIF (DC) is the minimum differential HSTL input voltage swing required for device functionality. 6. VX (DC) is the crosspoint of the differential HSTL input signal. Functional operation is obtained when the crosspoint is within the VX (DC) range and the input swing lies within the VPP (DC) specification. 7. Inputs have internal pullup/pulldown resistors which affect the input current. 8. Equivalent to a termination of 50 Ω to VTT. 9. ICC calculation: ICC = (number of differential output used) x (IOH + IOL) + IEE ICC = (number of differential output used) x (VOH – VTT) ÷ Rload + (VOL – V TT) ÷ Rload + IEE. 10. Using VBB to bias unused single-ended inputs is recommended only up to a clock reference frequency of 1 GHz. Above 1 GHz, only differential input signals should be used with the MC100ES6221. MC100ES6221 4 Advanced Clock Drivers Devices Freescale Semiconductor Table 6. ECL DC Characteristics (VEE = –2.5 V ± 5% or VEE = –3.3 V ± 5%, VCC = GND, TJ = 0°C to + 110°C) Symbol Characteristics Min Typ Max Unit Condition 0.1 1.3 V Differential operation VEE + 1.0 –0.3 V Differential operation ±100 µA VIN = VIL or VIN = VIH V Clock Input Pair CLK0, CLK0 (ECL differential signals) VPP VCMR IIN Differential Input Voltage(1) Differential Cross Point Junction to top of Package Voltage(2) Input Current(1) Clock Inputs (ECL single ended signals) VIH Input Voltage High –1.165 –0.880 VIL Input Voltage Low –1.810 –1.475 V IIN Input Current(3) ±100 µA VIN = VIL or VIN = VIH ECL Clock Outputs (Q0–A19, Q0–Q19) VOH Output High Voltage –1.1 –1.005 –0.7 V IOH = –30 mA(4) VOL Output Low Voltage –1.9 –1.705 –1.4 V IOL = –5 mA(4) 84 160 mA –1.20 V Supply Current and VBB IEE(5) Maximum Quiescent Supply Current without Output Termination Current VBB Output Reference Voltage (fref < 1.0 GHz)(6) –1.42 VEE pins IBB = 0.4 mA 1. VPP (DC) is the minimum differential input voltage swing required to maintain device functionality. 2. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC) range and the input swing lies within the VPP (DC) specification. 3. Inputs have internal pullup/pulldown resistors which affect the input current. 4. Equivalent to a termination of 50 Ω to VTT. 5. ICC calculation: ICC = (number of differential output used) x (IOH + IOL) + IEE ICC = (number of differential output used) x (VOH – VTT) ÷ Rload + (VOL – V TT) ÷ Rload + IEE. 6. VBB can be used to bias unused single-ended inputs up to a clock reference frequency of 1 GHz. Above 1 GHz, only differential signals should be used with the MC100ES6221. MC100ES6221 Advanced Clock Drivers Devices Freescale Semiconductor 5 Table 7. AC Characteristics (ECL: VEE = –3.3 V ± 5% or VEE = –2.5 V ± 5%, VCC = GND) or (PECL: VCC = 3.3 V ± 5% or VCC = 2.5 V ± 5%, VEE = GND, TJ = 0°C to + 110°C)(1) Symbol Characteristics Min Typ Max Unit Condition 0.2 1.3 V 1.0 VEE + 1.0 VCC – 0.3 –0.3 V V V 0 2000 MHz Differential 670 ps Differential 1.3 V VCC – 1.0 V 1000 MHz Differential 950 ps Differential Clock Input Pair CLK0, CLK0 (PECL or ECL differential signals) VPP VCMR Differential Input Voltage(2) (peak-to-peak) Differential Input Crosspoint Voltage fCLK Input Frequency tPD Propagation Delay CLK0 to Q0-19 (3) PECL ECL 400 540 Clock Input Pair CLK1, CLK1 (HSTL differential signals) VDIF VX Differential Input Voltage(4) (peak-to-peak) Differential Input Crosspoint 0.2 Voltage(5) fCLK Input Frequency tPD Propagation Delay CLK1 to Q0–19 0.1 0.68–0.9 0 650 780 0.375 TDB 0.630 0.250 PECL/ECL Clock Outputs (Q0–19, Q0–19) VO(P-P) Differential Output Voltage (peak-to-peak) fO < 1.0 GHz fO < 2.0 GHz tsk(O) Output-to-Output Skew tsk(PP) Output-to-Output Skew (part-to-part) tJIT(CC) Output Cycle-to-Cycle Jitter tSK(P) Output Pulse Skew(6) DCQ Output Duty Cycle tr, tf Output Rise/Fall Time 50 V V 100 ps Differential using CLK0 using CLK1 270 300 ps ps parts at one given TJ, VCC, fref 250 ps 1 ps 30 50 ps 50 50 50.5 55.0 % % DCREF = 50% DCREF = 50% 350 ps 20% to 80% Differential RMS (1σ) fREF < 0.1 GHz fREF < 1.0 GHz 49.5 45.0 50 1. AC characteristics apply for parallel output termination of 50 Ω to VTT. 2. VPP (AC) is the minimum differential ECL/PECL input voltage swing required to maintain AC characteristics including tPD and device-to-device skew. 3. VCMR (AC) is the crosspoint of the differential ECL/PECL input signal. Normal AC operation is obtained when the crosspoint is within the VCMR (AC) range and the input swing lies within the VPP (AC) specification. Violation of VCMR (AC) or VPP (AC) impacts the device propagation delay, device and part-to-part skew. 4. VDIF (AC) is the minimum differential HSTL input voltage swing required to maintain AC characteristics including tPD and device-to-device skew. Only applicable to CLKB. 5. VX (AC) is the crosspoint of the differential HSTL input signal. Normal AC operation is obtained when the crosspoint is within the VX (AC) range and the input swing lies within the VDIF (AC) specification. Violation of VX (AC) or VDIF (AC) impacts the device propagation delay, device and part-to-part skew. 6. Output pulse skew is the absolute difference of the propagation delay times: | tpLH – tpHL |. MC100ES6221 6 Advanced Clock Drivers Devices Freescale Semiconductor Z0 = 50 Ω Differential Pulse Generator Z = 50 Ω RT = 50 Ω Z0 = 50 Ω DUT MC100ES6221 RT = 50 Ω VTT VTT Figure 3. MC100ES6221 Test Reference CLKN VPP = 0.8 V VCMR = VCC – 1.3 V CLKN QX QX tPD (CLKN to QX) Figure 4. MC100ES6221 AC Test Reference Measurement Waveform MC100ES6221 Advanced Clock Drivers Devices Freescale Semiconductor 7 APPLICATIONS INFORMATION Understanding the Junction Temperature Range of the MC100ES6221 To make the optimum use of high clock frequency and low skew capabilities of the MC100ES6221, the MC100ES6221 is specified, characterized and tested for the junction temperature range of TJ = 0°C to +110°C. Because the exact thermal performance depends on the PCB type, design, thermal management and natural or forced air convection, the junction temperature provides an exact way to correlate the application specific conditions to the published performance data of this data sheet. The correlation of the junction temperature range to the application ambient temperature range and vice versa can be done by calculation: TJ = TA + Rthja ⋅ Ptot Assuming a thermal resistance (junction to ambient) of 17°C/W (2s2p board, 200 ft/min airflow, see Table 8) and a typical power consumption of 1148 mW (all outputs terminated 50 ohms to VTT, VCC = 3.3 V, frequency independent), the junction temperature of the MC100ES6221 is approximately TA + 21°C, and the minimum ambient temperature in this example case calculates to –21°C (the maximum ambient temperature is 89°C. See Table 8). Exceeding the minimum junction temperature specification of the MC100ES6221 does not have a significant impact on the device functionality. However, the continuous use the MC100ES6221 at high ambient temperatures requires thermal management to not exceed the specified maximum junction temperature. Please see the application note AN1545 for a power consumption calculation guideline. Maintaining Lowest Device Skew The MC100ES6221 guarantees low output-to-output bank skew of 50 ps and a part-to-part skew of max. 270 ps. To ensure low skew clock signals in the application, both outputs of any differential output pair need to be terminated identically, even if only one output is used. When fewer than all nine output pairs are used, identical termination of all output pairs within the output bank is recommended. This will reduce the device power consumption while maintaining minimum output skew. Power Supply Bypassing The MC100ES6221 is a mixed analog/digital product. The differential architecture of the MC100ES6221 supports low noise signal operation at high frequencies. In order to maintain its superior signal quality, all VCC pins should be bypassed by high-frequency ceramic capacitors connected to GND. If the spectral frequencies of the internally generated switching noise on the supply pins cross the series resonant point of an individual bypass capacitor, its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the noise bandwidth. VCC VCC 33...100 nF 0.1 nF MC100ES6221 Figure 5. VCC Power Supply Bypass Table 8. Ambient Temperature Ranges (Ptot = 1148 mW) Rthja (2s2p board) TA, min(1) TA, max Natural convection 20°C/W –23 °C 87°C 100 ft/min 18°C/W –21 °C 89°C 200 ft/min 17°C/W –20 °C 90°C 400 ft/min 16°C/W –18 °C 92°C 800 ft/min 15°C/W –17 °C 93°C 1. The MC100ES6221 device function is guaranteed from TA = –40°C to TJ = 110°C MC100ES6221 8 Advanced Clock Drivers Devices Freescale Semiconductor APPLICATIONS INFORMATION 4.8 all units mm 4.8 Thermal via array (3x3), 1.2 mm pitch, 0.3 mm diameter Exposed pad land pattern Figure 6. Recommended Thermal Land Pattern The via diameter is should be approx. 0.3 mm with 1 oz. copper via barrel plating. Solder wicking inside the via resulting in voids during the solder process must be avoided. If the copper plating does not plug the vias, stencil print solder paste onto the printed circuit pad. This will supply enough solder paste to fill those vias and not starve the solder joints. The attachment process for exposed pad package is equivalent to standard surface mount packages. Figure 7 shows a recommend solder mask opening with respect to the recommended 3 x 3 thermal via array. Because a large solder mask opening may result in a poor release, the opening should be subdivided as shown in Figure 7. For the nominal package standoff 0.1 mm, a stencil thickness of 5 to 8 mils should be considered. all units mm 0.2 1.0 1.0 0.2 4.8 Using the Thermally Enhanced Package of the MC100ES6221 The MC100ES6221 uses a thermally enhanced exposed pad (EP) 52 lead LQFP package. The package is molded so that the lead frame is exposed at the surface of the package bottom side. The exposed metal pad will provide the low thermal impedance that supports the power consumption of the MC100ES6221 high-speed bipolar integrated circuit and eases the power management task for the system design. A thermal land pattern on the printed circuit board and thermal vias are recommended in order to take advantage of the enhanced thermal capabilities of the MC100ES6221. Direct soldering of the exposed pad to the thermal land will provide an efficient thermal path. In multilayer board designs, thermal vias thermally connect the exposed pad to internal copper planes. Number of vias, spacing, via diameters and land pattern design depend on the application and the amount of heat to be removed from the package. A nine thermal via array, arranged in a 3 x 3 array and using a 1.2 mm pitch in the center of the thermal land is a requirement for MC100ES6221 applications on multi-layer boards. The recommended thermal land design comprises a 3 x 3 thermal via array as shown in Figure 6, providing an efficient heat removal path. 4.8 Thermal via array (3x3), 1.2 mm pitch, 0.3 mm diameter Exposed pad land pattern Figure 7. Recommended Solder Mask Openings For thermal system analysis and junction temperature calculation the thermal resistance parameters of the package is provided: Table 9. Thermal Resistance(1) ConvectionL FPM RTHJA(2) °C/W RTHJA(3) °C/W Natural 20 48 100 18 47 200 17 46 400 16 43 800 15 41 RTHJC °C/W RTHJB(4) °C/W 4(5) 29(6) 16 1. Applicable for a 3 x 3 thermal via array. 2. Junction to ambient, four conductor layer test board (2S2P), per JES51–7 and JESD 51–5. 3. Junction to ambient, single layer test board, per JESD51–3. 4. Junction to board, four conductor layer test board (2S2P) per JESD 51–8. 5. Junction to exposed pad. 6. Junction to top of package. It is recommended that users employ thermal modeling analysis to assist in applying the general recommendations to their particular application. The exposed pad of the MC100ES6221 package does not have an electrical low impedance path to the substrate of the integrated circuit and its terminals. The thermal land should be connected to GND through connection of internal board layers. MC100ES6221 Advanced Clock Drivers Devices Freescale Semiconductor 9 PACKAGE DIMENSIONS 4X 4X 13 TIPS 0.2 H A-B D 0.2 C A-B D D PIN 1 INDEX 52 (0.2) 7 40 1 39 A 10 6 B 0.20 R 0.08 0.75 0.45 (1) 7˚ 0˚ 4 5 6 0.25 GAUGE PLANE 0.20 0.05 12 13 0˚ MIN 0.20 R 0.08 1.5 1.3 0.05 VIEW AA 6 4 27 X 14 26 5 X=A, B OR D CL 6 B 6 4 10 6 48X B 12 4 0.65 VIEW Y H 4X 1.7 MAX (12˚) VIEW AA 8 BASE METAL (0.3) 52X 0.1 C 8 J 52X C SEATING PLANE 0.08 M 0.40 0.22 5 C A-B D 4X (12˚) J PLATING 0.20 0.09 0.16 0.07 0.35 0.20 8 8 SECTION B-B NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DATUMS A, B AND D TO BE DETERMINED AT DATUM PLANE H. 4. DIMENSION TO BE DETERMINED AT SEATING PLANE C. 5. THIS DIMENSION DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.46 mm. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD SHALL NOT BE LESS THAN 0.07 mm. 6. THIS DIMENSION DOES NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25mm PER SIDE. THIS DIMENSION IS MAXIMUM PLSTIC BODY SIZE DIMENSION INCLUDING MOLD MISMATCH. 7. EXACT SHAPE OF EACH CORNER IS OPTIONAL. 8. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10mm AND 0.25mm FROM THE LEAD TIP. 4.78 4.58 4.78 4.58 EXPOSED PAD VIEW Y VIEW J-J CASE 1336A-01 ISSUE O 52-LEAD LQFP PACKAGE MC100ES6221 10 Advanced Clock Drivers Devices Freescale Semiconductor NOTES MC100ES6221 Advanced Clock Drivers Devices Freescale Semiconductor 11 How to Reach Us: Home Page: www.freescale.com E-mail: [email protected] USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 +1-800-521-6274 or +1-480-768-2130 [email protected] Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) [email protected] Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064 Japan 0120 191014 or +81 3 5437 9125 [email protected] Asia/Pacific: Freescale Semiconductor Hong Kong Ltd. Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po, N.T., Hong Kong +800 2666 8080 [email protected] For Literature Requests Only: Freescale Semiconductor Literature Distribution Center P.O. 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