IRF IRAUDAMP4 120 w x 2 channel class d audio power amplifier Datasheet

IRAUDAMP4
120 W x 2 Channel Class D Audio Power Amplifier
Using IRS20955 and IRF6645
By
Johan Strydom, Jun Honda, and Jorge Cerezo
Table of Contents
Page
Introduction .......................................................................................... 1
Specifications ....................................................................................... 2
Functional Description.......................................................................... 4
Startup and Shutdown..........................................................................12
Protection .............................................................................................16
Typical Performance ............................................................................21
Design Documents ..............................................................................27
CAUTION: International Rectifier suggests the following guidelines for
safe operation and handling of IRAUDAMP4 Demo Board;
• Always wear safety glasses whenever operating Demo Board
• Avoid personal contact with exposed metal surfaces when operating
Demo Board
• Turn off Demo Board when placing or removing measurement probes
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Introduction
The IRAUDAMP4 reference design is an example of a two-channel 120 W half-bridge
Class D audio power amplifier. The reference design will demonstrate how to use the
IRS20955, implement protection circuits, and design an optimum PCB layout using the
IRF6645 DirectFET MOSFETs. The resulting design requires no heatsink for normal
operation (one-eighth of continuous rated power). The reference design contains all the
required housekeeping power supplies for ease of use. The two-channel design is
scalable, for power and the number of channels.
Applications
AV receivers
Home theater systems
Mini component stereos
Sub-woofers
Features
Output Power:
120 W x two channels,
Total Harmonic Distortion (THD) = 1%, 1 kHz
Residual Noise:
52 µV, IHF-A weighted, AES-17 filter
Distortion:
0.004% THD+N @ 60 W, 4 Ω
Efficiency:
96% @ 120 W, 4 Ω, single-channel driven, Class D stage
Multiple Protection Features: Over-current protection (OCP),
Over-voltage protection (OVP),
Under-voltage protection (UVP),
DC-protection (DCP),
Over-temperature protection (OTP)
PWM Modulator:
Self-oscillating half-bridge topology with optional clock
synchronization
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Specifications
General Test Conditions (unless otherwise noted)
Supply Voltage
±35 V
Load Impedance
4Ω
Self-Oscillating Frequency
400 kHz
Gain Setting
26.8 dB
Notes / Conditions
No input signal
1 Vrms input yields rated power
Electrical Data
IR Devices Used
Typical
Notes / Conditions
IRS20955 gate driver,
IRF6645 DirectFET MOSFET
Modulator
Self-oscillating, second order sigma-delta modulation, analog input
Power Supply Range
± 25 - 35 V
Output Power CH1-2: (1% THD+N)
120 W
1 kHz
Output Power CH1-2: (10% THD+N)
170 W
1 kHz
Rated Load Impedance
4Ω
Supply Current
100 mA
No input signal
Total Idle Power Consumption
7W
No input signal
Single-channel driven,
Channel Efficiency
96%
120 W, Class D stage
Audio Performance
THD+N, 1 W
THD+N, 10 W
THD+N, 60 W
Typical / Class D*
0.005%
0.002%
0.002%
0.001%
0.004%
0.003%
Dynamic Range
113 dB
120 dB
70 µV
50 µV
170
95 dB
80 dB
±1 dB
±3 dB
40 µV
20 µV
2000
100 dB
85 dB
Residual Noise, 20Hz - 20 kHz BW,
A-Weighted
Damping Factor
Channel Separation
Frequency Response : 20Hz-20 kHz
: 20Hz-40 kHz
Thermal Performance
Idling
2ch x 15 W (1/8 rated power)
2ch x 120 W (rated power)
Physical Specifications
Dimensions
Typical
TC =30 °C
TPCB=37 °C
TC =54 °C
TPCB=67 °C
TC =80 °C
TPCB=106 °C
Notes / Conditions
1 kHz, Single-channel driven
A-weighted, AES-17 filter,
Single-channel operation
Self-oscillating – 400 kHz
Internal clock – 300 kHz
1 kHz, relative to 4 Ω load
100 Hz
10 kHz
1W, 4 Ω - 8 Ω Load
Notes / Conditions
No signal input, TA=25 °C
Continuous, TA=25 °C
At OTP shutdown @ 150 s,
TA=25 °C
5.8 in (L) x 5.2 in (W)
Note: Specifications are typical and not guaranteed
*Class D refers to audio performance measurements of the Class D output power stage
only, with preamp and output filter bypassed.
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Connection Diagram
35 V, 5 A DC supply
35 V, 5 A DC supply
250 W, Non-inductive Resistors
4Ω
4Ω
G
J3
CH1
Output
LED
J4
TP1
S1
CH2
Output
J7
J9
TP2
Protection
CH1
Input
J8
J5
J6
CH2
Input
Normal
S2
S3
Volume
R113
Audio Signal Generator
Figure 1. Typical Test Setup
Pin Description
CH1 IN
CH2 IN
POWER
CH1 OUT
CH2 OUT
EXT CLK
DCP OUT
J6
J5
J7
J3
J4
J8
J9
Analog input for CH1
Analog input for CH2
Positive and negative supply (+B / -B)
Output for CH1
Output for CH2
External clock sync
DC protection relay output
Power-on and Power-off Procedure
Always apply or remove ±35 V bus supplies at the same time.
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Functional Description
Class D Operation
Referring to CH1 as an example, the op-amp U1 forms a front-end second-order
integrator with C11, C13 & R25 + R29P. This integrator receives a rectangular feedback
waveform from the Class D switching stage and outputs a quadratic oscillatory waveform
as a carrier signal. To create the modulated PWM signal, the input signal shifts the
average value of this quadratic waveform (through gain relationship between R13 and
R31 + R33) so that the duty varies according to the instantaneous value of the analog
input signal. The IRS20955 input comparator processes the signal to create the required
PWM signal. This PWM signal is internally level-shifted down to the negative supply rail
where this signal is split into two signals, with opposite polarity and added deadtime, for
high-side and low-side MOSFET gate signals, respectively. The IRS20955 drives two
IRF6645 DirectFET MOSFETs in the power stage to provide the amplified PWM
waveform. The amplified analog output is re-created by demodulating the amplified
PWM. This is done by means of the LC low-pass filter (LPF) formed by L1 and C23,
which filters out the Class D switching carrier signal.
Feedback
Daughter-board
U1
Σ
+B
U1
Integrator
GND
PWM
Modulator
and Level
Shifter
LPF
IRS20955S
Gate Driver
IRF6645
Direct-FET
-B
Figure 2. Simplified Block Diagram of Class D Amplifier
Power Supplies
The IRAUDAMP4 has all the necessary housekeeping power supplies onboard and only
requires a pair of symmetric power supplies ranging from ±25 V to ±35 V (+B, GND, -B)
for operation. The internally-generated housekeeping power supplies include a ±5 V
supply for analog signal processing (preamp, etc.), while a +12 V supply (VCC),
referenced to –B, is included to supply the Class D gate-driver stage.
For the externally-applied power, a regulated power supply is preferable for performance
measurements, but not always necessary. The bus capacitors, C31 and C32 on the
motherboard, along with high-frequency bypass-caps C15-C18 on daughter board,
address the high-frequency ripple current that result from switching action. In designs
involving unregulated power supplies, the designer should place a set of bus capacitors,
having enough capacitance to handle the audio-ripple current, externally. Overall
regulation and output voltage ripple for the power supply design are not critical when
using the IRAUDAMP4 Class D amplifier as the power supply rejection ratio (PSRR) of
the IRAUDAMP4 is excellent (Figure 3).
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+0
-10
-20
-30
-40
d
B
-B
-50
+B
-60
-70
-80
-90
20
50
100
200
500
1k
2k
5k
10k
20k
40k
Hz
Figure 3. Power Supply Rejection Ratio (PSRR) for Negative (-B) and Positive (+B) Supplies
Bus Pumping
Since the IRAUDAMP4 is a half-bridge configuration, bus pumping does occur. Under
normal operation during the first half of the cycle, energy flows from one supply through
the load and into the other supply, thus causing a voltage imbalance by pumping up the
bus voltage of the receiving power supply. In the second half of the cycle, this condition
is reversed, resulting in bus pumping of the other supply.
These conditions worsen bus pumping:
–
Lower frequencies (bus-pumping duration is longer per half cycle)
–
Higher power output voltage and/or lower load impedance (more energy
transfers between supplies)
–
Smaller bus capacitors (the same energy will cause a larger voltage increase)
The IRAUDAMP4 has protection features that will shutdown the switching operation if
the bus voltage becomes too high (>40 V) or too low (<20 V). One of the easiest
countermeasures is to drive both of the channels out of phase so that one channel
consumes the energy flow from the other and does not return it to the power supply. Bus
voltage detection is only done on the –B supply as the effect of the bus pumping on the
supplies is assumed to be symmetrical in amplitude (although opposite in phase).
Input
A proper input signal is an analog signal below 20 kHz, up to ±3.5 V peak, having a
source impedance of less than 600 Ω. A 30 kHz to 60 kHz input signal can cause LC
resonance in the output LPF, resulting in an abnormally large amount of reactive current
flowing through the switching stage (especially at 8 Ω or higher impedance towards open
load), causing OCP activation. The IRAUDAMP4 has an RC network, or Zobel network,
to damp the resonance and protect the board in such event, but is not thermally rated to
handle continuous supersonic frequencies. These supersonic input frequencies
therefore should be avoided. Separate mono RCA connectors provide input to each of
the two channels. Although both channels share a common ground, it is necessary to
connect each channel separately to limit noise and crosstalk between channels.
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Output
Both outputs for the IRAUDAMP4 are single-ended and therefore have terminals labeled
(+) and (-) with the (-) terminal connected to power ground. Each channel is optimized
for a 4 Ω speaker load for a maximum output power of 120 W, but is capable of
operating with higher load impedances (at reduced power), at which point the frequency
response will have a small peak at the corner frequency of the output LC low pass filter.
The IRAUDAMP4 is stable with capacitive-loading; however, it should be realized that
the frequency response degrades with heavy capacitive loading of more than 0.1 μF.
Gain Setting / Volume Control
The IRAUDAMP4 has an internal volume control (potentiometer R108 labeled,
“VOLUME”) for gain adjustment. Gain settings for both channels are tracked and
controlled by the volume control IC (U_2) setting the gain from the microcontroller IC
(U_1). The maximum volume setting (clockwise rotation) corresponds to a total gain of
+37.9 dB (78.8 V/V). The total gain is a product of the power-stage gain, which is
constant (+23.2 dB), and the input-stage gain that is directly-controlled by the volume
adjustment. The volume range is about 100 dB with minimum volume setting to mute the
system with an overall gain of less than -60 dB. For best performance in testing, the
internal volume control should be set to a gain of 21.9 V/V, or 1 Vrms input will result in
rated output power (120 W into 4 Ω), allowing for a >11 dB overdrive.
Output Filter Design, Preamplifier and Performance
The audio performance of the IRAUDAMP4 depends on a number of different factors.
The section entitled, “Typical Performance” presents performance measurements based
on the overall system, including the preamp and output filter. While the preamp and
output filter are not part of the Class D power stage, they have a significant effect on the
overall performance.
Output filter
Since the output filter is not included in the control loop of the IRAUDAMP4, the
reference design cannot compensate for performance deterioration due to the output
filter. Therefore, it is there important to understand what characteristics are preferable
when designing the output filter:
1) The DC resistance of the inductor should me minimized to 20 mΩ or less.
2) The linearity of the output inductor and capacitor should be high with respect to
load current and voltage.
Preamplifier
The preamp allows partial gain of the input signal, and in the IRAUDAMP4, controls the
volume. The preamp itself will add distortion and noise to the input signal, resulting in a
gain through the Class D output stage and appearing at the output. Even a few microvolts of noise can add significantly to the output noise of the overall amplifier. In fact, the
output noise from the preamp contributes more than half of the overall noise to the
system.
It is possible to evaluate the performance without the preamp and volume control, by
moving resistors R13 and R14 to R71 and R72, respectively. This effectively bypasses
the preamp and connects the RCA inputs directly to the Class D power stage input.
Improving the selection of preamp and/or output filter, will improve the overall system
performance to approach that of the stand-alone Class D power stage. In the “Typical
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Performance” section, only limited data for the stand-alone Class D power stage is
given. For example, results for THD+N vs. Output Power are provided, utilizing a range
of different inductors. By changing the inductor and repeating this test, a designer can
quickly evaluate a particular inductor.
100
TTTTTTT
10
1
%
0.1
0.01
0.001
0.0001
100m
200m
500m
1
2
5
10
20
50
100
200
W
Figure 4. Results of THD+N vs. Output Power with Different Output Inductors
Self-Oscillating PWM Modulator
The IRAUDAMP4 Class D audio power amplifier features a self-oscillating type PWM
modulator for the lowest component count and robust design. This topology represents
an analog version of a second-order sigma-delta modulation having a Class D switching
stage inside the loop. The benefit of the sigma-delta modulation, in comparison to the
carrier-signal based modulation, is that all the error in the audible frequency range is
shifted to the inaudible upper-frequency range by nature of its operation. Also, sigmadelta modulation allows a designer to apply a sufficient amount of correction.
The self-oscillating frequency is determined by the total delay time inside the control loop
of the system. The delay of the logic circuits, the IRS20955 gate-driver propagation
delay, the IRF6645 switching speed, the time-constant of front-end integrator (e.g. R25 +
R29P, C11 and C13 for CH1) and variations in the supply voltages are critical factors of
the self-oscillating frequency. Under nominal conditions, the switching-frequency is
around 400 kHz with no audio input signal and a +/-35 V supply.
Adjustments of Self-Oscillating Frequency
The PWM switching frequency in this type of self-oscillating switching scheme greatly
impacts the audio performance, both in absolute frequency and frequency relative to the
other channels. In absolute terms, at higher frequencies, distortion due to switching-time
becomes significant, while at lower frequencies, the bandwidth of the amplifier suffers. In
relative terms, interference between channels is most significant if the relative frequency
difference is within the audible range. Normally when adjusting the self-oscillating
frequency of the different channels, it is best to either match the frequencies accurately,
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or have them separated by at least 25 kHz. With the installed components, it is possible
to change the self-oscillating frequency from about 160 kHz up to 600 kHz.
Potentiometers for adjusting self-oscillating frequency
R29P
Switching frequency for CH1*
R30P
Switching frequency for CH2*
*Adjustments have to be done at an idling condition with no signal input.
Switches and Indicators
There are three different indicators on the reference design:
– An orange LED, signifying a fault / shutdown condition when lit.
– A green LED on the motherboard, signifying conditions are normal and no fault
condition is present.
– A green LED on the daughter board, signifying there is power.
There are three switches on the reference design:
– Switch S1 is a trip and reset push-button. Pushing this button has the same effect of
a fault condition. The circuit will restart about three seconds after the shutdown
button is released.
– Switch S2 is an internal clock-sync frequency selector. This feature allows the
designer to modify the switching frequency in order to avoid AM radio interference.
With S3 is set to INT, the two settings “H” and “L” will modify the internal clock
frequency by about 20 kHz to 40 kHz, either higher “H” or lower “L.” The actual
internal frequency is set by potentiometer R113 - “INT FREQ.”
– Switch S3 is an oscillator selector. This three-position switch is selectable for
internal self-oscillator (middle position – “SELF”), or either internal (“INT”) or
external (“EXT”) clock synchronization.
Switching Frequency Lock / Synchronization Feature
For single-channel operation, the use of the self-oscillating switching scheme will yield
the best audio performance. The self-oscillating frequency, however, does change with
the duty ratio. This varying frequency can interfere with AM radio broadcasts, where a
constant-switching frequency with its harmonics shifted away from the AM carrier
frequency, is preferred. In addition to AM broadcasts, multiple channels can also reduce
audio performance at low power, and can lead to increased residual noise. Clock
frequency locking/synchronization can address these unwanted characteristics.
Please note that the switching frequency lock / synchronization feature is not possible for
all frequencies and duty ratios, and operates within a limited frequency and duty-ratio
range around the self-oscillating frequency (Figure 5).
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600
Suggested clock frequency
for maximum locking range
Locking range
Operating Frequency (kHz)
500
400
300
200
Self-oscillating frequency
100
0
10%
20%
30%
40%
50%
60%
70%
80%
90%
Duty Cycle
Figure 5. Typical Lock Frequency Range vs. PWM Duty Ratio
(Self-oscillating frequency set to 400 kHz with no input)
As illustrated by the THD+N Ratio vs. Output Power results (Figure 6) , the noise levels
increase slightly when all channels are driven (ACD) with the self oscillator, especially
below the 5 W range. Residual noise typically increases by a third or more (see
“Specifications – Audio Performance”) compared to a single-channel driven (SCD)
configuration. Locking the oscillator frequency results in lowering the residual noise to
that of a single-channel-driven system. The output power range, for which the frequencylocking is successful, depends on what the locking frequency is with respect to the selfoscillating frequency. As illustrated in Figure 6, the locking frequency is lowered (from
450 kHz to 400 kHz to 350 kHz and then 300 kHz) as the output power range (where
locking is achieved) is extended. Once locking is lost, however, the audio performance
degrades, but the increase in THD seems independent from the clock frequency.
Therefore, a 300 kHz clock frequency is recommended.
It is possible to improve the THD performance by increasing the corner frequency of the
high pass filter (HPF) (R17 and C15 for Ch1) that is used to inject the clock signal. This
drop in THD, however, comes at the cost of reducing the locking range. Resistor values
of up to 100 kΩ and capacitor values down to 10 pF can be used.
In the IRAUDAMP4, this switching frequency lock/synchronization feature is achieved
with either an internal or external clock input (selectable through S3). If an internal (INT)
clock is selected, an internally-generated clock signal will be used, adjusted by setting
potentiometer R113 “INT FREQ.” If external (EXT) clock signal is selected, a 0 V to 5 V
square-wave (~50% duty ratio) logic signal must be applied to BNC connector J17.
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100
10
1
%
0.1 Self
Osc. (ACD)
Int. Clock @ 300 kHz
Int. Clock @ 450 kHz
0.01
Self Osc. (Single Channel Driven)
0.001
100m
200m
500m
1
2
5
10
20
50
100
200
Power (W)
Figure 6. THD+N Ratio vs. Output Power for Different Switching Frequency Lock/Synchronization
Conditions
IRS20955 Gate Driver IC
The IRAUDAMP4 uses the IRS20955, which is a high-voltage (up to 200 V), high-speed
power MOSFET gate driver with internal deadtime and protection functions specifically
designed for Class D audio amplifier applications. These functions include OCP and
UVP. A bi-directional current protection feature that protects both the high-side and lowside MOSFETs are internal to the IRS20955, and the trip levels for both MOSFETs can
be set independently. In this design, the deadtime can be selected for optimized
performance, by minimizing deadtime while limiting shoot-through. As a result, there is
no gate-timing adjustment on the board. Selectable deadtime through the DT pin voltage
is an easy and reliable function which requires only two external resistors, R11 and R9.
R11
R9
Figure 7. System-level View of Gate Driver IRS20955
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Selectable Deadtime
The IRS20955 determines its deadtime based on the voltage applied to the DT pin. An
internal comparator translates which pre-determined deadtime is being used by
comparing the DT voltage with internal reference voltages. A resistive voltage divider
from VCC sets threshold voltages for each setting, negating the need for a precise
absolute voltage to set the mode. The threshold voltages between deadtime settings are
set internally, based on different ratios of VCC as indicated in the diagram below. In order
to avoid drift from the input bias current of the DT pin, a bias current of greater than
0.5 mA is suggested for the external resistor divider circuit. Suggested values of
resistance that are used to set a deadtime are given below. Resistors with up to 5%
tolerance can be used.
Deadtime mode
DT1
DT2
DT3
DT4
Deadtime
~15 ns
~25 ns
~35 ns
~45 ns
R11
<10kΩ
5.6kΩ
8.2kΩ
Open
R9
Open
4.7kΩ
3.3kΩ
<10kΩ
DT Voltage
VCC
0.46(VCC)
0.29(VCC)
COM
Default
Figure 8. Deadtime Settings vs. VDT Voltage
Over-Current Protection (OCP)
In the IRAUDAMP4, the IRS20955 gate driver accomplishes OCP internally, a feature
discussed in greater detail in the “Protection” section.
Offset Null (DC Offset)
The IRAUDAMP4 is designed such that no output-offset nullification is required. DC
offsets are tested to be less than ±5 mV.
Bridged Output
The IRAUDAMP4 is not intended for BTL operation. However, BTL operation can be
achieved by feeding out-of-phase audio input signals to the two input channels. In BTL
operation, minimum load impedance is 8 Ω and rated power is 240 W non-clipping. The
installed clamping diodes D5 – D8 are required for BTL operation, since reactive energy
flowing from one output to the other during clipping can force the output voltage beyond
the voltage supply rails if not clamped.
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Startup and Shutdown
One of the most important aspects of any audio amplifier is the startup and shutdown
procedures. Typically, transients occurring during these intervals can result in audible
pop- or click-noise on the output speaker. Traditionally, these transients have been kept
away from the speaker through the use of a series relay that connects the speaker to the
audio amplifier only after the startup transients have passed and disconnects the
speaker prior to shutting down the amplifier. It is interesting to note that the audible noise
of the relay opening and closing is not considered “click noise”, although in some cases,
it can be louder than the click noise of non-relay-based solutions.
The IRAUDAMP4 does not use any series relay to disconnect the speaker from the
audible transient noise, but rather a shunt-based click noise reduction circuit that yields
audible noise levels that are far less that those generated by the relays they replace.
This results in a more reliable, superior performance system.
For the startup and shutdown procedures, the activation (and deactivation) of the clicknoise reduction circuit, the Class D power stage and the audio input (mute) controls
have to be sequenced correctly to achieve the required click noise reduction. The overall
startup sequencing, shutdown sequencing and shunt circuit operation are described
below.
Click-Noise Reduction Circuit (Solid-State Shunt)
To reduce the turn-on and turn-off click noise, a low impedance shunting circuit is used
to minimize the voltage across the speaker during transients. For this purpose, the
shunting circuit must include the following characteristics:
1) An impedance significantly lower than that of the speaker being shunted. In this
case, the shunt impedance is ~100 mΩ, compared to the nominal 4 Ω speaker
impedance.
2) When deactivated, the shunting circuit must be able to block voltage in both
directions due to the bi-directional nature of the audio output.
3) The shunt circuit requires some form of OCP. If one of the Class D output
MOSFETs fails, or is conducting when the speaker mute (SP MUTE) is activated,
the shunting circuit will effectively try to short one of the two supplies (+/-B).
The implemented click-noise reduction circuit is shown in Figure 9. Before startup or
shutdown of the Class D power stage, the click-noise reduction circuit is activated
through the SP MUTE control signal. With SP MUTE signal high, the speaker output is
shorted through the back-to-back MOSFETs (U9 for Channel 1) with an equivalent on
resistance of about 100 mΩ. The two transistors (U7 for Channel 1) are for the OCP
circuit.
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+B
Speaker Mute
Click noise
reduction circuit
-B
Transient
current paths
Over Current
Protection
Figure 9. Class D Output Stage with Click-Noise Reduction Circuit
Startup and Shutdown Sequencing
The IRAUDAMP4 sequencing is achieved through the charging and discharging of the
CStart capacitor C117. This, coupled to the charging and discharging of the voltage of
CSD (C3 on daughter board for CH1) of the IRS20955, is all that is required for complete
sequencing. The conceptual startup and shutdown timing diagrams are show in Figure
10.
CStart Ref1
CStart Ref2
+B
CSD= 2/3VDD
CSD
CStart
+5 V
Time
-5 V
VCC
UVP@-20 V
-B
CHx_O
SP MUTE
Audio MUTE
Class D startup
Music startup
Figure 10. Conceptual Startup Sequencing of Power Supplies and Audio Section Timing
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For startup sequencing, +/-B supplies startup at different intervals. As +/-B supplies
reach +5 V and -5 V respectively, the analog supplies (+/-5 V) start charging and, once
+B reaches ~16 V, VCC charges. Once –B reaches -20 V, the UVP is released and CSD
and CStart start charging. Once +/-5 V is established, the click-noise reduction circuit is
activated through the SP MUTE control signal. As CSD reaches two-thirds VDD, the
Class D stage starts oscillating. Once the startup transient has passed, SP MUTE is
released (CStart reaches Ref1). The Class D amplifier is now operational, but the
preamp output remains muted until CStart reaches Ref2. At this point, normal operation
begins. The entire process takes less than three seconds.
+B
CStart Ref2
CStart Ref1
CSD= 2/3VDD
CSD
CStart
+5 V
Time
-5 V
VCC
-B
UVP@-20 V
CHx_O
SP MUTE
Audio MUTE
Class D shutdown
Music shutdown
Figure 11. Conceptual Shutdown Sequencing of Power Supplies and Audio Section Timing
Shutdown sequencing is initiated once UVP is activated. As long as the supplies do not
discharge too quickly, the shutdown sequence can be completed before the IRS20955
trips UVP. Once UVP is activated, CSD and CStart are discharged at different rates. In
this case, threshold Ref2 is reached first and the preamp audio output is muted. Once
CStart reaches threshold Ref1, the click-noise reduction circuit is activated (SP MUTE).
It is then possible to shutdown the Class D stage (CSD reaches two-thirds VDD). This
process takes less than 200 ms.
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For any external fault condition (OTP, OVP, UVP or DCP – see “Protection”) that does
not lead to power supply shutdown, the system will trip in a similar manner as described
above. Once the fault is cleared, the system will reset (similar sequence as startup).
CStart Ref2
CStart Ref1
CStart Ref1
CStart Ref2
CSD= 2/3VDD
CSD
CStart
Time
External trip
Reset
CHx_O
SP MUTE
Audio MUTE
Music shutdown
Class D shutdown
Class D startup
Music startup
Figure 12. Conceptual Click Noise Reduction Sequencing at Trip and Reset
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Protection
The IRAUDAMP4 has a number of protection circuits to safeguard the system and
speaker during operation, which fall into one of two categories, internal faults and
external faults, and distinguished by the manner in which a fault condition is treated.
Internal faults are only relevant to the particular channel, while external faults affect the
whole board. For internal faults, only the offending channel is stopped. The channel will
hiccup until the fault is cleared. For external faults, the whole board is stopped using the
shutdown sequencing described earlier. Here, the system will also hiccup until the fault
is cleared at which time it will restart according to the startup sequencing described
earlier.
+B
VCC
20955
PWM
OCP
CSD
OTP
OVP/
UVP
-B
-B
Green
LED
To other Channel
Trip
Red
LED
DCP
Figure 13. Functional Block Diagram of Protection Circuit Implementation
Internal Faults
OCP and OTP are considered internal faults. These internal faults will only shutdown the
particular channel by pulling low the relevant CSD pin. The channel will shutdown for
about one-half a second and will hiccup until the fault is cleared.
Over-Temperature Protection (OTP)
A separate PTC resistor is placed in close proximity to the high-side IRF6645 DirectFET
MOSFET for each of the amplifier channels. If the resistor temperature rises above
100 °C, the OTP is activated. The OTP protection will only shutdown the relevant
channel by pulling low the CSD pin and will recover once the temperature at the PTC
has dropped sufficiently. This temperature protection limit yields a PCB temperature at
the MOSFET of about 100 °C. This setting is limited by the PCB material and not by the
operating range of the MOSFET.
Over-Current Protection (OCP)
The OCP internal to the IRS20955 shuts down the IC if an OCP is sensed in either of the
output MOSFETs. For a complete description of the OCP circuitry, please refer to the
IRS20955 datasheet. Here is a brief description:
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16
Low-Side Current Sensing
The low-side MOSFET is protected from an overload condition and will shutdown the
switching operation if the load current exceeds a preset trip level. The low-side current
sensing is based on measurement of MOSFET drain-to-source voltage during the lowside MOSFET on state. The voltage set on the OCSET pin programs the threshold for
low-side over-current sensing. Thus, if the VS voltage (during low-side conduction) is
higher than the OCSET voltage, the IRS20955 will trip. It is recommended to use VREF
to supply a reference voltage to a resistive divider (R5 and R7 for CH1) generating a
voltage to OCSET for better variability against VCC fluctuations. For IRAUDAMP4, the
low-side over-current trip level is set to 0.65 V. For the IRF6645 DirectFET MOSFETs
with a nominal RDS-ON of 28 mΩ at 25 °C, this results in a ~23 A maximum trip level.
Since the RDS-ON is a function of temperature, the trip level is reduced to ~15 A at 100 °C.
Figure 14. Simplified Functional Block Diagram of Low-Side Current Sensing (CH1)
High-Side Current Sensing
The high-side MOSFET is protected from an overload condition and will shutdown the
switching operation if the load current exceeds a preset trip level. High-side over-current
sensing monitors detect an overload condition by measuring drain-to-source voltage
(VDS) through the CSH and VS pins. The CSH pin detects the drain voltage with
reference to the VS pin, which is the source of the high-side MOSFET. In contrast to the
low-side current sensing, the threshold of CSH pin to engage OC protection is internally
fixed at 1.2 V. An external resistive divider R23 and R25 (for Ch1) can be used to
program a higher threshold. An additional external reverse blocking diode (D5 for Ch1) is
required to block high-voltage feeding into the CSH pin during low-side conduction. By
subtracting a forward voltage drop of 0.6 V at D5, the minimum threshold which can be
set in the high-side is 0.6 V across the drain-to-source. For IRAUDAMP4, the high-side
over-current trip level is set to 0.6 V across the high-side MOSFET. For the IRF6645
MOSFETs with a nominal RDS-ON of 28 mΩ at 25 °C, this results in a ~21 A maximum trip
level. Since the RDS-ON is a function of temperature, the trip level is reduced to ~14 A at
100 °C.
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Figure 15. Simplified Functional Block Diagram of High-Side Current Sensing (CH1)
For a complete description of calculating and designing the over-current trip limits,
please refer to the IRS20955 datasheet.
External Faults
OVP, UVP and DCP are considered external faults. In the event that any external fault
condition is detected, the shutdown circuit will activate for about three seconds, during
which time the orange “Protection” LED will turn on. If the fault condition has not cleared,
the protection circuit will hiccup until fault is removed. Once the fault is cleared, the
green “Normal” LED will turn on. There is no manual reset option.
Over-Voltage Protection (OVP)
OVP will shutdown the amplifier if the bus voltage between GND and -B exceeds 40 V.
The threshold is determined by the voltages sum of the Zener diode Z105, R140, and
VBE of Q109. As a result, it protects the board from bus pumping at very low audio signal
frequencies by shutting down the amplifier. OVP will automatically reset after three
seconds. Since the +B and –B supplies are assumed to be symmetrical (bus pumping,
although asymmetrical in time, will pump the bus symmetrically in voltage level). It is
sufficient to sense one of the two supply voltages only for OVP. It is therefore up to the
user to ensure that the power supplies are symmetrical.
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Under-Voltage Protection (UVP)
UVP will shutdown the amplifier if the bus voltage between GND and -B falls below 20 V.
The threshold is determined by the voltages sum of the Zener diode Z107, R145 and VBE
of Q110. Same as OVP, UVP will automatically reset after three seconds and only one
of the two supply voltages is monitored.
Speaker DC-Voltage Protection (DCP)
DCP is provided to protect against DC current flowing into the speakers. This abnormal
condition is rare and is likely caused when the power amplifier fails and one of the highside or low-side IRF6645 DirectFET MOSFETs remain in the ON state. DCP is activated
if either of the outputs has more than ±4 V DC offset (typical). Under this fault condition,
it is normally required to shutdown the feeding power supplies. Since these are external
to the reference design board, an isolated relay is provided (P1) for further systematic
evaluation of DC-voltage protection to transmit this condition to the power supply
controller and is accessible through connector J9 (pins of J9 are shorted during fault
condition).
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19
Thermal Considerations
The daughter board design can handle one-eighth of the continuous rated power, which
is generally considered to be a normal operating condition for safety standards. Without
the addition of a heatsink or forced air-cooling, the daughter board cannot handle
continuous rated power.
100.0%
90.0%
Power Stage Efficiency (%)
80.0%
70.0%
60.0%
50.0%
40.0%
30.0%
20.0%
10.0%
0.0%
0
20
40
60
80
100
120
140
160
180
Output Power (W)
Figure 16. Efficiency FV. Output Power, 4 Ω Single Channel Driven, ±B supply = ±35 V, 1 kHz
Audio Signal
67°C
54°C
Figure 17. Thermal image of Daughter Board
Two-Channel x 1/8th Rated Power (15 W) in Operation, TC = 54 °C at Steady State
±B supply = ±35 V, 4 Ω Load, 1 kHz audio signal, TA = 25 °C
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RD-0617
20
Typical Performance
±B supply = ± 35 V, load impedance = 4 Ω, 1 kHz audio signal,
Self oscillator @ 400 kHz and internal volume-control set to give required output with
1 Vrms input signal, unless otherwise noted.
+4
+2
8Ω
+0
d
B
4Ω
-2
r
-4
A
-6
-8
-10
20
50
100
200
500
Green
Red
1k
Hz
2k
5k
10k
20k
50k
200k
CH1 - 4 Ω, 2 V Output
CH1 - 8 Ω, 2 V Output
Figure 18. Frequency Characteristics vs. Load Impedance
+0
-20
-40
d
-60
B
-80
Int.
Self
-100
-120
20
50
Red
Green
100
200
500
Hz
1k
2k
5k
10k
20k
CH2 – CH1, 60 W, Self Oscillator @ 400 kHz
CH2 – CH1, 60 W, Internal Clock @ 300 kHz
Figure 19. Channel Separation vs. Frequency
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+0
-10
-20
-30
-40
-50
d
B
-60
-70
-80
Int.
-90
-100
Self
-110
-120
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Red
Green
CH2 – CH1, 60 W, Self Oscillator @ 400 kHz
CH2 – CH1, 60 W, Internal Clock @ 300 kHz
Figure 20. Stand-alone Class D Power Stage: Channel Separation vs. Frequency
100
50
10
1
% 0.1
0.01
0.001
0.0001
100m
200m
500m
1
2
5
10
20
50
100
200
W
Green
Red
CH1 - ACD, ±B = ± 35 V, Volume gain 21.9 V/V – AUX-25 filter
CH1 - ACD, ±B = ± 35 V, Volume gain 21.9 V/V – 3rd order RC filter
Figure 21. Stand-alone Class D Power Stage: THD+N Ratio vs. Output Power
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22
100
T
±30 V
10
±25 V
1
%
±35 V
0.1
0.01
0.001
100m
200m
500m
1
2
5
10
20
50
100
200
W
Green
Blue
Red
CH1, ±B = ±35 V, Volume gain 21.9 V/V
CH1, ±B = ±30 V, Volume gain 21.9 V/V
CH1, ±B = ±25 V, Volume gain 21.9 V/V
Figure 22. THD+N Ratio vs. Output Power
100
50
±30 V
10
5
±25 V
1
0.5
%
0.2
±35 V
0.1
0.02
0.01
0.002
0.001
100m
200m
500m
1
2
5
10
20
50
100
200
W
Green
Blue
Red
CH1 - ACD, ±B = ±35 V, Volume gain 21.9 V/V
CH1 - ACD, ±B = ±30 V, Volume gain 21.9 V/V
CH1 - ACD, ±B = ±25 V, Volume gain 21.9 V/V
Figure 23. THD+N Ratio vs. Output Power (ACD)
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RD-0617
23
100
10
1
100 W
0.1
%
0.01
1W
10 W
0.001
0.0001
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Green
Blue
Red
CH1, 1 W Output
CH1, 10 W Output
CH1, 100 W Output
Figure 24. THD+N Ratio vs. Frequency
100
10
1
%
100 W
0.1
0.01
1W
10 W
0.001
0.0001
20
50
100
Green
Yellow
Red
200
500
Hz
1k
2k
5k
10k
20k
CH1 - ACD, 1 W Output
CH1 - ACD, 10 W Output
CH1 - ACD, 100 W Output
Figure 25. THD+N Ratio vs. Frequency (ACD)
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RD-0617
24
+0
-20
-40
d
-60
B
V -80
Self
Int.
-100
-120
-140
10
20
50
Green
Red
100
200
500
Hz
1k
2k
5k
10k
20k
CH1 - ACD, 1 V, 1 kHz, Self Oscillator @ 400 kHz
CH1 - ACD, 1 V, 1 kHz, Internal Clock @ 300 kHz
Figure 26. Frequency Spectrum (ACD)
+0
-20
-40
d -60
B
V -80
Self
-100
Int.
-120
-140
10
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Green
Red
CH1 - ACD, No signal, Self Oscillator @ 400 kHz
CH1 - ACD, No signal, Internal Clock @ 300 kHz
Figure 27. Residual Noise (ACD)
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25
Red Trace: Total Distortion + Noise Voltage
Green Trace: Output Voltage
60 W / 4 Ω, 1 kHz, THD+N=0.004%
174 W / 4 Ω, 1 kHz, THD+N=10%
Figure 28. Measured Output and Distortion Waveforms
CSD pin
CSD pin
VS pin
VS pin
Load current
Load current
Figure 29. Typical OCP Waveforms Showing Load Current and Switch Node Voltage (VS)
CSD pin
CSD pin
VS pin
VS pin
Load current
Load current
Figure 30. Typical OCP Waveforms Showing CSD Trip and Hiccup
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RD-0617
26
IRAUDAMP4 Design Documents
Motherboard Schematics:
+B
I
E
S
SW
10K
S2
+5V
R142
68k
D106
1N4148
1
2
47k
D105
R138
OT
R112
820R
OT
R148
10k
VCC
1Y
6A
2A
6Y
2Y
5A
3A
5Y
3Y
4A
GND
4Y
DCP
R145
47K
R144
UVP
10k
Q109
Q110
MMBT5551
R141
47k
MMBT5551
U_3
1A
R146
47K
Q103
R113
R116
47R
R114
100R
10uF, 50V
Z108
8.2V
C114
74HC14
10nF, 50V
CLK
Q108
CLK
+5V
J8
BNC
A24497
R115
47R
R134
10k
R126
100K
MMBT5401
Q105
NORMAL
1k
MMBT5551
R137
MMBT5551
R119
R130
47K
47k
DC protection
PROTECTION
DCP
D104
1N4148
MUTE R117
MUTE
R125
10K
Q106
R135
82k
R118
1k
EXT. CLK
+B
C115
S
E
I
SW-3WAY_A-B
S3B SW
R136
68k
R131
47K
-5V
R128
6.8k
R124
10k
Q104
47R
R151
47k
HS1
+B
Z109
8.2V
-B
+B
R129
6.8k
R133
47k
Q112
MMBT5551
Earth
+B
-5V
+5V
R107
4.7K
P1
1
2
3
6
5
4
J9
2
1
Z103
15V
ED1567
PVT412
R132
47k
MMBT5551
Z102
4.7V
Z101
4.7V
R127
6.8k
R152
OPEN
Q107
-B
DC_PS
MMBT5401
47k
HEAT SINK 294-1086-ND
R106
47K
Q102
-B
+5V
U_4
MC78M05
C101
10uF, 50V
R104
47R, 1W
Vout
D101
MA2YD2300
C102
10uF, 50V
C107
4.7uF, 16V
-5V
U_5
C103
10uF, 50V
8
-5V
MC79M05
IN
GND
Vin
+5V
+5V
R108
CT2265
OUT
D102
MA2YD2300
GND
R102
47R, 1W
R105
R103
47R, 1W
C104
10uF, 50V
7
6
C108
10nF, 50V
5
10R
C109
4.7uF, 16V
U_2
VSS
VDD
VR0
CS
VR1
SDATA
CLK
SIMUL
1
2 CS
3 SDATAI
MMBT5401
VCC
VCC
U_6
MC78M12
Vout
CS
SDATAI
4
SCLK
C105
SCLK
FX941
Vin
C106
10uF, 50V
3310S06S
Q101
GND
R101
47R, 1W
R121
47k
R123
1K
R150
+B
R122
47k
C116
100uF, 16V
GND
CH2 O
100pF, 50V
S1
C119
SW-PB
0.1uF, 50V
OVP
-B
5K POT
CH1 O
C113
MMBT5551
Z107
18V
R149
47K
Z105
39V
1N4148
D107
C117
1N4148 100uF, 16V
R120
100R
R111
10K
100k
+5V
4.7k
CStart
SP MUTE
1N4148
R110
C112
1200pF, 50V
100pF, 50V
C111
R140
10k
R139
Z106
18V
SW_H-L
D103
C110
R147
47k
Q111
MMBT5401
R109
1K
1nF, 50V
SD
R143
SW-3WAY_A-B
S3A
Z104
24V
10uF, 50V
-B
IRAUDAMP VER.4 - POWER SUPPLY AND PROTECTION
Figure 31. Housekeeping and Protection Circuits
www.irf.com
RD-0617
27
R33
47K
R29
+5V
C11
R25
C7
3.3uF, 50V
U1
TLC081
D5
C23_1
0.47uF, 630V
OPEN
100R
C13
1nF, 200V
C25
R39
470R
R29P
1K
CH1 OUT
R49
2.2k
0.1uF, 400V
10, 1W
J3
C27
D7
R47
OPEN
1nF, 200V
R21
4.7R
C15
33pF
C23
1K
+5V
MURA120T3OSCT-ND
CH1 O
R31
R19
0R
D1
1N4148
L1
22uH
150pF, 500V
CH1 IN
R17
22k
+B
C17
R55
OPEN
C5
10uF, 50V
OPEN
1
2
U9
-B
MURA120T3OSCT-ND
C19
2.2uF, 16V
Z1
3
4
6
5
R35
1K
15V
R51
C29
IRF7341
C9
3.3uF, 50V
R23
R53
47K
1
2
8
7
R37
1K
D3
1N4148
SP Mute
D11
1N4148
277-1022
100K
U7
U3
-5V
4.7R
1
OPEN
5
74AHC1G04
CLK
R27
4
47R
J5
1418-ND
CLK
3
2
XN01215
R71
J1
SDATAI
47R
CS
R8
47R
SDATAI
R9
R14
C2
3.3K
2.2uF, 50V
SDATAI AOUTL
C1
10uF, 50V
VD+
+B
R5
C31
1000uF,50V
-5V
4.7R 4.7R
DGRD
VA+
SCLK
AOUTR
+5V
3.3K
47R
C3
2.2uF, 50V
R6
3
2
1
SDATAOAGNDR
MUTE
47R
R60
AINR
C34
OPEN
C32
1000uF,50V
J7
+5V
R11
MUTE
C33
OPEN
-5V
VA-
R13
R10
SCLK
+B
AGNDL
10R
+5V
CH2 O
R7
CS
CS
AINL
R57
100K
R58
100K
CH1 O
ZCEN
OT
VSS
-B
-B
Earth
277-1272
R4
100R
CS3310
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CH2 O
CH2 O
CH2O
CH2 O
-B
-B
-B
-B
CH1 O
CH1 O
CH1 O
CH1 O
+B
+B
+B
GND
PWM1
IN1
GND1
VAA
PWM2
VSS
GND2
VCC
SD
J2
R63
IN2
1
OT
2
-5V
3
4
5
6
+5V
7
8
-5V
9
10
11
SP Mute
VCC
SD
OPEN
R3
100R
U_1
D12
1N4148
SD
12
U10
R54
47K
R72
OPEN
OPEN
OPEN
R61
R64
OPEN
C41
J6
1418-ND
C18
R56
OPEN
C6
10uF, 50V
OPEN
R65
R18
22k
R32
C45
OPEN
OPEN
R66
OPEN
C46
R20
0R
R22
4.7R
C16
33pF
C8
3.3uF, 50V
U2
TLC081
R68
D2
1N4148
OPEN
R67
R69
100R
D6
C24_1
OPEN
C26
R40
470R
R30P
10, 1W
C20
2.2uF, 16V
R26
C14
1K
CH2 OUT
D8
R50
2.2k
-B
MURA120T3OSCT-ND
0.1uF, 400V
R48
OPEN
1nF, 200V
J4
C28
OPEN
1
2
15V
R52
IRF7341
C30
U8
277-1022
100K
OPEN
1
5
4
3
2
XN01215
R38
1K
R36
D4
1N4148
1K
C48
OPEN
R24
C10
3.3uF, 50V
-5V
4.7R
R28
OPEN
Z2
3
4
6
5
MURA120T3OSCT-ND
0.47uF,630V
+5V
R30
1nF, 200V
C24
1K
+5V
C12
OPEN
R34
47K
OPEN
C42
+B
L2
22uH
150pF, 500V
CH2 IN
C44
R62
1
2
8
7
R2
100K
OPEN
OPEN
OPEN
CON EISA31
OPEN
C43
CH2 O
OPEN
C40
SP MUTE
R1
100K
GND
CLK
OPEN
C47
C49
OPEN
OPEN
U4
74AHC1G04
47R
IRAUDAMP VER.4 - PREAMP AND POWER STAGE
Figure 32. Audio Channels 1 and 2
www.irf.com
RD-0617
28
Daughter Board Schematics:
1
OT
2
VSS
3
PWM1
PWM 1
4
IN1
5
GND1
VSS1
6
VAA
7
PWM2
CH2 O
VCC
R3
10K
CH1 O
CSD1
D1
1N4148
D3
MURA120T3OSCT-ND
PWM 1
C3
10uF, 16V
10
5
11
SD
R43
4.7K
R5
TP1
8.2k
12
IN2
3
4
VSS1
VCC
1
2
C11
47pF
D9
MA2YD2300
VSS2
SD
R7
1.2k
CON EISA31
R9
C5
OPEN
D7
S1DB-FDICT-ND
DS1
160-1414-1-ND
R19
47K
R21
10K
U1
9
VCC
R15
10R
R1
100R
C1
2.2uF, 25V
J2
PWM 2
R13
4.7R
SD
+B
8
VSS
GND2
+B
-B
VDD
CSH
CSD
VB
IN
HO
VSS
VS
NC
6
NC
VREF
7
8
8.2K
VCC
OC
LO
DT
COM
R23
0R
16
D5
BAV19WDICT-ND
Q3
15
10R
22uF, 25V
13
C15
0.1uF
R25
R27
10k
C7
14
C13
0.1uF,100V
J1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
IRF6645
CH1 O
12
Q5
11
R29
C9
2.2uF, 25V
10
10R
9
R31
IRF6645
1R
IRS20955S
-B
R11
-B
C17
0.1uF,100V
CH2 O
CH2 O
CH2O
CH2 O
-B
-B
-B
-B
CH1 O
CH1 O
CH1 O
CH1 O
+B
+B
+B
GND
3.3K
VCC
+B
OTP CH1
SD
Rp2
100C
R34
1K
1N4148
R33
1K
C22
47nF
R38
100K
R36
100K
MMBT5401
R35
100K
C21
47nF
R37
100K
MMBT5401
C2
2.2uF, 25V
D8
MA2YD2300
47pF
C4
10uF, 16V
R40
100K
CSD1
5
R6
R8
1.2k
R39
100K
Q7
R42
MMBT3904 10K
C24
C23
47nF
47nF
3
4
VSS2
8.2k
Q8
1
2
TP2
CSD2
R20
47K
10R
R22
10K
U2
C12
Q1
R16
D4
MURA120T3OSCT-ND
100R
Rp1
100C
PWM 2
Q2
R14
4.7R
CSD2
D2
R2
C6
OPEN
R10
8.2K
6
7
8
VDD
CSH
CSD
VB
IN
HO
VSS
VS
NC
VREF
NC
VCC
OC
LO
DT
COM
R24
0R
16
D6
BAV19WDICT-ND
Q4
15
14
C8
13
22uF, 25V
R26
10k
C16
0.1uF
R28
10R
IRF6645
C18
CH2 O
12
Q6
11
10
C10
2.2uF, 25V
9
R30
10R
IRF6645
R32
1R
IRS20955S
-B
R12
R41
10K
C14
0.1uF,100V
OTP CH2
+B
0.1uF,100V
R4
10K
+B
MMBT3904
3.3K
IRAUDAMP VER.4 - DAUGHTER BOARD
VSS2
VSS1
Figure 33. Daughter Board Schematic with Class D Stage for Two Audio Channels
www.irf.com
RD-0617
29
IRAUDAMP4 Bill of Materials
Motherboard:
IRAUDAMP4 MOTHERBOARD BILL OF MATERIAL
NO
23
24
25
26
27
Designator
C1, C5, C6, C101, C102, C103, C104,
C105, C106, C115
C2, C3
C7, C8, C9, C10
C11, C12, C13, C14
C15, C16
C17, C18
C19, C20
C119
C23, C24
C23_1, C24_1
C25, C26
C27, C28, C29, C30, C40, C41, C42,
C43, C44, C45, C46, C47
R29, R30, R55, R56, R60, R61, R62,
R63, R64, R65, R66, R67, R71, R72
C31, C32
C33, C34, C48, C49
C107, C109
C108, C114
C110
C111, C113
C112
C116, C117
D1, D2, D3, D4, D11, D12, D103, D104,
D105, D106, D107
D5, D6, D7, D8
D101, D102
HS1
J1A, J1B
J2A, J2B
28
J3, J4
2
MKDS5/2-9.5
277-1022
277-1271-ND or 6511714971
29
J5, J6
2
cp1418
1418-ND
CP-1418-ND
30
J7
1
J HEADER3
277-1272
277-1272-ND or 6511714984
31
32
J8
J9
1
1
BNC_RA CON
ED1567
BNC
ED1567
A32248-ND
ED1567
33
L1, L2
2
Inductor
22uH
'Sagami 7G17A-220MR
or
IN09063
34
35
36
37
38
NORMAL
P1
PROTECTION
Q101
Q102, Q104, Q106, Q111
Q103, Q105, Q107, Q108, Q109, Q110,
Q112
R1, R2, R51, R52, R57, R58, R110,
R126
R3, R4, R114
R5, R6
R7, R8, R10, R11, R27, R28, R115,
R116, R117
R9, R105
R13, R14
R17, R18
R53, R54, R106, R121, R122, R130,
R131, R132, R133, R137, R139, R141,
R145, R146, R147, R149, R150, R151
R152
R19, R20
R39, R40
R21, R22, R23, R24
1
1
1
1
4
Led rb2/5
DIP-6
Led rb2/5
SOT89
SOT23-BCE
404-1106-ND
PVT412
404-1109-ND
FX941
MMBT5401
160-1143-ND
PVT412-ND
160-1140-ND
FCX491CT-ND
MMBT5401DICT-ND
7
SOT23-BCE
MMBT5551
MMBT5551-7DICT-ND
Digikey
8
805
100K
P100KACT-ND
Digikey
3
2
805
1206
100R
4.7R
P100ACT-ND
P4.7ECT-ND
Digikey
Digikey
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
39
40
41
42
43
44
45
46
47
48
49
50
51
www.irf.com
#
Footprint
PartType
Part No
Vender
10
RB2/5
10uF, 50V
565-1106-ND
Digikey
2
4
4
2
2
2
1
2
2
2
1
2
1
4
2
4
2
2
1
2
1
2
1
1
4
2
1
2
2
RB2/5
CR3225-1210
1206
805
AXIAL0.19R
1206
1206
CAP MKP
AXIAL0.2R
CAP MKPs
2.2uF, 50V
3.3uF, 50V
1nF, 200V
33pF
150pF, 500V
2.2uF, 16V
0.1uF, 50V
0.47uF, 630V
OPEN
0.1uF, 400V
565-1103-ND
445-1432-1-ND
PCC2009CT-ND
478-1281-1-ND
338-1052-ND
PCC1931CT-ND
PCC104BCT-ND
495-1315-ND
495-1311-ND
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
805
OPEN
-
Digikey
805
OPEN
-
Digikey
RB5/12_5
AXIAL0.1R
805
805
805
805
805
rb2/5
1000uF,50V
OPEN
4.7uF, 16V
10nF, 50V
1nF, 50V
100pF, 50V
1200pF, 50V
100uF, 16V
565-1114-ND
PCC2323CT-ND
PCC103BNCT-ND
PCC102CGCT-ND
PCC101CGCT-ND
478-1372-1-ND
565-1037-ND
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
SOD-123
1N4148
1N4148WDICT-ND
Digikey
SMA
SOD-123
Heat_S6in1
CON EISA-31
CON_POWER
MURA120
MA2YD2300
HEAT SINK
CON EISA31
CON_POWER
MURA120T3OSCT-ND
MA2YD2300LCT-ND
294-1086-ND
A26453-ND
A26454-ND
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
or
Mouser
Digikey
Digikey
or
Mouser
Digikey
Digikey
'Inductor
s, Inc.
or
ICE
Compon
ents, Inc.
Digikey
Digikey
Digikey
Digikey
Digikey
9
805
47R
P47ACT-ND
Digikey
2
2
2
805
805
805
10R
3.3K, 1%
22k
P10ACT-ND
P3.3KZCT-ND
P22KACT-ND
Digikey
Digikey
Digikey
1
8
805
47k
P47KACT-ND
Digikey
1
2
2
4
805
805
805
805
OPEN
0R
470R
4.7R
P0.0ACT-ND
P470ACT-ND
P4.7ACT-ND
Digikey
Digikey
Digikey
Digikey
RD-0617
30
52
53
54
55
3
2
2
2
1206
POT_SRM
2512
1206
100R
1K
47K, 1%
1K
8
805
2
2
2
4
2
1
2512
1206
AXIAL-0.3
2512
805
V_Control
8
64
65
66
67
68
69
70
71
72
73
74
75
76
R25, R26, R120
R29P, R30P
R31, R32
R33, R34
R35, R36, R37, R38, R109, R118, R119,
R123
R47, R48
R49, R50
R68, R69
R101, R102, R103, R104
R107, R138
R108
R111, R124, R125, R134, R140, R143,
R144, R148
R112
R113
R127, R128, R129
R135
R136, R142
S1
S2
S3
U1, U2
U3, U4
U7, U8
U9, U10
U_1
1
1
3
1
2
1
1
1
2
2
2
2
1
77
U_2
1
78
79
80
81
82
U_3
U_4
U_5
U_6
Z1, Z2, Z103
1
1
1
1
3
56
57
58
59
60
61
62
63
P100ECT-ND
3361P-102GCT-ND
PT47KAFCT-ND
P1.0KECT-ND
Digikey
Digikey
Digikey
Digikey
1K
P1.0KACT-ND
Digikey
10, 1W
2.2k
OPEN
47R, 1W
4.7K
CT2265
PT10XCT
P2.2KECT-ND
PT47XCT-ND
P4.7KACT-ND
CT2265-ND
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
805
10K
P10KACT-ND
Digikey
805
POTs
1206
805
805
Switch
SW-EG1908-ND
SW-EG1944-ND
SO-8
SOT25
MINI5
SO-8
SOIC16
820R
5K POT
6.8k
82k
68k
SW-PB
SW_H-L
SW-3WAY
TLC081
74AHC1G04
XN01215
IRF7341
CS3310
P820ACT-ND
3362H-502-ND
P6.8KECT-ND
P82KACT-ND
P68KACT-ND
P8010S-ND
EG1908-ND
EG1944-ND
296-7264-1-ND
296-1089-1-ND
XN0121500LCT-ND
IRF7341
73C8016 or 72J5420
N8A
3310S06S
3310-IR01
M14A
TO-220 Fullpak
TO-220 Fullpak
TO-220 Fullpak
SOD-123
74HC14
MC78M05
MC79M05
MC78M12
15V
296-1194-1-ND
MC78M05BTOS-ND
MC79M05CTOS-ND
MC78M12CTOS-ND
BZT52C15-FDICT-ND
1SMA5917BT3GOSCTND
BZT52C24-FDICT-ND
BZT52C39-13-FDICTND
BZT52C18-FDICT-ND
BZT52C8V2-FDICT-ND
MCCPMB1
83
Z101, Z102
2
SMA
4.7V
84
Z104
1
SOD-123
24V
85
Z105
1
SOD-123
39V
86
87
88
Z106, Z107
Z108, Z109
Volume Knob
Thermalloy TO-220 mounting kit with
screw
1/2" Standoffs 4-40
4-40 Nut
No. 4 Lock Washer
2
2
1
SOD-123
SOD-123
18V
8.2V
89
90
91
92
3
5
5
5
100 per bag
100 per bag
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
IR
Newark
*Tachyon
ix
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Newark
46F4081
Newark
8401K-ND
H724-ND
H729-ND
Digikey
Digikey
Digikey
*Tachyonix Corporation,
14 Gonaka Jimokuji Jimokuji-cho,
Ama-gun Aichi, JAPAN 490-1111
http://www.tachyonix.co.jp
[email protected]
www.irf.com
RD-0617
31
Voltage regulator mounting:
Item Description
7
8
1
Insulator Thermalfilm
2
Shoulder Washer
3
Flat Washer #4
4
No. 4-40 UNC-2B Hex Nut
5
No. 4-40 UNC-2A X 1/2 Long Phillips
Pan Head Screw
6
Lockwasher, No.4
7
Heatsink
8
PCB
Daughter Board:
IRAUDAMP4 DAUTHER-BOARD BILL OF MATERIAL
NO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Designator
C1, C2, C9, C10
C3, C4
C5, C6
C7, C8
C11, C12
C13, C14
C15, C16, C17, C18
C21, C22, C23, C24
D1, D2
D3, D4
D5, D6
D7
D8, D9
DS1
J1
J2
Q1, Q2
#
4
2
2
2
2
2
4
4
2
2
2
1
2
1
1
1
2
18
Q3, Q4, Q5, Q6
4
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
Q7, Q8
R1, R2
R3, R4, R25, R26
R5, R6, R9, R10
R7, R8
R11, R12
R13, R14
R15, R16, R27, R28, R29, R30
R19, R20
R21, R22, R41, R42
R23, R24
R31, R32
R33, R34
R35, R36, R37, R38, R39, R40
R43
Rp1, Rp2
U1, U2
2
2
4
4
2
2
2
6
2
4
2
2
2
6
1
2
2
www.irf.com
Footprint
1206
T491
0805
1812
0805
0805
1206
0805
SOD-123
SMA
SOD-123
SMB
SOD-123
LED
CON EISA-31
CON_POWER
SOT23-BCE
DirectFET
MOSFET6645
SOT23-BCE
0805
1206
0805
0805
0805
0805
0805
0805
0805
0805
0805
0805
0805
0805
0805
M16A
Part Type
2.2 μF, 25 V
10 μF, 16 V
OPEN
22 μF, 25 V
47 pF
0.1 μF
0.1 μF,100 V
47 nF
1N4148
MURA120T3OSCT-ND
BAV19WDICT-ND
S1DB-FDICT-ND
MA2YD2300
160-1414-1-ND
CON EISA31
CON_POWER
MMBT5401
Part No
490-3368-1-ND
399-3706-1-ND
445-1607-1-ND
PCC470CGCT-ND
PCC1840CT-ND
PCC2239CT-ND
PCC1836CT-ND
1N4148WDICT-ND
MURA120T3OSCT-ND
BAV19W-FDICT-ND
RS1DB-FDICT-ND
MA2YD2300LCT-ND
160-1414-1-ND
2011-03-ND
2011-04-ND
MMBT5401DICT-ND
IRF6645
IRF6645
MMBT3904
100 Ω
10 kΩ
8.2 kΩ
1.2 kΩ
3.3 kΩ
4.7 Ω
10 Ω
33 kΩ
10 kΩ
0Ω
1Ω
1 kΩ
100 kΩ
4.7 kΩ
100 C
IRS20955SPBF
MMBT3904-FDICT-ND
P100ACT-ND
P10KECT-ND
P8.2KACT-ND
P1.2KACT-ND
P3.3KACT-ND
P4.7ACT-ND
P10ACT-ND
P33KACT-ND
P10KACT-ND
P0.0ACT-ND
P1.0ACT-ND
P1.0KACT-ND
P100KACT-ND
P4.7KACT-ND
594-2322-675-21007
IRS20955SPBF
RD-0617
Vendor
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
IR
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Mouser
IR
32
IRAUDAMP4 PCB Specifications
Figure 34. Motherboard and Daughter Board Layer Stack
Motherboard:
Material:
FR4, UL 125 °C
Layer stack:
2 layers, 1 oz. Cu
Dimensions:
5.2 in x 5.8 in x 0.062 in
Solder mask:
LPI solder mask, SMOBC on top and bottom layers
Plating:
Open copper solder finish
Silkscreen:
On top and bottom layers
Daughter board:
Material:
FR4, UL 125 °C
Layer stack:
2 Layers, 1 oz. Cu each, through-hole plated
Dimensions:
3.125 in x 1.52 in x 0.062 in
Solder mask:
LPI solder mask, SMOBC on top and bottom layers
Plating:
Open copper solder finish
Silkscreen:
On top and bottom layers
www.irf.com
RD-0617
33
IRAUDAMP4 PCB Layers
Motherboard:
Figure 35. Top Layer and Pads
www.irf.com
RD-0617
34
4.0
Figure 36. Top-Side Solder-Mask and Silkscreen
www.irf.com
RD-0617
35
Figure 37. Bottom Layer and Pads
www.irf.com
RD-0617
36
Figure 38. Bottom-Side Solder-Mask and Silkscreen
www.irf.com
RD-0617
37
Daughter Board:
Figure 39. PCB Layout – Top Layer and Pads
Figure 40. PCB Layout – Top-Side Solder-Mask and Silkscreen
www.irf.com
RD-0617
38
Figure 41. PCB Layout – Bottom Layer and Pads
Figure 42. PCB Layout – Bottom-Side Solder-Mask and Silkscreen
www.irf.com
RD-0617
39
IRAUDAMP4 Mechanical Construction
Motherboard
Figure 43. Top Side of Motherboard Showing Component Locations
www.irf.com
RD-0617
40
Figure 44. Bottom Side of Motherboard Showing Component Locations
www.irf.com
RD-0617
41
Daughter Board
Figure 45. Top Side Showing Component Locations
Figure 46. Bottom Side Showing Connector Locations
03/28/2007
www.irf.com
RD-0617
42
Date
3-28-07
Done by
JC
10-28-09
LZ
www.irf.com
REVISIONS HISTORY
Description
- Add caution note
- Modify the order of PCB layer figures
- Modify revision name and remove IR logo in
Daughterboard PCB
- Modify Motherboard PCB to add components, change
value and P/N of some components, remove IR logo
and update revision name.
Details of changes:
1. Change value of C19, C20, R39, and R40
2. Change P/N of Z101 and Z102
3. Add Q112, R150, R151, R152, and Z109
4. Add Lock Washer to the BOM
5. Remove IR logo
6. Update name as Rev. 3
BOM updated :Ice Components as a second vender of
the inductor
RD-0617
43