ICST ICS8430BYI-71LFT 700mhz, low jitter, crystal interface / lvcmos-to-3.3v lvpecl frequency synthesizer Datasheet

PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8430BI-71
700MHZ, LOW JITTER, CRYSTAL INTERFACE/
LVCMOS-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
GENERAL DESCRIPTION
FEATURES
The ICS8430BI-71 is a general purpose, dual outICS
put Crystal/LVCMOS-to-3.3V Differential LVPECL
HiPerClockS™ High Frequency Synthesizer and a member of the
HiPerClockS™ family of High Performance Clock
Solutions from ICS. The ICS8430BI-71 has a selectable crystal oscillator interface or LVCMOS TEST_CLK.
The VCO operates at a frequency range of 250MHz to
700MHz. With the output configured to divide the VCO
frequency by 2, output frequency steps as small as 2MHz
can be achieved using a 16MHz crystal or test clock. Output
frequencies up to 700MHz can be programmed using the
serial or parallel interfaces to the configuration logic. The low
jitter and frequency range of the ICS8430BI-71 make it an
ideal clock generator for most clock tree applications.
• Dual differential 3.3V LVPECL outputs
• Selectable crystal oscillator interface
or LVCMOS TEST_CLK
• Output frequency up to 700MHz
• Crystal input frequency range: 12MHz to 27MHz
• VCO range: 250MHz to 700MHz
• Parallel or serial interface for programming counter
and output dividers
• RMS period jitter: 9ps (maximum)
• Cycle-to-cycle jitter: 25ps (maximum)
• 3.3V supply voltage
• -40°C to 85°C ambient operating temperature
• Available in both standard and lead-free RoHS compliant
packages
BLOCK DIAGRAM
PIN ASSIGNMENT
XTAL_IN
nP_LOAD
M0
M1
M2
M3
M4
XTAL_SEL
VCO_SEL
VCO_SEL
32 31 30 29 28 27 26 25
TEST_CLK
0
XTAL_IN
OSC
1
XTAL_OUT
÷ 16
M5
1
24
XTAL_OUT
M6
2
23
TEST_CLK
M7
3
22
XTAL_SEL
M8
4
21
VCCA
N0
5
20
S_LOAD
N1
6
19
S_DATA
N2
7
18
S_CLOCK
VEE
8
17
MR
ICS8430BI-71
9 10 11 12 13 14 15 16
VEE
CONFIGURATION
INTERFACE
LOGIC
nFOUT0
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
FOUT0
1
÷2
VCCO
FOUT0
nFOUT0
FOUT1
nFOUT1
÷N
nFOUT1
÷M
0
FOUT1
VCO
MR
VCC
TEST
PLL
PHASE DETECTOR
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
TEST
M0:M8
N0:N2
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
8430BYI-71
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1
REV. A FEBRUARY 17, 2006
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8430BI-71
700MHZ, LOW JITTER, CRYSTAL INTERFACE/
LVCMOS-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
FUNCTIONAL DESCRIPTION
specific default state that will automatically occur during
power-up. The TEST output is LOW when operating in the
parallel input mode. The relationship between the VCO frequency, the crystal frequency and the M divider is defined as
follows: fVCO = fxtal x 2M
16
The M value and the required values of M0 through M8 are
shown in Table 3B, Programmable VCO Frequency Function
Table. Valid M values for which the PLL will achieve lock for a
16MHz reference are defined as 125 ≤ M ≤ 350. The frequency
out is defined as follows: fout = fVCO = fxtal x 2M
N
16
N
Serial operation occurs when nP_LOAD is HIGH and S_LOAD
is LOW. The shift register is loaded by sampling the S_DATA
bits with the rising edge of S_CLOCK. The contents of the
shift register are loaded into the M divider and N output divider when S_LOAD transitions from LOW-to-HIGH. The M
divide and N output divide values are latched on the HIGHto-LOW transition of S_LOAD. If S_LOAD is held HIGH, data
at the S_DATA input is passed directly to the M divider and N
output divider on each rising edge of S_CLOCK. The serial
mode can be used to program the M and N bits and test bits
T1 and T0. The internal registers T0 and T1 determine the state
of the TEST output as follows:
NOTE: The functional description that follows describes operation using a 16MHz crystal. Valid PLL loop divider values
for different crystal or input frequencies are defined in the Input Frequency Characteristics, Table 5, NOTE 1.
The ICS8430BI-71 features a fully integrated PLL and therefore requires no external components for setting the loop bandwidth. A parallel-resonant, fundamental crystal is used as the
input to the on-chip oscillator. The output of the oscillator is
divided by 16 prior to the phase detector. With a 16MHz crystal, this provides a 1MHz reference frequency. The VCO of
the PLL operates over a range of 250MHz to 700MHz. The
output of the M divider is also applied to the phase detector.
The phase detector and the M divider force the VCO output
frequency to be 2M times the reference frequency by adjusting the VCO control voltage. Note that for some values of M
(either too high or too low), the PLL will not achieve lock. The
output of the VCO is scaled by a divider prior to being sent to
each of the LVPECL output buffers. The divider provides a
50% output duty cycle.
The programmable features of the ICS8430BI-71 support two
input modes to program the M divider and N output divider.
The two input operational modes are parallel and serial. Figure 1 shows the timing diagram for each mode. In parallel
mode, the nP_LOAD input is initially LOW. The data on inputs
M0 through M8 and N0 through N2 is passed directly to the M
divider and N output divider. On the LOW-to-HIGH transition
of the nP_LOAD input, the data is latched and the M divider
remains loaded until the next LOW transition on nP_LOAD or
until a serial event occurs. As a result, the M and N bits can
be hardwired to set the M divider and N output divider to a
T1
T0
TEST Output
0
0
LOW
0
1
S_Data clocked into register
1
0
Output of M divider
1
1
CMOS Fout
SERIAL LOADING
S_CLOCK
T1
S_DATA
t
S_LOAD
S
t
T0
N2
N1
N0
M8
M7
M6
M5
M4
M3
M2
M1
M0
H
nP_LOAD
t
S
PARALLEL LOADING
M0:M8, N0:N2
M, N
nP_LOAD
t
S
t
H
S_LOAD
Time
FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS
8430BYI-71
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REV. A FEBRUARY 17, 2006
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8430BI-71
700MHZ, LOW JITTER, CRYSTAL INTERFACE/
LVCMOS-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
TABLE 1. PIN DESCRIPTIONS
Number
1, 2, 3,
28, 29, 30
31, 32
4
Name
M5, M6, M7,
M0, M1, M2,
M3, M4
M8
5, 6
N0, N1
Input
7
8, 16
N2
VEE
Input
Power
9
TEST
Output
10
VCC
FOUT1,
nFOUT1
VCCO
FOUT0,
nFOUT0
Power
Negative supply pins.
Test output which is ACTIVE in the serial mode of operation.
Output driven LOW in parallel mode. LVCMOS/LVTTL interface levels.
Core power supply pin.
Output
Differential output for the synthesizer. 3.3V LVPECL interface levels.
Power
Output supply pin.
Output
Differential output for the synthesizer. 3.3V LVPECL interface levels.
11, 12
13
14, 15
Type
Input
Input
Description
Pulldown M divider inputs. Data latched on LOW-to-HIGH transition of
nP_LOAD input. LVCMOS / LVTTL interface levels.
Pullup
Pulldown Determines output divider value as defined in Table 3C
Function Table. LVCMOS / LVTTL interface levels.
Pullup
Active High Master reset. When logic HIGH, the internal dividers are
reset causing the true outputs (FOUTx) to go low and the inver ted
17
MR
Input
Pulldown outputs (nFOUTx) to go high. When Logic LOW, the internal dividers
and the outputs are enabled. Asser tion of MR does not affect loaded
M, N, and T values. LVCMOS / LVTTL interface levels.
Clocks in serial data present at S_DATA input into the shift register
18
S_CLOCK
Input
Pulldown
on the rising edge of S_CLOCK. LVCMOS / LVTTL interface levels.
Shift register serial input. Data sampled on the rising edge of
19
S_DATA
Input
Pulldown
S_CLOCK. LVCMOS / LVTTL interface levels.
Controls transition of data from shift register into the dividers.
20
S_LOAD
Input
Pulldown
LVCMOS / LVTTL interface levels.
Power
Analog supply pin.
21
VCCA
Selects between the cr ystal oscillator or test clock as the
PLL reference source. Selects XTAL inputs when HIGH.
22
XTAL_SEL
Input
Pullup
Selects TEST_CLK when LOW. LVCMOS / LVTTL interface levels.
Pulldown Test clock input. LVCMOS interface levels.
23
TEST_CLK
Input
Cr ystal oscillator interface. XTAL_IN is the input.
24,
XTAL_OUT,
Input
XTAL_OUT is the output.
25
XTAL_IN
Parallel load input. Determines when data present at M8:M0 is
26
nP_LOAD
Input
Pulldown loaded into the M divider, and when data present at N2:N0 sets the
N output divider value. LVCMOS / LVTTL interface levels.
Determines whether synthesizer is in PLL or bypass mode.
27
VCO_SEL
Input
Pullup
LVCMOS / LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
CIN
Input Capacitance
Test Conditions
Minimum
Typical
4
Maximum
Units
pF
RPULLUP
Input Pullup Resistor
51
kΩ
RPULLDOWN
Input Pulldown Resistor
51
kΩ
8430BYI-71
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REV. A FEBRUARY 17, 2006
PRELIMINARY
Integrated
Circuit
Systems, Inc.
TABLE 3A. PARALLEL
AND
ICS8430BI-71
700MHZ, LOW JITTER, CRYSTAL INTERFACE/
LVCMOS-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
SERIAL MODE FUNCTION TABLE
Inputs
Conditions
MR
nP_LOAD
M
N
S_LOAD
S_CLOCK
S_DATA
H
X
X
X
X
X
X
Reset. Forces outputs LOW.
L
L
Data
Data
X
X
X
Data on M and N inputs passed directly to the M
divider and N output divider. TEST output forced LOW.
L
↑
Data
Data
L
X
X
L
H
X
X
L
↑
Data
L
H
X
X
↑
L
Data
L
H
X
X
↓
L
Data
L
H
X
X
L
X
X
H
↑
Data
L
H
X
X
NOTE: L = LOW
H = HIGH
X = Don't care
↑ = Rising edge transition
↓ = Falling edge transition
Data is latched into input registers and remains loaded
until next LOW transition or until a serial event occurs.
Serial input mode. Shift register is loaded with data on
S_DATA on each rising edge of S_CLOCK.
Contents of the shift register are passed to the
M divider and N output divider.
M divider and N output divider values are latched.
Parallel or serial input do not affect shift registers.
S_DATA passed directly to M divider as it is clocked.
TABLE 3B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE (NOTE 1)
125
256
M8
0
128
M7
0
64
M6
1
32
M5
1
16
M4
1
8
M3
1
4
M2
1
2
M1
0
1
M0
1
252
126
0
0
1
1
1
1
1
1
0
254
256
127
128
0
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
VCO Frequency
(MHz)
M Divide
250
•
•
696
698
700
NOTE 1: These M divide
16MHz.
•
•
•
•
348
1
349
1
350
1
values and the resulting
•
•
•
•
•
•
•
•
•
•
0
1
0
1
1
0
1
0
1
1
0
1
0
1
1
frequencies correspond to cr ystal or TEST_CLK
•
•
•
•
1
0
1
0
1
1
input frequency of
•
•
0
1
0
TABLE 3C. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE
Inputs
8430BYI-71
N Divider Value
FOUT0, nFOUT0 Output Frequency
(MHz)
Minimum
Maximum
125
350
N2
0
N1
0
N0
0
2
0
0
1
4
62.5
175
0
1
0
8
31.25
87.5
43.75
700
0
1
1
16
15.625
1
1
0
0
0
1
1
2
250
125
1
1
0
4
62.5
175
1
1
1
8
31.25
87.5
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4
350
REV. A FEBRUARY 17, 2006
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8430BI-71
700MHZ, LOW JITTER, CRYSTAL INTERFACE/
LVCMOS-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC
4.6V
Inputs, VI
-0.5V to VCC + 0.5V
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
Package Thermal Impedance, θJA
47.9°C/W (0 lfpm)
Storage Temperature, TSTG
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = -40°C TO 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
VCC
Core Supply Voltage
3.135
3.3
3.465
V
VCCA
Analog Supply Voltage
3.135
3.3
3.465
V
VCCO
Output Supply Voltage
3.135
3.3
3.465
V
IEE
Power Supply Current
140
mA
ICCA
Analog Supply Current
15
mA
Maximum
Units
2.35
VCC + 0.3
V
2
VCC + 0.3
V
-0.3
0.8
V
150
µA
VCC = VIN = 3.465V
5
µA
VCC = VIN = 3.465V
200
µA
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = -40°C TO 85°C
Symbol
VIH
VIL
IIH
Parameter
Test Conditions
TEST_CLK; NOTE 1
VCO_SEL, S_LOAD, S_DATA,
S_CLOCK, nP_LOAD, MR,
M0:M8, N0:N2, XTAL_SEL
Input Low Voltage
M0-M7, N0, N1, MR, nP_LOAD,
S_CLOCK, S_DATA, S_LOAD
Input
High Current M8, N2, XTAL_SEL, VCO_SEL
Input
High Voltage
TEST_CLK
IIL
Minimum
Input
Low Current
Typical
VCC = VIN = 3.465V
M0-M7, N0, N1, MR, nP_LOAD,
S_CLOCK, S_DATA, S_LOAD
VCC = 3.465V,
VIN = 0V
-5
µA
TEST_CLK, M8, N2,
XTAL_SEL, VCO_SEL
VCC = 3.465V,
VIN = 0V
-150
µA
2.6
V
Output
TEST; NOTE 2
High Voltage
Output
TEST; NOTE 2
VOL
Low Voltage
NOTE 1: Characterized with 1ns input edge rate.
NOTE 2: Outputs terminated with 50Ω to VCCO/2.
VOH
0.5
V
TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = -40°C TO 85°C
Symbol
Maximum
Units
VOH
Output High Voltage; NOTE 1
Parameter
Test Conditions
Minimum
VCC - 1.4
Typical
VCC - 0.9
V
VOL
Output Low Voltage; NOTE 1
VCC - 2.0
VCC - 1.7
V
1.0
V
VSWING
Peak-to-Peak Output Voltage Swing
0. 6
NOTE 1: Outputs terminated with 50Ω to VCCO - 2V. See "Parameter Measurement Information" section,
"3.3V Output Load Test Circuit" figure.
8430BYI-71
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REV. A FEBRUARY 17, 2006
PRELIMINARY
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ICS8430BI-71
700MHZ, LOW JITTER, CRYSTAL INTERFACE/
LVCMOS-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
TABLE 5. INPUT CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
fIN
Input Frequency
TEST_CLK; NOTE 1
XTAL_IN, XTAL_OUT;
NOTE 1
S_CLOCK
tr_input
Input Rise Time
TEST_CLK
Minimum
Typical
Maximum
Units
12
27
MHz
12
27
MHz
50
MHz
5
ns
NOTE 1: For the input crystal and reference frequency range, the M value must be set for the VCO to operate within the
250MHz to 700MHz range. Using the minimum input frequency of 12MHz, valid values of M are 167 ≤ M ≤ 466.
Using the maximum frequency of 27MHz, valid values of M are 75 ≤ M ≤ 207.
TABLE 6. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Mode of Oscillation
Typical Maximum
Units
Fundamental
Frequency
12
27
MHz
Equivalent Series Resistance (ESR)
50
Ω
Shunt Capacitance
7
pF
Drive Level
1
mW
TABLE 7. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = -40°C TO 85°C
Symbol
Parameter
FMAX
Output Frequency
Test Conditions
Minimum
Typical
Maximum
Units
700
MH z
fOUT > 87.5MHz
25
ps
fOUT < 87.5MHz
40
ps
t jit(cc)
Cycle-to-Cycle Jitter ; NOTE 1, 3
t jit(per)
Period Jitter, RMS; NOTE 1
9.5
ps
t sk(o)
Output Skew; NOTE 2, 3
15
ps
tR / tF
Output Rise/Fall Time
700
ps
20% to 80%
M, N to nP_LOAD
tS
tH
odc
Setup Time
Hold Time
200
5
S_DATA to S_CLOCK
5
ns
S_CLOCK to S_LOAD
5
ns
M, N to nP_LOAD
5
ns
S_DATA to S_CLOCK
5
ns
S_CLOCK to S_LOAD
5
ns
Output Duty Cycle
N≠1
48
52
%
N=1
45
55
%
1
ms
PLL Lock Time
tLOCK
See Parameter Measurement Information section.
NOTE 1: Jitter performance using XTAL inputs.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
8430BYI-71
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Systems, Inc.
ICS8430BI-71
700MHZ, LOW JITTER, CRYSTAL INTERFACE/
LVCMOS-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
2V
VCCA = 2V
nFOUTx
VCC,
VCCO
Qx
SCOPE
FOUTx
nFOUTy
LVPECL
FOUTy
nQx
VEE
tsk(o)
-1.3V ± 0.165V
OUTPUT SKEW
VOH
nFOUTx
VREF
FOUTx
➤
VOL
1σ contains 68.26% of all measurements
2σ contains 95.4% of all measurements
3σ contains 99.73% of all measurements
4σ contains 99.99366% of all measurements
6σ contains (100-1.973x10-7)% of all measurements
➤
tcycle n
➤
t jit(cc) = tcycle n –tcycle n+1
1000 Cycles
Histogram
Reference Point
tcycle n+1
➤
3.3V OUTPUT LOAD AC TEST CIRCUIT
Mean Period
(Trigger Edge)
(First edge after trigger)
PERIOD JITTER
CYCLE-TO-CYCLE JITTER
nFOUTx
80%
80%
FOUTx
VSW I N G
Clock
Outputs
t PW
20%
20%
tR
t
PERIOD
tF
odc =
t PW
x 100%
t PERIOD
OUTPUT RISE/FALL TIME
8430BYI-71
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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ICS8430BI-71
700MHZ, LOW JITTER, CRYSTAL INTERFACE/
LVCMOS-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS8430BI-71 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VCC, VCCA, and VCCO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 2 illustrates how
a 10Ω resistor along with a 10μF and a .01μF bypass
capacitor should be connected to each VCCA pin.
3.3V
VCC
.01μF
10Ω
VCCA
.01μF
10μF
FIGURE 2. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
A crystal can be characterized for either series or parallel mode
operation. The ICS8430BI-71 has a built-in crystal oscillator circuit.
This interface can accept either a series or parallel crystal without
additional components and generate frequencies with accuracy
suitable for most applications. Additional accuracy can be
achieved by adding two small capacitors C1 and C2 as shown in
Figure 3.
XTAL_OUT
C1
18p
X1
18pF Parallel Crystal
XTAL_IN
C2
22p
Figure 3. CRYSTAL INPUt INTERFACE
8430BYI-71
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ICS8430BI-71
700MHZ, LOW JITTER, CRYSTAL INTERFACE/
LVCMOS-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
OUTPUTS:
CRYSTAL INPUT:
For applications not requiring the use of the crystal oscillator
input, both XTAL_IN and XTAL_OUT can be left floating.
Though not required, but for additional protection, a 1kΩ
resistor can be tied from XTAL_IN to ground.
LVPECL OUTPUT
All unused LVPECL outputs can be left floating. We
recommend that there is no trace attached. Both sides of the
differential output pair should either be left floating or
terminated.
TEST_CLK INPUT:
For applications not requiring the use of the test clock, it can
be left floating. Though not required, but for additional
protection, a 1kΩ resistor can be tied from the TEST_CLK to
ground.
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
TERMINATION FOR LVPECL OUTPUTS
niques should be used to maximize operating frequency
and minimize signal distortion. There are a few simple termination schemes. Figures 4A and 4B show two different
layouts which are recommended only as guidelines. Other
suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee
compatibility across all printed circuit and clock component
process variations.
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
drive 50Ω transmission lines. Matched impedance tech-
3.3V
Zo = 50Ω
125Ω
FOUT
125Ω
FIN
Zo = 50Ω
Zo = 50Ω
FOUT
50Ω
RTT =
1
Z
((VOH + VOL) / (VCC – 2)) – 2 o
Zo = 50Ω
VCC - 2V
RTT
84Ω
FIGURE 4A. LVPECL OUTPUT TERMINATION
8430BYI-71
FIN
50Ω
84Ω
FIGURE 4B. LVPECL OUTPUT TERMINATION
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ICS8430BI-71
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LAYOUT GUIDELINE
The schematic of the ICS8430BI-71 layout example used in this
layout guideline is shown in Figure 5A. The ICS8430BI-71 recommended PCB board layout for this example is shown in Figure 5B. This layout example is used as a general guideline. The
layout in the actual system will depend on the selected component types, the density of the components, the density of
the traces, and the stack up of the P.C. board.
C1
C2
M5
M6
M7
M8
N0
N1
N2
VEE
VCC
ICS8430BI-71
X_OUT
TEST_CLK
XTAL_SEL
VCCA
S_LOAD
S_DATA
S_CLOCK
MR
TEST
VCC
FOUT1
nFOUT1
VCCO
FOUT0
nFOUT0
VEE
1
2
3
4
5
6
7
8
9
10
11
12
VCC
13
FOUT
14
FOUTN 15
16
U1
M4
M3
M2
M1
M0
VCO_SEL
nP_LOAD
X_IN
32
31
30
29
28
27
26
25
X1
VCC
24
23
22
21
20
19
18
17
R7
10
REF_IN
XTAL_SEL
VCCA
S_LOAD
S_DATA
S_CLOCK
C11
0.01u
C16
10u
VCC
R1
125
R3
125
Zo = 50 Ohm
IN+
C14
0.1u
TL1
C15
0.1u
+
Zo = 50 Ohm
IN-
TL2
R2
84
R4
84
FIGURE 5A. SCHEMATIC OF RECOMMENDED LAYOUT
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• The traces with 50Ω transmission lines TL1 and TL2
at FOUT and nFOUT should have equal delay and run
adjacent to each other. Avoid sharp angles on the clock
trace. Sharp angle turns cause the characteristic
impedance to change on the transmission lines.
The following component footprints are used in this layout
example: All the resistors and capacitors are size 0603.
POWER
AND
GROUNDING
Place the decoupling capacitors C14 and C15 as close as possible to the power pins. If space allows, placing the decoupling
capacitor at the component side is preferred. This can reduce
unwanted inductance between the decoupling capacitor and the
power pin generated by the via.
• Keep the clock trace on the same layer. Whenever possible, avoid any vias on the clock traces. Any via on the
trace can affect the trace characteristic impedance and
hence degrade signal quality.
• To prevent cross talk, avoid routing other signal traces in
parallel with the clock traces. If running parallel traces is
unavoidable, allow more space between the clock trace
and the other signal trace.
Maximize the pad size of the power (ground) at the decoupling
capacitor. Maximize the number of vias between power (ground)
and the pads. This can reduce the inductance between the power
(ground) plane and the component power (ground) pins.
• Make sure no other signal trace is routed between the
clock trace pair.
If VCCA shares the same power supply with VCC, insert the RC
filter R7, C11, and C16 in between. Place this RC filter as close
to the VCCA as possible.
CLOCK TRACES
AND
ICS8430BI-71
The matching termination resistors R1, R2, R3 and R4 should
be located as close to the receiver input pins as possible.
Other termination schemes can also be used but are not
shown in this example.
TERMINATION
The component placements, locations and orientations should be
arranged to achieve the best clock signal quality. Poor clock signal
quality can degrade the system performance or cause system failure. In the synchronous high-speed digital system, the clock signal
is less tolerable to poor signal quality than other signals. Any ringing on the rising or falling edge or excessive ring back can cause
system failure. The trace shape and the trace delay might be restricted by the available space on the board and the component
location. While routing the traces, the clock signal traces should be
routed first and should be locked prior to routing other signal traces.
CRYSTAL
The crystal X1 should be located as close as possible to the
pins 24 (XTAL_OUT) and 25 (XTAL_IN). The trace length between the X1 and U1 should be kept to a minimum to avoid
unwanted parasitic inductance and capacitance. Other signal
traces should not be routed near the crystal traces.
GND
C1
C2
VCC
X1
VIA
U1
PIN 1
C16
C11
VCCA
R7
Close to the input
pins of the
receiver
TL1N
C15
TL1
C14
TL1
R1
R2
TL1N
R3
R4
TL1, TL21N are 50 Ohm
traces and equal length
FIGURE 5B. PCB BOARD LAYOUT
8430BYI-71
FOR
ICS8430BI-71
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ICS8430BI-71
700MHZ, LOW JITTER, CRYSTAL INTERFACE/
LVCMOS-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8430BI-71.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8430BI-71 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 140mA = 485mW
Power (outputs)MAX = 30mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 30mW = 60mW
Total Power_MAX (3.465V, with all outputs switching) = 485mW + 60mW = 545mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1°C/W per Table 8 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.545W * 42.1°C/W = 108°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 8. THERMAL RESISTANCE θJA
FOR
32-PIN LQFP, FORCED CONVECTION
θJA by Velocity (Linear Feet per Minute)
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
500
67.8°C/W
47.9°C/W
55.9°C/W
42.1°C/W
50.1°C/W
39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
8430BYI-71
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3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 6.
VCCO
Q1
VOUT
RL
50
VCCO - 2V
FIGURE 6. LVPECL DRIVER CIRCUIT
TERMINATION
AND
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V - 2V.
CCO
•
For logic high, VOUT = V
OH_MAX
=V
CCO_MAX
– 0.9V
(VCCO_MAX - VOH_MAX) = 0.9V
•
For logic low, VOUT = V
OL_MAX
(V
CCO_MAX
-V
=V
CCO_MAX
– 1.7V
) = 1.7V
OL_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
– (V
CCO_MAX
- 2V))/R ] * (V
CCO_MAX
L
-V
OH_MAX
) = [(2V - (V
CCO_MAX
-V
OH_MAX
))/R ] * (V
CCO_MAX
L
-V
)=
OH_MAX
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW
Pd_L = [(V
OL_MAX
– (V
CCO_MAX
- 2V))/R ] * (V
L
CCO_MAX
-V
OL_MAX
) = [(2V - (V
CCO_MAX
-V
OL_MAX
))/R ] * (V
L
CCO_MAX
-V
)=
OL_MAX
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
8430BYI-71
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ICS8430BI-71
700MHZ, LOW JITTER, CRYSTAL INTERFACE/
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RELIABILITY INFORMATION
TABLE 9. θJAVS. AIR FLOW TABLE
FOR
32 LEAD LQFP
θJA by Velocity (Linear Feet per Minute)
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
500
67.8°C/W
47.9°C/W
55.9°C/W
42.1°C/W
50.1°C/W
39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8430BI-71 is: 3948
8430BYI-71
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PACKAGE OUTLINE - Y SUFFIX
FOR
ICS8430BI-71
700MHZ, LOW JITTER, CRYSTAL INTERFACE/
LVCMOS-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
32 LEAD LQFP
TABLE 10. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBA
SYMBOL
MINIMUM
NOMINAL
32
N
1.60
A
A1
MAXIMUM
0.05
0.15
A2
1.35
1.40
1.45
b
0.30
0.37
0.45
c
0.09
0.20
D
9.00 BASIC
D1
7.00 BASIC
D2
5.60
E
9.00 BASIC
E1
7.00 BASIC
E2
5.60
0.80 BASIC
e
L
0.45
θ
0°
0.60
0.75
7°
0.10
ccc
Reference Document: JEDEC Publication 95, MS-026
8430BYI-71
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ICS8430BI-71
700MHZ, LOW JITTER, CRYSTAL INTERFACE/
LVCMOS-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
TABLE 11. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
ICS8430BYI-71
ICS8430BYI-71
32 Lead LQFP
tray
-40°C to 85°C
ICS8430BYI-71T
ICS8430BYI-71
32 Lead LQFP
1000 tape & reel
-40°C to 85°C
ICS8430BYI-71LF
ICS8430BI-71L
32 Lead "Lead-Free" LQFP
tray
-40°C to 85°C
ICS8430BYI-71LFT
ICS8430BI-71L
32 Lead "Lead-Free" LQFP
1000 tape & reel
-40°C to 85°C
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements
are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
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