CA3078, CA3078A Data Sheet December 1998 File Number 535.5 2MHz, Micropower Operational Amplifier Features The CA3078 and CA3078A are high gain monolithic operational amplifiers which can deliver milliamperes of current yet only consume microwatts of standby power. Their operating points are externally adjustable and frequency compensation may be accomplished with one external capacitor. The CA3078 and CA3078A provide the designer with the opportunity to tailor the frequency response and improve the slew rate without sacrificing power. Operation with a single 1.5V battery is a practical reality with these devices. • Low Standby Power . . . . . . . . . . . . . . . As Low As 700nW • Wide Supply Voltage Range. . . . . . . . . . . ±0.75V to ±15V • High Peak Output Current . . . . . . . . . . . . . . . 6.5mA (Min) • Adjustable Quiescent Current • Output Short Circuit Protection Applications The CA3078A is a premium device having a supply voltage range of V± = 0.75V to V± = 15V. The CA3078 has the same lower supply voltage limit but the upper limit is V+ = +6V and V- = -6V. • Portable Electronics • Intrusion Alarms • Telemetry • Instrumentation • Medical Electronics Pinouts CA3078 (PDIP, SOIC) TOP VIEW Ordering Information PART NUMBER TEMP. (BRAND) RANGE (oC) COMP 1 PKG. NO. PACKAGE CA3078AE -55 to 125 8 Ld PDIP E8.3 CA3078AM (3078A) -55 to 125 8 Ld SOIC M8.15 CA3078AM96 (3078A) -55 to 125 8 Ld SOIC Tape and Reel M8.15 CA3078AT -55 to 125 8 Pin Metal Can T8.C 8 COMP INV. INPUT 2 NON-INV. 3 INPUT V- 4 7 V+ - + 6 OUTPUT 5 BIAS CA3078 (METAL CAN) TOP VIEW V+ COMP TAB 8 7 V+ 1 CA3078E 0 to 70 8 Ld PDIP E8.3 CA3078M (3078) 0 to 70 8 Ld SOIC M8.15 INV. 2 INPUT CA3078T 0 to 70 8 Pin Metal Can T8.C NON-INV. 3 INPUT RSET 6 OUTPUT + 5 BIAS 4 V- NOTE: Case Voltage = Floating Schematic Diagram 7 D2 D3 V+ 50Ω D5 Q10 Q12 Q18 Q6 Q4 NONINVERTING 3 Q1 Q3 INVERTING 2 BIAS 5 Q2 D1 Q7 D9 Q11 Q13 D8 Q15 Q8 D6 Q5 Q17 Q9 Q14 D7 D4 1 1 Q16 OUTPUT 6 COMPENSATION 50Ω V4 8 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 CA3078, CA3078A Absolute Maximum Ratings Thermal Information Supply Voltage (Between V+ and V- Terminal) CA3078 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14V CA3078A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36V Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V+ to VInput Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.1mA Output Short Circuit Duration (Note 1). . . . . . . . . . . . . No Limitation Thermal Resistance (Typical, Note 2) θJA (oC/W) θJC (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . 130 N/A SOIC Package . . . . . . . . . . . . . . . . . . . 165 N/A Metal Can Package . . . . . . . . . . . . . . . 175 100 Maximum Junction Temperature (Metal Can Package). . . . . . . .175oC Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range CA3078 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC CA3078A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Short circuit may be applied to ground or to either supply. 2. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications For Equipment Design CA3078 LIMITS CA3078A LIMITS RSET = 1MΩ RSET = 5.1MΩ TEST CONDITIONS TA = 0oC to 70oC TA = 25oC TA = -55oC to 125oC TA = 25oC PARAMETER V+ and V- RS (kΩ) RL (kΩ) MIN TYP MAX MIN MAX MIN TYP MAX MIN MAX UNITS VIO ±6V ≤10 - - 1.3 4.5 - 5 - 0.70 3.5 - 4.5 mV IIO - - - 6 32 - 40 - 0.50 2.5 - 5.0 nA IIB - - - 60 170 - 200 - 7 12 - 50 nA AOL - ≥10 88 92 - 86 - 92 100 - 90 - dB IQ - - - 100 130 - 150 - 20 25 - 45 µA PD - - - 1200 1560 - 1800 - 240 300 - 540 µW VOM - ≥10 ±5.1 ±5.3 - ±5 - ±5.1 ±5.3 - ±5 - V VICR ≤10 - - -5.5 to +5.8 - -5 to +5 - - -5.5 to +5.8 - -5 to +5 - V CMRR ≤10 - 80 110 - - - 80 115 - - - dB IOM+ or IOM- - - - 12 - 6.5 30 - 12 - 6.5 30 mA ∆VIO/∆V+ ≤10 - 76 93 - - - 76 105 - - - µV/V ∆VIO/∆V- ≤10 - 76 93 - - - 76 105 - - - µV/V RSET = 13MΩ ≤10 - - - - - - - 1.4 3.5 - 4.5 mV AOL - ≥10 - - - - - 92 100 - 88 - dB IQ - - - - - - - - 20 30 - 50 µA PD - - - - - - - - 600 750 - 1350 µW VOM - ≥10 - - - - - ±13.7 ±14.1 - ±13.5 - V CMRR ≤10 - - - - - - 80 106 - - - dB IIB - - - - - - - - 7 14 - 55 nA IIO - - - - - - - - 0.50 2.7 - 5.5 nA VIO ±15V 2 CA3078, CA3078A TA = 25oC, Typical Values Intended Only for Design Guidance Electrical Specifications CA3078 CA3078A PARAMETER V+ = +1.3V, V- = -1.3V RSET = 2MΩ V+ = +0.75V, V- = -0.75V RSET = 10MΩ V+ = +1.3V, V- = -1.3V RSET = 2MΩ V+ = +0.75V, V- = -0.75V RSET = 10MΩ UNITS VIO 1.3 1.5 0.7 0.9 mV IIO 1.7 0.5 0.3 0.054 nA IIB 9 1.3 3.7 0.45 nA AOL 80 60 84 65 dB IQ 10 1 10 1 µA PD 26 1.5 26 1.5 µW VOP-P 1.4 0.3 1.4 0.3 V VICR -0.8 to +1.1 -0.2 to +0.5 -0.8 to +1.1 -0.2 to +0.5 V CMRR 100 90 100 90 dB IOM± 12 0.5 12 0.5 mA ∆VIO/∆V± 20 50 20 50 µV/V TA = 25oC and VSUPPLY = ±6V, Typical Values Intended Only for Design Guidance Electrical Specifications CA3078 PARAMETER TEST CONDITIONS CA3078A RSET = 1MΩ RSET = 5.1MΩ RSET = 1MΩ UNITS ∆VIO/∆TA RS ≤10kΩ 6 5 6 µV/oC ∆IIO/∆TA RS ≤10kΩ 70 6.3 70 pA/oC AV = 100, C1 = 10pF 2 0.3 2 MHz 0.04 0.027 0.04 V/µs 1.5 0.5 1.5 V/µs 2.5 3 2.5 µs GBWP SR tR See Figures 23, 24 10% to 90% Rise Time RI - 0.87 7.4 1.7 MΩ RO - 0.8 1 0.8 kΩ eN(10Hz) RS = 0 25 40 - nV/√Hz iN(10Hz) RS = 1MΩ 1 0.25 - pA/√Hz 3 CA3078, CA3078A Test Circuits V+ V+ 100kΩ 100kΩ V+ 0V V+ 7 RSET 7 100kΩ 2 VIN R2 CA3078 CA3078A C2 3 + 6 8 VOUT 0V C2 V- VOUT 8 10kΩ CL 1 4 4 R1 OPTIONAL R2 - C2 COMP. 6 + 3 100kΩ CL 0V CA3078 CA3078A VIN 10kΩ 5 - R2 1 51kΩ 2 0V 5 - RSET VC1 R1 R1 OPTIONAL R2 - C2 COMP. FIGURE 1. TRANSIENT RESPONSE AND SLEW RATE, UNITY GAIN (INVERTING) TEST CIRCUIT R1 C1 FIGURE 2. SLEW RATE, UNITY GAIN (NON-INVERTING) TEST CIRCUIT INVERTING NON-INVERTING V+ INPUT RI 3 V+ RB INPUT + CA3078 CA3078A OUTPUT RI 2 - 6 CA3078 CA3078A RB 4 3 1M V- V+ 7 V+ - 2 1M RF 7 + 4 V- RF V- V- Value of RB required to have a null adjustment range of ±7.5mV RI RF V+ RB ≈ (RI + RF) 7.5 x 10-3 RI assuming RB > > OUTPUT 6 Value of RB required to have a null adjustment range of ±7.5mV RI V+ RB ≈ 7.5 x 10-3 assuming RB > > RI RI RF RI + RF FIGURE 3. OFFSET VOLTAGE NULL CIRCUITS 5.1MΩ 5.1MΩ RSET = 30MΩ 10MΩ 7 VP-P 510kΩ 2 1µF CA3078 CA3078A 7 1.5V “AA” CELL 5 - + 8 1 10MΩ 4 2 VP-P + 3 + 8 1 1µF FIGURE 4. INVERTING 20dB AMPLIFIER CIRCUIT 6 1µF 5µF 7pF 1.5V “AA” CELL 5 CA3078 CA3078A 510kΩ RL 4 + 6 + 3 RSET = 30MΩ 10MΩ 10MΩ 4 5µF RL 7pF FIGURE 5. NON-INVERTING 20dB AMPLIFIER CIRCUIT + - CA3078, CA3078A TABLE 1. UNITY GAIN SLEW RATE vs COMPENSATION - CA3078 AND CA3078A VSUPPLY = ±6V, Output Voltage (VO) = ±5V, Load Resistance (RL) = 10kΩ, Transient Response: 10% overshoot for an output voltage of 100mV, Ambient Temperature (TA) = 25oC UNITY GAIN (INVERTING) FIGURE 1 UNITY GAIN (NON-INVERTING) FIGURE 2 R1 C1 R2 C2 SLEW RATE R1 C1 R2 C2 SLEW RATE kΩ pF kΩ µF V/µs kΩ pF kΩ µF V/µs 0 750 ∞ 0 0.0085 0 1500 ∞ 0 0.0095 Resistor and Capacitor 3.5 350 ∞ 0 0.04 5.3 500 ∞ 0 0.024 Input ∞ 0 0.25 0.306 0.67 ∞ 0 0.311 0.45 0.67 Single Capacitor 0 300 ∞ 0 0.0095 0 800 ∞ 0 0.003 Resistor and Capacitor 14 100 ∞ 0 0.027 34 125 ∞ 0 0.02 Input ∞ 0 0.644 0.156 0.29 ∞ 0 0.77 0.4 0.4 COMPENSATION TECHNIQUE CA3078 - IQ = 100µA Single Capacitor CA3078A - IQ = 20µA Application Information Compensation Techniques The CA3078A and CA3078 can be phase compensated with one or two external components depending upon the closed loop gain, power consumption, and speed desired. The recommended compensation is a resistor in series with a capacitor connected from Terminal 1 to Terminal 8. Values of the resistor and capacitor required for compensation as a function of closed loop gain are shown in Figures 25 and 26. These curves represent the compensation necessary at quiescent currents of 100µA and 20µA, respectively, for a transient response with 10% overshoot. Figures 23 and 24 show the slew rates that can be obtained with the two different compensation techniques. Higher speeds can be achieved with input compensation, but this increases noise output. Compensation can also be accomplished with a single capacitor connected from Terminal 1 to Terminal 8, with speed being sacrificed for simplicity. Table 1 gives an indication of slew rates that can be obtained with various compensation techniques at quiescent currents of 100µA and 20µA. Single Supply Operation The CA3078A and CA3078 can operate from a single supply with a minimum total supply voltage of 1.5V. Figures 4 and 5 show the CA3078A or CA3078 in inverting and non-inverting 20dB amplifier configurations utilizing a 1.5V type “AA” cell for a supply. The total consumption for either circuit is approximately 675nW. The output voltage swing in this configuration is 300mVP-P with a 20kΩ load. Typical Performance Curves INPUT OFFSET CURRENT (nA) INPUT OFFSET VOLTAGE (mV) VS = ±6 TA = 25oC RS ≤ 10kΩ 3.0 2.4 1.8 CA3078 1.2 CA3078A VS = ±6 TA = 25oC 10 CA3078 1 CA3078A 0.1 0.6 0 1 10 100 1000 TOTAL QUIESCENT CURRENT (µA) FIGURE 6. INPUT OFFSET VOLTAGE vs TOTAL QUIESCENT CURRENT 5 0.01 1 10 1000 100 TOTAL QUIESCENT CURRENT (µA) 10000 FIGURE 7. INPUT OFFSET CURRENT vs TOTAL QUIESCENT CURRENT CA3078, CA3078A Typical Performance Curves (Continued) VS = ±6 TA = 25oC CA3078 CA3078A 1 10 100 1000 90 90 54 36 18 0 18 0 1 10 100 TOTAL QUIESCENT CURRENT (µA) 10 +3 -3 1 +1 -1 TA = 25oC 0.1 RSET CONNECTED BETWEEN TERMINAL 5 AND V+ 0.01 1000 MAXIMUM OUTPUT CURRENT (mA) BIAS SETTING RESISTANCE (MΩ) 100 +6 -6 10 1 0.1 0.01 TOTAL QUIESCENT CURRENT (µA) 0.001 1 TA = 25oC 120 RL = 50kΩ 1.0 10kΩ 5kΩ 2kΩ 1kΩ 500Ω 0.5 0 0.5 1.0 1.5 2.0 TOTAL QUIESCENT CURRENT (µA) FIGURE 12. OUTPUT VOLTAGE SWING vs TOTAL QUIESCENT CURRENT 6 10 100 1000 TOTAL QUIESCENT CURRENT (µA) FIGURE 11. MAXIMUM OUTPUT CURRENT vs TOTAL QUIESCENT CURRENT OPEN LOOP VOLTAGE GAIN (dB) OUTPUT VOLTAGE SWING (V) 10 1 VS = ±1.3V 0 VS = ±6 TO VS = ±15 TA = 25oC 0.1 100 FIGURE 10. BIAS SETTING RESISTANCE vs TOTAL QUIESCENT CURRENT 1.5 1000 FIGURE 9. OPEN LOOP VOLTAGE GAIN vs TOTAL QUIESCENT CURRENT 1000 100 54 36 10000 VS = ±15 72 10kΩ 2kΩ 72 TOTAL QUIESCENT CURRENT (µA) FIGURE 8. INPUT BIAS CURRENT vs TOTAL QUIESCENT CURRENT 108 RL = 1MΩ 108 0.1 1 126 126 VS = ±6 IQ = 100µA C1 = 0pF 100 C1 = 10pF C1 = 30pF 80 60 0 100 φ 100 300 1000 200 40 300 20 400 0 RL = 10kΩ, TA = 25oC C1- BETWEEN TERMINALS 1 AND 8 -20 0.1 1 101 102 103 104 105 106 FREQUENCY (Hz) FIGURE 13. OPEN LOOP VOLTAGE GAIN vs FREQUENCY PHASE ANGLE (DEGREES) 10 CA3078 OPEN LOOP VOLTAGE GAIN (dB) INPUT BIAS CURRENT (nA) 100 CA3078A TA = 25oC CA3078, CA3078A (Continued) 100 OPEN LOOP VOLTAGE GAIN (dB) IQ = 20µA TA = 25oC 10 PEAK OUTPUT VOLTAGE (V), COMMON MODE VOLTAGE RANGE (V) VICR VOM 1 VS = ±6 IQ = 20µA 120 100 C1 = 0pF 80 φ 60 300 20 400 0 RL = 10kΩ TA = 25oC -20 C1- BETWEEN TERMINALS 1 AND 8 0.1 +0.1 -0.1 +10 +100 -1 -10 -100 200 100 40 300 1000 1 101 0.1 +1 0 C1 = 10pF C1 = 30pF 100 PHASE ANGLE (DEGREES) Typical Performance Curves 102 103 104 105 106 FREQUENCY (Hz) FIGURE 15. OPEN LOOP VOLTAGE GAIN vs FREQUENCY SUPPLY VOLTS (V+, V-) -0.1 INPUT OFFSET VOLTAGE (mV) 1.75 -1 -VICR -VOM -10 VS = ±6 1.50 CA3078 IQ = 100µA 1.25 1.00 CA3078A IQ = 20µA 0.75 0.50 0.25 0 -75 -50 -25 0 25 50 75 100 125 TEMPERATURE (oC) 10 2.0 8 CA3078 IQ = 100µA 6 1.5 CA3078A IQ = 20µA 1.0 4 2 0.5 0 -75 -50 -25 0 25 50 TEMPERATURE (oC) 75 100 0 125 FIGURE 17. INPUT OFFSET CURRENT vs TEMPERATURE 7 15.0 CA3078A IQ = 20µA 12.5 10.0 100 7.5 75 5.0 50 CA3078 IQ = 100µA 25 2.5 0 -75 -50 -25 0 25 50 TEMPERATURE (oC) 75 100 0 125 FIGURE 18. INPUT BIAS CURRENT vs TEMPERATURE INPUT BIAS CURRENT (nA) - CA3078T 2.5 VS = ±6 INPUT BIAS CURRENT (nA) - CA3078AT VS = ±6 FIGURE 16. INPUT OFFSET VOLTAGE vs TEMPERATURE INPUT OFFSET CURRENT (nA) - CA3078T INPUT OFFSET CURRENT (nA) - CA3078AT FIGURE 14. OUTPUT AND COMMON MODE VOLTAGE vs SUPPLY VOLTAGE CA3078, CA3078A Typical Performance Curves VS = ±6 OPEN LOOP VOLTAGE GAIN (dB) 110 105 100 CA3078A IQ = 20µA 95 CA3078 IQ = 100µA 90 85 80 -75 -50 -25 0 25 50 75 100 125 VS = ±6 50 40 200 150 30 CA3078 0 -75 VS = ±6 TA = 25oC CA3078AT IQ = 20µA IQ = 100µA 10 0 101 102 103 104 FREQUENCY (Hz) FIGURE 21. EQUIVALENT INPUT NOISE VOLTAGE vs FREQUENCY 8 105 -50 -25 0 25 50 TEMPERATURE (oC) 75 100 0 125 FIGURE 20. TOTAL QUIESCENT CURRENT vs TEMPERATURE EQUIVALENT INPUT NOISE CURRENT (pA/√Hz) EQUIVALENT INPUT NOISE VOLTAGE (nV/√Hz) 100 100 50 10 TEMPERATURE (oC) FIGURE 19. OPEN LOOP VOLTAGE GAIN vs TEMPERATURE CA3078A 20 TOTAL QUIESCENT CURRENT (µA) - CA3078T TOTAL QUIESCENT CURRENT (µA) - CA3078AT (Continued) 1 VS = ±6 TA = 25oC CA3078AT IQ = 100µA 0.1 IQ = 20µA 0.01 101 102 103 104 FREQUENCY (Hz) FIGURE 22. EQUIVALENT INPUT NOISE CURRENT vs FREQUENCY 105 CA3078, CA3078A (Continued) 1.5 RESISTOR-CAPACITOR COMPENSATION (R1 - C1 BETWEEN 1.25 TERMINALS 1 AND 8) 0.6 1 SLEW RATE (V/µs) SLEW RATE (V/µs) Typical Performance Curves CAPACITOR COMPENSATION (BETWEEN TERMINALS 1 AND 8) 0.75 0.5 0.25 0 CAPACITOR COMPENSATION (BETWEEN TERMINALS 1 AND 8) 0.3 0.2 FIGURE 23. SLEW RATE vs CLOSED LOOP GAIN FOR IQ = 100mA - CA3078 CAPACITOR COMPENSATION (BETWEEN TERMINALS 1 AND 8) RESISTOR-CAPACITOR COMPENSATION (R1 - C1 BETWEEN TERMINALS 1 AND 8) 100 10 0 10 20 30 40 50 60 70 80 90 CLOSED LOOP NON-INVERTING VOLTAGE GAIN (dB) 6 19.1 29.7 40 50 60 70 80 CLOSED LOOP INVERTING VOLTAGE GAIN (dB) 90 Supply Volts: V+ = +6, V- = -6 Ambient Temperature (TA) = 25oC Load Impedance: RL = 10kΩ, CL = 100pF Feedback Resistance (RF) = 0.1MΩ Output Voltage (VOP-P) = 10V R1 determined for transient response with 10% overshoot on a 100mV output signal (R1 x C1 = 2.5 x 10-6) 1000 0 90 Supply Volts: V+ = +6, V- = -6 Quiescent Current (IQ) = 100µA PHASE COMPENSATION CAPACITOR (pF) 0.4 0 10 20 30 40 50 60 70 80 90 CLOSED LOOP NON-INVERTING VOLTAGE GAIN (dB) 6 19.1 29.7 40 50 60 70 80 CLOSED LOOP INVERTING VOLTAGE GAIN (dB) 1 0.5 0.1 10 20 30 40 50 60 70 80 90 CLOSED LOOP NON-INVERTING VOLTAGE GAIN (dB) 6 19.1 29.7 40 50 60 70 80 90 CLOSED LOOP INVERTING VOLTAGE GAIN (dB) Supply Volts: V+ = +6, V- = -6 Quiescent Current (IQ) = 100µA Ambient Temperature (TA) = 25oC Load Impedance: RL = 10kΩ, CL = 100pF Feedback Resistance (RF) = 0.1MΩ Output Voltage (VOP-P) = 100mV R1 determined for transient response with 10% overshoot on a 100mV output signal (R1 x C1 = 2.5 x 10-6) FIGURE 25. PHASE COMPENSATION CAPACITANCE vs CLOSED LOOP GAIN - CA3078 9 Quiescent Current (IQ) = 20µA Ambient Temperature (TA) = 25oC Load Impedance: RL = 10kΩ, CL = 100pF Feedback Resistance (RF) = 0.1MΩ Output Voltage (VOP-P) = 10V R1 determined for transient response with 10% overshoot on a 100mV output signal (R1 x C1 = 2 x 10-6) FIGURE 24. SLEW RATE vs CLOSED LOOP GAIN FOR IQ = 20mA - CA3078A PHASE COMPENSATION CAPACITOR (pF) 0 RESISTOR-CAPACITOR COMPENSATION (R1 - C1 BETWEEN TERMINALS 1 AND 8) CAPACITOR COMPENSATION (BETWEEN TERMINALS 1 AND 8) 1000 RESISTOR-CAPACITOR COMPENSATION (R1 - C1 BETWEEN TERMINALS 1 AND 8) 100 10 1 0 10 20 30 40 50 60 70 80 90 CLOSED LOOP NON-INVERTING VOLTAGE GAIN (dB) 6 19.1 29.7 40 50 60 70 80 90 CLOSED LOOP INVERTING VOLTAGE GAIN (dB) Supply Volts: V+ = +6, V- = -6 Quiescent Current (IQ) = 20µA Ambient Temperature (TA) = 25oC Load Impedance: RL = 10kΩ, CL = 100pF Feedback Resistance (RF) = 0.1MΩ Output Voltage (VOP-P) = 100mV R1 determined for transient response with 10% overshoot on a 100mV output signal (R1 x C1 = 2 x 10-6) FIGURE 26. PHASE COMPENSATION CAPACITANCE vs CLOSED LOOP GAIN - CA3078A CA3078, CA3078A Dual-In-Line Plastic Packages (PDIP) E8.3 (JEDEC MS-001-BA ISSUE D) N 8 LEAD DUAL-IN-LINE PLASTIC PACKAGE E1 INDEX AREA 1 2 3 INCHES N/2 -B- -AD E BASE PLANE A2 -C- SEATING PLANE A L D1 e B1 D1 eA A1 eC B 0.010 (0.25) M C L C A B S C eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). 10 MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A - 0.210 - 5.33 4 A1 0.015 - 0.39 - 4 A2 0.115 0.195 2.93 4.95 - B 0.014 0.022 0.356 0.558 - B1 0.045 0.070 1.15 1.77 8, 10 C 0.008 0.014 0.204 D 0.355 0.400 9.01 D1 0.005 - 0.13 - 5 E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 e 0.100 BSC eA 0.300 BSC eB - L 0.115 N 8 0.355 10.16 5 2.54 BSC - 7.62 BSC 6 0.430 - 0.150 2.93 8 10.92 7 3.81 4 9 Rev. 0 12/93 CA3078, CA3078A Small Outline Plastic Packages (SOIC) M8.15 (JEDEC MS-012-AA ISSUE C) 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE N INDEX AREA H 0.25(0.010) M B M E INCHES -B1 2 SYMBOL 3 L SEATING PLANE -A- h x 45o A D -C- e α A1 B 0.25(0.010) M C A M C B S NOTES: 11. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 12. Dimensioning and tolerancing per ANSI Y14.5M-1982. 13. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 14. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 15. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 16. “L” is the length of terminal for soldering to a substrate. 17. “N” is the number of terminal positions. 18. Terminal numbers are shown for reference only. 19. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 20. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 11 MAX MIN MAX NOTES A 0.0532 0.0688 1.35 1.75 - A1 0.0040 0.0098 0.10 0.25 - B 0.013 0.020 0.33 0.51 9 C 0.0075 0.0098 0.19 0.25 - D 0.1890 0.1968 4.80 5.00 3 E 0.1497 0.1574 3.80 4.00 4 e 0.10(0.004) MILLIMETERS MIN 0.050 BSC 1.27 BSC 0.2284 0.2440 h 0.0099 0.0196 0.25 0.50 5 L 0.016 0.050 0.40 1.27 6 8o 0o N α 5.80 8 0o 6.20 - H 8 - 7 8o Rev. 0 12/93 CA3078, CA3078A Metal Can Packages (Can) T8.C MIL-STD-1835 MACY1-X8 (A1) REFERENCE PLANE A 8 LEAD METAL CAN PACKAGE e1 L L2 L1 INCHES ØD2 4.19 4.70 - 0.019 0.41 0.48 1 Øb1 0.016 0.021 0.41 0.53 1 N Øb2 0.016 0.024 0.41 0.61 - ØD 0.335 0.375 8.51 9.40 - α ØD1 0.305 0.335 7.75 8.51 - ØD2 0.110 0.160 2.79 4.06 - k C L e BASE AND SEATING PLANE Q BASE METAL Øb1 NOTES 0.185 1 F MAX 0.016 k1 β MIN 0.165 Øe Øb1 Øb MAX A A 2 MIN Øb A ØD ØD1 MILLIMETERS SYMBOL LEAD FINISH Øb2 SECTION A-A NOTES: 1. (All leads) Øb applies between L1 and L2. Øb1 applies between L2 and 0.500 from the reference plane. Diameter is uncontrolled in L1 and beyond 0.500 from the reference plane. 0.200 BSC 5.08 BSC - e1 0.100 BSC F - 0.040 - 2.54 BSC 1.02 - k 0.027 0.034 0.69 0.86 - k1 0.027 0.045 0.69 1.14 2 12.70 19.05 1 1.27 1 L 0.500 0.750 L1 - 0.050 L2 0.250 - 6.35 - 1 Q 0.010 0.045 0.25 1.14 - α - β 45o BSC 45o BSC 45o BSC 45o BSC N 8 8 2. Measured from maximum diameter of the product. 3 3 4 Rev. 0 5/18/94 3. α is the basic spacing from the centerline of the tab to terminal 1 and β is the basic spacing of each lead or lead position (N -1 places) from α, looking at the bottom of the package. 4. N is the maximum number of terminal positions. 5. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 6. Controlling dimension: INCH. All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. 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