Micron N25Q032A13E1241F 32-mbit 3 v, multiple i/o, 4-kbyte subsector erase, xip enabled, serial flash memory with 108 mhz spi bus interface Datasheet

N25Q032
32-Mbit 3 V, multiple I/O, 4-Kbyte subsector erase,
XiP enabled, serial flash memory with 108 MHz SPI bus interface
Features
„ SPI-compatible serial bus interface
„ 108 MHz (maximum) clock frequency
„ 2.7 V to 3.6 V single supply voltage
„ Supports legacy SPI protocol and new Quad
I/O or Dual I/O SPI protocol
„ Quad/Dual I/O instructions resulting in an
equivalent clock frequency up to 432 MHz:
„ XIP mode for all three protocols
– Configurable via volatile or non-volatile
registers (enabling the memory to work in
XiP mode directly after power on)
„ Program/Erase suspend instructions
„ Continuous read of entire memory via single
instruction:
– Fast Read
– Quad or Dual Output Fast Read
– Quad or Dual I/O Fast Read
„ Electronic signature
– JEDEC standard two-byte signature
(BA16h)
– Additional 2 Extended Device ID (EDID)
bytes to identify device factory options
– Unique ID code (UID) with 14 bytes readonly, factory programmed
„ More than 100,000 program/erase cycles per
sector
„ More than 20 years data retention
„ Packages (All packages RoHS compliant):
– F4 = UFDFPN8 4 x 3 mm (MLP8)
– F6 = VDFPN8 6 x 5 mm (MLP8)
– F8 = VDFPN8 8 x 6 mm (MLP8)
– SC = SO8N (150 mils body width)
– SE = SO8W (208 mils body width)
– SF = SO16 (300 mils body width)
– 12 = TBGA24 6 x 8 mm
„ Flexible to fit application:
– Configurable number of dummy cycles
– Output buffer configurable
– Reset function available upon customer
request
„ 64-byte user-lockable, one-time programmable
(OTP) area
„ Erase capability
– Subsector (4-Kbyte) granularity on the
entire memory array.
– Sector (64-Kbyte) granularity
„ Write protections
– Software write protection applicable to
every 64-Kbyte sector (volatile lock bit)
– Hardware write protection: protected area
size defined by five non-volatile bits (BP0,
BP1, BP2, and TB bit)
– Additional smart protections available upon
customer request
July 2011
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
Rev 2
1/153
Contents
M25Q032 - 3 V
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2
Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.1
Serial data output (DQ1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2
Serial data input (DQ0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.3
Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.4
Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.5
Hold (HOLD) or Reset (Reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.6
Write protect/enhanced program supply voltage (W/VPP), DQ2 . . . . . . . 16
2.7
VCC supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.8
VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3
SPI Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4
SPI Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5
4.1
Extended SPI protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.2
Dual I/O SPI (DIO-SPI) protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.3
Quad SPI (QIO-SPI) protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.1
5.2
Extended SPI Protocol Operating features . . . . . . . . . . . . . . . . . . . . . . . 22
5.1.1
Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.1.2
Page programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.1.3
Dual input fast program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.1.4
Dual Input Extended Fast Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.1.5
Quad Input Fast Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1.6
Quad Input Extended Fast Program . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1.7
Subsector erase, sector erase and bulk erase . . . . . . . . . . . . . . . . . . . 23
5.1.8
Polling during a write, program or erase cycle . . . . . . . . . . . . . . . . . . . . 23
5.1.9
Active power and standby power modes . . . . . . . . . . . . . . . . . . . . . . . . 24
5.1.10
Hold (or Reset) condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Dual SPI (DIO-SPI) Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.2.1
Multiple I/O Read Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
M25Q032 - 3 V
5.3
6
Contents
5.2.2
Dual Command Fast reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.2.3
Page programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.2.4
Subsector Erase, Sector Erase and Bulk Erase . . . . . . . . . . . . . . . . . . 27
5.2.5
Polling during a Write, Program or Erase cycle . . . . . . . . . . . . . . . . . . . 27
5.2.6
Read and Modify registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.2.7
Active Power and Standby Power modes . . . . . . . . . . . . . . . . . . . . . . . 27
5.2.8
HOLD (or Reset) condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Quad SPI (QIO-SPI)Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.3.1
Multiple I/O Read Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.3.2
Quad Command Fast reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.3.3
QUAD Command Page programming . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.3.4
Subsector Erase, Sector Erase and Bulk Erase . . . . . . . . . . . . . . . . . . 29
5.3.5
Polling during a Write, Program or Erase cycle . . . . . . . . . . . . . . . . . . . 29
5.3.6
Read and Modify registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.3.7
Active Power and Standby Power modes . . . . . . . . . . . . . . . . . . . . . . . 30
5.3.8
HOLD (or Reset) condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.3.9
VPP pin Enhanced Supply Voltage feature . . . . . . . . . . . . . . . . . . . . . . 30
Volatile and Non Volatile Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.1
6.2
6.3
6.4
Legacy SPI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.1.1
WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.1.2
WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.1.3
Block Protect bits (BP2, BP1, BP0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.1.4
TB bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.1.5
SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Non Volatile Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.2.1
Dummy clock cycles NV configuration bits (NVCR bits from 15 to 12) . 36
6.2.2
XIP NV configuration bits (NVCR bits from 11 to 9) . . . . . . . . . . . . . . . . 37
6.2.3
Output Driver Strength NV configuration bits (NVCR bits from 8 to 6) . . 37
6.2.4
Hold (Reset) disable NV configuration bit (NVCR bit 4) . . . . . . . . . . . . 37
6.2.5
Quad Input NV configuration bit (NVCR bit 3) . . . . . . . . . . . . . . . . . . . . 37
6.2.6
Dual Input NV configuration bit (NVCR bit 2) . . . . . . . . . . . . . . . . . . . . . 37
Volatile Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.3.1
Dummy clock cycle: VCR bits 7:4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.3.2
XIP Volatile Configuration bits (VCR bit 3) . . . . . . . . . . . . . . . . . . . . . . . 39
6.3.3
Wrap: VCR bits 1:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Volatile Enhanced Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . 39
3/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
Contents
M25Q032 - 3 V
6.5
7
6.4.1
Quad Input Command VECR<7> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
6.4.2
Dual Input Command VECR<6> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6.4.3
Reset/Hold disable VECR<4> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6.4.4
Accelerator pin enable: QIO-SPI protocol / QIFP/QIEFP VECR<3> . . . 41
6.4.5
Output Driver Strength VECR<2:0> . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Flag Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6.5.1
P/E Controller Status bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6.5.2
Erase Suspend Status bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
6.5.3
Erase Status bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
6.5.4
Program Status bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
6.5.5
VPP Status bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
6.5.6
Program Suspend Status bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
6.5.7
Protection Status bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
7.1
SPI Protocol-related protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
7.2
Specific hardware and software protection . . . . . . . . . . . . . . . . . . . . . . . . 46
8
Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
9
Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
9.1
Extended SPI Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
9.1.1
Read Identification (RDID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
9.1.2
Read Data Bytes (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
9.1.3
Read Data Bytes at Higher Speed (FAST_READ) . . . . . . . . . . . . . . . . 57
9.1.4
Read Serial Flash Discovery Parameter . . . . . . . . . . . . . . . . . . . . . . . . 58
9.1.5
Dual Output Fast Read (DOFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
9.1.6
Dual I/O Fast Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
9.1.7
Quad Output Fast Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
9.1.8
Quad I/O Fast Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
9.1.9
Read OTP (ROTP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
9.1.10
Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
9.1.11
Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
9.1.12
Page Program (PP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
9.1.13
Dual Input Fast Program (DIFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
9.1.14
Dual Input Extended Fast Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
9.1.15
Quad Input Fast Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
4/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
M25Q032 - 3 V
9.2
Contents
9.1.16
Quad Input Extended Fast Program . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
9.1.17
Program OTP instruction (POTP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
9.1.18
Subsector Erase (SSE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
9.1.19
Sector Erase (SE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
9.1.20
Bulk Erase (BE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
9.1.21
Program/Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
9.1.22
Program/Erase Resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
9.1.23
Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
9.1.24
Write status register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
9.1.25
Read Lock Register (RDLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
9.1.26
Write to Lock Register (WRLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
9.1.27
Read Flag Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
9.1.28
Clear Flag Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
9.1.29
Read NV Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
9.1.30
Write NV Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
9.1.31
Read Volatile Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
9.1.32
Write Volatile Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
9.1.33
Read Volatile Enhanced Configuration Register . . . . . . . . . . . . . . . . . . 85
9.1.34
Write Volatile Enhanced Configuration Register . . . . . . . . . . . . . . . . . . 86
DIO-SPI Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
9.2.1
Multiple I/O Read Identification protocol . . . . . . . . . . . . . . . . . . . . . . . . 89
9.2.2
Read Serial Flash Discovery Parameter . . . . . . . . . . . . . . . . . . . . . . . . 89
9.2.3
Dual Command Fast Read (DCFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
9.2.4
Read OTP (ROTP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
9.2.5
Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
9.2.6
Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
9.2.7
Dual Command Page Program (DCPP) . . . . . . . . . . . . . . . . . . . . . . . . 92
9.2.8
Program OTP instruction (POTP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
9.2.9
Subsector Erase (SSE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
9.2.10
Sector Erase (SE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
9.2.11
Bulk Erase (BE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
9.2.12
Program/Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
9.2.13
Program/Erase Resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
9.2.14
Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
9.2.15
Write status register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
9.2.16
Read Lock Register (RDLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
9.2.17
Write to Lock Register (WRLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
5/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
Contents
M25Q032 - 3 V
9.3
10
9.2.18
Read Flag Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
9.2.19
Clear Flag Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
9.2.20
Read NV Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
9.2.21
Write NV Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
9.2.22
Read Volatile Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . 100
9.2.23
Write Volatile Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . 101
9.2.24
Read Volatile Enhanced Configuration Register . . . . . . . . . . . . . . . . . 101
9.2.25
Write Volatile Enhanced Configuration Register . . . . . . . . . . . . . . . . . 102
QIO-SPI Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
9.3.1
Multiple I/O Read Identification (MIORDID) . . . . . . . . . . . . . . . . . . . . . 105
9.3.2
Read Serial Flash Discovery Parameter . . . . . . . . . . . . . . . . . . . . . . . 106
9.3.3
Quad Command Fast Read (QCFR) . . . . . . . . . . . . . . . . . . . . . . . . . . 106
9.3.4
Read OTP (ROTP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
9.3.5
Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
9.3.6
Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
9.3.7
Quad Command Page Program (QCPP) . . . . . . . . . . . . . . . . . . . . . . . 110
9.3.8
Program OTP instruction (POTP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
9.3.9
Subsector Erase (SSE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
9.3.10
Sector Erase (SE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
9.3.11
Bulk Erase (BE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
9.3.12
Program/Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
9.3.13
Program/Erase Resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
9.3.14
Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
9.3.15
Write status register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
9.3.16
Read Lock Register (RDLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
9.3.17
Write to Lock Register (WRLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
9.3.18
Read Flag Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
9.3.19
Clear Flag Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
9.3.20
Read NV Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
9.3.21
Write NV Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
9.3.22
Read Volatile Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . 122
9.3.23
Write Volatile Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . 123
9.3.24
Read Volatile Enhanced Configuration Register . . . . . . . . . . . . . . . . . 124
9.3.25
Write Volatile Enhanced Configuration Register . . . . . . . . . . . . . . . . . 125
XIP Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
10.1
Enter XIP mode by setting the Non Volatile Configuration Register . . . . 128
6/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
M25Q032 - 3 V
11
Contents
10.2
Enter XIP mode by setting the Volatile Configuration Register . . . . . . . 129
10.3
XIP mode hold and exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
10.4
XIP Memory reset after a controller reset . . . . . . . . . . . . . . . . . . . . . . . . 131
Power-up and power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
11.1
Rescue sequence in case of power loss during WRNVCR . . . . . . . . . . 133
12
Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
13
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
14
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
15
Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
16
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
17
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
7/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
List of tables
M25Q032 - 3 V
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Status register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Non-Volatile Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Maximum operative frequency by dummy clock cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Volatile Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Sequence of Bytes Read during Wrap Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Volatile Enhanced Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Flag Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Software protection truth table (Sectors 0 to 63, 64 Kbyte granularity) . . . . . . . . . . . . . . . 46
Protected area sizes, Upper (TB bit = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Protected area sizes, Lower (TB bit = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Instruction set: extended SPI protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Read Identification data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Extended Device ID table (first byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Suspend Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Operations Allowed / Disallowed During Device States . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Lock Register out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Lock Register in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Instruction set: DIO-SPI protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Instruction set: QIO-SPI protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
NVCR XIP bits setting example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
VCR XIP bits setting example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Power-up timing and VWI threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Reset Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
UFDFPN8 (MLP8) Ultra Thin Dual Flat Package, No lead, 4×3 mm Dimensions . . . . . . 143
VDFPN8 (MLP8) Very Thin Dual Flat Package No leads 6×5 mm Dimensions . . . . . . . . 144
VDFPN8 (MLP8) Very Thin Dual Flat Package 8 leads 8×6x1 mm Dimensions . . . . . . . 145
SO8 Wide – 8 Lead Plastic Small Outline, 208 mils Body Width, Dimensions . . . . . . . . . 146
SO16 Wide – 16 Lead Plastic Small Outline, 300 mils Body Width, Dimensions . . . . . . . 147
TBGA 6x8 mm 24-Ball, Dimensions, Symbols A to eE. . . . . . . . . . . . . . . . . . . . . . . . . . . 149
TBGA 6x8 mm 24-Ball, Dimensions, Symbols FD to fff . . . . . . . . . . . . . . . . . . . . . . . . . . 149
SO8N – 8 Lead Plastic Small Outline, 150 mils Body Width, Dimensions . . . . . . . . . . . . 149
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Valid Order Information Line Items . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
8/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
M25Q032 - 3 V
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
Figure 47.
Figure 48.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
SO8N, SO8W and MLP8 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
SO16 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
BGA connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Bus master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Hold condition activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Non Volatile and Volatile configuration Register Scheme . . . . . . . . . . . . . . . . . . . . . . . . . 32
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Read identification instruction and data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Read Data Bytes instruction and data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Read Data Bytes at Higher Speed instruction and data-out sequence . . . . . . . . . . . . . . . 58
Read Serial Flash Discovery Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Dual Output Fast Read instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Dual I/O Fast Read instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Quad Output Fast Read instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Quad Input/ Output Fast Read instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Read OTP instruction and data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Write Enable instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Write Disable instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Page Program Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Dual Input Fast Program Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Dual Input Extended Fast Program instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . 69
Quad Input Fast Program instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Quad Input Extended Fast Program instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . 71
Program OTP instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
How to permanently lock the OTP bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Subsector Erase instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Sector Erase instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Bulk Erase instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Read Status Register instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Write Status Register instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Read Lock Register instruction and data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Write to Lock Register instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Read Flag Status Register instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Clear Flag Status Register instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Read NV Configuration Register instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Write NV Configuration Register instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Read Volatile Configuration Register instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . 84
Write Volatile Configuration Register instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . 85
Read Volatile Enhanced Configuration Register instruction sequence. . . . . . . . . . . . . . . . 86
Write Volatile Enhanced Configuration Register instruction sequence. . . . . . . . . . . . . . . . 87
Multiple I/O Read Identification instruction and data-out sequence DIO-SPI . . . . . . . . . . . 89
Dual Read Serial Flash Discovery Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Dual Command Fast Read instruction and data-out sequence DIO-SPI . . . . . . . . . . . . . . 90
Read OTP instruction and data-out sequence DIO-SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Write Enable instruction sequence DIO-SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Write Disable instruction sequence DIO-SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
9/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
List of figures
Figure 49.
Figure 50.
Figure 51.
Figure 52.
Figure 53.
Figure 54.
Figure 55.
Figure 56.
Figure 57.
Figure 58.
Figure 59.
Figure 60.
Figure 61.
Figure 62.
Figure 63.
Figure 64.
Figure 65.
Figure 66.
Figure 67.
Figure 68.
Figure 69.
Figure 70.
Figure 71.
Figure 72.
Figure 73.
Figure 74.
Figure 75.
Figure 76.
Figure 77.
Figure 78.
Figure 79.
Figure 80.
Figure 81.
Figure 82.
Figure 83.
Figure 84.
Figure 85.
Figure 86.
Figure 87.
Figure 88.
Figure 89.
Figure 90.
Figure 91.
Figure 92.
Figure 93.
Figure 94.
Figure 95.
Figure 96.
Figure 97.
Figure 98.
Figure 99.
Figure 100.
M25Q032 - 3 V
Dual Command Page Program instruction sequence DIO-SPI, 02h . . . . . . . . . . . . . . . . . 92
Dual Command Page Program instruction sequence DIO-SPI, A2h . . . . . . . . . . . . . . . . . 93
Dual Command Page Program instruction sequence DIO-SPI, D2h . . . . . . . . . . . . . . . . . 93
Program OTP instruction sequence DIO-SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Subsector Erase instruction sequence DIO-SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Sector Erase instruction sequence DIO-SPI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Bulk Erase instruction sequence DIO-SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Program/Erase Suspend instruction sequence DIO-SPI . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Program/Erase Resume instruction sequence DIO-SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Read Status Register instruction sequence DIO-SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Write Status Register instruction sequence DIO-SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Read Lock Register instruction and data-out sequence DIO-SPI. . . . . . . . . . . . . . . . . . . . 98
Write to Lock Register instruction sequence DIO-SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Read Flag Status Register instruction sequence DIO-SPI . . . . . . . . . . . . . . . . . . . . . . . . . 99
Clear Flag Status Register instruction sequence DIO-SPI . . . . . . . . . . . . . . . . . . . . . . . . . 99
Read NV Configuration Register instruction sequence DIO-SPI . . . . . . . . . . . . . . . . . . . 100
Write NV Configuration Register instruction sequence DIO-SPI . . . . . . . . . . . . . . . . . . . 100
Read Volatile Configuration Register instruction sequence DIO-SPI . . . . . . . . . . . . . . . . 101
Write Volatile Configuration Register instruction sequence DIO-SPI . . . . . . . . . . . . . . . . 101
Read Volatile Enhanced Configuration Register instruction sequence DIO-SPI . . . . . . . 102
Write Volatile Enhanced Configuration Register instruction sequence DIO-SPI . . . . . . . 102
Multiple I/O Read Identification instruction and data-out sequence QIO-SPI . . . . . . . . . . 105
Quad Read Serial Flash Discovery Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Quad Command Fast Read instruction and data-out sequence QIO-SPI, 0Bh . . . . . . . . 107
Quad Command Fast Read instruction and data-out sequence QIO-SPI, 6Bh . . . . . . . . 107
Quad Command Fast Read instruction and data-out sequence QIO-SPI, EBh . . . . . . . . 108
Read OTP instruction and data-out sequence QIO-SPI . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Write Enable instruction sequence QIO-SPI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Write Disable instruction sequence QIO-SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Quad Command Page Program instruction sequence QIO-SPI, 02h. . . . . . . . . . . . . . . . 111
Quad Command Page Program instruction sequence QIO-SPI, 12h. . . . . . . . . . . . . . . . 111
Quad Command Page Program instruction sequence QIO-SPI, 32h. . . . . . . . . . . . . . . . 112
Program OTP instruction sequence QIO-SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Subsector Erase instruction sequence QIO-SPI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Sector Erase instruction sequence QIO-SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Bulk Erase instruction sequence QIO-SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Program/Erase Suspend instruction sequence QIO-SPI . . . . . . . . . . . . . . . . . . . . . . . . . 115
Program/Erase Resume instruction sequence QIO-SPI. . . . . . . . . . . . . . . . . . . . . . . . . . 116
Read Status Register instruction sequence QIO-SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Write Status Register instruction sequence QIO-SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Read Lock Register instruction and data-out sequence QIO-SPI . . . . . . . . . . . . . . . . . . 118
Write to Lock Register instruction sequence QIO-SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Read Flag Status Register instruction sequence QIO-SPI . . . . . . . . . . . . . . . . . . . . . . . . 120
Clear Flag Status Register instruction sequence QIO-SPI . . . . . . . . . . . . . . . . . . . . . . . . 120
Read NV Configuration Register instruction sequence QIO-SPI . . . . . . . . . . . . . . . . . . . 121
Write NV Configuration Register instruction sequence QIO-SPI . . . . . . . . . . . . . . . . . . . 122
Read Volatile Configuration Register instruction sequence QIO-SPI . . . . . . . . . . . . . . . . 123
Write Volatile Configuration Register instruction sequence QIO-SPI . . . . . . . . . . . . . . . . 124
Read Volatile Enhanced Configuration Register instruction sequence QIO-SPI . . . . . . . 124
Write Volatile Enhanced Configuration Register instruction sequence QIO-SPI . . . . . . . 125
N25Q032 Read functionality Flow Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
XIP mode directly after power on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
10/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
M25Q032 - 3 V
Figure 101.
Figure 102.
Figure 103.
Figure 104.
Figure 105.
Figure 106.
Figure 107.
Figure 108.
Figure 109.
Figure 110.
Figure 111.
Figure 112.
Figure 113.
Figure 114.
Figure 115.
Figure 116.
List of figures
XiP: enter by VCR 2/2 (QIOFR in normal SPI protocol example) . . . . . . . . . . . . . . . . . . . 130
Power-up timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Reset AC waveforms while a program or erase cycle is in progress . . . . . . . . . . . . . . . . 139
Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Write protect setup and hold timing during WRSR when SRWD=1 . . . . . . . . . . . . . . . . . 141
Hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
VPPH timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
UFDFPN8 (MLP8) Ultra Thin Dual Flat Package, No lead, 4×3 mm Drawing . . . . . . . . . 143
VDFPN8 (MLP8) Very Thin Pitch Dual Flat Package, No lead, 6×5 mm Drawing . . . . . . 144
VDFPN8 (MLP8) Very Thin Dual Flat Package 8 leads, 8×6x1 mm Drawing . . . . . . . . . 145
SO8W – 8 Lead Plastic Small Outline, 208 mils Body Width, Drawing . . . . . . . . . . . . . . 146
SO16 Wide – 16 Lead Plastic Small Outline, 300 mils Body Width, Drawing. . . . . . . . . . 147
TBGA - 6 x 8 mm, 24-Ball, Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
SO8N – 8 Lead Plastic Small Outline, 150 mils Body Width, Drawing . . . . . . . . . . . . . . . 149
11/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
Description
1
N25Q032 - 3 V
Description
The N25Q032 is a 32 Mbit (4Mb x 8) serial Flash memory, with advanced write protection
mechanisms. It is accessed by a high speed SPI-compatible bus and features the possibility
to work in XIP (“eXecution in Place”) mode.
The N25Q032 supports innovative, high-performance quad/dual I/O instructions, these new
instructions allow to double or quadruple the transfer bandwidth for read and program
operations.
Furthermore the memory can be operated with 3 different protocols:
z
Standard SPI (Extended SPI protocol)
z
Dual I/O SPI
z
Quad I/O SPI
The Standard SPI protocol is enriched by the new quad and dual instructions (Extended SPI
protocol). For Dual I/O SPI (DIO-SPI) all the instructions codes, the addresses and the data
are always transmitted across two data lines. For Quad I/O SPI (QIO-SPI) the instructions
codes, the addresses and the data are always transmitted across four data lines thus
enabling a tremendous improvement in both random access time and data throughput.
The memory can work in “XIP mode”, that means the device only requires the addresses
and not the instructions to output the data. This mode dramatically reduces random access
time thus enabling many applications requiring fast code execution without shadowing the
memory content on a RAM.
The XIP mode can be used with QIO-SPI, DIO-SPI, or Extended SPI protocol, and can be
entered and exited using different dedicated instructions to allow maximum flexibility: for
applications required to enter in XIP mode right after power up of the device, this can be set
as default mode by using dedicated Non Volatile Register (NVR) bits.
Another feature is the ability to pause and resume program and erase cycles by using
dedicated Program/Erase Suspend and Resume instructions.
The N25Q032 memory offers the following additional features to be configured by using the
Non Volatile Configuration Register (NVCR) for default /Non-Volatile settings or by using the
Volatile and Volatile Enhanced Configuration Registers for Volatile settings:
z
the number of dummy cycles for fast read instructions (single, dual and, quad I/O)
according to the operating frequency
z
the output buffer impedance
z
the type of SPI protocol (extended SPI, DIO-SPI or QIO-SPI)
z
the required XIP mode
z
the Hold (Reset) functionality enabling/disabling
z
the Wrap mode enabling/disabling.
The memory is organized as 64 (64-Kbyte) main sectors that are further divided into 16
subsectors each (1024 subsectors in total). The memory can be erased a 4-KByte
subsector at a time, a 64-KByte sector at a time, or as a whole.
The memory can be write protected by software using a mix of volatile and non-volatile
protection features, depending on the application needs. The protection granularity is of 64Kbyte (sector granularity) for volatile protections.
12/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
N25Q032 - 3 V
Description
The N25Q032 has 64 one-time-programmable bytes (OTP bytes) that can be read and
programmed using two dedicated instructions, Read OTP (ROTP) and Program OTP
(POTP), respectively. These 64 bytes can be permanently locked by a particular Program
OTP (POTP) sequence. Once they have been locked, they become read-only and this state
cannot be reversed.
Many different N25Q032 configurations are available, please refer to the ordering scheme
page for the possibilities. Additional features are available as security options (The Security
features are described in a dedicated Application Note). Please contact your nearest
Numonyx Sales office for more information.
Figure 1.
Logic diagram
VCC
DQ0
DQ1
C
S
W/VPP/DQ2
HOLD/DQ3
VSS
Logic_Diagram_x25x
Note:
Reset functionality is available in devices with a dedicated part number. See Section 16:
Ordering information.
Table 1.
Signal names
Signal
Description
I/O
C
Serial Clock
Input
DQ0
Serial Data input
I/O(1)
DQ1
Serial Data output
I/O(2)
S
Chip Select
Input
W/VPP/DQ2
Write Protect/Enhanced Program supply voltage/additional data I/O
I/O(3)
HOLD/DQ3(4)
Hold (Reset function available upon customer request)/additional data I/O
I/O(3)
VCC
Supply voltage
–
VSS
Ground
–
1. Provides dual and quad I/O for Extended SPI protocol instructions, dual I/O for Dual I/O SPI protocol instructions, and
quad I/O for Quad I/O SPI protocol instructions.
2. Provides dual and quad instruction input for Extended SPI protocol, dual instruction input for Dual I/O SPI protocol, and
quad instruction input for Quad I/O SPI protocol.
3. Provides quad I/O for Extended SPI protocol instructions, and quad I/O for Quad I/O SPI protocol instructions.
4. Reset functionality available with a dedicated part number. See Section 16: Ordering information.
Note:
There is an exposed central pad on the underside of the MLP8 package. This is pulled,
internally, to VSS, and must not be allowed to be connected to any other voltage or signal
line on the PCB.
13/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
Description
N25Q032 - 3 V
Figure 2.
SO8N, SO8W and MLP8 connections
S
DQ1
W/VPP/DQ2
VSS
VCC
HOLD/DQ3
8
7
6
5
1
2
3
4
C
DQ0
1. Reset functionality available in devices with a dedicated part number. See Section 16: Ordering
information.
Figure 3.
SO16 connections
HOLD/DQ3
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
VCC
DU
DU
DU
DU
S
DQ1
C
DQ0
DU
DU
DU
DU
VSS
W/VPP/DQ2
1. DU = don’t use.
2. See Package mechanical section for package dimensions, and how to identify pin-1.
3. Reset functionality available in devices with a dedicated part number. See Section 16: Ordering
information.
Figure 4.
BGA connections
1
A
B
2
3
4
5
NC
NC
NC
NC
C
VSS
VCC
NC
NC
S
C
NC
NC
DQ1
D
NC
E
NC
W/VPP/DQ2
NC
NC
DQ0 HOLD/DQ3
NC
NC
NC
NC
1. NC = No Connect.
2. See Figure 115.: TBGA - 6 x 8 mm, 24-Ball, Drawing.
14/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
N25Q032 - 3 V
2
Signal descriptions
2.1
Serial data output (DQ1)
Signal descriptions
This output signal is used to transfer data serially out of the device. Data are shifted out on
the falling edge of Serial Clock (C). When used as an Input, It is latched on the rising edge
of the Serial Clock (C).
In the Extended SPI protocol, during the Quad and Dual Input Fast Program (QIFP, DIFP)
instructions and during the Quad and Dual Input Extended Fast Program (QIEFP, DIEFP)
instructions, pin DQ1 is used also as an input.
In the Dual I/O SPI protocol (DIO-SPI) the DQ1 pin always acts as an input/output.
In the Quad I/O SPI protocol (QIO-SPI) the DQ1 pin always acts as an input/output, with the
exception of the Program or Erase cycle performed with the Enhanced Program Supply
Voltage (VPP). In this case the device temporarily goes in Extended SPI protocol. The
protocol then becomes QIO-SPI as soon as the VPP pin voltage goes low.
2.2
Serial data input (DQ0)
This input signal is used to transfer data serially into the device. It receives instructions,
addresses, and the data to be programmed. Values are latched on the rising edge of Serial
Clock (C). Data are shifted out on the falling edge of the Serial Clock (C).
In the Extended SPI protocol, during the Quad and Dual Output Fast Read (QOFR, DOFR)
and the Quad and Dual Input/Output Fast Read (QIOFR, DIOFR) instructions, pin DQ0 is
also used as an input/output.
In the DIO-SPI protocol the DQ0 pin always acts as an input/output.
In the QIO-SPI protocol, the DQ0 pin always acts as an input/output, with the exception of
the Program or Erase cycle performed with the enhanced program supply voltage (VPP). In
this case the device temporarily goes in Extended SPI protocol. Then, the protocol returns
to QIO-SPI as soon as the VPP pin voltage goes low.
2.3
Serial Clock (C)
This input signal provides the timing for the serial interface. Instructions, addresses, or data
present at serial data input (DQ0) are latched on the rising edge of Serial Clock (C). Data
are shifted out on the falling edge of the Serial Clock (C).
2.4
Chip Select (S)
When this input signal is high, the device is deselected and serial data output (DQ1) is at
high impedance. Unless an internal program, erase or write status register cycle is in
progress, the device will be in the standby power mode (this is not the deep power-down
mode). Driving Chip Select (S) low enables the device, placing it in the active power mode.
After power-up, a falling edge on Chip Select (S) is required prior to the start of any
instruction.
15/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
Signal descriptions
2.5
N25Q032 - 3 V
Hold (HOLD) or Reset (Reset)
The Hold (HOLD) signal is used to pause any serial communications with the device without
deselecting the device.
Reset functionality is present instead of Hold in devices with a dedicated part number. See
Section 16: Ordering information.
During Hold condition, the Serial Data output (DQ1) is in high impedance, and Serial Data
input (DQ0) and Serial Clock (C) are Don't Care.
To start the Hold condition, the device must be selected, with Chip Select (S) driven Low.
For devices featuring Reset instead of Hold functionality, the Reset (Reset) input provides a
hardware reset for the memory.
When Reset (Reset) is driven High, the memory is in the normal operating mode. When
Reset (Reset) is driven Low, the memory will enter the Reset mode. In this mode, the output
is high impedance.
Driving Reset (Reset) Low while an internal operation is in progress will affect this operation
(write, program or erase cycle) and data may be lost.
In the Extended SPI protocol, during the QOFR, QIOFR, QIFP and the Quad Extended Fast
Program (QIEFP) instructions, the Hold (Reset) / DQ3 is used as an input/output (DQ3
functionality).
In QIO-SPI, the Hold (Reset) / DQ3 pin acts as an I/O (DQ3 functionality), and the HOLD
(Reset) functionality disabled when the device is selected. When the device is deselected (S
signal is high), in parts with Reset functionality, it is possible to reset the device unless this
functionality is not disabled by mean of dedicated registers bits.
The HOLD (Reset) functionality can be disabled using bit 3 of the NVCR or bit 4 of the
VECR.
2.6
Write protect/enhanced program supply voltage (W/VPP),
DQ2
W/VPP/DQ2 can be used as:
z
A protection control input.
z
A power supply pin.
z
I/O in Extended SPI protocol quad instructions and in QIO-SPI protocol instructions.
When the device is operated in Extended SPI protocol with single or dual instructions, the
two functions W or VPP are selected by the voltage range applied to the pin. If the W/VPP
input is kept in a low voltage range (0 V to VCC) the pin is seen as a control input. This input
signal is used to freeze the size of the area of memory that is protected against program or
erase instructions (as specified by the values in the BP[0:3] bits of the Status Register. (See
Table 2.: Status register format).
If VPP is in the range of VPPH, it acts as an additional power supply during the Program or
Erase cycles (See Table 27.: Operating conditions). In this case VPP must be stable until
the Program or Erase algorithm is completed.
During the Extended SPI protocol, the QOFR and QIOFR instructions, and the QIO-SPI
protocol instructions, the pin W/VPP/DQ2 is used as an input/output (DQ2 functionality).
16/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
N25Q032 - 3 V
Signal descriptions
Using the Extended SPI protocol the QIFP, QIEFP and the QIO-SPI Program/Erase
instructions, it is still possible to use the VPP additional power supply to speed up internal
operations. However, to enable this possibility it is necessary to set bit 3 of the Volatile
Enhanced Configuration Register to 0.
In this case the W/VPP/DQ2 pin is used as an I/O pin until the end of the instruction
sequence. After the last input data is shifted in, the application should apply VPP voltage to
W/VPP/DQ2 within 200 ms to speed up the internal operations. If the VPP voltage is not
applied within 200 ms the Program/Erase operations start with standard speed.
The default value of the VECR bit 3 is 1, and the VPP functionality for Quad I/O modify
instruction is disabled.
2.7
VCC supply voltage
VCC is the supply voltage.
2.8
VSS ground
VSS is the reference for the VCC supply voltage.
17/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
SPI Modes
3
N25Q032 - 3 V
SPI Modes
These devices can be driven by a micro controller with its SPI peripheral running in either of
the two following modes:
CPOL=0, CPHA=0
CPOL=1, CPHA=1
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and
output data is available from the falling edge of Serial Clock (C).
The difference between the two modes, as shown in Figure 5, is the clock polarity when the
bus master is in standby mode and not transferring data:
C remains at 0 for (CPOL=0, CPHA=0)
C remains at 1 for (CPOL=1, CPHA=1)
Figure 5.
Bus master and memory devices on the SPI bus
VSS
VCC
R
SDO
SPI interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
SDI
SCK
VCC
C
SPI Bus Master
R
CS3
VCC
C
DQ1DQ0
VSS
SPI memory
device
R
VCC
C
DQ1 DQ0
VSS
DQ1DQ0
SPI memory
device
R
SPI memory
device
VSS
CS2 CS1
S
W
HOLD
S
W
HOLD
S
W
HOLD
AI13725b
Shown here is an example of three devices working in Extended SPI protocol for simplicity
connected to an MCU, on an SPI bus. Only one device is selected at a time, so only one
device drives the serial data output (DQ1) line at a time; the other devices are high
impedance. Resistors R ensures that the N25Q032 is not selected if the bus master leaves
the S line in the high impedance state. As the bus master may enter a state where all
inputs/outputs are in high impedance at the same time (for example, when the bus master is
reset), the clock line (C) must be connected to an external pull-down resistor so that, when
all inputs/outputs become high impedance, the S line is pulled High while the C line is pulled
Low. This ensures that S and C do not become High at the same time, and so that the tSHCH
requirement is met. The typical value of R is 100 kΩ, assuming that the time constant R*Cp
18/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
N25Q032 - 3 V
SPI Modes
(Cp = parasitic capacitance of the bus line) is shorter than the time during which the bus
master leaves the SPI bus in high impedance.
Example: Cp = 50 pF, that is R*Cp = 5 µs <=> the application must ensure that the bus
master never leaves the SPI bus in the high impedance state for a time period shorter than
5 µs. The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as
appropriate.
Figure 6.
SPI modes supported
CPOL CPHA
0
0
C
1
1
C
DQ0
DQ1
MSB
MSB
AI13730
19/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
SPI Protocols
4
N25Q032 - 3 V
SPI Protocols
The N25Q032 memory can work with 3 different Serial protocols:
z
Extended SPI protocol.
z
Dual I/O SPI (DIO-SPI) protocol.
z
Quad I/O SPI (QIO-SPI) protocol.
It is possible to choose among the three protocols by means of user volatile or non-volatile
configuration bits.It's not possible to mix Extended SPI, DIO-SPI, and QIO-SPI protocols.
The device can operate in XIP mode in all 3 protocols.
4.1
Extended SPI protocol
This is an extension of the standard (legacy) SPI protocol. Instructions are transmitted on a
single data line (DQ0), while addresses and data are transmitted by one, two or four data
lines (DQ0, DQ1, W/VPP(DQ2) and HOLD / (DQ3) according to the instruction.
When used in the Extended SPI protocol, these devices can be driven by a micro controller
in either of the two following modes:
z
CPOL=0, CPHA=0
z
CPOL=1, CPHA=1
Please refer to the SPI modes for a detailed description of these two modes
4.2
Dual I/O SPI (DIO-SPI) protocol
Dual I/O SPI (DIO-SPI) protocol: instructions, addresses and I/O data are always
transmitted on two data lines (DQ0 and DQ1).
Also when in DIO-SPI mode, the device can be driven by a micro controller in either of the
two following modes:
z
CPOL= 0, CPHA= 0
z
CPOL= 1, CPHA= 1
Please refer to the SPI modes for a detailed description of these two modes.
Note:
Extended SPI protocol Dual I/O instructions allow only address and data to be transmitted
over two data lines. However, DIO-SPI allows instructions, addresses, and data to be
transmitted on two data lines.
This mode can be set using two ways
z
Volatile: by setting bit 6 of the VECR to 0. The device enters DIO-SPI protocol
immediately after the Write Enhanced Volatile Configuration Register sequence
completes. The device returns to the default working mode (defined by NVCR) on
power on.
z
Default/ Non-Volatile: This is default mode on power-up. By setting bit 2 of the NVCR
to 0. The device enters DIO-SPI protocol on the subsequent power-on. After all
subsequent power-on sequences, the device still starts in DIO-SPI protocol unless bit 2
of NVCR is set to 1 (default value, corresponding to Extended SPI protocol) or bit 3 of
NVCR is set to 0 (corresponding to QIO-SPI protocol).
20/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
N25Q032 - 3 V
4.3
SPI Protocols
Quad SPI (QIO-SPI) protocol
Quad SPI (QIO-SPI) protocol: instructions, addresses, and I/O data are always transmitted
on four data lines DQ0, DQ1, W/VPP(DQ2), and HOLD / (DQ3).
The exception is the Program/Erase cycle performed with the VPP, in which case the device
temporarily goes to Extended SPI protocol. Going temporarily into Extended SPI protocol
allows the application either to:
Note:
z
check the polling bits: WIP bit in the Status Register or Program/Erase Controller bit in
the Flag Status Register
z
perform Program/Erase suspend functions.
As soon as the VPP pin voltage goes low, the protocol returns to the QIO-SPI protocol.
In QIO-SPI protocol the W and HOLD/ (RESET) functionality is disabled when the device is
selected (S signal low).
When used in the QIO-SPI mode, these devices can be driven by a micro controller in either
of the two following modes:
z
CPOL=0, CPHA=0
z
CPOL=1, CPHA=1
Please refer to the SPI modes for a detailed description of the 2 modes.
Note:
In the Extended SPI protocol only Address and data are allowed to be transmitted on 4 data
lines, However in QIO-SPI protocol, the address, data and instructions are transmitted
across 4 data lines.
This working mode is set in either bit 7 of the Volatile Enhanced Configuration Register
(VECR) or in bit 3 of the Non Volatile Configuration Register (NVCR).
This mode can be set using two ways
z
Volatile: by setting bit 7 of the VECR to 0, the device enters QIO-SPI protocol
immediately after the Write Enhanced Volatile Configuration Register sequence
completes. The device returns to the default working protocol (defined by the NVCR)
on the next power on.
z
Default/ Non- Volatile: This is default protocol on power up. By setting bit 3 of the
NVCR to 0, the device enters QIO-SPI protocol on the subsequent power-on. After all
subsequent power-on sequences, the device still starts in QIO-SPI protocol unless bit 3
of the NVCR is set to 1 (default value, corresponding to Extended SPI mode).
21/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
Operating features
N25Q032 - 3 V
5
Operating features
5.1
Extended SPI Protocol Operating features
5.1.1
Read Operations
To read the memory content in Extended SPI protocol different instructions are available:
READ, Fast Read, Dual Output Fast Read, Dual Input Output Fast Read, Quad Output Fast
Read and Quad Input Output Fast read, allowing the application to choose an instruction to
send addresses and receive data by one, two or four data lines.
Note:
In the Extended SPI protocol the instruction code is always sent on one data line (DQ0): to
use two or four data lines the user must use either the DIO-SPI or the QIO-SPI protocol
respectively.
For fast read instructions the number of dummy clock cycles is configurable by using VCR
bits [7:4] or NVCR bits [15:12].
After a successful reading instruction a reduced tSHSL equal to 20 ns is allowed to further
improve random access time (in all the other cases tSHSL should be at least 50 ns). See
Table 31.: AC Characteristics.
5.1.2
Page programming
To program one data byte, two instructions are required: write enable (WREN), which is one
byte, and a page program (PP) sequence, which consists of four bytes plus data. This is
followed by the internal program cycle (of duration tPP).
To spread this overhead, the page program (PP) instruction allows up to 256 bytes to be
programmed at a time (changing bits from ‘1’ to ‘0’), provided that they lie in consecutive
addresses on the same page of memory.
For optimized timings, it is recommended to use the page program (PP) instruction to
program all consecutive targeted bytes in a single sequence versus using several page
program (PP) sequences with each containing only a few bytes (see Section 5.2.3: Page
programming and Table 31: AC Characteristics).
5.1.3
Dual input fast program
The dual input fast program (DIFP) instruction makes it possible to program up to 256 bytes
using two input pins at the same time (by changing bits from ‘1’ to ‘0’).
For optimized timings, it is recommended to use the DIFP instruction to program all
consecutive targeted bytes in a single sequence rather using several DIFP sequences each
containing only a few bytes (see Section 9.1.13: Dual Input Fast Program (DIFP)).
5.1.4
Dual Input Extended Fast Program
The Dual Input Extended Fast Program (DIEFP) instruction is an enhanced version of the
Dual Input Fast Program instruction, allowing to transmit address across two data lines.
For optimized timings, it is recommended to use the DIEFP instruction to program all
consecutive targeted bytes in a single sequence rather than using several DIEFP
sequences, each containing only a few bytes.
22/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
N25Q032 - 3 V
5.1.5
Operating features
Quad Input Fast Program
The Quad Input Fast Program (QIFP) instruction makes it possible to program up to 256
bytes using 4 input pins at the same time (by changing bits from 1 to 0).
For optimized timings, it is recommended to use the QIFP instruction to program all
consecutive targeted bytes in a single sequence rather than using several QIFP sequences
each containing only a few bytes.
5.1.6
Quad Input Extended Fast Program
The Quad Input Extended Fast Program (QIEFP) instruction is an enhanced version of the
Quad Input Fast Program instruction, allowing parallel input on the 4 input pins, including
the address being sent to the device.
For optimized timings, it is recommended to use the QIEFP instruction to program all
consecutive targeted bytes in a single sequence rather than using several QIEFP
sequences each containing only a few bytes.
5.1.7
Subsector erase, sector erase and bulk erase
The page program (PP) instruction allows bits to be reset from ‘1’ to’0’. In order to do this the
bytes of memory need to be erased to all 1s (FFh).
This can be achieved as follows:
z
a subsector at a time, using the subsector erase (SSE) instruction. See Section 16:
Ordering information;
z
a sector at a time, using the sector erase (SE) instruction;
z
throughout the entire memory, using the bulk erase (BE) instruction.
This starts an internal erase cycle (of duration tSSE, tSE or tBE). The erase instruction must
be preceded by a write enable (WREN) instruction.
5.1.8
Polling during a write, program or erase cycle
A further improvement in the time to Write Status Register (WRSR), POTP, PP,
DIFP,DIEFP,QIFP, QIEFP or Erase (SSE, SE or BE) can be achieved by not waiting for the
worst case delay (tW, tPP, tSSE, tSE, or tBE). The application program can monitor if the
required internal operation is completed, by polling the dedicated register bits to establish
when the previous Write, Program or Erase cycle is complete.
The information on the memory being in progress for a Program, Erase, or Write instruction
can be checked either on the Write In Progress (WIP) bit of the Status Register or in the
Program/Erase Controller bit of the Flag Status Register.
Note:
The Program/Erase Controller bit is the opposite state of the WIP bit in the Status Register.
In the Flag Status Register additional information can be checked, as eventual
Program/Erase failures by mean of the Program or erase Error bits.
23/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
Operating features
5.1.9
N25Q032 - 3 V
Active power and standby power modes
When Chip Select (S) is Low, the device is selected, and in the active power mode.
When Chip Select (S) is High, the device is deselected, but could remain in the active power
mode until all internal cycles have completed (program, erase, write status register). The
device then goes in to the standby power mode. The device consumption drops to ICC1.
5.1.10
Hold (or Reset) condition
The Hold (HOLD) signal is used to pause serial communications with the device without
resetting the clocking sequence. However, taking this signal Low does not terminate any
write status register, program or erase cycle that is currently in progress.
To enter the hold condition, the device must be selected, with Chip Select (S) Low.
The hold condition starts on the falling edge of the Hold (HOLD) signal, provided that the
Serial Clock (C) is Low (as shown in Figure 7).
The hold condition ends on the rising edge of the Hold (HOLD) signal, provided that the
Serial Clock (C) is Low.
If the falling edge does not coincide with Serial Clock (C) being Low, the hold condition
starts after Serial Clock (C) next goes Low. Similarly, if the rising edge does not coincide
with Serial Clock (C) being Low, the hold condition ends after Serial Clock (C) next goes
Low (this is shown in Figure 7).
During the hold condition, the serial data output (DQ1) is high impedance, and serial data
input (DQ0) and Serial Clock (C) are don’t care.
Normally, the device is kept selected, with Chip Select (S) driven Low for the whole duration
of the hold condition. This is to ensure that the state of the internal logic remains unchanged
from the moment of entering the hold condition.
If Chip Select (S) goes High while the device is in the Hold condition, this has the effect of
resetting the internal logic of the device. To restart communication with the device, it is
necessary to drive Hold (HOLD) High, and then to drive Chip Select (S) Low. This prevents
the device from going back to the hold condition.
Figure 7.
Hold condition activation
C
HOLD
Hold
condition
(standard use)
Hold
condition
(non-standard use)
AI02029D
Reset functionality is available instead of Hold in parts with a dedicated part number. See
Section 16: Ordering information.
Driving Reset (Reset) Low while an internal operation is in progress will affect this operation
(write, program or erase cycle) and data may be lost. On Reset going Low, the device enters
the reset mode and a time of tRHSL is then required before the device can be reselected by
24/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
N25Q032 - 3 V
Operating features
driving Chip Select (S) Low. For the value of tRHSL, see Table 31.: AC Characteristics. All
the lock bits are reset to 0 after a Reset Low pulse.
The Hold/Reset feature is not available when the Hold (Reset) / DQ3 pin is used as I/O
(DQ3 functionality) during Quad Instructions: QOFR, QIOFR,QIFP and QIEFP.
The Hold/Reset feature can be disabled by using of the bit 4 of the VECR.
25/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
Operating features
5.2
N25Q032 - 3 V
Dual SPI (DIO-SPI) Protocol
In the Dual SPI (DIO-SPI) protocol all the instructions, addresses and I/O data are
transmitted on two data lines. All the functionality available in the Extended SPI protocol is
also available in the DIO-SPI protocol. The DIO-SPI instructions are comparable with the
Extended SPI instructions; however, in DIO-SPI, the instructions are multiplexed on the two
data lines, DQ0 and DQ1.
The only exceptions are the READ, Quad Read, and Program instructions, which are not
available in DIO-SPI protocol, and the RDID instruction, which is replaced in the DIO-SPI
protocol by the Multiple I/O Read Identification (MIORDID) instruction.
The Multiple I/O Read Identification Instruction reads just the standard SPI electronic ID (3
bytes), while the Extended SPI protocol RDID instruction allows access to the UID bytes.
To help the application code port from Extended SPI to DIO-SPI protocol, the instructions
available in the DIO-SPI protocol have the same operation code as the Extended SPI
protocol, the only exception being the MIORDID instruction.
5.2.1
Multiple I/O Read Identification
The Multiple I/O Read Identification (MIORDID) instruction is available to read the device
electronic ID.With respect to the RDID instruction of the Extended SPI protocol, the output
data, shifted out on the 2 data lines DQ0 and DQ1.
Since the read ID instruction in the DIO-SPI protocol is limited to 3 bytes of the standard
electronic ID, the UID bytes are not read with the MIORDID instruction
5.2.2
Dual Command Fast reading
Reading the memory data multiplexing the instruction, the addresses and the output data on
2 data lines can be achieved in DIO-SPI protocol by mean of the Dual Command Fast Read
instruction, that has 3 instruction codes (BBh, 3Bh and 0Bh) to help the application code
porting from Extended SPI protocol to DIO-SPI protocol. Of course quad and single I/O
Read instructions are not available in DIO-SPI mode.
For Dual Command fast read instructions the number of dummy clock cycles is configurable
by using VCR bits [7:4] or NVCR bits [15:12].
After a successful reading instruction, a reduced tSHSL equal to 20ns is allowed to further
improve random access time (in all the other cases tSHSL should be at least 50 ns). See
Table 31.: AC Characteristics.
5.2.3
Page programming
Programming the memory by transmitting the instruction, addresses and the output data on
2 data lines can be achieved in DIO-SPI protocol by using the Dual Command Page
Program instruction, that has 3 instruction codes (D2h, A2h and 02h) to help port from
Extended SPI protocol to DIO-SPI protocol
Quad and single input Program instructions are not available in DIO-SPI mode.
26/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
N25Q032 - 3 V
Operating features
The DIO-SPI protocol is similar to the Extended SPI protocol i.e., to program one data byte
two instructions are required:
z
Write Enable (WREN), which is one byte, and a
z
Dual Command Page Program (DCPP) sequence, which consists of four bytes plus
data.
This is followed by the internal Program cycle (of duration tPP).
To spread this overhead, the Dual Command Page Program (DCPP) instruction allows up to
256 bytes to be programmed at a time (changing bits from 1 to 0), provided that they are
consecutive addresses on the same page of memory.
For optimized timings, it is recommended to use the DCPP instruction to program all
consecutive targeted bytes in a single sequence versus using several DCPP sequences
with each containing only a few bytes. See Table 31.: AC Characteristics.
5.2.4
Subsector Erase, Sector Erase and Bulk Erase
Similar to the Extended SPI protocol, in the DIO-SPI protocol to erase the memory bytes to
all 1s (FFh) the Subsector Erase (SSE), the Sector Erase (SE) and the Bulk Erase (BE)
instructions are available. These instructions start an internal Erase cycle (of duration tSSE,
tSE or tBE).
The Erase instruction must be preceded by a Write Enable (WREN) instruction.
5.2.5
Polling during a Write, Program or Erase cycle
Similar to the Extended SPI protocol, in the DIO-SPI protocol it is possible to monitor if the
internal write, program or erase operation is completed, by polling the dedicated register bits
by using the Read Status Register (RDSR) or Read Flag Status Register (RFSR)
instructions, the only obvious difference is that instruction codes, addresses and output data
are transmitted across two data lines.
5.2.6
Read and Modify registers
Similar to the Extended SPI protocol, the only obvious difference is that instruction codes,
addresses and output data are transmitted across two data lines
5.2.7
Active Power and Standby Power modes
Similar to the Extended SPI protocol, when Chip Select (S) is Low, the device is selected,
and in the Active Power mode. When Chip Select (S) is High, the device is deselected, but
could remain in the Active Power mode until all internal cycles have completed (Program,
Erase, Write Cycles). The device then goes in to the Standby Power mode. The device
consumption drops to ICC1.
5.2.8
HOLD (or Reset) condition
The HOLD (or Reset i.e. for parts having the reset functionality instead of hold pin) signal
has exactly the same behavior in DIO-SPI protocol as do in Extended SPI protocol, so
please refer to section 5.1.10, Hold (or Reset) condition” in the Extend SPI protocol section
for further details.
27/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
Operating features
5.3
N25Q032 - 3 V
Quad SPI (QIO-SPI)Protocol
In the Quad SPI (QIO-SPI) protocol all the Instructions, addresses and I/O data are
transmitted on four data lines, with the exception of the polling instructions performed during
a Program or Erase cycle performed with VPP, in this case the device temporarily goes in
Extended SPI protocol. The protocol again becomes QIO-SPI as soon as the VPP voltage
goes low.
All the functionality available in the Extended SPI protocol are also available in the QIO-SPI
mode, with equivalent instruction transmitted on the 4 data lines DQ0, DQ1, DQ2 and DQ3.
The exceptions are the READ, Dual Read and Dual Program instructions, that are not
available in QIO-SPI protocol, and the RDID instruction, that is replaced in the QIO-SPI
protocol by the Multiple I/O Read Identification (MIORDID) instruction. The Multiple I/O
Read Instruction reads just the standard SPI electronic ID (3 bytes), while with the Extended
SPI protocol RDID instruction is possible to access also the UID bytes.
To help the application code port from Extended SPI to QIO-SPI protocol, the instructions
available in the QIO-SPI protocol have the same operation code as in the Extended SPI
protocol, the only exception is the MIORDID instruction.
5.3.1
Multiple I/O Read Identification
The Multiple I/O Read Identification (MIORDID) instruction is available to read the device
electronic ID. With respect to the RDID instruction of the Extended SPI protocol, the output
data, shifted out on the 4 data lines DQ0, DQ1, DQ2 and DQ3.
Since in the QIO-SPI protocol the Read ID instruction is limited to 3 bytes of the standard
electronic ID, the UID bytes are not read with the MIORDID instruction.
5.3.2
Quad Command Fast reading
The Array Data can be read by the Quad Command Fast Read instruction using 3
instructions (EBh, 6Bh and 0Bh) to help the application code port from Extended SPI
protocol to DIO-SPI protocol. The instruction, address and output data are transmitted
across 4 data lines.
The Dual and Single I/O Read instructions are not available in QIO-SPI protocol.
5.3.3
QUAD Command Page programming
The memory can be programmed in QIO-SPI protocol by the Quad Command Page
Program instruction using (02h, 12h and 32h). The instruction, address and input data are
transmitted across 4 data lines
The Dual and Single I/O Program instructions are not available in QIO-SPI protocol
Programming the memory by multiplexing the instruction, the addresses and the output data
on 4 wires can be achieved in QIO-SPI protocol by mean of the Quad Command Page
Program instruction, that has 3 instruction codes (02h, 12h and 32h) to help the application
code porting from Extended SPI protocol to QIO-SPI protocol.
Similar to the Extended SPI protocol in the QIO-SPI protocol, to program one data byte two
instructions are required:
z
Write Enable (WREN), which is one byte, and
z
Quad Command Page Program (QCPP) sequence, which consists of instruction (one
byte), address (3 bytes) and input data.
28/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
N25Q032 - 3 V
Operating features
This is followed by the internal Program cycle (of duration tPP).
To spread this overhead, the Quad Command Page Program (QCPP) instruction allows up
to 256 bytes to be programmed at a time (changing bits from 1 to 0), provided that they are
in consecutive addresses on the same page of memory.
For optimized timings, it is recommended to use the QCPP instruction to program all
consecutive targeted bytes in a single sequence versus using several QCPP sequences
with each containing only a few bytes. See Table 31.: AC Characteristics.
The QCPP instruction is transmitted across 4 data lines except when VPP is raised to
VPPH.
The VPP can be raised to VPPH to decrease programming time (provided that the bit 3 of
the VECR has been set to 0 in advance). When bit 3 of VECR is set to 0 after the Quad
Command Page Program instruction sequence has been received, the memory temporarily
goes in Extended SPI protocol, and is possible to perform polling instructions (checking the
WIP bit of the Status Register or the Program/Erase Controller bit of the Flag Status
Register) or Program/Erase Suspend instruction even if DQ2 is temporarily used in this VPP
functionality. The memory automatically comes back in QIO-SPI protocol as soon as the
VPP pin goes Low.
5.3.4
Subsector Erase, Sector Erase and Bulk Erase
Similar to the Extended SPI protocol, Subsector Erase (SSE), the Sector Erase (SE) and
the Bulk Erase (BE) instructions are used to erase the memory in the QIO-SPI protocol.
These instructions start an internal Erase cycle (of duration tSSE, tSE or tBE).
The Erase instruction must be preceded by a Write Enable (WREN) instruction.
The erase instructions are transmitted across 4 data lines unless the VPP is raised to
VPPH.
The VPP can be raised to VPPH to decrease erasing time, provided that the bit 3 of the
VECR has been set to 0 in advance. In this case, after the erase instruction sequence has
been received, the memory temporarily goes in extended SPI protocol, and it is possible to
perform polling instructions (checking the WIP bit of the Status Register or the
Program/Erase Controller bit of the Flag Status Register) or Program/Erase Suspend
instruction even if DQ2 is temporarily used in this VPP functionality. The memory
automatically comes back in QIO-SPI protocol as soon as the VPP pin goes Low.
5.3.5
Polling during a Write, Program or Erase cycle
It is possible to check if the internal write, program or erase operation is completed, by
polling the dedicated register bits of the Read Status Register (RDSR) or Read Flag Status
Register (RFSR).
When the Program or Erase cycle is performed with the VPP, the device temporarily goes in
single I/O SPI mode. The protocol became again QIO-SPI as soon as the VPP pin voltage
goes low.
5.3.6
Read and Modify registers
The read and modify register instructions are available and behave in QIO-SPI protocol
exactly as they do in Extended SPI protocol, the only difference is that instruction codes,
addresses and output data are transmitted across 4 data lines.
29/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
Operating features
5.3.7
N25Q032 - 3 V
Active Power and Standby Power modes
Exactly as in Extended SPI protocol, when Chip Select (S) is Low, the device is selected,
and in the Active Power mode. When Chip Select (S) is High, the device is deselected, but
could remain in the Active Power mode until all internal (Program, Erase, Write) Cycles
have completed. The device then goes in to the Standby Power mode. The device
consumption drops to ICC1.
5.3.8
HOLD (or Reset) condition
The HOLD (Hold) feature (or Reset feature, for parts having the reset functionality instead of
hold) is disabled in QIO-SPI protocol when the device is selected: the Hold (or Reset)/ DQ3
pin always behaves as an I/O pin (DQ3 function) when the device is deselected. For parts
with reset functionality, it is still possible to reset the memory when it is deselected (C signal
high).
5.3.9
VPP pin Enhanced Supply Voltage feature
It is possible in the QIO-SPI protocol to use the VPP pin as an enhanced supply voltage, but
the intention to use VPP as accelerated supply voltage must be declared by setting bit 3 of
the VECR to 0.
In this case, to accelerate the Program cycle the VPP pin must be raised to VPPH after the
device has received the last data to be programmed within 200ms. If the VPP is not raised
within 200ms, the program operation starts with the standard internal cycle speed as if the
Vpp high voltage were not used, and a flag error appears on Flag Status Register bit 3".
30/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
N25Q032 - 3 V
6
Volatile and Non Volatile Registers
Volatile and Non Volatile Registers
The device features many different registers to store, in volatile or non volatile mode, many
parameters and operating configurations:
z
Legacy SPI Status Register
z
3 configuration registers:
–
Non Volatile Configuration Register (NVCR), 16 bits
–
Volatile Configuration Register (VCR), 8 bits
–
Volatile Enhanced Configuration Register (VECR), 8 bits
The Non Volatile Configuration Register (NVCR) affects the memory configuration starting
from the successive power-on. It can be used to make the memory start in a determined
condition.
The VCR and VECR affect the memory configuration after every execution of the related
Write Volatile configuration Register (WRVCR) and Write Enhanced Volatile Configuration
register (WRVECR) instructions. These instructions overwrite the memory configuration set
at POR by NVCR.
As described in Figure 8.: Non Volatile and Volatile configuration Register Scheme, the
working condition of the memory is set by an internal configuration register, which is not
accessible by the user. The working parameters of the internal configuration register are
loaded from the NVCR during the boot phase of the device. In this sense the NVCR can be
seen as having the default settings of the memory.
During the normal life of the application, every time a write volatile or enhanced volatile
configuration register instruction is performed, the new configuration parameters set in the
volatile registers are also copied in the internal configuration register, thus instantly affecting
the memory behavior. Please note that on the next power on the memory will start again in
the working protocol set by the Non Volatile Register parameters.
31/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
Volatile and Non Volatile Registers
Figure 8.
N25Q032 - 3 V
Non Volatile and Volatile configuration Register Scheme
NVCR
(Non Volatile Configuratio n Register)
Register download executed only
during the power on phase
VCR (Volatile Co nfiguratio n Register)
and VECR (Volatile Enhanced
Co nfiguratio n Register)
Registers download executed after
a WRVCR or WRVECR
instructions, it overwrites NVCR
configurations on iCR
iCR
(internal Configuration Register)
Device behaviour
A Flag Status Register (FSR), 8 bits, is also available to check the status of the device,
detecting possible errors or a Program/Erase internal cycle in progress.
Each register can be read and modified by means of dedicated instructions in all the 3
protocols (Extended SPI, DIO-SPI, and QIO-SPI).
Reading time for all registers is comparable; writing time instead is very different: NVCR bits
are set as Flash Cell memory content requiring a longer time to perform internal writing
cycles. See Table 31.: AC Characteristics.
32/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
N25Q032 - 3 V
6.1
Volatile and Non Volatile Registers
Legacy SPI Status Register
The Status Register contains a number of status and control bits that can be read or set by
specific instructions: Read Status Register (RDSR) and Write Status Register (WRSR). This
is available in all the 3 protocols (Extended SPI, DIO-SPI, and QIO-SPI).
Table 2.
Status register format
b7
SRWD
b0
0
TB
BP2
BP1
BP0
WEL
WIP
Status register write protect
Top/bottom bit
Block protect bits
Write enable latch bit
Write in progress bit
6.1.1
WIP bit
The Write In Progress (WIP) bit set to 1 indicates that the memory is busy with a Write
Status Register, Program or Erase cycle. 0 indicates no cycle is in progress.
6.1.2
WEL bit
The Write Enable Latch (WEL) bit set to 1 indicates that the internal Write Enable Latch is
set. When set to 0 the internal Write Enable Latch is reset and no Write Status Register,
Program or Erase instruction is accepted.
6.1.3
Block Protect bits (BP2, BP1, BP0)
The Block Protect (BP2, BP1, BP0) bits are non-volatile. They define the size of the area to
be software protected against Program and Erase instructions. These bits are written with
the Write Status Register (WRSR) instruction. When one or more of the Block Protect (BP2,
BP1, BP0) bits is set to 1, the relevant memory area, as defined in Table 10.: Protected area
sizes, Upper (TB bit = 0) becomes protected against all program and erase instructions. The
Block Protect (BP2, BP1, BP0) bits can be written provided that the Hardware Protected
mode has not been set. The Bulk Erase (BE) instruction is executed if, and only if, all Block
Protect (BP2, BP1, BP0) bits are 0.
6.1.4
TB bit
The Top/Bottom (TB) bit is non-volatile. It can be set and reset with the Write Status Register
(WRSR) instruction provided that the Write Enable (WREN) instruction has been issued.
33/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
Volatile and Non Volatile Registers
N25Q032 - 3 V
The Top/Bottom (TB) bit is used in conjunction with the Block Protect (BP2, BP1, BP0) bits
to determine if the protected area defined by the Block Protect bits starts from the top or the
bottom of the memory array:
z
When TB is reset to '0' (default value), the area protected by the Block Protect bits
starts from the top of the memory array.
z
When TB is set to '1', the area protected by the Block Protect bits starts from the bottom
of the memory array.
The TB bit cannot be written when the SRWD bit is set to '1' and the W pin is driven Low.
6.1.5
SRWD bit
The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write
Protect (W/VPP) signal. The Status Register Write Disable (SRWD) bit and the Write Protect
(W/VPP) signal allow the device to be put in the hardware protected mode (when the Status
Register Write Disable (SRWD) bit is set to '1', and Write Protect ((W/VPP) is driven Low). In
this mode, the non-volatile bits of the Status Register (TB, BP2, BP1, BP0) become readonly bits and the Write Status Register (WRSR) instruction is no longer accepted for
execution.
6.2
Non Volatile Configuration Register
The Non Volatile Configuration Register (NVCR) bits affects the default memory
configuration after power-on. It can be used to make the memory start in the configuration to
fit the application requirements.
The device is delivered with Non Volatile Configuration Register (NVCR) bits all erased to 1
(FFFFh).
The purpose of the NVCR is to define the default memory settings after the power-on
sequence related to many features:
z
The number of dummy clock cycle for fast read instructions,
z
XIP mode configurations,
z
output driver strengths,
z
Reset (or Hold) disabling
z
Multiple I/O protocol enabling.
The NVCR can be read by the Read Non Volatile Configuration Register (RDNVCR)
instruction and written by the Write Non Volatile Configuration Register (WRNVCR) in all the
3 available SPI protocols. See the sections that follow as well as Table 3.: Non-Volatile
Configuration Register.
34/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
N25Q032 - 3 V
Table 3.
Non-Volatile Configuration Register
Bit
NVCR<15:12>
NVCR<11:9>
NVCR<8:6>
Volatile and Non Volatile Registers
Parameter
Value
Description
0000
As '1111'
0001
1
0010
2
0011
3
0100
4
0101
5
0110
6
0111
7
1000
Dummy clock
1001
cycles
8
To optimize instruction execution
(FASTREAD, DOFR,DIOFR,QOFR,
QIOFR, ROTP, RDSFDP) according to the
frequency
9
1010
10
1011
11
1100
12
1101
13
1110
14
1111
Target on maximum
allowed frequency fc
(108MHz) and to
guarantee backward
compatibility (default)
000
XIP for SIO Read
001
XIP for DOFR
010
XIP for DIOFR
011
XIP for QOFR
100
XIP for QIOFR
101
reserved
110
reserved
111
XIP disabled (default)
000
reserved
001
90
010
60
Output Driver 011
Strength
100
45
101
20
110
15
111
30 (default)
XIP enabling
at POR
Note
Impedance at Vcc/2
reserved
35/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
Volatile and Non Volatile Registers
Table 3.
Bit
N25Q032 - 3 V
Non-Volatile Configuration Register
Parameter
Value
Description
NVCR<5>
Reserved
x
Don’t Care
Reset/Hold
disable
0
disabled
NVCR<4>
1
enabled (default)
Quad Input
Command
0
enabled
1
disabled (default)
Dual Input
Command
0
enabled
1
disabled (default)
Reserved
xx
Don't care
NVCR<3>
NVCR<2>
NVCR<1:0>
6.2.1
Note
Default value = 1
Disable Pad Hold/Reset functionality
Enable command on four input lines
Enable command on two input lines
Default value = "11"
Dummy clock cycles NV configuration bits (NVCR bits from 15 to 12)
The bits from 15 to 12 of the Non Volatile Configuration register store the default settings for
the dummy clock cycles number after the fast read instructions (in all the 3 available
protocols). The dummy clock cycles number can be set from 1 up to 15 as described here,
according to operating frequency (the higher is the operating frequency, the bigger must be
the dummy clock cycle number) to optimize the fast read instructions performance.
The default values of these bits allow the memory to be safely used with fast read
instructions at the maximum frequency (108 MHz). Please note that if the dummy clock
number is not sufficient for the operating frequency, the memory reads wrong data.
Table 4.
Maximum operative frequency by dummy clock cycles
Maximum allowed frequency (MHz) (1)
Dummy Clock
FASTREAD
DOFR
DIOFR
QOFR
QIOFR
1
54
50
39
43
20
2
95
85
59
56
39
3
105
95
75
70
49
4
108
105
88
83
59
5
108
108
94
94
69
6
108
108
105
105
78
7
108
108
108
108
86
8
108
108
108
108
95
9
108
108
108
108
105
10
108
108
108
108
108
1. All the values are guaranteed by characterization and not 100% tested in production
36/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
N25Q032 - 3 V
6.2.2
Volatile and Non Volatile Registers
XIP NV configuration bits (NVCR bits from 11 to 9)
The bits from 11 to 9 of the Non Volatile Configuration register store the default settings for
the XIP operation, allowing the memory to start working directly on the required XIP mode
after successive POR sequence: the device then accepts only address on one, two, or four
wires (skipping the instruction) depending on the NVCR XIP bits settings.
The default settings for the XIP bits of the NVCR enable the memory to start working in
Extended SPI mode after the POR sequence (XIP directly after POR is disabled).
6.2.3
Output Driver Strength NV configuration bits (NVCR bits from 8 to 6)
The bits from 8 to 6 of the Non Volatile Configuration register store the default settings for
the output driver strength, enabling to optimize the impedance at Vcc/2 output voltage for
the specific application.
The default values of Output Driver Strength bits of the NVCR set the output impedance at
Vcc/2 equal to 30 Ohms.
6.2.4
Hold (Reset) disable NV configuration bit (NVCR bit 4)
The Hold (RESET) disable bit can be used to disable the Hold (Reset) functionality of the
Hold (Reset) / DQ3 pin as described in Table 3.: Non-Volatile Configuration Register. This
feature can be useful to avoid accidental Hold or Reset condition entries in applications that
never require the Hold (Reset) functionality.
The default values of Hold (Reset) bit of the NVCR is set to enable the Hold (Reset)
functionality.
Note:
Reset functionality is available instead of Hold in devices with a dedicated part number. See
Section 16: Ordering information.
6.2.5
Quad Input NV configuration bit (NVCR bit 3)
The Quad Input NV configuration bit can be used to make the memory start working in QIOSPI protocol directly after the power on sequence. The products are delivered with this set
to 1, making the memory default in Extended SPI protocol. If the application sets this bit to
0, the device will enter in DIO-SPI protocol right after the next power on.
Please note that in case both QIO-SPI and DIO-SPI are enabled (both bit 3 and bit 2 of the
Non Volatile Configuration Register set to 0), the memory will work in QIO-SPI.
6.2.6
Dual Input NV configuration bit (NVCR bit 2)
The Dual Input NV configuration bit can be used to make the memory start working in DIOSPI protocol directly after the power on sequence. The products are delivered with this set
to 1, making the memory default in Extended SPI protocol, if the application sets this bit to 0
the device will enter in QIO-SPI protocol right after the next power on.
Please note that in case both QIO-SPI and DIO-SPI are enabled (both bit 3 and bit 2 of the
Non Volatile Configuration Register set to 0), the memory will work in QIO-SPI.
37/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
Volatile and Non Volatile Registers
6.3
N25Q032 - 3 V
Volatile Configuration Register
The Volatile Configuration Register (VCR) affects the memory configuration after every
execution of Write Volatile Configuration Register (WRVCR) instruction: this instruction
overwrite the memory configuration set at POR by the Non Volatile Configuration Register
(NVCR). Its purpose is to define the dummy clock cycles number and to make the device
ready to enter in the required XIP mode.
Table 5.
Bit
Volatile Configuration Register
Parameter
Dummy
VCR<7:4> clock
cycles (1)
VCR<3>
VCR<2>
XIP (2)
Reserved
Binary Decimal
Value
Value
Description
0000
As '1111'
0001
1
0010
2
0011
3
0100
4
0101
5
0110
6
0111
7
1000
8
1001
9
1010
10
1011
11
1100
12
1101
13
1110
14
1111
15
Targets maximum allowed frequency fc (108MHz) and guarantees
backward compatibility (default)
0
0
Ready to enter XIP mode
1
1
XIP disabled (default)
x
reserved Fixed value = 0b
00
0
16-byte wrap: Output data wraps within an aligned 16-byte boundary
starting from the address issued after the command code.
01
1
32-byte wrap: Output data wraps within an aligned 32-byte boundary
starting from the address issued after the command code.
10
2
64-byte wrap: Output data wraps within an aligned 64-byte boundary
starting from the address issued after the command code.
11
3
Continous reading (Default): All bytes are read sequentially
VCR<1:0> Wrap
To optimize instruction execution (FASTREAD, DOFR, DIOFR,
QOFR, QIOFR, ROTP, RDSFDP) according to the frequency
1. To optimize instruction execution (FASTREAD, DOFR,DIOFR,QOFR, QIOFR, ROTP) according to the frequency.
2. To make the data on DQ0 during the first dummy clock NOT “Don’t Care.” For devices with feature set digit equal to 2 or 4
in the part number (Basic XiP), this bit is always Don't Care."
38/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
N25Q032 - 3 V
6.3.1
Volatile and Non Volatile Registers
Dummy clock cycle: VCR bits 7:4
The bits from 7 to 4 of the Volatile Configuration Register, as the bits from 15 to 12 of the
Non-Volatile Configuration register, set the dummy clock cycles number after the fast read
instructions (in all the 3 available protocols). The dummy clock cycles number can be set
from 1 up to 15 as described in Table 5.: Volatile Configuration Register, according to
operating frequency (the higher is the operating frequency, the bigger must be the dummy
clock cycle number, according to Table 4.: Maximum operative frequency by dummy clock
cycles) to optimize the fast read instructions performance.
Note:
If the dummy clock number is not sufficient for the operating frequency, the memory reads
wrong data.
6.3.2
XIP Volatile Configuration bits (VCR bit 3)
The bit 3 of the Volatile Configuration Register is the XIP enabling bit, this bit must be set to
0 to enable the memory working on XIP mode. For devices with a feature set digit equal to 2
or 4 in the part number (Basic XiP), this bit is always Don't Care, and it is possible to operate
the memory in XIP mode without setting it to 0. See Section 16: Ordering information.
6.3.3
Wrap: VCR bits 1:0
The bits from 1 to 0 allow the Wrap mode to be available for each kind of read instruction
and protocol. A specific setting provides the ability to read the memory from sequentially
(standard) mode to a wrap mode, where the reads can be confined inside the 16, 32, or 64
byte boundary. For Wrap setting options, see Table 5.: Volatile Configuration Register. The
following table shows an example of the sequence of bytes in the 16-byte, 32-byte, and 64byte options, according to the starting address.
Table 6.
Sequence of Bytes Read during Wrap Mode
Starting Address
16-Byte Wrap
32-Byte Wrap
64-Byte Wrap
0
0-1-2- . . . -15-0-1- . .
0-1-2- . . . -31-0-1- . .
0-1-2- . . . -63-0-1- . .
1
1-2- . . . -15-0-1-2- . .
1-2- . . . -31-0-1-2- . .
1-2- . . . -63-0-1-2- . .
15
15-0-1-2-3- . . . -15-0-1- . .
15-16-17- . . . -31-0-1- . .
15-16-17- . . . -63-0-1- . .
31
31-16-17- . . . -31-16-17- . .
31-0-1-2-3- . . . -31-0-1- . .
31-32-33- . . . -63-0-1- . .
63
63-48-49- . . . -63-48-49- . .
63-32-33- . . . -63-32-33- . .
63-0-1- . . . -63-0-1- . .
6.4
Volatile Enhanced Configuration Register
The Volatile Enhanced Configuration Register (VECR) affects the memory configuration
after every execution of Write Volatile Enhanced Configuration Register (WRVECR)
instruction: this instruction overwrite the memory configuration set during the POR
sequence by the Non Volatile Configuration Register (NVCR). Its purpose is:
z
enabling of QIO-SPI protocol and DIO-SPI protocol
39/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
Volatile and Non Volatile Registers
Warning:
Table 7.
Bit
N25Q032 - 3 V
WARNING: in case of both QIO-SPI and DIO-SPI enabled, the
memory works in QIO-SPI
z
HOLD (Reset) functionality disabling
z
To enable the VPP functionality in Quad I/O modify operations
z
To define output driver strength (3 bit)
Volatile Enhanced Configuration Register
Parameter
Value
Description
Quad Input
Command
0
Enabled
1
Disabled (default)
Dual Input
Command
0
Enabled
1
Disabled (default)
VECR<5>
Reserved
x
Reserved
Reset/Hold
disable
0
Disabled
VECR<4>
1
Enabled (default)
Accelerator
pin enable in
QIO-SPI
protocol or in
QIFP/QIEFP
0
Enabled
VECR<7>
VECR<6>
VECR<3>
VECR<2:0>
6.4.1
Note
Enable command on four input lines
Enable command on two input lines
Fixed value = 0b
Disable Pad Hold/Reset functionality
1
Disabled (default)
000
reserved
001
90
010
60
Output Driver 011
Strength
100
45
101
20
110
15
111
30 (default)
The bit must be considered in case of QIFP,
QIEFP, or QIO-SPI protocol. It is “Don’t
Care” otherwise.
Impedance at VCC/2
reserved
Quad Input Command VECR<7>
The Quad Input Command configuration bit can be used to make the memory start working
in QIO-SPI protocol directly after the Write Volatile Enhanced Configuration Register
(WRVECR) instruction. The default value of this bit is 1, corresponding to Extended SPI
protocol, If this bit is set to 0 the memory works in QIO-SPI protocol. If VECR bit 7 is set
back to 1 the memory start working again in Extended SPI protocol, unless the bit 6 is set to
0 (in this case the memory start working in DIO-SPI mode).
Please note that in case both QIO-SPI and DIO-SPI are enabled (both bit 7and bit 6 of the
VECR set to 0), the memory will work in QIO-SPI.
40/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
N25Q032 - 3 V
6.4.2
Volatile and Non Volatile Registers
Dual Input Command VECR<6>
The Dual Input Command configuration bit can be used to make the memory start working
in DIO-SPI protocol directly after the Write Volatile Enhanced Configuration Register
(WRVECR) instruction. The default value of this bit is 1, corresponding to Extended SPI
protocol, if this bit is set to 0 the memory works in DIO-SPI protocol (unless the Volatile
Enhanced Configuration Register bit 7 is also set to 0). If the Volatile Enhanced
Configuration Register bit 6 is set back to 1 the memory start working again in Extended SPI
protocol.
Please note that in case both QIO-SPI and DIO-SPI are enabled (both bit 7 and bit 6 of the
VECR are set to 0), the memory will work in QIO-SPI.
6.4.3
Reset/Hold disable VECR<4>
The Hold (RESET) disable bit can be used to disable the Hold (Reset) functionality of the
Hold (Reset) / DQ3 pin right after the Write Volatile Enhanced Configuration Register
(WRVECR) instruction. This feature can be useful to avoid accidental Hold or Reset
condition entries in applications that never require the Hold (Reset) functionality. If this bit is
set to 0 the Hold (Reset) functionality is disabled, it is possible to enable it back by setting
this bit to 1.
Please note that after the next power on the Hold (Reset) functionality will be enabled again
unless the bit 4 of the Non Volatile Configuration Register is set to 0.
Note:
Reset functionality is available instead of Hold in devices with a dedicated part number. See
Section 16: Ordering information.
6.4.4
Accelerator pin enable: QIO-SPI protocol / QIFP/QIEFP VECR<3>
The bit 3 of the Volatile Enhanced Configuration Register determines whether it is possible
to use the Vpp accelerating voltage to speed up internal modify operation with Quad
program and erase instructions (both in Extended or QIO-SPI protocols).
If we want to use the Vpp voltage with Quad I/O modify instructions, we must set previously
this bit to 0 (his default value is 1, in this case the Vpp pin functionality is disabled in all
Quad I/O operations: both in Extended SPI and QIO-SPI protocols).
If the Volatile Enhanced Configuration Register bit 3 is set to 0, using the QIO-SPI protocol,
after a Quad Command Page Program instruction or an Erase instruction is received (with
all input data in the Program case) and the memory is de-selected, the protocol temporarily
switches to Extended SPI protocol until Vpp passes from Vpph to normal I/O value (this
transition is mandatory to come back to QIO-SPI protocol), to enable the possibility to
perform polling instructions (to check if the internal modify cycle is finished by means of the
WIP bit of the Status Register or of the Program/Erase controller bit of the Flag Status
register) or Program/Erase Suspend instruction even if the DQ2 pin is temporarily used in
his Vpp functionality.
If the Volatile Enhanced Configuration Register bit 3 is set to 0, after any quad modify
instruction (both in Extended SPI protocol and QIO-SPI protocol) there is a maximum
allowed time-out of 200ms after the last instruction input is received and the memory is deselected to raise the Vpp signal to Vpph, otherwise the modify instruction start at normal
speed, without the Vpph enhancement, and a flag error appears on Flag Status Register bit
3.
41/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
Volatile and Non Volatile Registers
6.4.5
N25Q032 - 3 V
Output Driver Strength VECR<2:0>
The bits from 2 to 0 of the VECR set the value of the output driver strength, enabling to
optimize the impedance at Vcc/2 output voltage for the specific application as described in
Table 7.: Volatile Enhanced Configuration Register.
The default values of Output Driver Strength is set by the dedicated bits of the Non Volatile
Configuration Register (NVCR), the parts are delivered with the output impedance at Vcc/2
equal to 30 Ohms.
6.5
Flag Status Register
The Flag Status Register is a powerful tool to investigate the status of the device, checking
information regarding what is actually doing the memory and detecting possible error
conditions.
The Flag status register is composed by 8 bit.Three bits (Program/Erase Controller bit,
Erase Suspend bit and Program Suspend bit) are a “Status Indicator bit”, they are set and
reset automatically by the memory. Four bits (Erase error bit, Program error bit, VPP 1 to 0
error bit and Protection error bit) are “Error Indicators bits”, they are set by the memory
when some program or erase operation fails or the user tries to perform a forbidden
operation. The user can clear the Error Indicators bits by mean of the Clear Flag Status
Register (CLFSR) instruction.
All the Flag Status Register bits can be read by mean of the Read Status Register (RFSR)
instruction.
Table 8.
Flag Status Register
BIT
6.5.1
Description
Note
7
P/E Controller (not WIP)
Status
6
Erase Suspend
Status
5
Erase
Error
4
Program
Error
3
VPP
Error
2
Program Suspend
Status
1
Protection
Error
0
RESERVED
P/E Controller Status bit
The bit 7 of the Flag Status register represents the Program/Erase Controller Status bit, It
indicates whether there is a Program/Erase internal cycle active. When P/E Controller
Status bit is Low (FSR<7>=0) the device is busy; when the bit is High (FSR<7>=1) the
device is ready to process a new command.
This bit has the same meaning of Write In Progress (WIP) bit of the standard SPI Status
Register, but with opposite logic: FSR<7> = not WIP
It's possible to make the polling instructions, to check if the internal modify operations are
finished, both on the Flag Status register bit 7 or on WIP bit of the Status Register.
42/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
N25Q032 - 3 V
6.5.2
Volatile and Non Volatile Registers
Erase Suspend Status bit
The bit 6 of the Flag Status register represents the Erase Suspend Status bit, It indicates
that an Erase operation has been suspended or is going to be suspended.
The bit is set (FSR<6>=1) within the Erase Suspend Latency time, that is as soon as the
Program/Erase Suspend command (PES) has been issued, therefore the device may still
complete the operation before entering the Suspend Mode.
The Erase Suspend Status should be considered valid when the P/E Controller bit is high
(FSR<7>=1).
When a Program/Erase Resume command (PER) is issued the Erase Suspend Status bit
returns Low (FSR<6>=0)
6.5.3
Erase Status bit
The bit 5 of the Flag Status Register represents the Erase Status bit. It indicates an erase
failure or a protection error when an erase operation is issued.
When the Erase Status bit is High (FSR<5>=1) after an Erase failure that means that the
P/E Controller has applied the maximum pulses number to the portion to be erased and still
failed to verify that it has correctly erased.
The Erase Status bit should be read once the P/E Controller Status bit is High.
The Erase Status bit is related to all possible erase operations: Sector Erase, Sub Sector
Erase, and Bulk Erase in all the three available protocols (SPI, DIO-SPI and QIO-SPI).
Once the bit 5 is set High, it can only be reset Low (FSR<5>=0) by a Clear Flag Status
Register command (CLFSR).
If set High it should be reset before a new Erase command is issued; otherwise the new
command will appear to fail.
6.5.4
Program Status bit
The bit 4 of the Flag Status Register represents the Program Status bit. It indicates:
z
a Program failure
z
an attempt to program a '1' on '0' when VPP=VPPH (only when the pattern is a multiple
of 64 bits, otherwise this bit is "Don't care").
z
a protection error when a program is issued
When the Program Status bit is High (FSR<4>=1) after a Program failure that means that
the P/E Controller has applied the maximum pulses number to the bytes and it still failed to
verify that the required data have been correctly programmed.
After an attempt to program '1' on '0', the FSR<4> only goes High (FSR<4>=1) if
VPP=VPPH and the data pattern is a multiple of 64 bits: if VPP is not VPPH, FSR<4>
remains Low and the attempt is not shown while if VPP is equal to VPPh but the pattern is
not a 64 bits multiple the bit 4 is Don't Care. The Program Status bit should be read once the
P/E Controller Status bit is High.
The Program Status bit is related to all possible program operations in the Extended SPI
protocol: Page Program, Dual and Quad Input Fast Program, Dual and Quad Input
Extended Fast Program, and OTP Program.
43/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
Volatile and Non Volatile Registers
N25Q032 - 3 V
The Program Status bit is related to the following program operations in the DIO-SPI and
QIO-SPI protocols: Dual and Quad Command Page program and OTP program.
Once the bit is set High, it can only be reset Low (FSR<4>=0) by a Clear Flag Status
Register command (CLFSR). If set High it should be reset before a new Program command
is issued, otherwise the new command will appear to fail.
6.5.5
VPP Status bit
The bit 3 of the Flag Status Register represents the VPP Status bit. It indicates an invalid
voltage on the VPP pin during Program and Erase operations. The VPP pin is sampled at
the beginning of a Program or Erase operation.
If VPP becomes invalid during an operation, that is the voltage on VPP pin is below the
VPPH Voltage (9V), the VPP Status bit goes High (FSR<3>=1) and indeterminate results
can occur.
Once set High, the VPP Status bit can only be reset Low (FSR<3>=0) by a Clear Flag Status
Register command (CLFSR). If set High it should be reset before a new Program or Erase
command is issued; otherwise, the new command will appear to fail.
6.5.6
Program Suspend Status bit
The bit 2 of the Flag Status register represents the Program Suspend Status bit. It indicates
that a Program operation has been suspended or is going to be suspended.
The bit is set (FSR<2>=1) within the Program Suspend Latency time; that is, as soon as the
Program/Erase Suspend command (PES) has been issued. Therefore the device may still
complete the operation before entering the Suspend Mode.
The Program Suspend Status should be considered valid when the P/E Controller bit is high
(FSR<7>=1).
When a Program/Erase Resume command (PER) is issued the Program Suspend Status bit
returns Low (FSR<2>=0)
6.5.7
Protection Status bit
The bit 1 of the Flag Status Register represents the Protection Status bit. It indicates that an
Erase or Program operation has tried to modify the contents of a protected array sector, or
that a modify operation has tried to access to a locked OTP space. The Protection Status bit
is related to all possible protection violations as follows:
n
The sector is protected by Software Protection Mode 1 (SPM1) Lock registers,
n
The sector is protected by Software Protection Mode 2 (SPM2) Block Protect Bits
(standard SPI Status Register),
n
An attempt to program OTP when locked,
n
A Write Status Register command (WRSR) on STD SPI Status Register when locked by
the SRWD bit in conjunction with the Write Protect (W/VPP) signal (Hardware Protection
Mode).
Once set High, the Protection Status bit can only be reset Low (FSR<1>=0) by a Clear Flag
Status Register command (CLFSR). If set High it should be reset before a new command is
issued, otherwise the new command will appear to fail.
44/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
N25Q032 - 3 V
7
Protection modes
Protection modes
There are protocol-related and specific hardware and software protection modes. They are
described below.
7.1
SPI Protocol-related protections
This applies to all three protocols. The environments where non-volatile memory devices
are used can be very noisy. No SPI device can operate correctly in the presence of
excessive noise. To help combat this, the N25Q032 features the following data protection
mechanisms:
z
Power On Reset and an internal timer (tVTW) can provide protection against
inadvertent changes while the power supply is outside the operating specification.
z
Program, Erase, and Write Status Register instructions are checked to ensure the
instruction includes a number of clock pulses that is a multiple of a byte before they are
accepted for execution.
z
All instructions that modify data must be preceded by a Write Enable (WREN)
instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state
by the following events (in Extended SPI protocol mode):
–
Power-up
–
Write Disable (WRDI) instruction completion
–
Write Status Register (WRSR) instruction completion
–
Write to Lock Register (WRLR) instruction completion
–
Program OTP (POTP) instruction completion
–
Page Program (PP) instruction completion
–
Dual Input Fast Program (DIFP) instruction completion
–
Dual Input Extended Fast Program (DIEFP) instruction completion
–
Quad Input Fast Program (QIFP) instruction completion
–
Quad Input Extended Fast Program (QIEFP) instruction completion
–
Subsector Erase (SSE) instruction completion
–
Sector Erase (SE) instruction completion
–
Bulk Erase (BE) instruction completion
–
Write Non-Volatile Configuration Register (WRNVCR) instruction completion
This bit is also returned to its reset state after all the analogous events in DIO-SPI and QIOSPI protocol modes.
45/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
Protection modes
7.2
N25Q032 - 3 V
Specific hardware and software protection
There are two software protected modes, SPM1 and SPM2, that can be combined to protect
the memory array as required. The SPM2 can be locked by hardware with the help of the W
input pin.
SPM1
The first software protected mode (SPM1) is managed by specific Lock Registers assigned
to each 64 Kbyte sector.
The Lock Registers can be read and written using the Read Lock Register (RDLR) and
Write to Lock Register (WRLR) instructions.
In each Lock Register two bits control the protection of each sector: the Write Lock bit and
the Lock Down bit.
z
Write Lock bit: The Write Lock bit determines whether the contents of the sector can be
modified (using the Program or Erase instructions). When the Write Lock bit is set to '1',
the sector is write protected - any operations that attempt to change the data in the
sector will fail. When the Write Lock bit is reset to '0', the sector is not write protected by
the Lock Register, and may be modified.
z
Lock Down bit: The Lock Down bit provides a mechanism for protecting software data
from simple hacking and malicious attack. When the Lock Down bit is set to '1', further
modification to the Write Lock and Lock Down bits cannot be performed. A powerup is
required before changes to these bits can be made. When the Lock Down bit is reset to
'0', the Write Lock and Lock Down bits can be changed.
The definition of the Lock Register bits is given in Table 19.: Lock Register out.
SPM2
The second software protected mode (SPM2) uses the Block Protect bits (BP2, BP1, BP0)
and the Top/Bottom bit (TB bit) to allow part of the memory to be configured as read-only.
See Section 16: Ordering information.
Table 9.
Software protection truth table (Sectors 0 to 63, 64 Kbyte granularity)
Sector Lock Register
Protection Status
Lock Down
bit
Write Lock
bit
0
0
Sector unprotected from Program/Erase operations, protection status reversible.
0
1
Sector protected from Program/Erase operations, protection status reversible.
1
0
Sector unprotected from Program/Erase operations.
Sector protection status cannot be changed except by a power-up.
1
1
Sector protected from Program/Erase operations.
Sector protection status cannot be changed except by a power-up.
As a second level of protection, the Write Protect signal (applied on the W/VPP pin) can
freeze the Status Register in a read-only mode. In this mode, the Block Protect bits (BP2,
BP1, BP0), the Top/Bottom (TB) bit, and the Status Register Write Disable bit (SRWD) are
protected.
46/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
N25Q032 - 3 V
Table 10.
Protection modes
Protected area sizes, Upper (TB bit = 0)
Status Register Content
Memory Content
TB bit BP2 Bit BP1 Bit BP0 Bit
Protected Area
Unprotected Area
0
0
0
0
None
All sectors
0
0
0
1
Upper 64th
Sectors 0 to 62
0
0
1
0
Upper 32th
Sectors 0 to 61
0
0
1
1
Upper 16th
Sectors 0 to 59
0
1
0
0
Upper eighth
Sectors 0 to 55
0
1
0
1
Upper quarter
Sectors 0 to 47
0
1
1
0
Upper half
Sectors 0 to 31
0
1
1
1
All sectors
None
Table 11.
Protected area sizes, Lower (TB bit = 1)
Status Register Content
Memory Content
TB bit BP2 Bit BP1 Bit BP0 Bit
Protected Area
Unprotected Area
1
0
0
0
None
All sectors
1
0
0
1
Lower 64th
Sectors 1 to 63
1
0
1
0
Lower 32nd
Sectors 2 to 63
1
0
1
1
Lower 16th
Sectors 4 to 63
1
1
0
0
Lower eighth
Sectors 8 to 63
1
1
0
1
Lower quarter
Sectors 16 to 63
1
1
1
0
Lower half
Sectors 32 to 63
1
1
1
1
All sectors
None
47/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
Memory organization
8
N25Q032 - 3 V
Memory organization
The memory is organized as:
z
4,194,304 bytes (8 bits each)
z
64 sectors (64 Kbytes each)
z
1,024 subsectors (4 Kbytes each)
z
16,384 pages (256 bytes each)
z
64 OTP bytes located outside the main memory array
Each page can be individually programmed: bits are programmed from 1 to 0. The device is
Subsector eraseble, Sector eraseble or Bulk Erasable but not Page Erasable: bits are
erased from 0 to 1.
Figure 9.
Block diagram
HOLD
W/VPP
High voltage
generator
Control logic
64 OTP bytes
S
C
DQ0
I/O shift register
DQ1
Address register
and counter
Status
register
256 byte
data buffer
Y decoder
3FFFFFh
00000h
000FFh
256 bytes (page size)
X decoder
AI13722b
48/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
N25Q032 - 3 V
Memory organization
Subsector
...
...
...
...
...
340FFFh
1007
3EF000h
3EFFFFh
831
33F000h
33FFFFh
...
...
...
...
...
...
51
992
3E0000h
3E0FFFh
816
330000h
330FFFh
991
3DF000h
3DFFFFh
815
32F000h
32FFFFh
...
...
...
...
...
...
50
976
3D0000h
3D0FFFh
800
320000h
320FFFh
975
3CF000h
3CFFFFh
799
31F000h
31FFFFh
...
...
...
...
...
...
49
960
3C0000h
3C0FFFh
784
310000h
310FFFh
959
3BF000h
3BFFFFh
783
30F000h
30FFFFh
...
...
...
...
...
...
48
944
3B0000h
3B0FFFh
768
300000h
300FFFh
943
3AF000g
3AFFFFh
767
2FF000h
2FFFFFh
...
...
...
...
...
47
928
3A0000h
3A0FFFh
752
2F0000h
2F0FFFh
927
39F000h
39FFFFh
751
2EF000h
2EFFFFh
...
...
...
...
...
46
912
390000h
390FFFh
736
2E0000h
2E0FFFh
911
38F000h
38FFFFh
735
2DF000h
2DFFFFh
...
...
...
...
...
45
896
380000h
380FFFh
720
2D0000h
2D0FFFh
895
37F000h
37FFFFh
719
2CF000h
2CFFFFh
...
...
...
...
44
880
370000h
370FFFh
704
2C0000h
2C0FFFh
879
36F000h
36FFFFh
703
2BF000h
2BFFFFh
...
...
...
...
43
864
360000h
360FFFh
688
2B0000h
2B0FFFh
863
35F000h
35FFFFh
687
2AF000h
2AFFFFh
42
848
350000h
350FFFh
...
53
340000h
...
54
832
...
55
3F0FFFh
...
56
3F0000h
...
57
1008
...
58
34FFFFh
...
59
52
34F000h
...
60
847
Address range
...
61
Subsector
...
62
3FFFFFh
...
63
3FF000h
Sector
...
1023
Address range
...
Sector
Memory organization
...
Table 12.
672
2A0000h
2A0FFFh
49/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
Memory organization
Subsector
...
...
...
...
...
1E0FFFh
655
28F000h
28FFFFh
479
1DF000h
1DFFFFh
...
...
...
...
...
...
29
640
280000h
280FFFh
464
1D0000h
1D0FFFh
639
27F000h
27FFFFh
463
1CF000h
1CFFFFh
...
...
...
...
...
...
28
624
270000h
270FFFh
448
1C0000h
1C0FFFh
623
26F000h
26FFFFh
447
1BF000h
1BFFFFh
...
...
...
...
...
...
27
608
260000h
260FFFh
432
1B0000h
1B0FFFh
607
25F000h
25FFFFh
431
1AF000h
1AFFFFh
...
...
...
...
...
...
26
592
250000h
250FFFh
416
1A0000h
1A0FFFh
591
24F000h
24FFFFh
415
19F000h
19FFFFh
...
...
...
...
...
25
576
240000h
240FFFh
400
190000h
190FFFh
575
23F000h
23FFFFh
399
18F000h
18FFFFh
...
...
...
...
...
24
560
230000h
230FFFh
384
180000h
180FFFh
559
22F000h
22FFFFh
383
17F000h
17FFFFh
...
...
...
...
...
23
544
220000h
220FFFh
368
170000h
170FFFh
543
21F000h
21FFFFh
367
16F000h
16FFFFh
...
...
...
...
22
528
210000h
210FFFh
352
160000h
160FFFh
527
20F000h
20FFFFh
351
15F000h
15FFFFh
...
...
...
...
21
512
200000h
200FFFh
336
150000h
150FFFh
511
1FF000h
1FFFFFh
335
14F000h
14FFFFh
20
496
1F0000h
1F0FFFh
...
31
1E0000h
...
32
480
...
33
290FFFh
...
34
290000h
...
35
656
...
36
1EFFFFh
...
37
30
1EF000h
...
38
495
Address range
...
39
Subsector
...
40
29FFFFh
...
41
29F000h
Sector
...
671
Address range
...
Sector
Memory organization (continued)
...
Table 12.
N25Q032 - 3 V
320
140000h
140FFFh
50/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
N25Q032 - 3 V
Memory organization
Subsector
...
...
...
...
...
128
80000h
80FFFh
303
12F000h
12FFFFh
127
7F000h
7FFFFh
...
...
...
...
...
...
7
288
120000h
120FFFh
112
70000h
70FFFh
287
11F000h
11FFFFh
111
6F000h
6FFFFh
...
...
...
...
...
...
6
272
110000h
110FFFh
96
60000h
60FFFh
271
10F000h
10FFFFh
95
5F000h
5FFFFh
...
...
...
...
...
...
5
256
100000h
100FFFh
80
50000h
50FFFh
255
FF000h
FFFFFh
79
4F000h
4FFFFh
...
...
...
...
...
4
240
F0000h
F0FFFh
64
40000h
40FFFh
239
EF000h
EFFFFh
63
3F000h
3FFFFh
...
...
...
...
...
3
224
E0000h
E0FFFh
48
30000h
30FFFh
223
DF000h
DFFFFh
47
2F000h
2FFFFh
...
...
...
...
...
2
208
D0000h
D0FFFh
32
20000h
20FFFh
207
CF000h
CFFFFh
31
1F000h
1FFFFh
...
...
192
C0000h
C0FFFh
16
10000h
10FFFh
191
BF000h
BFFFFh
15
0F000h
0FFFFh
...
...
1
...
11
130FFFh
...
12
130000h
...
13
304
...
14
176
B0000h
B0FFFh
4
04000h
04FFFh
175
AF000h
AFFFFh
3
03000h
03FFFh
2
02000h
02FFFh
10
0
A0FFFh
1
01000h
01FFFh
159
9F000h
9FFFFh
0
00000h
00FFFh
...
A0000h
...
160
...
9
8FFFFh
...
15
8
8F000h
...
16
143
Address range
...
17
Subsector
...
18
13FFFFh
...
19
13F000h
Sector
...
319
Address range
...
Sector
Memory organization (continued)
...
Table 12.
144
90000h
90FFFh
51/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
Instructions
9
N25Q032 - 3 V
Instructions
The device can work in three different protocols: Extended SPI, DIO-SPI and QIO-SPI.
Each protocol has a dedicated instruction set, and each instruction set features the same
functionality:
z
Read, program and erase the memory and the 64 byte OTP area,
z
Suspend and resume the program or erase operations,
z
Read and modify all the registers, read the Serial Flash Discovery Parameter area
(SFDP), and read the device ID: please note that in this case there is a small
functionality difference among the single and the multiple I/O read ID instructions. See
Section 9.2.1: Multiple I/O Read Identification protocol and Section 9.3.1: Multiple I/O
Read Identification (MIORDID).
The application can choose in every time of the device life which protocol to use by setting
the dedicated bits either in the Non Volatile Configuration Register or the Volatile Enhanced
Configuration Register.
Note:
In multiple SPI protocols, all instructions, addresses, and data are parallel on two lines (DIOSPI protocol) or four lines (QIO-SPI protocol).
All instructions, addresses and data are shifted in and out of the device, most significant bit
first.
Serial Data input(s) is (are) sampled on the first rising edge of Serial Clock (C) after Chip
Select (S) is driven Low. Then, the one-byte instruction code must be shifted in to the
device, most significant bit first, on Serial Data input(s), each bit being latched on the rising
edges of Serial Clock (C). Instruction code is shifted into the device just on DQ0 in Extended
SPI protocol, on DQ0 and DQ1 in DIO-SPI protocol and on DQ0, DQ1, DQ2, and DQ3 in
QIO-SPI protocol.
In standard mode every instruction sequence starts with a one-byte instruction code.
Depending on the instruction, this might be followed by address bytes, or by data bytes, or
by both or none.
In XIP modes only read operation and exit XIP mode can be performed, and to read the
memory content no instructions code are needed: the device directly receives addresses
and after a configurable number of dummy clock cycles, it outputs the required data.
9.1
Extended SPI Instructions
In Extended SPI protocol instruction set the instruction code is always shifted into the device
just on DQ0 pin, while depending on the instruction addresses and input/output data can run
on single, two or four wires.
In the case of a Read Instructions Data Bytes (READ), Read Data Bytes at Higher Speed
(FAST_READ), Dual Output Fast Read (DOFR), Dual Input/Output Fast Read (DIOFR),
Quad Output Fast Read (QOFR), Quad Input/Output Fast Read (QIOFR), Read OTP
(ROTP), Read Lock Registers (RDLR), Read Status Register (RDSR), Read Flag Status
Register (RFSR), Read NV Configuration Register (RDNVCR), Read Volatile Configuration
Register (RDVCR), Read Volatile Enhanced Configuration Register (RDVECR), Read Serial
Flash Discovery Parameter (RDSFDP), and Read Identification (RDID) instruction, the
shifted-in instruction sequence is followed by a data-out sequence. Chip Select (S) can be
driven High after any bit of the data-out sequence is being shifted out.
52/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
N25Q032 - 3 V
Instructions
In the case of a Page Program (PP), Program OTP (POTP), Dual Input Fast Program
(DIFP), Dual Input Extended Fast Program (DIEFP), Quad Input Fast Program (QIFP),
Quad Input Extended Fast Program (QIEFP), Subsector Erase (SSE), Sector Erase (SE),
Bulk Erase (BE), Write Status Register (WRSR), Clear Flag Status Register (CLFSR), Write
to Lock Register (WRLR), Write Configuration Register (WRVCR), Write Enhanced
Configuration Register (WRVECR), Write NV Configuration Register (WRNVCR), Write
Enable (WREN) or Write Disable (WRDI) instruction, Chip Select (S) must be driven High
exactly at a byte boundary, otherwise the instruction is rejected, and is not executed. That
is, Chip Select (S) must driven High when the number of clock pulses after Chip Select (S)
being driven Low is an exact multiple of eight.
All attempts to access the memory array are ignored during:
–
Write Status Register cycle
–
Write Non Volatile Configuration Register
–
Program cycle
–
Erase cycle
The following continue unaffected, with one exception:
–
Internal Write Status Register cycle,
–
Write Non Volatile Configuration Register,
–
Program cycle,
–
Erase cycle
The only exception is the Program/Erase Suspend instruction (PES), that can be used to
pause all the program and the erase cycles except for:
–
Program OTP (POTP),
–
Bulk Erase,
–
Write Status Register,
–
Write Non Volatile Configuration Register.
The suspended program or erase cycle can be resumed by the Program/Erase Resume
instruction (PER). During the program/erase cycles, the polling instructions (both on the
Status register and on the Flag Status register) are also accepted to allow the application to
check the end of the internal modify cycles.
Note:
These polling instructions don't affect the internal cycles performing.
53/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
Instructions
Table 13.
N25Q032 - 3 V
Instruction set: extended SPI protocol (page 1 of 2)
Instruction
Description
One-byte
One-byte
Instruction Address Dummy
Instruction
Code
bytes
clock
Code (BIN)
(HEX)
cycle
Data
bytes
RDID
Read Identification
1001 111x
9Eh / 9Fh
0
0
1 to 20
READ
Read Data Bytes
0000 0011
03h
3
0
1 to ∞
0000 1011
0Bh
3
8 (1)
1 to ∞
3
8
(1)
1 to ∞
8
(1)
1 to ∞
(1)
1 to ∞
1 to ∞
FAST_READ Read Data Bytes at Higher Speed
RDSFDP
DOFR
Read Serial Flash Discovery Parameter
Dual Output Fast Read
01011010
0011 1011
5Ah
3Bh
3
DIOFR
Dual Input/Output Fast Read
1011 1011
BB
3
8
QOFR
Quad Output Fast Read
0110 1011
6Bh
3
8 (1)
QIOFR
Quad Input/Output Fast Read
1110 1011
EBh
3
10
(1
(1)
1 to ∞
1 to 65
ROTP
Read OTP (Read of OTP area)
0100 1011
4Bh
3
8
WREN
Write Enable
0000 0110
06h
0
0
0
WRDI
Write Disable
0000 0100
04h
0
0
0
PP
Page Program
0000 0010
02h
3
0
1 to 256
DIFP
Dual Input Fast Program
1010 0010
A2h
3
0
1 to 256
DIEFP
Dual Input Extended Fast Program
1101 0010
D2h
3
0
1 to 256
QIFP
Quad Input Fast Program
0011 0010
32h
3
0
1 to 256
QIEFP
Quad Input Extended Fast Program
0001 0010
12h
3
0
1 to 256
POTP
Program OTP (Program of OTP area)
0100 0010
42h
3
0
1 to 65
SSE
SubSector Erase
0010 0000
20h
3
0
0
SE
Sector Erase
1101 1000
D8h
3
0
0
BE
Bulk Erase
1100 0111
C7h
0
0
0
PER
Program/Erase Resume
0111 1010
7Ah
0
0
0
PES
Program/Erase Suspend
0111 0101
75h
0
0
0
RDSR
Read Status Register
0000 0101
05h
0
0
1 to ∞
WRSR
Write Status Register
0000 0001
01h
0
0
1
RDLR
Read Lock Register
1110 1000
E8h
3
0
1 to ∞
WRLR
Write to Lock Register
1110 0101
E5h
3
0
1
RFSR
Read Flag Status Register
0111 0000
70h
0
0
1 to ∞
CLFSR
Clear Flag Status Register
0101 0000
50h
0
0
0
RDNVCR
Read NV Configuration Register
1011 0101
B5h
0
0
2
WRNVCR
Write NV Configuration Register
1011 0001
B1h
0
0
2
RDVCR
Read Volatile Configuration Register
1000 0101
85h
0
0
1 to ∞
WRVCR
Write Volatile Configuration Register
1000 0001
81h
0
0
1
54/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
N25Q032 - 3 V
Table 13.
Instructions
Instruction set: extended SPI protocol (page 2 of 2)
Instruction
One-byte
One-byte
Instruction Address Dummy
Instruction
Code
bytes
clock
Code (BIN)
(HEX)
cycle
Description
Data
bytes
RDVECR
Read Volatile Enhanced Configuration
Register
0110 0101
65h
0
0
1 to ∞
WRVECR
Write Volatile Enhanced Configuration
Register
0110 0001
61h
0
0
1
1. The Number of dummy clock cycles is configurable by user
9.1.1
Read Identification (RDID)
The Read Identification (RDID) instruction allows to read the device identification data:
–
Manufacturer identification (1 byte)
–
Device identification (2 bytes)
–
A Unique ID code (UID) (17 bytes, of which 14 are factory programmed
The manufacturer identification is assigned by JEDEC, and has the value 20h. The device
identification is assigned by the device manufacturer, and indicates the memory type in the
first byte (BAh), and the memory capacity of the device in the second byte (16h). The UID is
composed by 17 read only bytes, containing the length of the following data in the first byte
(set to 10h), 2 bytes of Extended Device ID (EDID) to identify the specific device
configuration (Top, Bottom or uniform architecture, Hold or Reset functionality), and 14
bytes of the optional Customized Factory Data (CFD) content. The CFD bytes are factory
programmed with specific data for each device.
Any Read Identification (RDID) instruction while an Erase or Program cycle is in progress, is
not decoded, and has no effect on the cycle that is in progress.
The device is first selected by driving Chip Select (S) Low. Then, the 8-bit instruction code
for the instruction is shifted in. After this, the 24-bit device identification, stored in the
memory, the 17 bytes of UID content will be shifted out on Serial Data output (DQ1). Each
bit is shifted out during the falling edge of Serial Clock (C).
The instruction sequence is shown in Figure 10.
The Read Identification (RDID) instruction is terminated by driving Chip Select (S) High at
any time during data output.
When Chip Select (S) is driven High, the device is put in the Standby Power mode. Once in
the Standby Power mode, the device waits to be selected, so that it can receive, decode and
execute instructions.
Table 14.
Read Identification data-out sequence
Manufacturer
Identification
20h
Device identification
UID
Memory type
Memory capacity
EDID+CFD length
EDID
CFD
BAh
16h
10h
2 bytes
14 bytes
55/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
Instructions
Table 15.
Bit 7
N25Q032 - 3 V
Extended Device ID table (first byte)
Bit 6
Bit 5
Bit 4
Reserved Reserved Reserved
VCR XIP bit setting:
0 = required,
1 = not required
Bit 3
Bit 2
Hold/Reset function:
0 = HOLD,
1 = Reset
Bit 1
Addressing:
0 = by Byte,
Bit 0
Architecture:
00 = Uniform,
Figure 10. Read identification instruction and data-out sequence
S
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18
28 29 30 31
C
Instruction
DQ0
Manufacturer identification
UID
Device identification
High Impedance
DQ1
15 14 13
MSB
9.1.2
MSB
3
2
1
0
MSB
Read Data Bytes (READ)
The device is first selected by driving Chip Select (S) Low. The instruction code for the Read
Data Bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit being
latched-in during the rising edge of Serial Clock (C). Then the memory contents at that
address are shifted out on Serial Data output (DQ1), each bit being shifted out at a
maximum frequency fR during the falling edge of Serial Clock (C).
The first byte addressed can be at any location. The address is automatically incremented
to the next higher address after each byte of data is shifted out. The whole memory can,
therefore, be read with a single Read Data Bytes (READ) instruction. When the highest
address is reached, the address counter rolls over to 000000h, allowing the read sequence
to be continued indefinitely.
The Read Data Bytes (READ) instruction is terminated by driving Chip Select (S) High. Chip
Select (S) can be driven High at any time during data output. Any Read Data Bytes (READ)
instruction, while an Erase or Program cycle is in progress, is rejected without having any
effects on the cycle that is in progress.
56/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
N25Q032 - 3 V
Instructions
Figure 11.
Read Data Bytes instruction and data-out sequence
S
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
C
Instruction
24-bit address*
23 22 21
DQ0
3
2
1
0
MSB
Data Out 1
High Impedance
DQ1
7
6
5
4
3
Data Out 2
2
1
0
7
MSB
Address bits A23 and A22 are “Don’t Care.”
9.1.3
Read Data Bytes at Higher Speed (FAST_READ)
The device is first selected by driving Chip Select (S) Low. The instruction code for the Read
Data Bytes at Higher Speed (FAST_READ) instruction is followed by a 3-byte address (A23A0) and a configurable number of dummy clock cycles, each bit being latched-in during the
rising edge of Serial Clock (C).
Then the memory contents, at that address, are shifted out on Serial Data output (DQ1) at a
maximum frequency fC, during the falling edge of Serial Clock (C).
The first byte addressed can be at any location. The address is automatically incremented
to the next higher address after each byte of data is shifted out. The whole memory can,
therefore, be read with a single Read Data Bytes at Higher Speed (FAST_READ)
instruction. When the highest address is reached, the address counter rolls over to
000000h, allowing the read sequence to be continued indefinitely.
The Read Data Bytes at Higher Speed (FAST_READ) instruction is terminated by driving
Chip Select (S) High. Chip Select (S) can be driven High at any time during data output. Any
Read Data Bytes at Higher Speed (FAST_READ) instruction, while an Erase or Program
cycle is in progress, is rejected without having any effects on the cycle that is in progress.
57/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
Instructions
N25Q032 - 3 V
Figure 12. Read Data Bytes at Higher Speed instruction and data-out sequence
S
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
C
Instruction
24-bit address*
23 22 21
DQ0
3
2
1
0
High Impedance
DQ1
S
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
C
Dummy cycles
DQ0
7
6
5
4
3
2
1
0
DATA OUT 2
DATA OUT 1
DQ1
7
6
5
4
3
2
1
0
7
6
MSB
MSB
5
4
3
2
1
0
7
MSB
*Address bits A23 and A22 are “Don’t Care.”
9.1.4
Read Serial Flash Discovery Parameter
The Read Serial Flash Discovery Parameter (RDSFDP) instruction allows reading the Serial
Flash Discovery Parameter area (SFDP). This SFDP area is composed of 2048 read-only
bytes containing operating characteristics and vendor specific information. The SFDP area
is factory programmed.
Note:
Data to be written to the SFDP area is in definition phase.
If the SFDP area is blank, the device is shipped with all the SFDP bytes at FFh. If only a
portion of the SFDP area is written to, the portion not used is shipped with bytes in erased
state (FFh).
The instruction sequence for RDSFDP has the same structure as that of a Fast Read
instruction. First, the device is selected by driving Chip Select (S) Low. Next, the 8-bit
instruction code (5Ah) and the 24-bit address are shifted in, followed by a configurable
number of dummy clock cycles.
Therefore, the entire SFDP area can be read with a single RDSFDP instruction. When the
highest address (7FFh) is reached, the address counter rolls over to 000h, allowing the read
sequence to be continued indefinitely.
58/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
N25Q032 - 3 V
Instructions
The bytes of SFDP content are shifted out on the Serial Data Output (DQ1) starting from the
specified address. Each bit is shifted out during the falling edge of Serial Clock (C). The
Read SFDP instruction is terminated by driving Chip Select (S) High at any time during data
output.
Any Read Serial Flash Discovery Parameter (RDSFDP) instruction issued while an Erase or
Program cycle is in progress, is rejected without having any effect on the cycle that is in
progress.
Figure 13. Read Serial Flash Discovery Sequence
S
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
C
Instruction
24-bit address*
23 22 21
DQ0
3
2
1
0
High Impedance
DQ1
S
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
C
Dummy cycles
DQ0
7
6
5
4
3
2
1
0
DATA OUT 2
DATA OUT 1
DQ1
7
6
5
4
MSB
3
2
1
0
7
MSB
6
5
4
3
2
1
0
7
MSB
*Address bits A[23:11] are “Don’t Care.”
9.1.5
Dual Output Fast Read (DOFR)
The Dual Output Fast Read (DOFR) instruction is very similar to the Read Data Bytes at
Higher Speed (FAST_READ) instruction, except that the data are shifted out on two pins
(pin DQ0 and pin DQ1) instead of only one. Outputting the data on two pins instead of one
doubles the data transfer bandwidth compared to the Read Data Bytes at Higher Speed
(FAST_READ) instruction.
The device is first selected by driving Chip Select (S) Low. The instruction code for the Dual
Output Fast Read instruction is followed by a 3-byte address (A23-A0) and a configurable
number of dummy clock cycles, each bit being latched-in during the rising edge of Serial
Clock (C). Then the memory contents, at that address, are shifted out on DQ0 and DQ1 at a
maximum frequency Fc, during the falling edge of Serial Clock (C).
The first byte addressed can be at any location. The address is automatically incremented
to the next higher address after each byte of data is shifted out on DQ0 and DQ1. The whole
memory can, therefore, be read with a single Dual Output Fast Read (DOFR) instruction.
59/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
Instructions
N25Q032 - 3 V
When the highest address is reached, the address counter rolls over to 00 0000h, so that
the read sequence can be continued indefinitely.
Figure 14. Dual Output Fast Read instruction sequence
S
Mode 3
C
0
1
2
3
4
5
6
7
8
Instruction
28 29 30 31
*24-bit Address
23 22 21
DQ0
DQ1
9 10
Mode 2
3
2
1
0
High Impedance
S
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
C
Dummy cycles
DQ0
6
4
2
0
DATA OUT 1
DQ1
7
MSB
5
3
1
6
4
2
0
DATA OUT 2
7
5
MSB
3
1
6
4
2
0
DATA OUT 3
7
MSB
5
3
1
6
4
2
0
DATA OUT n
7
MSB
5
3
1
MSB
*Address bits A23 and A22 are “Don’t Care.”
9.1.6
Dual I/O Fast Read
The Dual I/O Fast Read (DIOFR) instruction is very similar to the Dual Output Fast Read
(DOFR), except that the address bits are shifted in on two pins (pin DQ0 and pin DQ1)
instead of only one.
60/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
N25Q032 - 3 V
Instructions
Figure 15. Dual I/O Fast Read instruction sequence
S
Mode 3
C
0
1
2
3
4
5
6
7
8
10 11 12 13 14 15 16 17 18 19 20
9
Mode 0
*24-bit Address
Instruction
DQ0
22 20 18 16 14 12 10
8
6
4
2
0
DQ1
23 21 19 17 15 13 11
9
7
5
3
1
Dummy Cycles
S
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
C
IO switches from Input to Output
6
4
2
0
6
4
2
0
6
4
2
0
6
4
2
0
6
7
5
3
1
7
5
3
1
7
5
3
1
7
5
3
1
7
DQ0
DQ1
Byte 1
Byte 2
Byte 3
Byte 4
*Address bits A23 and A22 are “Don’t Care.”
9.1.7
Quad Output Fast Read
The Quad Output Fast Read (QOFR) instruction is very similar to the Dual Output Fast
Read (DOFR) instruction, except that the data are shifted out on four pins (pin DQ0, pin
DQ1, pin W/VPP/DQ2 and pin HOLD/DQ3 (1) instead of only two. Outputting the data on
four pins instead of one doubles the data transfer bandwidth compared to the Dual Output
Fast Read (DOFR) instruction.
The device is first selected by driving Chip Select (S) Low. The instruction code for the Quad
Output Fast Read instruction is followed by a 3-byte address (A23-A0) and a configurable
number of dummy clock cycles, each bit being latched-in during the rising edge of Serial
Clock (C). Then the memory contents, at that address, are shifted out on pin DQ0, pin DQ1,
pin W/VPP/DQ2 and pin HOLD/DQ3 (1) at a maximum frequency fC, during the falling edge
of Serial Clock (C).
The first byte addressed can be at any location. The address is automatically incremented
to the next higher address after each byte of data is shifted out on pin DQ0, pin DQ1, pin
W/VPP/DQ2 and pin HOLD/DQ3 (1). The whole memory can, therefore, be read with a
single Quad Output Fast Read (QOFR) instruction.
When the highest address is reached, the address counter rolls over to 00 0000h, so that
the read sequence can be continued indefinitely.
Note:
Reset functionality is available instead of Hold in devices with a dedicated part number. See
Section 16: Ordering information.
61/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
Instructions
N25Q032 - 3 V
Figure 16. Quad Output Fast Read instruction sequence
S
Mode 3
C
1
0
2
3
4
5
6
7
8
9 10 11
30 31 32
39 40 41 42 43 44 45
Mode 0
IO switches from Input to Output
*24-bit Address
Instruction
23 22 21 20
DQ0
1
0
4
0
4
0
4
5
1
5
1
5
6
2
6
2
6
7
3
7
3
7
Don’t Care
DQ1
Don’t Care
DQ2
DQ3
‘1’
Dummy (ex.: 10)
Byte 1 Byte 2
*Address bits A23 and A22 are “Don’t Care.”
9.1.8
Quad I/O Fast Read
The Quad I/O Fast Read (QIOFR) instruction is very similar to the Quad Output Fast Read
(QOFR), except that the address bits are shifted in on four pins (pin DQ0, pin DQ1, pin
W/VPP/DQ2 and pin HOLD/DQ3 (1)) instead of only one.
Note:
Reset functionality is available instead of Hold in devices with a dedicated part number. See
Section 16: Ordering information.
Figure 17. Quad Input/ Output Fast Read instruction sequence
S
Mode 3
C
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
21 22 23 24 25 26 27
Mode 0
IO switches from Input to Output
Instruction
DQ0
DQ1
DQ2
20 16 12 8
4
0
4
0
4
0
4
21 17 13 9
5
1
5
1
5
1
5
22 18 14 10
6
2
6
2
6
2
6
23 19 15 11
7
3
7
3
7
3
7
Don’t Care
Don’t Care
DQ3
‘1’
*24-bit Address
Dummy (ex.: 10)
Byte 1 Byte 2
*Address bits A23 and A22 are “Don’t Care.”
62/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
N25Q032 - 3 V
9.1.9
Instructions
Read OTP (ROTP)
The device is first selected by driving Chip Select (S) Low. The instruction code for the Read
OTP (ROTP) instruction is followed by a 3-byte address (A23- A0) and a configurable
number of dummy clock cycles. Each bit is latched in on the rising edge of Serial Clock (C).
Then the memory contents at that address are shifted out on Serial Data output (DQ1).
Each bit is shifted out at the maximum frequency, fCmax, on the falling edge of Serial Clock
(C). The address is automatically incremented to the next higher address after each byte of
data is shifted out.
There is no rollover mechanism with the Read OTP (ROTP) instruction. This means that the
Read OTP (ROTP) instruction must be sent with a maximum of 65 bytes to read. All other
bytes outside the OTP area are “Don’t Care.”
The Read OTP (ROTP) instruction is terminated by driving Chip Select (S) High. Chip
Select (S) can be driven High at any time during data output. Any Read OTP (ROTP)
instruction issued while an Erase or Program cycle is in progress, is rejected without having
any effect on the cycle that is in progress.
Figure 18. Read OTP instruction and data-out sequence
S
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
C
Instruction
24-bit address
23 22 21
DQ0
3
2
1
0
High Impedance
DQ1
S
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
C
Dummy cycles
DQ0
7
6
5
4
3
2
1
0
DATA OUT n
DATA OUT 1
DQ1
7
MSB
6
5
4
3
2
1
0
7
MSB
6
5
4
3
2
1
0
7
MSB
63/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
Instructions
9.1.10
N25Q032 - 3 V
Write Enable (WREN)
The Write Enable (WREN) instruction sets the Write Enable Latch (WEL) bit.
The Write Enable Latch (WEL) bit must be set prior to every Program or Erase instruction:
Page Program (PP), Dual Input Fast Program (DIFP), Dual Input Extended Fast Program
(DIEFP), Quad Input Fast Program (QIFP), Quad Input Extended Fast Program (QIEFP),
Program OTP (POTP), Write to Lock Register (WRLR), Subsector Erase (SSE), Sector
Erase (SE), Bulk Erase (BE), Write Status Register (WRSR), Write Volatile Configuration
Register (WRVCR), Write Volatile Enhanced Configuration Register (WRVECR) and Write
NV Configuration Register (WRNVCR) instruction.
The Write Enable (WREN) instruction is entered by driving Chip Select (S) Low, sending the
instruction code, and then driving Chip Select (S) High.
At the end of the POR sequence the WEL bit is low, so the next modify instruction can be
accepted.
Figure 19. Write Enable instruction sequence
S
0
1
2
3
4
5
6
7
C
Instruction
DQ0
High Impedance
DQ1
AI13731
9.1.11
Write Disable (WRDI)
The Write Disable (WRDI) instruction resets the Write Enable Latch (WEL) bit. The Write
Disable (WRDI) instruction is entered by driving Chip Select (S) Low, sending the instruction
code, and then driving Chip Select (S) High.
64/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
N25Q032 - 3 V
Instructions
The Write Enable Latch (WEL) bit is reset under the following conditions:
z
Power-up
z
Write Disable (WRDI) instruction completion
z
Write Status Register (WRSR) instruction completion
z
Write to Lock Register (WRLR) instruction completion
z
Write Non Volatile Configuration Register (WRNVCR) instruction completion
z
Write Volatile Configuration Register (WRVCR) instruction completion
z
Write Volatile Enhanced Configuration Register (WRVECR) instruction completion
z
Page Program (PP) instruction completion
z
Dual Input Fast Program (DIFP) instruction completion
z
Dual Input Extended Fast Program (DIEFP) instruction completion
z
Quad Input Fast Program (QIFP) instruction completion
z
Quad Input Extended Fast Program (QIEFP) instruction completion
z
Program OTP (POTP) instruction completion
z
Subsector Erase (SSE) instruction completion
z
Sector Erase (SE) instruction completion
z
Bulk Erase (BE) instruction completion
Figure 20. Write Disable instruction sequence
S
0
1
2
3
4
5
6
7
C
Instruction
DQ0
High Impedance
DQ1
9.1.12
Page Program (PP)
The Page Program (PP) instruction allows bytes to be programmed in the memory
(changing bits from 1 to 0). Before it can be accepted, a Write Enable (WREN) instruction
must previously have been executed. After the Write Enable (WREN) instruction has been
decoded, the device sets the Write Enable Latch (WEL).
The Page Program (PP) instruction is entered by driving Chip Select (S) Low, followed by
the instruction code, three address bytes, and at least one data byte on Serial Data input
(DQ0). If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that
go beyond the end of the current page are programmed from the start address of the same
page (from the address whose 8 least significant bits (A7-A0) are all zero). Chip Select (S)
must be driven Low for the entire duration of the sequence.
If more than 256 bytes are sent to the device, previously latched data are discarded and the
last 256 data bytes are guaranteed to be programmed correctly within the same page. If less
65/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
Instructions
N25Q032 - 3 V
than 256 data bytes are sent to device, they are correctly programmed at the requested
addresses without having any effects on the other bytes of the same page.
For optimized timings, it is recommended to use the Page Program (PP) instruction to
program all consecutive targeted bytes in a single sequence versus using several Page
Program (PP) sequences with each containing only a few bytes. See Table 31.: AC
Characteristics.
Chip Select (S) must be driven High after the eighth bit of the last data byte has been
latched in, otherwise the Page Program (PP) instruction is not executed.
As soon as Chip Select (S) is driven High, the self-timed Page Program cycle (whose
duration is tPP) is initiated. While the Page Program cycle is in progress, the Status Register
and the Flag Status Register may be read to check if the internal modify cycle is finished. At
some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is
reset.
A Page Program (PP) instruction applied to a page which is protected by the Block Protect
(BP2, BP1, BP0 and TB) bits is not executed.
Page Program cycle can be paused by mean of Program/Erase Suspend (PES) instruction
and resumed by mean of Program/Erase Resume (PER) instruction.
Figure 21. Page Program Instruction Sequence
S
0
1
2
3
4
5
6
7
8
28 29 30 31 32 33 34 35 36 37 38 39
9 10
C
Instruction
*24-bit Address
23 22 21
DQ0
3
2
Data byte 1
1
0
7
6
5
4
3
2
1
0
MSB
MSB
2078
2079
2077
2076
2075
2074
2073
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
2072
S
1
0
C
Data byte 2
DQ0
7
MSB
6
5
4
3
2
Data byte 3
1
0
7
6
5
4
3
2
MSB
Data byte 256
1
0
7
6
5
4
3
2
MSB
*Address bits A23 and A22 are “Don’t Care.”
66/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
N25Q032 - 3 V
9.1.13
Instructions
Dual Input Fast Program (DIFP)
The Dual Input Fast Program (DIFP) instruction is very similar to the Page Program (PP)
instruction, except that the data are entered on two pins (pin DQ0 and pin DQ1) instead of
only one. Inputting the data on two pins instead of one doubles the data transfer bandwidth
compared to the Page Program (PP) instruction.
The Dual Input Fast Program (DIFP) instruction is entered by driving Chip Select (S) Low,
followed by the instruction code, three address bytes and at least one data byte on Serial
Data input (DQ0).
If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that go
beyond the end of the current page are programmed from the start address of the same
page (from the address whose 8 least significant bits (A7-A0) are all zero). Chip Select (S)
must be driven Low for the entire duration of the sequence.
If more than 256 bytes are sent to the device, previously latched data are discarded and the
last 256 data bytes are guaranteed to be programmed correctly within the same page. If less
than 256 data bytes are sent to device, they are correctly programmed at the requested
addresses without having any effects on the other bytes in the same page.
For optimized timings, it is recommended to use the Dual Input Fast Program (DIFP)
instruction to program all consecutive targeted bytes in a single sequence rather to using
several Dual Input Fast Program (DIFP) sequences each containing only a few bytes. See
Table 31.: AC Characteristics.
Chip Select (S) must be driven High after the eighth bit of the last data byte has been
latched in, otherwise the Dual Input Fast Program (DIFP) instruction is not executed.
As soon as Chip Select (S) is driven High, the self-timed Page Program cycle (whose
duration is tPP) is initiated. While the Dual Input Fast Program (DIFP) cycle is in progress,
the Status Register and the Flag Status Register may be read to check if the internal modify
cycle is finished. At some unspecified time before the cycle is completed, the Write Enable
Latch (WEL) bit is reset.
A Dual Input Fast Program (DIFP) instruction applied to a page that belongs to a hardware
or software protected sector is not executed.
Dual Input Fast Program cycle can be paused by mean of Program/Erase Suspend (PES)
instruction and resumed by mean of Program/Erase Resume (PER) instruction.
67/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
Instructions
N25Q032 - 3 V
Figure 22. Dual Input Fast Program Instruction Sequence
S
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
C
Instruction
*24-bit Address
23 22 21
DQ0
3
2
1
0
High Impedance
DQ1
S
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
C
DQ0
6
4
2
0
DATA IN 1
DQ1
7
MSB
5
3
6
4
2
0
DATA IN 2
1
7
MSB
5
3
6
4
2
0
6
DATA IN 3
1
7
MSB
5
3
4
2
0
6
DATA IN 4
1
7
5
MSB
3
4
2
0
DATA IN 5
1
7
MSB
5
3
6
4
2
0
DATA IN 256
1
7
5
3
1
MSB
*Address bits A23 and A22 are “Don’t Care.”
9.1.14
Dual Input Extended Fast Program
The Dual Input Extended Fast Program (DIEFP) instruction is very similar to the Dual Input
Fast Program (DIFP), except that the address bits are shifted in on two pins (pin DQ0 and
pin DQ1) instead of only one.
68/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
N25Q032 - 3 V
Instructions
Figure 23. Dual Input Extended Fast Program instruction sequence
S
Mode 3
C
1
0
2
3
4
5
6
7
8
10 11 12 13 14 15 16 17 18 19 20
9
Mode 0
Instruction
24-bit Address
DQ0
22 20 18 16 14 12 10
8
6
4
2
0
DQ1
23 21 19 17 15 13 11
9
7
5
3
1
6
4
2
S
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
C
DQ0
6
4
2
0
6
Data In 1
DQ1
7
5
3
MSB
4
2
0
6
Data In 2
1
7
5
3
1
MSB
4
2
0
6
5
3
1
MSB
2
0
7
5
3
MSB
1
0
Data In 256
Data In 4
Data In 3
7
4
7
5
3
1
MSB
*Address bits A23 and A22 are “Don’t Care.”
9.1.15
Quad Input Fast Program
The Quad Input Fast Program (QIFP) instruction is very similar to the Dual Input Fast
Program (DIFP) instruction, except that the data are entered on four pins (pin DQ0, pin
DQ1, pin W/VPP/DQ2 and pin HOLD/ (DQ3) instead of only two. Inputting the data on four
pins instead of two doubles the data transfer bandwidth compared to the Dual Input Fast
Program (DIFP) instruction.
The Quad Input Fast Program (QIFP) instruction is entered by driving Chip Select (S) Low,
followed by the instruction code, three address bytes on Serial Data input (DQ0), and at
least one data byte on Serial Data I/Os (DQ0, DQ1, DQ2, DQ3).
If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that go
beyond the end of the current page are programmed from the start address of the same
page (from the address whose 8 least significant bits (A7-A0) are all zero). Chip Select (S)
must be driven Low for the entire duration of the sequence.
If more than 256 bytes are sent to the device, previously latched data are discarded and the
last 256 data bytes are guaranteed to be programmed correctly within the same page. If less
than 256 data bytes are sent to device, they are correctly programmed at the requested
addresses without having any effects on the other bytes in the same page.
For optimized timings, it is recommended to use the Quad Input Fast Program (QIFP)
instruction to program all consecutive targeted bytes in a single sequence rather to using
69/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
Instructions
N25Q032 - 3 V
several Quad Input Fast Program (QIFP) sequences each containing only a few bytes See
Table 31.: AC Characteristics.
Chip Select (S) must be driven High after the eighth bit of the last data byte has been
latched in; otherwise, the Quad Input Fast Program (QIFP) instruction is not executed.
As soon as Chip Select (S) is driven High, the self-timed Page Program cycle (whose
duration is tPP) is initiated. While the Quad Input Fast Program (QIFP) cycle is in progress,
the Status Register may be read to check the value of the Write In Progress (WIP) bit. The
Write In Progress (WIP) bit is 1 during the self-timed Page Program cycle, and 0 when it is
completed. At some unspecified time before the cycle is completed, the Write Enable Latch
(WEL) bit is reset. Alternately, it is possible to read the Flag Status Register to check if the
internal modify cycle is finshed.
A Quad Input Fast Program (QIFP) instruction applied to a page that belongs to a hardware
or software protected sector is not executed.
A Quad Input Fast Program cycle can be paused by mean of Program/Erase Suspend
(PES) instruction and resumed by mean of Program/Erase Resume (PER) instruction.
Figure 24. Quad Input Fast Program instruction sequence
S
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
C
Instruction
1
23 22 21
DQ0
3
2
1
0
Data In
Data In
Data In
*24-bit Address
2
3
4
5
6
4
0
4
0
4
0
4
0
4
0
4
0
5
1
5
1
5
1
5
1
5
1
5
1
6
2
6
2
6
2
6
2
6
2
6
2
7
3
7
3
7
3
7
3
7
3
7
3
Don’t Care
DQ1
Don’t Care
DQ2
Don’t Care
DQ3
‘1’
MSB
MSB
MSB
MSB
MSB
MSB
*Address bit A23 is “Don’t Care.”
*Address bits A23 and A22 are “Don’t Care.”
9.1.16
Quad Input Extended Fast Program
The Quad Input Extended Fast Program (QIEFP) instruction is very similar to the Quad
Input Fast Program (QIFP), except that the address bits are shifted in on four pins (pin DQ0,
pin DQ1, pin W/VPP/DQ2 and pin HOLD/DQ3) instead of only one.
70/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
N25Q032 - 3 V
Instructions
Figure 25. Quad Input Extended Fast Program instruction sequence
S
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
C
Instruction
Data In
*24-bit Address
2
1
DQ0
Data In
Data In
3
5
4
7
6
20 16 12 8
4
0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
21 17 13 9
5
1
5
1
5
1
5
1
5
1
5
1
5
1
5
1
22 18 14 10
6
2
6
2
6
2
6
2
6
2
6
2
6
2
6
2
23 19 15 11
7
3
7
3
7
3
7
3
7
3
7
3
7
3
7
3
Don’t Care
DQ1
Don’t Care
DQ2
DQ3
‘1’
MSB
MSB
MSB
MSB
MSB
MSB
MSB
*Address bits A23 and A22 are “Don’t Care.”
9.1.17
Program OTP instruction (POTP)
The Program OTP instruction (POTP) is used to program at most 64 bytes to the OTP
memory area (by changing bits from 1 to 0, only). Before it can be accepted, a Write Enable
(WREN) instruction must previously have been executed. After the Write Enable (WREN)
instruction has been decoded, the device sets the Write Enable Latch (WEL) bit.
The Program OTP instruction is entered by driving Chip Select (S) Low, followed by the
instruction opcode, three address bytes and at least one data byte on Serial Data input
(DQ0). Chip Select (S) must be driven High after the eighth bit of the last data byte has been
latched in, otherwise the Program OTP instruction is not executed.
There is no rollover mechanism with the Program OTP (POTP) instruction. This means that
the Program OTP (POTP) instruction must be sent with a maximum of 65 bytes to program,
once all 65 bytes have been latched in, any following byte will be discarded.
As soon as Chip Select (S) is driven High, the self-timed Page Program cycle (whose
duration is tPP) is initiated. While the Program OTP cycle is in progress, the Status Register
may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress
(WIP) bit is 1 during the self-timed Program OTP cycle, and it is 0 when it is completed. At
some unspecified time before the cycle is complete, the Write Enable Latch (WEL) bit is
reset. Alternately, it is possible to read the Flag Status Register to check if the internal
modify cycle is finished.
Bit 0 of the OTP control byte, that is byte 64, is used to permanently lock the OTP memory
array.
z
When bit 0 of byte 64 = '1', the 64 bytes of the OTP memory array can be programmed.
z
When bit 0 of byte 64 = '0', the 64 bytes of the OTP memory array are read-only and
cannot be programmed anymore.
Once a bit of the OTP memory has been programmed to '0', it can no longer be set to '1'.
71/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
Instructions
N25Q032 - 3 V
Therefore, as soon as bit 0 of byte 64 (control byte) is set to '0', the 64 bytes of the OTP
memory array become read-only in a permanent way.
Any Program OTP (POTP) instruction issued while an Erase or Program is in progress is
rejected without having any effect on the cycle that is in progress. A Program OTP cycle
cannot be paused by a Program/Erase Suspend (PES) instruction.
Figure 26. Program OTP instruction sequence
S
0
1
2
3
4
5
6
7
8
28 29 30 31 32 33 34 35 36 37 38 39
9 10
C
Instruction
24-bit address
23 22 21
DQ0
3
2
Data byte 1
1
0
7
6
5
4
3
2
0
1
MSB
MSB
S
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
C
Data byte 2
DQ0
7
6
MSB
5
4
3
2
Data byte 3
1
0
7
MSB
6
5
4
3
2
Data byte n
1
0
7
6
5
4
3
2
1
0
MSB
72/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
N25Q032 - 3 V
Instructions
Figure 27. How to permanently lock the OTP bytes
64 data bytes
OTP control byte
Byte Byte Byte
0
1
2
Byte Byte
63 64
X
X
X
X
X
X
X
bit 0 When bit 0 = 0
the 64 OTP bytes
become read only
Bit 1 to bit 7 are not programmable
ai13587
9.1.18
Subsector Erase (SSE)
The Subsector Erase (SSE) instruction sets to '1' (FFh) all bits inside the chosen subsector.
Before it can be accepted, a Write Enable (WREN) instruction must previously have been
executed. After the Write Enable (WREN) instruction has been decoded, the device sets the
Write Enable Latch (WEL).
The Subsector Erase (SSE) instruction is entered by driving Chip Select (S) Low, followed
by the instruction code, and three address bytes on Serial Data input (DQ0). Any address
inside the subsector is a valid address for the Subsector Erase (SSE) instruction. Chip
Select (S) must be driven Low for the entire duration of the sequence.
Chip Select (S) must be driven High after the eighth bit of the last address byte has been
latched in, otherwise the Subsector Erase (SSE) instruction is not executed. As soon as
Chip Select (S) is driven High, the self-timed Subsector Erase cycle (whose duration is
tSSE) is initiated. While the Subsector Erase cycle is in progress, the Status Register may
be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP)
bit is 1 during the self-timed Subsector Erase cycle, and is 0 when it is completed. At some
unspecified time before the cycle is complete, the Write Enable Latch (WEL) bit is reset.
Alternately, it is possible to read the Flag Status Register to check if the internal modify cycle
is finished.
A Subsector Erase (SSE) instruction issued to a sector that is hardware or software
protected, is not executed. Any Subsector Erase (SSE) instruction, while an Erase or
Program cycle is in progress, is rejected without having any effects on the cycle that is in
progress. A Subsector Erase cycle can be paused by a Program/Erase Suspend (PES)
instruction and resumed by a Program/Erase Resume (PER) instruction.
73/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
Instructions
N25Q032 - 3 V
Figure 28. Subsector Erase instruction sequence
S
0
1
2
3
4
5
6
7
8
9
29 30 31
C
Instruction
*24 Bit Address
2
23 22
DQ0
0
1
MSB
*Address bits A23 and A22 are “Don’t Care.”
9.1.19
Sector Erase (SE)
The Sector Erase (SE) instruction sets to '1' (FFh) all bits inside the chosen sector. Before it
can be accepted, a Write Enable (WREN) instruction must previously have been executed.
After the Write Enable (WREN) instruction has been decoded, the device sets the Write
Enable Latch (WEL).
The Sector Erase (SE) instruction is entered by driving Chip Select (S) Low, followed by the
instruction code, and three address bytes on Serial Data input (DQ0). Any address inside
the sector is a valid address for the Sector Erase (SE) instruction. Chip Select (S) must be
driven Low for the entire duration of the sequence.
Chip Select (S) must be driven High after the eighth bit of the last address byte has been
latched in; otherwise, the Sector Erase (SE) instruction is not executed. As soon as Chip
Select (S) is driven High, the self-timed Sector Erase cycle (whose duration is tSE) is
initiated. While the Sector Erase cycle is in progress, the Status Register may be read to
check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1
during the self-timed Sector Erase cycle, and is 0 when it is completed. At some unspecified
time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. Alternately, it
is possible to read the Flag Status Register to check if the internal modify cycle is finished.
A Sector Erase (SE) instruction applied to a page that is hardware or software protected is
not executed. A Sector Erase cycle can be paused by mean of Program/Erase Suspend
(PES) instruction and resumed by mean of Program/Erase Resume (PER) instruction.
Figure 29. Sector Erase instruction sequence
S
0
1
2
3
4
5
6
7
8
9
29 30 31
C
Instruction
DQ0
*24 Bit Address
23 22
2
1
0
MSB
74/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
N25Q032 - 3 V
9.1.20
Instructions
Bulk Erase (BE)
The Bulk Erase (BE) instruction sets all bits to '1' (FFh). Before it can be accepted, a Write
Enable (WREN) instruction must previously have been executed. After the Write Enable
(WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL).
The Bulk Erase (BE) instruction is entered by driving Chip Select (S) Low, followed by the
instruction code on Serial Data input (DQ0). Chip Select (S) must be driven Low for the
entire duration of the sequence.
Chip Select (S) must be driven High after the eighth bit of the instruction code has been
latched in, otherwise the Bulk Erase instruction is not executed. As soon as Chip Select (S)
is driven High, the self-timed Bulk Erase cycle (whose duration is tBE) is initiated. While the
Bulk Erase cycle is in progress, the Status Register may be read to check the value of the
Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Bulk
Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is
completed, the Write Enable Latch (WEL) bit is reset.
The Bulk Erase (BE) instruction is ignored if one or more sectors are hardware or software
protected. The Bulk Erase (BE) cycle cannot be paused by a Program Erase Suspend
(PES) instruction.
Figure 30. Bulk Erase instruction sequence
S
0
1
2
3
4
5
6
7
C
Instruction
DQ0
AI13743
9.1.21
Program/Erase Suspend
The Program/Erase Suspend instruction allows the controller to interrupt a Program or an
Erase instruction, in particular: Sector Erase, Subsector Erase, Page Program, Dual Input
Page Program, Dual Input Extended Page Program, Quad Input Page Program and Quad
Input Extended Page Program instructions can be suspended and resumed.
Note:
Bulk Erase, Write Status Register, Write Non Volatile Configuration Register, and Program
OTP cannot be suspended.
After a Program/Erase Suspend instruction the bit 2 of the Flag Status register is
immediately set to 1 and, after a latency time, both the WIP bit of the Status Register and
the Program/Erase controller bit (Not WIP) of the Flag Status Register are cleared (to 0 and
to 1 respectively).
The Suspended state is reset if a power-off is performed or after resume. After a sector
erase instruction has been suspended, another erase instruction is not allowed; however, it
is possible to perform program and reading instructions on all the sectors except the one
75/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
Instructions
N25Q032 - 3 V
whose erase cycle is suspended. Any read instruction issued on this sector outputs Don't
Care data.
After a subsector erase instruction has been suspended, neither an erase instruction or a
program instruction is allowed; only a read instruction is allowed on all sectors except the
one containing the subsector whose erase cycle is suspended. Any read instruction issued
on this sector outputs Don't Care data.
After a program instruction has been suspended, neither a program instruction or an erase
instructions is allowed; however, it is possible to perform a read instruction on all pages
except the one whose program cycle is suspended. Any read instruction issued on this page
outputs Don't Care data.
It's possible to nest a suspend instruction inside another suspended one just once, meaning
that it's possible for example to send to the device an erase instruction, then suspend it,
then send a program instruction and in the end suspend it as well. In this case, the next
Program/Erase Resume Instruction resumes the more recent suspended modify cycle, and
another Program/Erase Resume Instruction is need to resume also the former modify cycle.
76/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
N25Q032 - 3 V
Instructions
Table 16.
Suspend Parameters
Parameter
Condition
Typ
Max
Unit
Erase to Suspend
Sector Erase or Erase Resume to
Erase Suspend
700
µs
Timing not internally controlled
Program to
Suspend
Program Resume to Program
Suspend
5
µs
Timing not internally controlled
SSErase to
Suspend
Sub Sector Erase or Sub Sector
Erase Resume to Erase Suspend
50
µs
Timing not internally controlled
Program
7
µs
Any Read instruction accepted
Sub Sector Erase
15
µs
Any Read instruction accepted
Erase
15
µs
Any instruction accepted but
SE, SSE, BE, WRSR,
WRNVCR, POTP
Suspend Latency
Note
Note:
As shown here, the device can be in only one state at a time, such as Standby or Program.
Table 17.
Operations Allowed / Disallowed During Device States
Device States and Sector (Same/Other) in Which Operation is Allowed/Disallowed (Yes/No)
Operation
Standby
State
Sector
Program State
Erase State
(SE/SSE)
Subsector
Erase
Suspended
State
Program
Suspended
State
Erase
Suspended
State
Sector
Sector
Sector
Sector
Sector
Same Other Same
Other Same Other
All Reads
except RDSR /
RFSR
Yes
Yes
No
No
No
No
Array Program:
PP / DIFP /
QIFP / DIEFP /
QIEFP
Yes
Yes
No
No
No
Sector Erase
Yes
Yes
No
No
Sub-Sector
Erase
Yes
Yes
No
No
Same
Other
Same Other Same Other
Yes(1)
Yes
Yes
Yes
Yes(1) Yes
No
No
No
No
No
No
Yes
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
WRLR / POTP /
BE / WRSR /
WRNVCR
Yes
No
No
No
No
No
WRVCR /
WRVECR
Yes
No
No
Yes
Yes
Yes
RDSR / RFSR
Yes
Yes
Yes
Yes
Yes
Yes
Program /
Erase Suspend
No
Yes
Yes
No
No
No
1. The Read operation is accepted but the data output is not guaranteed until the program or erase has completed.
77/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
Instructions
9.1.22
N25Q032 - 3 V
Program/Erase Resume
After a Program/Erase suspend instruction, a Program/Erase Resume instruction is
required to continue performing the suspended Program or Erase sequence.
Program/Erase Resume instruction is ignored if the device is not in a Program/Erase
Suspended status. The WIP bit of the Status Register and Program/Erase controller bit (Not
WIP) of the Flag Status Register both switch to the busy state (1 and 0 respectively) after
Program/Erase Resume instruction until the Program or Erase sequence is completed.
In this case the next Program/Erase Resume Instruction resumes the more recent
suspended modify cycle, and another Program/Erase Resume Instruction is needed to
resume also the former modify cycle.
9.1.23
Read Status Register (RDSR)
The Read Status Register (RDSR) instruction allows the Status Register to be read. The
Status Register may be read at any time, even while a Program, Erase or Write Status
Register cycle is in progress. When one of these cycles is in progress, it is recommended to
check the Write In Progress (WIP) bit (or the Program/Erase controller bit of the Flag Status
Register) before sending a new instruction to the device. It is also possible to read the
Status Register continuously, as shown here.
Figure 31. Read Status Register instruction sequence
S
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
C
Instruction
DQ0
Status register out
Status register out
High Impedance
DQ1
7
6
5
MSB
9.1.24
4
3
2
1
0
7
6
5
4
3
2
1
0
7
MSB
Write status register (WRSR)
The write status register (WRSR) instruction allows new values to be written to the status
register. Before it can be accepted, a write enable (WREN) instruction must previously have
been executed. After the write enable (WREN) instruction has been decoded and executed,
the device sets the write enable latch (WEL).
The write status register (WRSR) instruction is entered by driving Chip Select (S) Low,
followed by the instruction code and the data byte on serial data input (DQ0).
The write status register (WRSR) instruction has no effect on b1 and b0 of the status
register.
Chip Select (S) must be driven High after the eighth bit of the data byte has been latched in.
If not, the write status register (WRSR) instruction is not executed. As soon as Chip Select
(S) is driven High, the self-timed write status register cycle (whose duration is tW) is
78/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
N25Q032 - 3 V
Instructions
initiated. While the write status register cycle is in progress, the status register may still be
read to check the value of the write in progress (WIP) bit. The write in progress (WIP) bit is 1
during the self-timed write status register cycle, and is 0 when it is completed. When the
cycle is completed, the write enable latch (WEL) is reset.
The write status register (WRSR) instruction allows the user to change the values of the
block protect (BP2, BP1, BP0) bits, to define the size of the area that is to be treated as
read-only, as defined in Table 10.: Protected area sizes, Upper (TB bit = 0) and Table 11.:
Protected area sizes, Lower (TB bit = 1).
The write status register (WRSR) instruction also allows the user to set and reset the status
register write disable (SRWD) bit in accordance with the Write Protect (W/VPP) signal. The
status register write disable (SRWD) bit and Write Protect (W/VPP) signal allow the device
to be put in the hardware protected mode (HPM). The write status register (WRSR)
instruction is not executed once the hardware protected mode (HPM) is entered.
Figure 32. Write Status Register instruction sequence
S
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
C
Instruction
Status
register in
7
DQ0
High Impedance
6
5
4
3
2
1
0
MSB
DQ1
When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial
delivery state), it is possible to write to the Status Register provided that the Write Enable
Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction, regardless
of the whether Write Protect (W/VPP) is driven High or Low.
When the Status Register Write Disable (SRWD) bit of the Status Register is set to '1', two
cases need to be considered, depending on the state of Write Protect (W/VPP):
z
If Write Protect (W/VPP) is driven High, it is possible to write to the Status Register
provided that the Write Enable Latch (WEL) bit has previously been set by a Write
Enable (WREN) instruction.
z
If Write Protect (W/VPP) is driven Low, it is not possible to write to the Status Register
even if the Write Enable Latch (WEL) bit has previously been set by a Write Enable
(WREN) instruction (attempts to write to the Status Register are rejected, and are not
accepted for execution). As a consequence, all the data bytes in the memory area that
are software protected (SPM2) by the Block Protect (BP2, BP1, BP0) bits and the
Top/Bottom (T/B) bit of the Status Register, are also hardware protected against data
modification.
79/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
Instructions
N25Q032 - 3 V
Regardless of the order of the two events, the Hardware Protected mode (HPM) can be
entered in either of the following ways:
z
setting the Status Register Write Disable (SRWD) bit after driving Write Protect
(W/VPP) Low
z
driving Write Protect (W/VPP) Low after setting the Status Register Write Disable
(SRWD) bit.
The only way to exit the Hardware Protected mode (HPM) once entered is to pull Write
Protect (W/VPP) High.
If Write Protect (W/VPP) is permanently tied High, the Hardware Protected mode (HPM) can
never be activated, and only the Software Protected mode (SPM2), using the Block Protect
(BP2, BP1, BP0) bits and the Top/Bottom (T/B) bits of the Status Register, can be used.
Table 18.
W / VPP
Signal
Protection modes
SRWD
bit
1
0
0
0
1
1
0
1
Mode
Write protection of the status
register
Memory content
Protected area (1)
Unprotected area (1)
Software
protected
(SPM2)
Status register is writeable, if the
WREN instruction has set the WEL
bit.
The values in the SRWD, TB, BP2,
BP1, and BP0 bits can be
changed.
Protected against PP,
DIFP, DIEFP, QIFP,
QIEFP, SSE, SE and
BE instructions.
Ready to accept PP,
DIFP, DIEFP, QIFP,
QIEFP, SSE, and SE
instructions.
Hardware
protected
(HPM)
Status Register is hardware write
protected. The values in the
SRWD, TB, BP2, BP1 and BP0 bits
cannot be changed
PP, DIFP, DIEFP,
QIFP, QIEFP, SSE,
SE and BE
instructions.
PP, DIFP, DIEFP,
QIFP, QIEFP, SSE,
and SE instructions.
1. As defined by the values in the Block Protect (TB, BP2, BP1, BP0) bits of the Status Register, as shown in Table 2: Status
register format.
9.1.25
Read Lock Register (RDLR)
The device is first selected by driving Chip Select (S) Low. The instruction code for the Read
Lock Register (RDLR) instruction is followed by a 3-byte address (A23-A0) pointing to any
location inside the concerned sector. Each address bit is latched-in during the rising edge of
Serial Clock (C). Then the value of the Lock Register is shifted out on Serial Data output
(DQ1), each bit being shifted out, at a maximum frequency fC, during the falling edge of
Serial Clock (C).
The Read Lock Register (RDLR) instruction is terminated by driving Chip Select (S) High at
any time during data output.
Any Read Lock Register (RDLR) instruction, while an Erase, Program or Write cycle is in
progress, is rejected without having any effects on the cycle that is in progress.
80/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
N25Q032 - 3 V
Instructions
Figure 33. Read Lock Register instruction and data-out sequence
S
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
C
Instruction
*24-bit Address
23 22 21
DQ0
3
2
1
0
MSB
Lock Register Out
High Impedance
7
DQ1
6
5
4
3
2
1
0
MSB
*Address bits A23 and A22 are “Don’t Care.”
Table 19.
Bit
Lock Register out(1)
Bit name
Value
b7-b2
b1
b0
Function
Reserved
Sector Lock
Down
‘1’
The Write Lock and Lock Down bits cannot be changed. Once a ‘1’ is written to the
Lock Down bit it cannot be cleared to ‘0’, except by a power-up.
‘0’
The Write Lock and Lock Down bits can be changed by writing new values to them.
‘1’
Program and Erase operations in this sector will not be executed. The memory
contents will not be changed.
‘0’
Program and Erase operations in this sector are executed and will modify the sector
contents.
Sector
Write Lock
1. Values of (b1, b0) after power-up are defined in Section 7: Protection modes.
9.1.26
Write to Lock Register (WRLR)
The Write to Lock Register (WRLR) instruction allows bits to be changed in the Lock
Registers. Before it can be accepted, a Write Enable (WREN) instruction must previously
have been executed. After the Write Enable (WREN) instruction has been decoded, the
device sets the Write Enable Latch (WEL).
The Write to Lock Register (WRLR) instruction is entered by driving Chip Select (S) Low,
followed by the instruction code, three address bytes (pointing to any address in the
targeted sector and one data byte on Serial Data input (DQ0). The instruction sequence is
shown in Figure 22. Chip Select (S) must be driven High after the eighth bit of the data byte
has been latched in, otherwise the Write to Lock Register (WRLR) instruction is not
executed.
Lock Register bits are volatile, and therefore do not require time to be written. When the
Write to Lock Register (WRLR) instruction has been successfully executed, the Write
Enable Latch (WEL) bit is reset after a delay time less than tSHSL minimum value.
Any Write to Lock Register (WRLR) instruction, while an Erase or Program cycle is in
progress, is rejected without having any effects on the cycle that is in progress.
81/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
Instructions
N25Q032 - 3 V
Figure 34. Write to Lock Register instruction sequence
S
0
1
2
3
4
5
6
7
8
9
28 29 30 31 32 33 34 35 36 37 38 39
10
C
Instruction
Lock Register
In
*24-Bit Address
23 22 21
DQ0
3
2
1
0
7
6
5
4
3
2
1
0
MSB
MSB
*Address bits A23 and A22 are “Don’t Care.”
Table 20.
Lock Register in(1)
Sector
All sectors
Bit
Value
b7-b2
‘0’
b1
Sector Lock Down bit value (refer to Table 19)
b0
Sector Write Lock bit value (refer to Table 19)
1. Values of (b1, b0) after power-up are defined in Section 7: Protection modes.
9.1.27
Read Flag Status Register
The Read Flag Status Register (RFSR) instruction allows the Flag Status Register to be
read. The Status Register may be read at any time, even while a Program or Erase is in
progress. When one of these cycles is in progress, it is recommended to check the P/E
Controller bit (Not WIP) bit before sending a new instruction to the device. It is also possible
to read the Flag Register continuously, as shown here.
Figure 35. Read Flag Status Register instruction sequence
S
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
C
Instruction
DQ0
Flag Status Register Out
Flag Status Register Out
High Impedance
DQ1
7
6
5
4
MSB
9.1.28
3
2
1
0
7
6
5
4
3
2
1
0
7
MSB
Clear Flag Status Register
The Clear Flag Status Register (CLFSR) instruction reset the error Flag Status Register bits
(Erase Error bit, Program Error bit, VPP Error bit, Protection Error bit). It is not necessary to
set the WEL bit before the Clear Flag Status Register instruction is executed. The WEL bit
will be unchanged after this command is executed.
82/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
N25Q032 - 3 V
Instructions
Figure 36. Clear Flag Status Register instruction sequence
S
0
1
2
3
4
5
6
7
8
C
Instruction
DQ0
High Impedance
MSB
DQ1
9.1.29
Read NV Configuration Register
The Read Non Volatile Configuration Register (RDNVCR) instruction allows the Non Volatile
Configuration Register to be read.
Figure 37. Read NV Configuration Register instruction sequence
S
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
C
Instruction
DQ0
NVCR Out
NVCR Out
High Impedance
DQ1
7
6
5
4
3
LS Byte
9.1.30
2
1
0 15 14 13 12 11 10 9
8
MS Byte
Write NV Configuration Register
The Write Non Volatile Configuration register (WRNVCR) instruction allows new values to
be written to the Non Volatile Configuration register. Before it can be accepted, a write
enable (WREN) instruction must previously have been executed. After the write enable
(WREN) instruction has been decoded and executed, the device sets the write enable latch
(WEL).
The Write Non Volatile Configuration register (WRNVCR) instruction is entered by driving
Chip Select (S) Low, followed by the instruction code and the data bytes on serial data input
(DQ0).
Chip Select (S) must be driven High after the 16th bit of the data bytes has been latched in.
If not, the Write Non Volatile Configuration register (WRNVCR) instruction is not executed.
As soon as Chip Select (S) is driven High, the self-timed write NV configuration register
cycle (whose duration is tWRNVCR) is initiated.
83/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
Instructions
N25Q032 - 3 V
While the Write Non Volatile Configuration register cycle is in progress, it is possible to
monitor the end of the process by polling status Register write in progress (WIP) bit or the
Flag Status Register Program/Erase Controller bit. The write in progress (WIP) bit is 1
during the self-timed Write Non Volatile Configuration register cycle, and is 0 when it is
completed. When the cycle is completed, the write enable latch (WEL) is reset.
The Write Non Volatile Configuration register (WRNVCR) instruction allows the user to
change the values of all the Non Volatile Configuration Register bits, described in Table 3.:
Non-Volatile Configuration Register.
The Write Non Volatile Configuration Register impacts the memory behavior only after the
next power on sequence.
Figure 38. Write NV Configuration Register instruction sequence
S
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
C
NVCR In
Instruction
Byte
7
DQ0
6
5
4
Byte
3
2
1
0 15 14 13 12 11 10 9
8
MS Byte
LS Byte
High Impedance
DQ1
9.1.31
Read Volatile Configuration Register
The Read Volatile Configuration Register (RDVCR) instruction allows the Volatile
Configuration Register to be read. See Table 5.: Volatile Configuration Register.
Figure 39. Read Volatile Configuration Register instruction sequence
S
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
C
Instruction
DQ0
Volatile Configuration
Register Out
High Impedance
DQ1
7
6
5
4
3
MSB
2
1
Volatile Configuration
Register Out
0
7
6
5
4
3
2
1
0
7
MSB
84/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
N25Q032 - 3 V
9.1.32
Instructions
Write Volatile Configuration Register
The Write Volatile Configuration register (WRVCR) instruction allows new values to be
written to the Volatile Configuration register. Before it can be accepted, a write enable
(WREN) instruction must have been executed. After the write enable (WREN) instruction
has been decoded and executed, the device sets the write enable latch (WEL).
The Write Volatile Configuration register (WRVCR) instruction is entered by driving Chip
Select (S) Low, followed by the instruction code and the data byte on serial data input
(DQ0).
Chip Select (S) must be driven High after the eighth bit of the data byte has been latched in.
If not, the Write Volatile Configuration register (WRVCR) instruction is not executed.
When the new data are latched, the write enable latch (WEL) is reset.
The Write Volatile Configuration register (WRVCR) instruction allows the user to change the
values of all the Volatile Configuration Register bits, described in Table 5.: Volatile
Configuration Register.
The Write Volatile Configuration Register impacts the memory behavior right after the
instruction is received by the device.
Figure 40. Write Volatile Configuration Register instruction sequence
S
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
C
Instruction
Volatile Configuration
Register In
7
DQ0
High Impedance
6
5
4
3
2
1
0
MSB
DQ1
9.1.33
Read Volatile Enhanced Configuration Register
The Read Volatile Enhanced Configuration Register (RDVECR) instruction allows the
Volatile Configuration Register to be read.
85/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
Instructions
N25Q032 - 3 V
Figure 41. Read Volatile Enhanced Configuration Register instruction sequence
S
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
C
Instruction
DQ0
High Impedance
DQ1
Volatile Enhanced
Configuration Register Out
Volatile Enhanced
Configuration Register Out
7
6
5
4
3
2
1
0
7
6
MSB
9.1.34
5
4
3
2
1
0
7
MSB
Write Volatile Enhanced Configuration Register
The Write Volatile Enhanced Configuration register (WRVECR) instruction allows new
values to be written to the Volatile Enhanced Configuration register. Before it can be
accepted, a write enable (WREN) instruction must previously have been executed. After the
write enable (WREN) instruction has been decoded and executed, the device sets the write
enable latch (WEL).
The Write Volatile Enhanced Configuration register (WRVECR) instruction is entered by
driving Chip Select (S) Low, followed by the instruction code and the data byte on serial data
input (DQ0).
Chip Select (S) must be driven High after the eighth bit of the data byte has been latched in.
If not, the Write Volatile Enhanced Configuration register (WRVECR) instruction is not
executed.
When the new data are latched, the write enable latch (WEL) is reset.
The Write Volatile Enhanced Configuration register (WRVECR) instruction allows the user to
change the values of all the Volatile Enhanced Configuration Register bits, described in
Table 7.: Volatile Enhanced Configuration Register.
The Write Volatile Enhanced Configuration Register impacts the memory behavior right after
the instruction is received by the device.
86/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
N25Q032 - 3 V
Instructions
Figure 42. Write Volatile Enhanced Configuration Register instruction sequence
S
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
C
Instruction
VECR In
7
DQ0
High Impedance
6
5
4
3
2
1
0
MSB
DQ1
9.2
DIO-SPI Instructions
In DIO-SPI protocol, instructions, addresses and input/Output data always run in parallel on
two wires: DQ0 and DQ1.
In the case of a Dual Command Fast Read (DCFR), Read OTP (ROTP), Read Lock
Registers (RDLR), Read Status Register (RDSR), Read Flag Status Register (RFSR), Read
NV Configuration Register (RDNVCR), Read Volatile Configuration Register (RDVCR),
Read Volatile Enhanced Configuration Register (RDVECR), Read Serial Flash Discovery
Parameter (RDSFDP), and Multiple I/O Read Identification (MIORDID) instruction, the
shifted-in instruction sequence is followed by a data-out sequence. Chip Select (S) can be
driven High after any bit of the data-out sequence is being shifted out.
In the case of a Dual Command Page Program (DCPP), Program OTP (POTP), Subsector
Erase (SSE), Sector Erase (SE), Bulk Erase (BE), Program/Erase Suspend (PES),
Program/Erase Resume (PER), Write Status Register (WRSR), Clear Flag Status Register
(CLFSR), Write to Lock Register (WRLR), Write Volatile Configuration Register (WRVCR),
Write Volatile Enhanced Configuration Register (WRVECR), Write NV Configuration
Register (WRNVCR), Write Enable (WREN) or Write Disable (WRDI) instruction, Chip
Select (S) must be driven High exactly at a byte boundary, otherwise the instruction is
rejected, and is not executed.
All attempts to access the memory array during a Write Status Register cycle, a Write Non
Volatile Configuration Register, a Program cycle, or an Erase cycle are ignored. The internal
Write Status Register cycle, Write Non Volatile Configuration Register, Program cycle, or
Erase cycle continues unaffected. The exception is the Program/Erase Suspend instruction
(PES), that can be used to pause all the Program and Erase cycles, except for the Program
OTP (POTP), the Write Status Register, the Bulk Erase (BE), and the Write Non Volatile
Configuration Register.
The suspended program or erase cycle can be resumed by mean of the Program/Erase
Resume instruction (PER). During the program/erase cycles also the polling instructions (to
check if the internal modify cycle is finished by mean of the WIP bit of the Status Register or
of the Program/Erase controller bit of the Flag Status register) are also accepted to allow the
application checking the end of the internal modify cycles, of course these polling
instructions don't affect the internal cycles performing.
87/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
Instructions
Table 21.
N25Q032 - 3 V
Instruction set: DIO-SPI protocol
Instruction
MIORDID
RDSFDP
DCFR
Description
Multiple I/O read identification
Read Serial Flash Discovery Parameter
Dual Command Fast Read
One-byte
Instruction
Code (BIN)
1010 1111
01011010
One-byte
Dummy
Address
Instruction
clock
bytes
Code (HEX)
cycle
AFh
5Ah
0
3
0
1 to 3
8
(1)
1 to ∞
(1)
1 to ∞
0000 1011
0Bh
3
8
0011 1011
3Bh
3
8(1)
1011 1011
BBh
3
Data
bytes
1 to ∞
8
(1)
1 to ∞
(1)
1 to 65
ROTP
Read OTP
0100 1011
4Bh
3
8
WREN
Write Enable
0000 0110
06h
0
0
0
WRDI
Write Disable
0000 0100
04h
0
0
0
0000 0010
02h
3
0
1 to 256
1010 0010
A2h
3
0
1 to 256
1101 0010
D2h
3
0
1 to 256
DCPP
Dual Command Page Program
POTP
Program OTP
0100 0010
42h
3
0
1 to 65
SSE
SubSector Erase
0010 0000
20h
3
0
0
SE
Sector Erase
1101 1000
D8h
3
0
0
BE
Bulk Erase
1100 0111
C7h
0
0
0
PER
Program/Erase Resume
0111 1010
7Ah
0
0
0
PES
Program/Erase Suspend
0111 0101
75h
0
0
0
RDSR
Read Status Register
0000 0101
05h
0
0
1 to ∞
WRSR
Write Status Register
0000 0001
01h
0
0
1
RDLR
Read Lock Register
1110 1000
E8h
3
0
1 to ∞
WRLR
Write to Lock Register
1110 0101
E5h
3
0
1
RFSR
Read Flag Status Register
0111 0000
70h
0
0
1 to ∞
CLFSR
Clear Flag Status Register
0101 0000
50h
0
0
0
RDNVCR
Read NV Configuration Register
1011 0101
B5h
0
0
2
WRNVCR
Write NV Configuration Register
1011 0001
B1h
0
0
2
RDVCR
Read Volatile Configuration Register
1000 0101
85h
0
0
1 to ∞
WRVCR
Write Volatile Configuration Register
1000 0001
81h
0
0
1
RDVECR
Read Volatile Enhanced Configuration
Register
0110 0101
65h
0
0
1 to ∞
WRVECR
Write Volatile Enhanced Configuration
Register
0110 0001
61h
0
0
1
1) The
number of Dummy Clock cycles is configurable by the user
88/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
N25Q032 - 3 V
9.2.1
Instructions
Multiple I/O Read Identification protocol
The Multiple Input/Output Read Identification (MIORDID) instruction allows to read the
device identification data in the DIO-SPI protocol:
–
Manufacturer identification (1 byte)
–
Device identification (2 bytes)
Unlike the RDID instruction of the Extended SPI protocol, the Multiple Input/Output
instruction can not read the Unique ID code (UID) (17 bytes).
For further details on the manufacturer and device identification codes please refer to
Section 9.1.1: Read Identification (RDID).
Any Multiple Input/Output Read Identification (MIORDID) instruction while an Erase or
Program cycle is in progress, is not decoded, and has no effect on the cycle that is in
progress.
The device is first selected by driving Chip Select (S) Low. Then, the 8-bit instruction code
for the instruction is shifted in parallel on the 2 pins DQ0 and DQ1. After this, the 24-bit
device identification, stored in the memory, will be shifted out on again in parallel on DQ1
and DQ0. Each two bits are shifted out during the falling edge of Serial Clock (C).
The Read Identification (RDID) instruction is terminated by driving Chip Select (S) High at
any time during data output.
When Chip Select (S) is driven High, the device is put in the Standby Power mode. Once in
the Standby Power mode, the device waits to be selected, so that it can receive, decode and
execute instructions.
Figure 43. Multiple I/O Read Identification instruction and data-out sequence DIOSPI
S
0
1
2
3
4
5
6
7
9 10 11 12 13 14 15
8
C
9.2.2
DEV.
code
MAN.
code
AFh
SIZE
code
DQ0
6
4
2
0
6
4
2
0
6
4
2
0
DQ1
7
5
3
1
7
5
3
1
7
5
3
1
Read Serial Flash Discovery Parameter
The Read Serial Flash Discovery Parameter (RDSFDP) instruction allows reading the Serial
Flash Discovery Parameter area (SFDP) in the DIO-SPI protocol. The instruction
functionality is exactly the same as the Read Serial Flash Discovery Parameter instruction
of the Extended SPI protocol; the only difference is that in the DIO-SPI protocol instruction
code, address and output data are all parallelized on the two pins DQ0 and DQ1.
89/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
Instructions
Note:
N25Q032 - 3 V
The dummy bits can not be parallelized since these clock cycles are requested to perform
the internal reading operation.
Figure 44. Dual Read Serial Flash Discovery Parameter
S
0
1
2
3
4
5
6
8
7
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
C
Instruction
*24-Bit Address
Data Out n
Data Out 1
Dummy cycles
DQ0
22 20 18 16 14 12 10 8
6
4
2
0
6
4
2
0
6
4
2
0
DQ1
23 21 19 17 15 13 11 9
7
5
3
1
7
5
3
1
7
5
3
1
MSB
MSB
The dummy clock cycle depends on the dummy clock configuration in the NVCR/VCR register (default = 8).
*Address bits A[23:11] are “Don’t Care.”
9.2.3
Dual Command Fast Read (DCFR)
The Dual Command Fast Read (DCFR) instruction allows to read the memory in DIO-SPI
protocol, parallelizing the instruction code, the address and the output data on two pins
(DQ0 and DQ1). The Dual Command Fast Read (DCFR) instruction can be issued, when
the device is set in DIO-SPI mode, by sending to the memory indifferently one of the 3
instructions codes: 0Bh, 3Bh or BBh, the effect is exactly the same. The 3 instruction codes
are all accepted to help the application code porting from Extended SPI protocol to DIO-SPI
protocol.
Apart for the parallelizing on two pins of the instruction code, the Dual Command Fast Read
instruction functionality is exactly the same as the Dual I/O Fast Read of the Extended SPI
protocol.
Figure 45. Dual Command Fast Read instruction and data-out sequence DIO-SPI
S
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
C
Instruction
*24-bit Address
22 20 18 16 14 12 10
8
6
4
2
0
DQ1
23 21 19 17 15 13 11
9
7
5
3
1
Data Out n
Data Out 1
Dummy cycles
DQ0
6
4
2
0
7
5
3
1
MSB
6
4
2
0
7
5
3
1
MSB
*Address bits A23 and A22 are “Don’t Care.”
90/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
N25Q032 - 3 V
9.2.4
Instructions
Read OTP (ROTP)
The Read OTP (ROTP) instruction is used to read the 64 bytes OTP area in the DIO-SPI
protocol. The instruction functionality is exactly the same as the Read OTP instruction of the
Extended SPI protocol; the only difference is that in the DIO-SPI protocol instruction code,
address and output data are all parallelized on the two pins DQ0 and DQ1.
Note:
The dummy bits can not be parallelized since these clock cycles are requested to perform
the internal reading operation.
Figure 46. Read OTP instruction and data-out sequence DIO-SPI
S
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
C
Instruction
24-bit Address
DQ0
22 20 18 16 14 12 10 8
6
4
2
0
DQ1
23 21 19 17 15 13 11 9
7
5
3
1
Data Out n
Data Out 1
Dummy cycles
6
4
2
0
7
5
3
1
MSB
9.2.5
6
4
2
0
7
5
3
1
MSB
Write Enable (WREN)
The Write Enable (WREN) instruction sets the Write Enable Latch (WEL) bit.
Except for the parallelizing of the instruction code on the two pins DQ0 and DQ1, the
instruction functionality is exactly the same as the Write Enable (WREN) instruction of the
Extended SPI protocol.
Figure 47. Write Enable instruction sequence DIO-SPI
S
0
1
2
3
4
C
Instruction
DQ0
DQ1
9.2.6
Write Disable (WRDI)
The Write Disable (WRDI) instruction resets the Write Enable Latch (WEL) bit.
91/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
Instructions
N25Q032 - 3 V
Except for the parallelizing of the instruction code on the two pins DQ0 and DQ1, the
instruction functionality is exactly the same as the Write Disable (WRDI) instruction of the
Extended SPI protocol.
Figure 48. Write Disable instruction sequence DIO-SPI
S
0
1
2
3
4
C
Instruction
DQ0
DQ1
9.2.7
Dual Command Page Program (DCPP)
The Dual Command Page Program (DCPP) instruction allows to program the memory
content in DIO-SPI protocol, parallelizing the instruction code, the address and the input
data on two pins (DQ0 and DQ1). Before it can be accepted, a Write Enable (WREN)
instruction must previously have been executed. The Dual Command Page Program
(DCPP) instruction can be issued, when the device is set in DIO-SPI mode, by sending to
the memory indifferently one of the 3 instructions codes: 02h, A2h or D2h, the effect is
exactly the same. The 3 instruction codes are all accepted to help the application code
porting from Extended SPI protocol to DIO-SPI protocol.
Apart for the parallelizing on two pins of the instruction code, the Dual Command Page
Program instruction functionality is exactly the same as the Dual Input Extended Fast
Program of the Extended SPI protocol.
Figure 49. Dual Command Page Program instruction sequence DIO-SPI, 02h
S
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
1037 1039
1036
1038
C
Instruction
*24-bit Address
Data Byte 1
Data Byte 256
Data Byte 2
DQ0
22 20 18 16 14 12 10
8
6
4
2
0
6
4
2
0
6
4
2
0
6
4
2
0
DQ1
23 21 19 17 15 13 11
9
7
5
3
1
7
5
3
1
7
5
3
1
7
5
3
1
*Address bits A[23:22] are “Don’t Care.”
92/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
N25Q032 - 3 V
Instructions
Figure 50. Dual Command Page Program instruction sequence DIO-SPI, A2h
S
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
1039
1037
1036
1038
C
Instruction
*24-bit Address
Data Byte 1
Data Byte 256
Data Byte 2
DQ0
22 20 18 16 14 12 10
8
6
4
2
0
6
4
2
0
6
4
2
0
6
4
2
0
DQ1
23 21 19 17 15 13 11
9
7
5
3
1
7
5
3
1
7
5
3
1
7
5
3
1
*Address bits A[23:22] are “Don’t Care.”
Figure 51. Dual Command Page Program instruction sequence DIO-SPI, D2h
S
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
1039
1037
1036
1038
C
Instruction
*24-bit Address
Data Byte 1
Data Byte 256
Data Byte 2
DQ0
22 20 18 16 14 12 10
8
6
4
2
0
6
4
2
0
6
4
2
0
6
4
2
0
DQ1
23 21 19 17 15 13 11
9
7
5
3
1
7
5
3
1
7
5
3
1
7
5
3
1
*Address bits A[23:22] are “Don’t Care.”
9.2.8
Program OTP instruction (POTP)
The Program OTP instruction (POTP) is used to program at most 64 bytes to the OTP
memory area (by changing bits from 1 to 0, only). Before it can be accepted, a Write Enable
(WREN) instruction must previously have been executed.
Except for parallelizing the instruction code, address, and input data on pins DQ0 and DQ1,
the instruction functionality and the locking OTP method are the same as the Program OTP
(POTP) instruction of the Extended SPI protocol.
93/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
Instructions
N25Q032 - 3 V
Figure 52. Program OTP instruction sequence DIO-SPI
S
0
1
2
3
4
5
6
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
8
7
C
Instruction
24-Bit Address
Data Byte 1
Data Byte n
Data Byte 2
DQ0
22 20 18 16 14 12 10 8
6
4
2
0
6
4
2
0
6
4
2
0
6
4
2
0
DQ1
23 21 19 17 15 13 11 9
7
5
3
1
7
5
3
1
7
5
3
1
7
5
3
1
9.2.9
Subsector Erase (SSE)
The Subsector Erase (SSE) instruction sets to '1' (FFh) all bits inside the chosen subsector.
Before it can be accepted, a Write Enable (WREN) instruction must have been executed
previously.
Except for parallelizing the instruction code and the address on pins DQ0 and DQ1, the
instruction functionality is the same as the Subsector Erase (SSE) instruction of the
Extended SPI protocol.
Figure 53. Subsector Erase instruction sequence DIO-SPI
S
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
C
Instruction
9.2.10
*24-bit Address
DQ0
22 20 18 16 14 12 10
8
6
4
2
0
DQ1
23 21 19 17 15 13 11
9
7
5
3
1
Sector Erase (SE)
The Sector Erase (SE) instruction sets to '1' (FFh) all bits inside the chosen sector. Before it
can be accepted, a Write Enable (WREN) instruction must previously have been executed.
Except for parallelizing the instruction code and the address on the two pins DQ0 and DQ1,
the instruction functionality is the same as the Sector Erase (SE) instruction of the Extended
SPI protocol.
94/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
N25Q032 - 3 V
Instructions
Figure 54. Sector Erase instruction sequence DIO-SPI
S
0
1
2
3
4
5
6
8
7
9
10 11 12 13 14 15
C
*24-bit Address
Instruction
DQ0
22 20 18 16 14 12 10
8
6
4
2
0
DQ1
23 21 19 17 15 13 11
9
7
5
3
1
9.2.11
Bulk Erase (BE)
The Bulk Erase (BE) instruction sets all bits to '1' (FFh). Before it can be accepted, a Write
Enable (WREN) instruction must previously have been executed.
Except for the parallelizing of the instruction code on the two pins DQ0 and DQ1, the
instruction functionality is exactly the same as the Bulk Erase (BE) instruction of the
Extended SPI protocol.
Figure 55. Bulk Erase instruction sequence DIO-SPI
S
0
1
2
3
C
Instruction
DQ0
DQ1
9.2.12
Program/Erase Suspend
The Program/Erase Suspend (PES) instruction allows the controller to interrupt a Program
or an Erase instruction, in particular: Subsector Erase (SSE), Sector Erase (SE) and Dual
Command Page Program (DCPP) can be suspended and resumed while Bulk Erase (BE),
Write Status Register (WRSR), Write Non Volatile Configuration Register (WRNVCR), and
Program OTP (POTP) cannot be suspended.
Apart for the parallelizing of the instruction code on the two pins DQ0 and DQ1, the
instruction functionality is exactly the same as the Program/Erase Suspend (PES)
instruction of the Extended SPI protocol.
95/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
Instructions
N25Q032 - 3 V
Figure 56. Program/Erase Suspend instruction sequence DIO-SPI
S
0
1
2
3
4
C
Instruction
DQ0
DQ1
9.2.13
Program/Erase Resume
After a Program/Erase suspend instruction, a Program/Erase Resume instruction is
required to continue performing the suspended Program or Erase sequence.
Except for the parallelizing of the instruction code on the two pins DQ0 and DQ1, the
instruction functionality is exactly the same as the Program/Erase Resume (PER)
instruction of the Extended SPI protocol.
Figure 57. Program/Erase Resume instruction sequence DIO-SPI
S
0
1
2
3
4
C
Instruction
DQ0
DQ1
Dual_Program_Erase_Resume
9.2.14
Read Status Register (RDSR)
The Read Status Register (RDSR) instruction allows the Status Register to be read. Except
for the parallelizing of the instruction code and the output data on the two pins DQ0 and
DQ1, the instruction functionality is exactly the same as the Read Status Register (RDSR)
instruction of the Extended SPI protocol.
96/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
N25Q032 - 3 V
Instructions
Figure 58. Read Status Register instruction sequence DIO-SPI
S
0
1
2
3
4
5
6
7
8
9 10 11
C
Status Register Out
Byte
Byte
Instruction
DQ0
6
4
2
0
6
4
2
0
DQ1
7
5
3
1
7
5
3
1
Dual_Read_SR
9.2.15
Write status register (WRSR)
The write status register (WRSR) instruction allows new values to be written to the status
register. Before it can be accepted, a write enable (WREN) instruction must previously have
been executed. Except for the parallelizing of the instruction code and the input data on the
two pins DQ0 and DQ1, the instruction functionality and the protection feature management
is exactly the same as the Write Status Register (WRSR) instruction of the Extended SPI
protocol.
Figure 59. Write Status Register instruction sequence DIO-SPI
S
0
1
2
3
4
5
6
7
C
Status Register In
Byte
Instruction
DQ0
6
4
2
0
DQ1
7
5
3
1
*Address bits A[23:22] are “Don’t Care.”
9.2.16
Read Lock Register (RDLR)
The Read Lock Register instruction is used to read the lock register content.
Except for the parallelizing of the instruction code, the address and the output data on the
two pins DQ0 and DQ1, the instruction functionality is exactly the same as the Read Lock
Register (RDLR) instruction of the Extended SPI protocol.
97/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
Instructions
N25Q032 - 3 V
Figure 60. Read Lock Register instruction and data-out sequence DIO-SPI
S
0
1
2
3
4
5
6
9 10 11 12 13 14 15 16 17 18 19
8
7
C
Instruction
24-Bit Address*
Lock Register Out
DQ0
22 20 18 16 14 12 10 8
6
4
2
0
6
4
2
0
DQ1
23 21 19 17 15 13 11 9
7
5
3
1
7
5
3
1
*Address bits A23 and A22 are “Don’t Care.”
9.2.17
Write to Lock Register (WRLR)
The Write to Lock Register (WRLR) instruction allows bits to be changed in the Lock
Registers. Before it can be accepted, a Write Enable (WREN) instruction must previously
have been executed.
Except for the parallelizing of the instruction code, the address and the input data on the two
pins DQ0 and DQ1, the instruction functionality is exactly the same as the Write to Lock
Register (WRLR) instruction of the Extended SPI protocol.
Figure 61. Write to Lock Register instruction sequence DIO-SPI
S
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 12 13 14 15
C
Instruction
Lock Register In
*24-bit Address
DQ0
22 20 18 16 14 12 10
8
6
4
2
0
6
4
2
0
DQ1
23 21 19 17 15 13 11
9
7
5
3
1
7
5
3
1
*Address bits A23 and A22 are “Don’t Care.”
9.2.18
Read Flag Status Register
The Read Flag Status Register (RFSR) instruction allows the Flag Status Register to be
read.
Except for the parallelizing of the instruction code and the output data on the two pins DQ0
and DQ1, the instruction functionality is exactly the same as the Read Flag Status Register
(RFSR) instruction of the Extended SPI protocol.
98/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
N25Q032 - 3 V
Instructions
Figure 62. Read Flag Status Register instruction sequence DIO-SPI
S
0
1
2
3
4
5
6
7
8
9 10 11
C
Instruction
9.2.19
Flag Status Register Out
Byte
Byte
DQ0
6
4
2
0
6
4
2
0
DQ1
7
5
3
1
7
5
3
1
Clear Flag Status Register
The Clear Flag Status Register (CLFSR) instruction reset the error Flag Status Register bits
(Erase Error bit, Program Error bit, VPP Error bit, Protection Error bit). It is not necessary to
set the WEL bit before the Clear Flag Status Register instruction is executed. The WEL bit
will be unchanged after this command is executed.
Figure 63. Clear Flag Status Register instruction sequence DIO-SPI
S
0
1
2
3
C
Instruction
DQ0
DQ1
9.2.20
Read NV Configuration Register
The Read Non Volatile Configuration Register (RDNVCR) instruction allows the Non Volatile
Configuration Register to be read.
99/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
Instructions
N25Q032 - 3 V
Figure 64. Read NV Configuration Register instruction sequence DIO-SPI
S
0
1
2
3
4
5
6
8
7
9 10 11
C
NVCR Out
Byte
Instruction
Byte
DQ0
6
4
2
0
14 12 10 8
DQ1
7
5
3
1
15 13 11 9
LS Byte
9.2.21
MS Byte
Write NV Configuration Register
The Write Non Volatile Configuration register (WRNVCR) instruction allows new values to
be written to the Non Volatile Configuration register. Before it can be accepted, a write
enable (WREN) instruction must previously have been executed.
Except for the parallelizing of the instruction code and the input data on the two pins DQ0
and DQ1, the instruction functionality is exactly the same as the Write Non Volatile
Configuration Register (WNVCR) instruction of the Extended SPI protocol.
Figure 65. Write NV Configuration Register instruction sequence DIO-SPI
S
0
1
2
3
4
5
6
7
8
9 10 11
C
NVCR In
Byte
Instruction
DQ0
6
4
2
0
14 12 10 8
DQ1
7
5
3
1
15 13 11 9
LS Byte
9.2.22
Byte
MS Byte
Read Volatile Configuration Register
The Read Volatile Configuration Register (RDVCR) instruction allows the Volatile
Configuration Register to be read. See Table 5.: Volatile Configuration Register.
100/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
N25Q032 - 3 V
Instructions
Figure 66. Read Volatile Configuration Register instruction sequence DIO-SPI
S
0
1
2
3
4
5
6
8
7
9 10 11
C
Volatile Configuration
Register Out
Byte
Byte
Instruction
9.2.23
DQ0
6
4
2
0
6
4
2
0
DQ1
7
5
3
1
7
5
3
1
Write Volatile Configuration Register
The Write Volatile Configuration register (WRVCR) instruction allows new values to be
written to the Volatile Configuration register. Before it can be accepted, a write enable
(WREN) instruction must have been executed previously.
Except for the parallelizing of the instruction code and the input data on the two pins DQ0
and DQ1, the instruction functionality is exactly the same as the Write Volatile Configuration
Register (WVCR) instruction of the Extended SPI protocol.
Figure 67. Write Volatile Configuration Register instruction sequence DIO-SPI
S
0
1
2
3
4
5
6
7
C
Volatile Configuration
Register In
Byte
Instruction
9.2.24
DQ0
6
4
2
0
DQ1
7
5
3
1
Read Volatile Enhanced Configuration Register
The Read Volatile Enhanced Configuration Register (RDVECR) instruction allows the
Volatile Configuration Register to be read.
101/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
Instructions
N25Q032 - 3 V
Figure 68. Read Volatile Enhanced Configuration Register instruction sequence
DIO-SPI
S
0
1
2
3
4
5
6
7
8
9 10 11
C
Volatile Enhanced
Configuration Register Out
Byte
Byte
Instruction
9.2.25
DQ0
6
4
2
0
6
4
2
0
DQ1
7
5
3
1
7
5
3
1
Write Volatile Enhanced Configuration Register
The Write Volatile Enhanced Configuration register (WRVECR) instruction allows new
values to be written to the Volatile Enhanced Configuration register. Before it can be
accepted, a write enable (WREN) instruction must previously have been executed.
Except for the parallelizing of the instruction code and the input data on the two pins DQ0
and DQ1, the instruction functionality is exactly the same as the Write Volatile Enhanced
Configuration Register (WRVECR) instruction of the Extended SPI protocol.
Figure 69. Write Volatile Enhanced Configuration Register instruction sequence
DIO-SPI
S
0
1
2
3
4
5
6
7
C
Volatile Enhanced
Configuration Register In
Byte
Instruction
DQ0
6
4
2
0
DQ1
7
5
3
1
102/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
N25Q032 - 3 V
9.3
Instructions
QIO-SPI Instructions
In QIO-SPI protocol, instructions, addresses and Input/Output data always run in parallel on
four wires: DQ0, DQ1, DQ2 and DQ3 with the already mentioned exception of the modify
instruction (erase and program) performed with the VPP=VPPh.
In the case of a Quad Command Fast Read (QCFR), Read OTP (ROTP), Read Lock
Registers (RDLR), Read Status Register (RDSR), Read Flag Status Register (RFSR), Read
NV Configuration Register (RDNVCR), Read Volatile Configuration Register (RDVCR),
Read Volatile Enhanced Configuration Register (RDVECR), Read Serial Flash Discovery
Parameter (RDSFDP), and Multiple I/O Read Identification (MIORDID) instruction, the
shifted-in instruction sequence is followed by a data-out sequence. Chip Select (S) can be
driven High after any bit of the data-out sequence is being shifted out.
In the case of a Quad Command Page Program (QCPP), Program OTP (POTP), Subsector
Erase (SSE), Sector Erase (SE), Bulk Erase (BE), Program/Erase Suspend (PES),
Program/Erase Resume (PER), Write Status Register (WRSR), Clear Flag Status Register
(CLFSR), Write to Lock Register (WRLR), Write Volatile Configuration Register (WRVCR),
Write Volatile Enhanced Configuration Register (WRVECR), Write NV Configuration
Register (WRNVCR), Write Enable (WREN) or Write Disable (WRDI) instruction, Chip
Select (S) must be driven High exactly at a byte boundary, otherwise the instruction is
rejected, and is not executed.
All attempts to access the memory array during a Write Status Register cycle, a Write Non
Volatile Configuration Register, a Program cycle or an Erase cycle are ignored, and the
internal Write Status Register cycle, Write Non Volatile Configuration Register, Program
cycle or Erase cycle continues unaffected, the only exception is the Program/Erase
Suspend instruction (PES), that can be used to pause all the program and the erase cycles
but the Program OTP (POTP), Write Status Register (WRSR), Bulk Erase (BE) and Write
Non Volatile Configuration Register. The suspended program or erase cycle can be
resumed by mean of the Program/Erase Resume instruction (PER). During the
program/erase cycles also the polling instructions (to check if the internal modify cycle is
finished by mean of the WIP bit of the Status Register or of the Program/Erase controller bit
of the Flag Status register) are also accepted to allow the application checking the end of
the internal modify cycles, of course these polling instructions don't affect the internal cycles
performing.
103/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
Instructions
Table 22.
N25Q032 - 3 V
Instruction set: QIO-SPI protocol
Instruction
MIORDID
RDSFDP
QCFR
Description
Multiple I/O read identification
Read Serial Flash Discovery Parameter
Quad Command Fast Read
One-byte
Instruction
Code (BIN)
One-byte
Dummy
Instruction Address
clock
Code
bytes
cycle
(HEX)
1010 1111
AFh
0
0
Data
bytes
1 to 3
(1)
1 to ∞
01011010
5Ah
3
10
0000 1011
0Bh
3
10 (1)
1 to ∞
3
10
(1)
1 to ∞
10
(1)
1 to ∞
(1)
1 to 65
0110 1011
1110 1011
6Bh
EBh
3
ROTP
Read OTP (Read of OTP area)
0100 1011
4Bh
3
10
WREN
Write Enable
0000 0110
06h
0
0
0
WRDI
Write Disable
0000 0100
04h
0
0
0
0000 0010
02h
3
0
1 to 256
0011 0010
32h
3
0
1 to 256
0001 0010
12h
3
0
1 to 256
QCPP
Quad Command Page Program
POTP
Program OTP (Program of OTP area)
0100 0010
42h
3
0
1 to 65
SSE
SubSector Erase
0010 0000
20h
3
0
0
SE
Sector Erase
1101 1000
D8h
3
0
0
BE
Bulk Erase
1100 0111
C7h
0
0
0
PER
Program/Erase Resume
0111 1010
7Ah
0
0
0
PES
Program/Erase Suspend
0111 0101
75h
0
0
0
RDSR
Read Status Register
0000 0101
05h
0
0
1 to ∞
WRSR
Write Status Register
0000 0001
01h
0
0
1
RDLR
Read Lock Register
1110 1000
E8h
3
0
1 to ∞
WRLR
Write to Lock Register
1110 0101
E5h
3
0
1
RFSR
Read Flag Status Register
0111 0000
70h
0
0
1 to ∞
CLFSR
Clear Flag Status Register
0101 0000
50h
0
0
0
RDNVCR
Read NV Configuration Register
1011 0101
B5h
0
0
2
WRNVCR
Write NV Configuration Register
1011 0001
B1h
0
0
2
RDVCR
Read Volatile Configuration Register
1000 0101
85h
0
0
1 to ∞
WRVCR
Write Volatile Configuration Register
1000 0001
81h
0
0
1
RDVECR
Read Volatile Enhanced Configuration
Register
0110 0101
65h
0
0
1 to ∞
WRVECR
Write Volatile Enhanced Configuration
Register
0110 0001
61h
0
0
1
1) The
number of Dummy Clock cycles is configurable by the user.
104/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
N25Q032 - 3 V
9.3.1
Instructions
Multiple I/O Read Identification (MIORDID)
The Multiple Input/Output Read Identification (MIORDID) instruction allows to read the
device identification data in the QIO-SPI protocol:
z
Manufacturer identification (1 byte)
z
Device identification (2 bytes)
Unlike the RDID instruction of the Extended SPI protocol, the Multiple Input/Output
instruction can not read the Unique ID code (UID) (17 bytes).
For further details on the manufacturer and device identification codes, see 9.1.1: Read
Identification (RDID).
Any Multiple Input/Output Read Identification (MIORDID) instruction while an Erase or
Program cycle is in progress, is not decoded, and has no effect on the cycle that is in
progress.
The device is first selected by driving Chip Select (S) Low. Then, the 8-bit instruction code
for the instruction is shifted in parallel on the 4 pins DQ0, DQ1, DQ2 and DQ3. After this, the
24-bit device identification, stored in the memory, will be shifted out on again in parallel on
DQ0, DQ1, DQ2 and DQ3. The identification bits are shifted out 4 at a time during the falling
edge of Serial Clock (C).
The Read Identification (RDID) instruction is terminated by driving Chip Select (S) High at
any time during data output.
When Chip Select (S) is driven High, the device is put in the Standby Power mode. Once in
the Standby Power mode, the device waits to be selected, so that it can receive, decode and
execute instructions.
Figure 70. Multiple I/O Read Identification instruction and data-out sequence QIOSPI
S
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
C
MAN.
code
DEV.
code
SIZE
code
DQ0
4
0
4
0
4
0
DQ1
5
1
5
1
5
1
DQ2
6
2
6
2
6
2
DQ3
7
3
7
3
7
3
AFh
105/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
Instructions
9.3.2
N25Q032 - 3 V
Read Serial Flash Discovery Parameter
The Read Serial Flash Discovery Parameter (RDSFDP) instruction allows reading the Serial
Flash Discovery Parameter area (SFDP) in the QIO-SPI protocol. The instruction
functionality is exactly the same as the Read Serial Flash Discovery Parameter instruction
of the Extended SPI protocol. The only difference is that in the QIO-SPI protocol instruction
code, address and output data are all parallelized on the four pins DQ0, DQ1, DQ2 and
DQ3.
Note:
The dummy byte bits can not be parallelized: 10 clock cycles are requested to perform the
internal reading operation at highest frequency (108MHz).
Figure 71. Quad Read Serial Flash Discovery Parameter
S
Mode 3
C
0
1
2
3
4
5
6
7
8
9 10
15 16 17 18 19 20 21 22 23 24 25 26 27
Mode 0
Instruction
*24 bit Address
IO switches from Input to Output
DQ0
20 16 12 8
4
0
4
0
4
0
4
0
4
0
4
0
4
0
DQ1
21 17 13 9
5
1
5
1
5
1
5
1
5
1
4
0
4
0
DQ2
22 18 14 10
6
2
6
2
6
2
6
2
6
2
4
0
4
0
DQ3
23 19 15 11
7
3
7
3
7
3
7
3
7
3
4
0
4
0
Dummy (ex.: 10)
Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6
The dummy clock cycle depends on the Fast Read configuration in the NVCR/VCR register (default = 8).
*Address bits A[23:11] are “Don’t Care.”
9.3.3
Quad Command Fast Read (QCFR)
The Quad Command Fast Read (QCFR) instruction allows to read the memory in QIO-SPI
protocol, parallelizing the instruction code, the address and the output data on four pins
(DQ0, DQ1, DQ2 and DQ3). The Quad Command Fast Read (QCFR) instruction can be
issued, after the device is set in QIO-SPI mode, by sending to the memory indifferently one
of the 3 instructions codes: 0Bh, 6Bh or EBh, the effect is exactly the same. The 3
instruction codes are all accepted to help the application code porting from Extended SPI
protocol to QIO-SPI protocol.
Apart for the parallelizing on four pins of the instruction code, the Quad Command Fast
Read instruction functionality is exactly the same as the Quad I/O Fast Read of the
Extended SPI protocol.
106/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
N25Q032 - 3 V
Instructions
Figure 72. Quad Command Fast Read instruction and data-out sequence QIO-SPI,
0Bh
S
Mode 3
C
0
1
2
3
4
5
6
7
8
9 10
15 16 17 18 19 20 21 22 23 24 25 26 27
Mode 0
IO switches from Input to Output
*24-bit Address
Instruction
DQ0
20 16 12 8
4
0
4
0
4
0
4
0
4
0
4
0
4
0
DQ1
21 17 13 9
5
1
5
1
5
1
5
1
5
1
4
0
4
0
DQ2
22 18 14 10
6
2
6
2
6
2
6
2
6
2
4
0
4
0
DQ3
23 19 15 11
7
3
7
3
7
3
7
3
7
3
4
0
4
0
Dummy (ex.: 10)
Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6
*Address bits A23 and A22 are “Don’t Care.”
Figure 73. Quad Command Fast Read instruction and data-out sequence QIO-SPI,
6Bh
S
Mode 3
C
0
1
2
3
4
5
6
7
8
9 10
15 16 17 18 19 20 21 22 23 24 25 26 27
Mode 0
Instruction
IO switches from Input to Output
*24-bit Address
DQ0
20 16 12 8
4
0
4
0
4
0
4
0
4
0
4
0
4
0
DQ1
21 17 13 9
5
1
5
1
5
1
5
1
5
1
4
0
4
0
DQ2
22 18 14 10
6
2
6
2
6
2
6
2
6
2
4
0
4
0
DQ3
23 19 15 11
7
3
7
3
7
3
7
3
7
3
4
0
4
0
Dummy (ex.: 10)
Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6
*Address bits A23 and A22 are “Don’t Care.”
107/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
Instructions
N25Q032 - 3 V
Figure 74. Quad Command Fast Read instruction and data-out sequence QIO-SPI,
EBh
S
Mode 3
C
0
1
2
3
4
5
6
7
8
9 10
15 16 17 18 19 20 21 22 23 24 25 26 27
Mode 0
Instruction
*24-bit Address
IO switches from Input to Output
DQ0
20 16 12 8
4
0
4
0
4
0
4
0
4
0
4
0
4
0
DQ1
21 17 13 9
5
1
5
1
5
1
5
1
5
1
4
0
4
0
DQ2
22 18 14 10
6
2
6
2
6
2
6
2
6
2
4
0
4
0
DQ3
23 19 15 11
7
3
7
3
7
3
7
3
7
3
4
0
4
0
Dummy (ex.: 10)
Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6
*Address bits A23 and A22 are “Don’t Care.”
9.3.4
Read OTP (ROTP)
The Read OTP (ROTP) instruction is used to read the 64 bytes OTP area in the QIO-SPI
protocol. The instruction functionality is exactly the same as the Read OTP instruction of the
Extended SPI protocol. The only difference is that in the QIO-SPI protocol instruction code,
address and output data are all parallelized on the four pins DQ0, DQ1, DQ2 and DQ3.
Note:
The dummy byte bits can not be parallelized: 10 clock cycles are requested to perform the
internal reading operation at highest frequency (108MHz).
108/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
N25Q032 - 3 V
Instructions
Figure 75. Read OTP instruction and data-out sequence QIO-SPI
S
0
1
2
3
4
5
6
7
8
9 10
15 16 17 18 19 20 21 22 23
C
Instruction
Data
out 1
Data
out n
DQ0
20 16 12 8
4
0
4
0
4
0
4
0
DQ1
21 17 13 9
5
1
5
1
5
1
5
1
DQ2
22 18 14 10
6
2
6
2
6
2
6
2
DQ3
23 19 15 11
7
3
7
3
7
3
7
3
Dummy (ex.: 10)
9.3.5
Write Enable (WREN)
The Write Enable (WREN) instruction sets the Write Enable Latch (WEL) bit. Except for the
parallelizing of the instruction code on the four pins DQ0, DQ1, DQ2 and DQ3, the
instruction functionality is exactly the same as the Write Enable instruction of the Extended
SPI protocol.
Figure 76. Write Enable instruction sequence QIO-SPI
S
0
1
C
Instruction
DQ0
DQ1
DQ2
DQ3
Quad_Write_Enable
109/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
Instructions
9.3.6
N25Q032 - 3 V
Write Disable (WRDI)
The Write Disable (WRDI) instruction resets the Write Enable Latch (WEL) bit.
Except for the parallelizing of the instruction code on the four pins DQ0, DQ1, DQ2 and
DQ3, the instruction functionality is exactly the same as the Write Disable (WRDI)
instruction of the Extended SPI protocol.
Figure 77. Write Disable instruction sequence QIO-SPI
S
0
1
C
Instruction
DQ0
DQ1
DQ2
DQ3
Quad_Write_Disable
9.3.7
Quad Command Page Program (QCPP)
The Quad Command Page Program (QCPP) instruction allows to program the memory
content in DIO-SPI protocol, parallelizing the instruction code, the address and the input
data on four pins (DQ0, DQ1, DQ2 and DQ3). Before it can be accepted, a Write Enable
(WREN) instruction must previously have been executed. The Quad Command Page
Program (QCPP) instruction can be issued, when the device is set in QIO-SPI mode, by
sending to the memory indifferently one of the 3 instructions codes: 02h, 12h or 32h, the
effect is exactly the same. The 3 instruction codes are all accepted to help the application
code porting from Extended SPI protocol to QIO-SPI protocol.
Apart for the parallelizing on four pins of the instruction code, the Quad Command Page
Program instruction functionality is exactly the same as the Quad Input Extended Fast
Program of the Extended SPI protocol.
110/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
N25Q032 - 3 V
Instructions
Figure 78. Quad Command Page Program instruction sequence QIO-SPI, 02h
S
Mode 3
C
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
514
515
516
517
518
519
Mode 0
*24-bit Address
1
2
Data In
3
Data In
254
255
4
256
DQ0
20 16 12
8
4
0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
DQ1
21 17 13
9
5
1
5
1
5
1
5
1
5
1
5
1
5
1
5
1
DQ2
22 18 14 10
6
2
6
2
6
2
6
2
6
2
6
2
6
2
6
2
DQ3
23 19 15 11
7
3
7
3
7
3
7
3
7
3
3
7
3
7
3
MSB
MSB
MSB
7
MSB
MSB
MSB
*Address bits A[23:22] are “Don’t Care.”
Figure 79. Quad Command Page Program instruction sequence QIO-SPI, 12h
S
Mode 3
C
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
514
515
516
517
518
519
Mode 0
*24-bit Address
1
2
Data In
3
Data In
254
255
4
256
DQ0
20 16 12
8
4
0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
DQ1
21 17 13
9
5
1
5
1
5
1
5
1
5
1
5
1
5
1
5
1
DQ2
22 18 14 10
6
2
6
2
6
2
6
2
6
2
6
2
6
2
6
2
DQ3
23 19 15 11
7
3
7
3
7
3
7
3
7
3
3
7
3
7
3
MSB
MSB
MSB
7
MSB
MSB
MSB
*Address bits A[23:22] are “Don’t Care.”
111/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
Instructions
N25Q032 - 3 V
Figure 80. Quad Command Page Program instruction sequence QIO-SPI, 32h
S
Mode 3
C
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
514
515
516
517
518
519
Mode 0
*24-bit Address
1
2
Data In
3
Data In
254
255
4
256
DQ0
20 16 12
8
4
0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
DQ1
21 17 13
9
5
1
5
1
5
1
5
1
5
1
5
1
5
1
5
1
DQ2
22 18 14 10
6
2
6
2
6
2
6
2
6
2
6
2
6
2
6
2
DQ3
23 19 15 11
7
3
7
3
7
3
7
3
7
3
3
7
3
7
3
MSB
MSB
7
MSB
MSB
MSB
MSB
*Address bits A[23:22] are “Don’t Care.”
9.3.8
Program OTP instruction (POTP)
The Program OTP instruction (POTP) is used to program at most 64 bytes to the OTP
memory area (by changing bits from 1 to 0, only). Before it can be accepted, a Write Enable
(WREN) instruction must previously have been executed.
Except for the parallelizing of the instruction code, address and input data on the four pins
DQ0, DQ1, DQ2 and DQ3, the instruction functionality (as well as the locking OTP method)
is exactly the same as the Program OTP (POTP) instruction of the Extended SPI protocol.
Figure 81. Program OTP instruction sequence QIO-SPI
S
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14
C
Instruction
24-Bit Address
Data
byte1
Data Data
byte 2 byte n
DQ0
20 16 12 8
4
0
4
0
4
0
4
0
DQ1
21 17 13 9
5
1
5
1
5
1
5
1
DQ2
22 18 14 10 6
2
6
2
6
2
6
2
DQ3
23 19 15 11
3
7
3
7
3
7
3
7
112/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
N25Q032 - 3 V
9.3.9
Instructions
Subsector Erase (SSE)
The Subsector Erase (SSE) instruction sets to '1' (FFh) all bits inside the chosen subsector.
Before it can be accepted, a Write Enable (WREN) instruction must previously have been
executed.
Except for the parallelizing of the instruction code and the address on the four pins DQ0,
DQ1, DQ2 and DQ3, the instruction functionality is exactly the same as the Subsector Erase
(SSE) instruction of the Extended SPI protocol.
Figure 82. Subsector Erase instruction sequence QIO-SPI
S
0
1
2
3
4
5
6
7
8
9
C
Instruction
*24-Bit Address
DQ0
20 16 12 8
4
0
DQ1
21 17 13 9
5
1
DQ2
22 18 14 10
6
2
DQ3
23 19 15 11
7
3
*Address bits A[23:22] are “Don’t Care.”
9.3.10
Sector Erase (SE)
The Sector Erase (SE) instruction sets to '1' (FFh) all bits inside the chosen sector. Before it
can be accepted, a Write Enable (WREN) instruction must previously have been executed.
Except for the parallelizing of the instruction code and the address on the four pins DQ0,
DQ1, DQ2 and DQ3, the instruction functionality is exactly the same as the Sector Erase
(SE) instruction of the Extended SPI protocol.
113/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
Instructions
N25Q032 - 3 V
Figure 83. Sector Erase instruction sequence QIO-SPI
S
0
1
2
3
4
5
6
7
8
9
C
Instruction
*24-bit Address
DQ0
20 16 12
8
4
0
DQ1
21 17 13
9
5
1
DQ2
22 18 14 10
6
2
DQ3
23 19 15 11
7
3
*Address bits A[23:22] are “Don’t Care.”
9.3.11
Bulk Erase (BE)
The Bulk Erase (BE) instruction sets all bits to '1' (FFh). Before it can be accepted, a Write
Enable (WREN) instruction must previously have been executed.
Except for parallelizing the instruction code on the four pins DQ0, DQ1, DQ2 and DQ3, the
instruction functionality is exactly the same as the Bulk Erase (BE) instruction of the
Extended SPI protocol.
Figure 84. Bulk Erase instruction sequence QIO-SPI
S
0
1
C
Instruction
DQ0
DQ1
DQ2
DQ3
9.3.12
Program/Erase Suspend
The Program/Erase Suspend (PES) instruction allows the controller to interrupt a Program
or an Erase instruction. In particular, Subsector Erase (SSE), Sector Erase (SE), and Dual
Command Page Program (DCPP) can be suspended and resumed while Bulk Erase (BE),
114/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
N25Q032 - 3 V
Instructions
Write Status Register (WRSR), Write Non Volatile Configuration Register (WRNVCR), and
Program OTP (POTP) cannot be suspended.
Except for parallelizing the instruction code on four pins (DQ0, DQ1, DQ2, DQ3) the
instruction functionality is the same as the Program/Erase Suspend (PES) instruction of the
Extended SPI protocol.
Figure 85. Program/Erase Suspend instruction sequence QIO-SPI
S
0
1
C
Instruction
DQ0
DQ1
DQ2
DQ3
9.3.13
Program/Erase Resume
After a Program/Erase suspend instruction, a Program/Erase Resume instruction is
required to continue performing the suspended Program or Erase sequence. Except for
parallelizing the instruction code on four pins (DQ0, DQ1, DQ2, DQ3) the instruction
functionality is the same as the Program/Erase Resume (PER) instruction of the Extended
SPI protocol.
115/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
Instructions
N25Q032 - 3 V
Figure 86. Program/Erase Resume instruction sequence QIO-SPI
S
0
1
C
Instruction
DQ0
DQ1
DQ2
DQ3
9.3.14
Read Status Register (RDSR)
The Read Status Register (RDSR) instruction allows the Status Register to be read. Except
for the parallelizing of the instruction code and the output data on the four pins DQ0, DQ1,
DQ2 and DQ3, the instruction functionality is exactly the same as the Read Status Register
(RDSR) instruction of the Extended SPI protocol.
Figure 87. Read Status Register instruction sequence QIO-SPI
S
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18
C
Status Register Out
Instruction
DQ0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
DQ1
5
1
5
1
5
1
5
1
5
1
5
1
5
1
5
1
DQ2
6
2
6
2
6
2
6
2
6
2
6
2
6
2
6
2
DQ3
7
3
7
3
7
3
7
3
7
3
7
3
7
3
7
3
116/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
N25Q032 - 3 V
9.3.15
Instructions
Write status register (WRSR)
The write status register (WRSR) instruction allows new values to be written to the status
register. Before it can be accepted, a write enable (WREN) instruction must previously have
been executed.
The instruction code and the input data are sent on four pins DQ0, DQ1, DQ2 and DQ3. The
instruction functionality is exactly the same as the Write Status Register (WRSR) instruction
of the Extended SPI protocol. However, the protection feature management is different. In
particular, once SRWD bit is set to '1' the device enters in the hardware protected mode
(HPM) independently from Write Protect (W/VPP) signal value. To exit the HPM mode is
needed to switch temporarily to the Extended SPI protocol.
Figure 88. Write Status Register instruction sequence QIO-SPI
S
0
1
2
3
C
Status Register In
9.3.16
DQ0
4
0
DQ1
5
1
DQ2
6
2
DQ3
7
3
Read Lock Register (RDLR)
The Read Lock Register instruction is used to read the lock register content. Apart from
parallelizing the instruction code, the address, and the output data on four pins (DQ0, DQ1,
DQ2, DQ3) the instruction functionality is the same as the Read Lock Register (RDLR)
instruction of the Extended SPI protocol.
117/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
Instructions
N25Q032 - 3 V
Figure 89. Read Lock Register instruction and data-out sequence QIO-SPI
S
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
C
Instruction
*24-bit Address
Lock Register Out
DQ0
20 16 12 8
4
0
4
0
4
0
4
0
4
0
DQ1
21 17 13 9
5
1
5
1
5
1
5
1
5
1
DQ2
22 18 14 10
6
2
6
2
6
2
6
2
6
2
DQ3
23 19 15 11
7
3
7
3
7
3
7
3
7
3
*Address bits A23 and A22 are “Don’t Care.”
9.3.17
Write to Lock Register (WRLR)
The Write to Lock Register (WRLR) instruction allows bits to be changed in the Lock
Registers. Before it can be accepted, a Write Enable (WREN) instruction must previously
have been executed.
Except for the parallelizing of the instruction code, the address and the input data on the
four pins DQ0, DQ1, DQ2 and DQ3, the instruction functionality is exactly the same as the
Write to Lock Register (WRLR) instruction of the Extended SPI protocol.
118/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
N25Q032 - 3 V
Instructions
Figure 90. Write to Lock Register instruction sequence QIO-SPI
S
0
1
2
3
4
5
6
7
8
9
C
Instruction
*24-bit Address
Lock Register In
DQ0
20 16 12 8
4
0
4
0
DQ1
21 17 13 9
5
1
5
1
DQ2
22 18 14 10 6
2
6
2
DQ3
23 19 15 11
3
7
3
7
*Address bits A23 and A22 are “Don’t Care.”
9.3.18
Read Flag Status Register
The Read Flag Status Register (RFSR) instruction allows the Flag Status Register to be
read.
Except for the parallelizing of the instruction code and the output data on the four pins DQ0,
DQ1, DQ2 and DQ3, the instruction functionality is exactly the same as the Read Flag
Status Register (RFSR) instruction of the Extended SPI protocol.
119/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
Instructions
N25Q032 - 3 V
Figure 91. Read Flag Status Register instruction sequence QIO-SPI
S
Mode 3
C
0
1
2
3
4
5
6
7
9 10 11 12 13 14 15
Mode 0
Flag Status Register Out
Instruction
9.3.19
8
DQ0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
DQ1
5
1
5
1
5
1
5
1
5
1
5
1
5
1
DQ2
6
2
6
2
6
2
6
2
6
2
6
2
6
2
DQ3
7
3
7
3
7
3
7
3
7
3
7
3
7
3
Clear Flag Status Register
The Clear Flag Status Register (CLFSR) instruction reset the error Flag Status Register bits
(Erase Error bit, Program Error bit, VPP Error bit, Protection Error bit). It is not necessary to
set the WEL bit before the Clear Flag Status Register instruction is executed. The WEL bit
will be unchanged after this command is executed.
Figure 92. Clear Flag Status Register instruction sequence QIO-SPI
S
0
1
C
Instruction
DQ0
DQ1
DQ2
DQ3
9.3.20
Read NV Configuration Register
The Read Non Volatile Configuration Register (RDNVCR) instruction allows the Non Volatile
Configuration Register to be read.
120/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
N25Q032 - 3 V
Instructions
Figure 93. Read NV Configuration Register instruction sequence QIO-SPI
S
0
1
2
3
4
5
C
Instruction
Nonvolatile Configuration
Register Out
DQ0
4
0 12 8
DQ1
5
1 13 9
DQ2
6
2 14 10
DQ3
7
3 15 11
LS Byte MS Byte
9.3.21
Write NV Configuration Register
The Write Non Volatile Configuration register (WRNVCR) instruction allows new values to
be written to the Non Volatile Configuration register. Before it can be accepted, a write
enable (WREN) instruction must previously have been executed.
Except for the parallelizing of the instruction code and the input data on the four pins DQ0,
DQ1, DQ2 and DQ3, the instruction functionality is exactly the same as the Write Non
Volatile Configuration Register (WRNVCR) instruction of the Extended SPI protocol.
121/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
Instructions
N25Q032 - 3 V
Figure 94. Write NV Configuration Register instruction sequence QIO-SPI
S
0
1
2
3
4
5
C
Instruction
Nonvolatile Configuration
Register In
DQ0
4
0 12 8
DQ1
5
1 13 9
DQ2
6
2 14 10
DQ3
7
3 15 11
LS Byte MS Byte
9.3.22
Read Volatile Configuration Register
The Read Volatile Configuration Register (RDVCR) instruction allows the Volatile
Configuration Register to be read.
122/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
N25Q032 - 3 V
Instructions
Figure 95. Read Volatile Configuration Register instruction sequence QIO-SPI
S
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
C
Volatile Configuration Register Out
Instruction
9.3.23
DQ0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
DQ1
5
1
5
1
5
1
5
1
5
1
5
1
5
1
DQ2
6
2
6
2
6
2
6
2
6
2
6
2
6
2
DQ3
7
3
7
3
7
3
7
3
7
3
7
3
7
3
Write Volatile Configuration Register
The Write Volatile Configuration register (WRVCR) instruction allows new values to be
written to the Volatile Configuration register. Before it can be accepted, a write enable
(WREN) instruction must previously have been executed.
Except for the parallelizing of the instruction code and the input data on the four pins DQ0,
DQ1, DQ2 and DQ3, the instruction functionality is exactly the same as the Write Volatile
Configuration Register (WRVCR) instruction of the Extended SPI protocol.
123/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
Instructions
N25Q032 - 3 V
Figure 96. Write Volatile Configuration Register instruction sequence QIO-SPI
S
0
1
2
3
C
Volatile Configuration
Register In
9.3.24
DQ0
4
0
DQ1
5
1
DQ2
6
2
DQ3
7
3
Read Volatile Enhanced Configuration Register
The Read Volatile Enhanced Configuration Register (RDVECR) instruction allows the
Volatile Configuration Register to be read.
Figure 97. Read Volatile Enhanced Configuration Register instruction sequence
QIO-SPI
S
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
C
Volatile Enhanced
Configuration Register Out
Instruction
DQ0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
DQ1
5
1
5
1
5
1
5
1
5
1
5
1
5
1
DQ2
6
2
6
2
6
2
6
2
6
2
6
2
6
2
DQ3
7
3
7
3
7
3
7
3
7
3
7
3
7
3
124/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
N25Q032 - 3 V
9.3.25
Instructions
Write Volatile Enhanced Configuration Register
The Write Volatile Enhanced Configuration register (WRVECR) instruction allows new
values to be written to the Volatile Enhanced Configuration register. Before it can be
accepted, a write enable (WREN) instruction must previously have been executed.
Except for the parallelizing of the instruction code and the input data on the four pins DQ0,
DQ1, DQ2 and DQ3, the instruction functionality is exactly the same as the Write Volatile
Enhanced Configuration Register (WRVECR) instruction of the Extended SPI protocol.
Figure 98. Write Volatile Enhanced Configuration Register instruction sequence
QIO-SPI
S
0
1
2
3
C
Instruction
Volatile Enhanced
Configuration Register In
DQ0
4
0
DQ1
5
1
DQ2
6
2
DQ3
7
3
125/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
XIP Operations
10
N25Q032 - 3 V
XIP Operations
XIP (eXecution in Place) mode is available in each protocol: Extended SPI, DIO-SPI, and
QIO-SPI. XIP mode allows the memory to be read simply by sending an address to the
device and then receiving the data on one, two, or four pins in parallel, depending on the
customer requirements. It offers maximum flexibility to the application, saves instruction
overhead, and allows a dramatic reduction to the Random Access time.
You can enable XIP mode in two ways:
z
Using the Volatile Configuration Register: this is dedicated to applications that boot in
SPI mode (Extended SPI, DIO-SPI or QIO-SPI) and then during the application life
need to switch to XIP mode to directly execute some code in the flash.
z
Using the Non Volatile Configuration Register: this is dedicated to applications that
need to boot directly in XIP mode.
Setting to 0 the bit 3 of the Volatile Configuration Register the device is ready to enter in XIP
mode right after the next fast read instruction (by 1, 2 or 4 pin).
While acting on the Non Volatile Configuration Register (bit 11 to bit 9, depending on which
XIP type is required, single, dual or quad I/O) the memory enters in the selected XIP mode
only after the next power-on sequence. The Non Volatile Configuration Register XIP
configuration bits allows the memory to start directly in the required XIP mode (Single, Dual
or Quad) after the power on.
The XIP mode status must be confirmed forcing the XIP confirmation bit to "0", the XIP
confirmation bit is the value on the DQ0 pin during the first dummy clock cycle after the
address in XIP reading instruction. Forcing the bit "1" on DQ0 during the first dummy clock
cycle after the address (XIP Confirmation bit) the memory returns in the previous standard
read mode, that means it will codify as an instruction code the next byte received on the
input pin(s) after the next chip select. Instead, if the XIP mode is confirmed (by forcing the
XIP confirmation bit to 0), after the device next de-selection and selection cycle, the memory
codify the first 3 bytes received on the inputs pin(s) as a new address.
Besides not confirming the XIP mode during the first dummy clock cycle, it is possible to exit
the XIP mode by mean of a dedicated rescue sequence.
Note:
For devices with a feature set digit equal to 2 or 4 in the part number (Basic XiP), it is not
necessary to set the Volatile Configuration Register bit 3 to enter XIP mode: it is possible to
enter XIP mode directly by setting XIP Confirmation bit to 0 during the first dummy clock
cycle after a fast read instruction.See Section 16: Ordering information.
126/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
N25Q032 - 3 V
XIP Operations
Figure 99. N25Q032 Read functionality Flow Chart
Power On
NVCR Check
No
Is XIP enabled ?
Yes
SPI standard mode (no
XiP, VCR <3> = 1)
VCR<3> = 0 ?
Yes
SPI mode (no XIP) but
ready to enter XIP
No
No
XIP mode
Read Instructions ?
Yes
Yes
No
XiP Confirmation
bit = 0 ?
No
XiP Confirmation
bit = 0 ?
Yes
127/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
XIP Operations
10.1
N25Q032 - 3 V
Enter XIP mode by setting the Non Volatile Configuration
Register
To use the Non Volatile Configuration Register method to enter in XIP mode it is necessary
to set the Non Volatile Configuration Register bits from 11 to 9 with the pattern
corresponding to the required XIP mode by mean of the Write Non Volatile Configuration
Register (WRNVCR) instruction. (See Table 23.: NVCR XIP bits setting example.)
This instruction doesn't affect the XIP state until the next Power on sequence. In this case,
after the next power on sequence, the memory directly accept addresses and then, after the
dummy clock cycles (configurable), outputs the data as described in Table 23.: NVCR XIP
bits setting example. For example to enable XIP on QIOFR in normal SPI protocol with six
dummy clock cycles the following pattern must be issued:
Table 23.
B1h
(WRNVCR
opcode)
NVCR XIP bits setting example
+ 0110
100
111
x
1
11
xx
6 dummy cycles
for fast read
instructions
XIP set as
default; Quad
I/O mode
Output Buffer
driver strength
default
Don’t Care
Hold/Reset
not disabled
Extended
SPI protocol
Don’t
Care
128/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
N25Q032 - 3 V
XIP Operations
Figure 100. XIP mode directly after power on
NVCR check: XIP enabled
Vd
tVSI (<100μ)
S
Mode 3
C
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
Mode 0
*24-bit Address
IO switches from Input to Output
DQ0
20 16 12
8
4
0 Xb
4
0
4
0
4
DQ1
21 17 13
9
5
1
5
1
5
1
5
DQ2
22 18 14 10
6
2
6
2
6
2
6
DQ3
23 19 15 11
7
3
7
3
7
3
7
Dummy (ex.: 6)
Byte 1 Byte 2
Xb is the XIP Confirmation bit and should be set as follows: 0 to keep XIP state; 1 to exit XIP mode and return to standard read mode.
10.2
Enter XIP mode by setting the Volatile Configuration Register
To use the Volatile Configuration Register method to enter XIP mode, it is necessary to write
a 0 to bit 3 of the Volatile Configuration Register to make the device ready to enter XIP
mode (2). This instruction doesn't permit to enter XIP state directly: a Fast Read instruction
(either Single, Dual or Quad) is needed once to start the XIP Reading.
After the Fast Read instruction (Single, Dual or Quad) the XIP confirmation bit must be set
to 0. (first bit on DQ0 during the first dummy cycle after the address has been received),
Then after the next de-select and select cycle (S pin set to 1 and then to 0) the memory
codify the first 3 bytes received on the input pin(s) directly as an address, without any
instruction code, and after the dummy clock cycles (configurable) directly outputs the data.
For example to enable the XIP (without enter) with six dummy clock cycles, the pattern in
Table 24.: VCR XIP bits setting example must be issued, and after that it is possible to enter,
for example, in XIP mode from extended SPI read mode by mean of Quad Input Output Fast
Read instruction, as described in Table 24.: VCR XIP bits setting example.
Note:
For devices with a feature set digit equal to 2 or 4 in the part number (Basic XiP), it is not
necessary to set the Volatile Configuration Register bit 3 to enter in XIP mode: it is possible
to enter directly in XIP mode by setting XIP Confirmation bit to 1 during the first dummy
clock cycle after a fast read instruction. See Section 16: Ordering information.
Table 24.
VCR XIP bits setting example
81h (WRVCR opcode)
+ 0110
0
011
6 dummy
cycles
129/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
XIP Operations
N25Q032 - 3 V
Table 24.
VCR XIP bits setting example
Ready for
XIP
Reserved
Figure 101. XiP: enter by VCR 2/2 (QIOFR in normal SPI protocol example)
S
Mode 3
C
1
0
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Mode 0
Instruction
DQ0
IO switches from Input to Output
*24-bit Address
20 16 12 8
4
0 Xb
4
0
4
0
4
21 17 13 9
5
1
5
1
5
1
5
22 18 14 10
6
2
6
2
6
2
6
23 19 15 11
7
3
7
3
7
3
7
Don’t Care
DQ1
Don’t Care
DQ2
DQ3
‘1’
Dummy (ex.: 6)
Byte 1 Byte 2
Xb is the XIP Confirmation bit and should be set as follows: 0 to keep XIP state; 1 to exit XIP mode and return to standard read mode.
10.3
XIP mode hold and exit
The XIP mode does require at least one additional clock cycle to allow the XIP Confirmation
bit to be sent to the memory on DQ0 during the first dummy clock cycle.
The device decodes the XIP Confirmation bit with the scheme:
z
XIP Confirmation bit=0 means to hold XIP Mode
z
XIP Confirmation bit=1 means to exit XIP Mode and comes back to read mode, that
means codifying the first byte after the next chip select as an instruction code.
In Dual I/O XIP mode, the values of DQ1 during the first dummy clock cycle after the
addresses is always Don't Care.
In Quad I/O XIP mode, the values of DQ3, DQ2 and DQ1 during the first dummy clock cycle
after the addresses are always Don't Care.
In Dual and Single I/O XIP mode, in presence of the RESET pin enabled (in devices with a
dedicated part number), a low pulse on that pin resets the XIP protocol as defined by the
Volatile Configuration Register, reporting the memory at the state of last power up, as
defined by the Non Volatile Configuration Register. In Quad I/O XiP modes, it is possible to
reset the memory (for devices with a dedicated part number) only when the device is
deselected. See Section 16: Ordering information.
130/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
N25Q032 - 3 V
10.4
XIP Operations
XIP Memory reset after a controller reset
If during the application life the system controller is reset during operation, and the device
features the RESET functionality (in devices with a dedicated part number), and the feature
has not been disabled, after the controller resets, the memory returns to POR state and
there is no issue. See Section 16: Ordering information.
In all the other cases, it is possible to exit the memory from the XIP mode by sending the
following rescue sequence at the first chip selection after a system reset:
DQ0= '1' for:
7 clock cycles within S low (S becomes high before 8th clock cycle)
+ 13 clock cycles within S low (S becomes high before 14th clock cycle)
+ 25 clock cycles within S low (S becomes high before 26th clock cycle)
The global effect is only to exit from XIP without any other reset.
131/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
Power-up and power-down
11
N25Q032 - 3 V
Power-up and power-down
At power-up and power-down, the device must not be selected (that is Chip Select (S) must
follow the voltage applied on VCC) until VCC reaches the correct value:
z
VCC(min) at power-up
z
VSS at power-down
A safe configuration is provided in Section 3: SPI Modes.
To avoid data corruption and inadvertent write operations during power-up, a Power On
Reset (POR) circuit is included. The logic inside the device is held reset while VCC is less
than the Power On Reset (POR) threshold voltage, VWI - all operations are disabled, and
the device does not respond to any instruction.
During a standard power-up phase the device ignores all the instructions but RDSR and
RFSR (they can be used to check the memory internal state according to Figure 102.:
Power-up timing.
After power-up, the device is in the following state:
z
The device is in the Standby Power mode
z
The Write Enable Latch (WEL) bit is reset
z
The Write In Progress (WIP) bit is reset
z
The Lock Registers are configured as: (Write Lock bit, Lock Down bit) = (0,0).
Normal precautions must be taken for supply line decoupling, to stabilize the VCC supply.
Each device in a system should have the VCC line decoupled by a suitable capacitor close
to the package pins (generally, this capacitor is of the order of 100 nF).
At power-down, when VCC drops from the operating voltage, to below the Power On Reset
(POR) threshold voltage, VWI, all operations are disabled and the device does not respond
to any instruction (the designer needs to be aware that if power-down occurs while a
Program or Erase cycle is in progress, some data corruption may result).
VPPH must be applied only when VCC is stable and in the VCC(min) to VCC(max) voltage
range.
Figure 102. Power-up timing
Vcc
V C C (m a x )
C h ip s e le c tio n n o t a llo w e d
V C C (m in )
tV T W = tV T R
C h ip
P o llin g a llo w e d
D e v ic e fu lly a c c e s s ib le
re s e t
VWI
S P I p ro to c o l
S ta rti n g p ro to c o l d e f i n e d b y N V C R
W IP = 1
W IP = 0
W EL = 0
W EL = 0
t im e
132/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
N25Q032 - 3 V
Power-up and power-down
Table 25.
Power-up timing and VWI threshold
Symbol
tVTR(1)
Min
Max
Unit
VCC(min) to Read
150
µs
(1)
VCC(min) to device fully accessible
150
µs
(1)
Write inhibit voltage
2.5
V
tVTW
VWI
Parameter
1.5
1. These parameters are characterized only.
11.1
Rescue sequence in case of power loss during WRNVCR
If a power loss occurs during a Write Non Volatile Configuration Register instruction, after
the next power on the device could eventually wake up in a not determined state, for
example a not required protocol or XIP mode. In that case a particular rescue sequence
must be used to recover the device at a fixed state (Extended SPI protocol without XIP) until
the next power up. Then to fix the problem definitively is recommended to run the Write Non
Volatile configuration Register again.
The rescue sequence is composed of two parts that have to be run in the correct order.
During all the sequence the TSHSL must be 50ns at least. The sequence is:
DQ0 (PAD DATA) equal to '1' for:
7 clock cycles within S low (S becomes high before 8th clock cycle)
+ 13 clock cycles within S low S becomes high before 14th clock cycle)
+ 25 clock cycles within S low (S becomes high before 26th clock cycle)
To exit from XIP.
DQ0 (PAD DATA) and DQ3 (PAD HOLD) equal to '1' for:
8 clock cycles within S low (S becomes high before 9th clock cycle) to force Normal SPI
protocol.
133/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
Initial delivery state
12
N25Q032 - 3 V
Initial delivery state
The device is delivered with the memory array erased: all bits are set to 1 (each byte
contains FFh). The Status Register contains 00h (all Status Register bits are 0).
134/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
N25Q032 - 3 V
13
Maximum rating
Maximum rating
Stressing the device outside the ratings listed here may cause permanent damage to the
device. These are stress ratings only, and operation of the device at these, or any other
conditions outside those indicated in the operating sections of this specification, is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Table 26.
Absolute maximum ratings
Symbol
Parameter
TSTG
Storage temperature
TLEAD
Lead temperature during soldering
Min
Max
Unit
–65
150
°C
see(1)
°C
VIO
Input and output voltage (with respect to ground)
–0.6
VCC + 0.6
V
VCC
Supply voltage
–0.6
4.0
V
VPP
Fast program/erase voltage
–0.2
10.0
V
VESD
Electrostatic discharge voltage (human body model)(2)
–2000
2000
V
1. Compliant with JEDEC Std. J-STD-020C (for small body, Sn-Pb or Pb assembly), the Numonyx
ECOPACK® 7191395 specification, and the European directive on Restrictions on Hazardous
Substances (RoHS) 2002/95/EU.
2. JEDEC Std JESD22-A114A (C1 = 100 pF, R1 = 1500 Ω, R2 = 500 Ω).
135/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
DC and AC parameters
14
N25Q032 - 3 V
DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC characteristics tables that
follow are derived from tests performed under the measurement conditions summarized in
the relevant tables. Designers should check that the operating conditions in their circuit
match the measurement conditions when relying on the quoted parameters.
Table 27.
Operating conditions
Symbol
VCC
VPPH
TA
Table 28.
Parameter
Typ
Max
Unit
Supply voltage
2.7
3.6
V
Supply voltage on VPP
8.5
9.5
V
Ambient operating temperature
–40
85
°C
AC measurement conditions
Symbol
CL
Min
Parameter
Min
Max
Unit
30(1)
Load capacitance
Input rise and fall times
pF
5
Input pulse voltages
0.2VCC to
Input timing reference voltages
ns
0.8VCC(2)
V
0.3VCC to 0.7VCC
V
VCC / 2
V
Output timing reference voltages
1) Output Buffers are configurable by user.
2) For QUAD/DUAL operations: 0 to Vcc.
Figure 103. AC measurement I/O waveform
Input levels
Input and output
timing reference levels
0.8VCC
0.7VCC
0.5VCC
0.3VCC
0.2VCC
AI07455
Note:
For 0.8VCC: for QUAD/DUAL operations, this is VCC; for 0.2VCC: for QUAD/DUAL
operations, this is 0V
Table 29.
Symbol
CIN/OUT
CIN
Capacitance(1)
Parameter
Input/output capacitance
(DQ0/DQ1/DQ2/DQ3)
Input capacitance (other pins)
Test condition
Min
Max
Unit
VOUT = 0 V
8
pF
VIN = 0 V
6
pF
1. Sampled only, not 100% tested, at TA=25 °C and a frequency of 54 MHz.
136/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
N25Q032 - 3 V
Table 30.
Symbol
DC and AC parameters
DC Characteristics
Parameter
Test condition (in addiction
to those in Table 27.:
Operating conditions)
Min
Max
Unit
ILI
Input leakage current
±2
µA
ILO
Output leakage current
±2
µA
ICC1
Standby current
S = VCC, VIN = VSS or VCC
100
µA
C = 0.1VCC / 0.9VCC at 108
MHz, DQ1 = open
15
mA
C = 0.1VCC / 0.9VCC at 54
MHz, DQ1 = open
6
mA
Operating current (Fast Read Dual I/O)
C = 0.1VCC / 0.9VCC at
108 MHz
18
mA
Operating current (Fast Read Quad I/O)
C = 0.1VCC / 0.9VCC at
108 MHz
20
mA
ICC4
Operating current (Page Program Single,
Dual and Quad I/O)
S = VCC
20
mA
ICC5
Operating current (WRSR)
S= VCC
20
mA
ICC6
Operating current (SE)
S = VCC
20
mA
VIL
Input low voltage
– 0.5
0.3VCC
V
VIH
Input high voltage
0.7VCC
VCC+0.4
V
VOL
Output low voltage
IOL = 1.6 mA
0.4
V
VOH
Output high voltage
IOH = –100 uA
Operating current (Fast Read Single I/O)
ICC3
Note:
VCC–0.2
V
The AC Characteristics data is preliminary.
137/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
DC and AC parameters
Table 31.
AC Characteristics (page 1 of 2)
Symbol
fC
N25Q032 - 3 V
Alt.
fC
fR
Parameter
Typ(2)
Min
Max
Clock frequency for the all the
instructions (Extended SPI, DIO-SPI and
D.C.
QIO-SPI protocol) but the READ instruction
108
Clock frequency for read instructions
D.C.
54
Unit
MHz
MHz
tCH(1)
tCLH
Clock High time
4
ns
(2)
tCLL
Clock Low time
4
ns
Clock rise time(4) (peak to peak)
0.1
V/ns
0.1
V/ns
4
ns
4
ns
tCL
tCLCH(3)
tCHCL(3)
tSLCH
Clock fall
tCSS
time(4)
(peak to peak)
S active setup time (relative to C)
tCHSL
tDVCH
tDSU
Data in setup time
2
ns
tCHDX
tDH
Data in hold time
3
ns
tCHSH
S active hold time (relative to C)
4
ns
tSHCH
S not active setup time (relative to C)
4
ns
S deselect time after a correct read
instruction
20
S deselect time after a not correct read or
after any different instruction
50
tSHSL
ns
tCSH
tSHQZ(3)
tDIS
tCLQV
tV
ns
Output disable time
8
ns
Clock Low to Output valid under 30 pF
7
ns
Clock Low to Output valid under 10 pF
5
ns
Output hold time
1
ns
tHLCH
HOLD setup time (relative to C)
4
ns
tCHHH
HOLD hold time (relative to C)
4
ns
tHHCH
HOLD setup time (relative to C)
4
ns
tCHHL
HOLD hold time (relative to C)
4
ns
tCLQX
tHO
tHHQX(3)
tLZ
HOLD to Output Low-Z
8
ns
tHLQZ(3)
tHZ
HOLD to Output High-Z
8
ns
tWHSL(5)
Write protect setup time
20
ns
tSHWL(5)
Write protect hold time
100
ns
tVPPHSL(6)
Enhanced program supply voltage High
(VPPH) to Chip Select Low for Single and
Dual I/O Page Program
200
tW
Write status register cycle time
1.3
tCFSR
Clear flag status register cycle time
40
ns
8
ms
ns
138/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
N25Q032 - 3 V
Table 31.
Symbol
DC and AC parameters
AC Characteristics (page 2 of 2)
Alt.
Parameter
Typ(2)
Min
Max
Unit
s
tWNVCR
Write non volatile configuration register
cycle time
0.2
tWVCR
Write volatile configuration register cycle
time
40
tWRVECR
Write volatile enhanced
configurationregister cycle time
40
Page Program Cycle Time (256 Bytes)
0.5
5
Page Program Cycle Time (n Bytes)
int(n/8) ×
0.015(8)
5
Page Program Cycle Time Vpp=VPPH (256
Bytes)
0.4
5
Program OTP cycle time (64 bytes)
0.2
Subsector erase cycle time
0.3
3
s
Sector Erase Cycle Time
0.7
3
s
Sector Erase Cycle Time Vpp=VPPH
0.6
3
Bulk erase cycle time
30
60
s
Bulk erase cycle time (with VPP=VPPH)
25
60
s
tPP(7)
tSSE
3
ns
ns
ms
ms
tSE
tBE
1. tCH + tCL must be greater than or equal to 1/ fC.
2. Typical values given for TA = 25 °C
3. Value guaranteed by characterization, not 100% tested in production.
4. Expressed as a slew-rate.
5. Only applicable as a constraint for a WRSR instruction when SRWD is set to '1'.
6. VPPH should be kept at a valid level until the program or erase operation has completed and its result (success or failure)
is known.
7. When using the page program (PP) instruction to program consecutive bytes, optimized timings are obtained with one
sequence including all the bytes versus several sequences of only a few bytes (1 < n < 256).
8. int(A) corresponds to the upper integer part of A. For example int(12/8) = 2, int(32/8) = 4 int(15.3) =16.
Figure 104. Reset AC waveforms while a program or erase cycle is in progress
S
tSHRV
Reset
tRHSL
tRLRH
See Table 32.: Reset Conditions.
139/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
DC and AC parameters
Table 32.
Symbol
tRLRH
(1)(2)
tRHSL(1)
N25Q032 - 3 V
Reset Conditions
Alt.
tRST
tREC
Parameter
Conditions
Typ
Reset pulse width
Reset Recovery
Time
S# deselect to R
valid
tSHRV(1)
Min
Max Unit
50
ns
Device selected (S low), while decoding
any modify instruction, during all read
operations, CLFSR, WRDI, WREN,
WRLR, WRVCR, WRVECR.
40
ns
Under completion of an internal erase or
program cycle related to POTP, PP, DIEFP,
DIFP, QIEFP, QIFP, SE, BE, PER, PES.
30
µs
Under completion of an SSE operation.
tSSE
ms
Under completion of an WRSR operation.
tW
ms
Under completion of an WRNVCR
operation.
tWNVCR
ms
Device deselected (S high) and in XiP
mode.
40
ns
Device deselected (S high) and in Standby
mode.
40
ns
Deselect to R valid in Quad Output or in
QIO-SPI.
2
ns
1. All values are guaranteed by characterization and not 100% tested in production.
2. The device reset is possible but not guaranteed if tRLRH < 50 ns.
Figure 105. Serial input timing
tSHSL
S
tCHSL
tSLCH
tCHSH
tSHCH
C
tDVCH
tCHCL
tCHDX
DQ0
DQ1
MSB IN
tCLCH
LSB IN
High Impedance
AI13728
140/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
N25Q032 - 3 V
DC and AC parameters
Figure 106. Write protect setup and hold timing during WRSR when SRWD=1
W/VPP
tSHWL
tWHSL
S
C
DQ0
High Impedance
DQ1
AI07439c
Figure 107. Hold timing
S
tHLCH
tCHHL
tHHCH
C
tCHHH
tHLQZ
tHHQX
DQ1
DQ0
HOLD
AI13746
141/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
DC and AC parameters
N25Q032 - 3 V
Figure 108. Output timing
S
tCH
C
tCLQV
tCLQX
tCLQV
tCL
tCLQX
LSB OUT
DQ1
DQ0
tSHQZ
ADDR.
LSB IN
AI13729
Figure 109. VPPH timing
End of command
(identified by WIP polling)
S
C
DQ0
VPPH
VPP
tVPPHSL
ai13726-b
142/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
N25Q032 - 3 V
15
Package mechanical
Package mechanical
To meet environmental requirements, Numonyx offers these devices in RoHS compliant
packages, which have a lead-free second level interconnect. The category of second level
interconnect is marked on the package and on the inner box label in compliance with
JEDEC Standard JESD97. Maximum ratings related to soldering conditions are also marked
on the inner box label.
Figure 110. UFDFPN8 (MLP8) Ultra Thin Dual Flat Package, No lead, 4×3 mm Drawing
D
A
B
0.20 DIA TYP.
E
2X d
0.10
C
1
2X d
0.10
2
C
THIRD ANGLE
PROJECTION
TOP VIEW
INTERPRET DIM AND TOL PER
ASME Y14.5M - 1994
f
6
d
0.10
0.05
C
C
A
C
SEATING PLANE
A3
A1
SIDE VIEW
DATUM A OR B
(DATUM A)
D2
1
D2
2
e
NX L
6
e/2
(DATUM B)
3
TERMINAL TIP
E2
EVEN TERMINAL/SIDE
DETAIL "A"
N
N-1
NX b
e
SEE DETAIL "A"
(ND-1) X e
3
j
0.10
M C A B
j
0.05
M C
2
BOTTOM VIEW
1. Drawing is not to scale.
Table 33.
UFDFPN8 (MLP8) Ultra Thin Dual Flat Package, No lead, 4×3 mm Dimensions
Symbol
mm
A
A1
A3
θ
D2
E2
e
N
ND
b
L
D
E
Typ
0.55
0.02
—
—
0.80
0.20
0.80
8
4
0.30
0.60
4
3
Min
0.45
0
0.127
0°
0.70
0.10
—
—
—
0.25
0.55
3.90
2.90
Max
0.60
0.05
0.15
12°
0.90
0.30
—
—
—
0.35
0.65
4.10
3.10
143/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
Package mechanical
N25Q032 - 3 V
Figure 111. VDFPN8 (MLP8) Very Thin Pitch Dual Flat Package, No lead, 6×5 mm
Drawing
A
D
aaa C A
R1
D1
E1
E2
e
bbb
E
M C A B
B
2x
b
aaa C B
0.10 C B
D2
θ
0.10 C A
L
A2
ddd
A
C
A1 A3
1. Drawing is not to scale.
2. The circle in the top view of the package indicates the position of pin 1.
Table 34.
VDFPN8 (MLP8) Very Thin Dual Flat Package No leads 6×5 mm Dimensions
Symbol
mm
A
A1
A2
A3
b
D2
5.75 3.40
E
E1
E2
5
4.75
4
e
R1
L
1.27 0.10 0.60
Q
aaa bbb ddd
—
Min 0.80
0
—
—
0.35
—
—
3.20
—
—
3.80
—
0
0.50
0.05
—
—
0.48
—
—
3.60
—
—
4.30
—
—
0.75 12° 0.15 0.10 0.05
1
6
D1
Typ 0.85
Max
0.65 0.20 0.40
D
—
—
—
—
—
—
—
—
144/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
N25Q032 - 3 V
Package mechanical
Figure 112. VDFPN8 (MLP8) Very Thin Dual Flat Package 8 leads, 8×6x1 mm Drawing
2X
aaa C
D
A
CL
B
A
Pin 1 ID R 0.20
7
2
6
3
5
4
//
2X
aaa C
e
E2
E
CL
(NE-1) x e
1
Ø0,3
eee M C A B
fff M C
8
8X b
A1
bbb C
ddd C
L
K
D2
ISO E
1. Drawing is not to scale.
2. The circle in the top view of the package indicates the position of pin 1.
Table 35.
VDFPN8 (MLP8) Very Thin Dual Flat Package 8 leads 8×6x1 mm Dimensions
Symbol
mm
A
A1
b
D
D2
E
E2
e
K
L
Typ
0.85
—
0.4
8
5.16
6
4.8
1.27
(basic)
—
0.5
Min
—
0
0.35
—
—
—
—
1.27
(basic)
0.2
0.45
Max
1
0.05
0.48
—
—
—
—
1.27
(basic)
—
0.6
145/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
Package mechanical
N25Q032 - 3 V
Figure 113. SO8W – 8 Lead Plastic Small Outline, 208 mils Body Width, Drawing
A2
A
c
b
CP
e
D
N
E E1
1
A1
k
L
1. Drawing is not to scale.
Table 36.
SO8 Wide – 8 Lead Plastic Small Outline, 208 mils Body Width, Dimensions
Symbol
mm
A
A1
A2
b
c
D
E
E1
e
k
L
Typ
1.91
0.10
1.80
—
0.20
5.28
5.28
7.90
1.27
4°
0.64
Min
1.78
0.05
1.70
0.36
0.15
5.08
5.08
7.70
—
0°
0.51
Max
2.16
0.25
1.91
0.48
0.25
5.49
5.49
8.10
—
8°
0.80
146/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
N25Q032 - 3 V
Package mechanical
Figure 114. SO16 Wide – 16 Lead Plastic Small Outline, 300 mils Body Width, Drawing
D
h x 45˚
9
16
C
E
1
θ
8
A2
B
H
A1
A
L
ddd
e
1. Drawing is not to scale.
Table 37.
SO16 Wide – 16 Lead Plastic Small Outline, 300 mils Body Width, Dimensions
Symbol
mm
A
A1
B
C
D
E
e
H
h
L
θ
ddd
Typ
—
—
—
—
—
—
1.27
—
—
—
—
—
Min
2.35
0.10
0.33
0.23
10.10
7.40
—
10
0.25
0.40
0°
—
Max
2.65
0.30
0.51
0.32
10.50
7.60
—
10.65
0.75
1.27
8°
0.10
147/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
Package mechanical
N25Q032 - 3 V
Figure 115. TBGA - 6 x 8 mm, 24-Ball, Drawing
1. Drawing is not to scale.
148/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
N25Q032 - 3 V
Table 38.
Package mechanical
TBGA 6x8 mm 24-Ball, Dimensions, Symbols A to eE
Symbol
mm
A
A1
A2
θb
D
D1
E
E1
eD
eE
Typ
—
0.20
—
0.35
5.90
—
7.90
—
—
—
Min
—
—
0.79
0.40
6.00
4
8
4
1
1
Max
1.20
—
—
0.45
6.10
—
8.10
—
—
—
Table 39.
TBGA 6x8 mm 24-Ball, Dimensions, Symbols FD to fff
Symbol
mm
FD
FE
MD
ME
n
aaa
bbb
ddd
eee
fff
Typ
—
—
5
5
24 balls
—
—
—
—
—
Min
1
2
5
5
24 balls
—
—
—
—
—
Max
—
—
5
5
24 balls
0.15
0.10
0.10
0.15
0.08
Figure 116. SO8N – 8 Lead Plastic Small Outline, 150 mils Body Width, Drawing
h x 45˚
A2
A
c
ccc
b
e
0.25 mm
GAUGE PLANE
D
k
8
E1
E
1
L
A1
L1
1. Drawing is not to scale.
Table 40.
SO8N – 8 Lead Plastic Small Outline, 150 mils Body Width, Dimensions
Symbol
mm
A
A1
A2
b
c
ccc
D
E
E1
e
h
k
L
L1
Typ
—
—
—
—
—
—
4.90
6
3.90
1.27
—
—
—
1.04
Min
—
0.10
1.25
0.28
0.17
—
4.80
5.80
3.80
—
0.25
0°
0.40
—
Max
1.75
0.25
—
0.48
0.23
0.10
5
6.20
4
—
0.50
8°
1.27
—
149/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
Ordering information
16
Ordering information
Table 41.
Ordering information scheme
Example:
N25Q032 - 3 V
N25Q032
A 1 3
E
F8 4
0
E
Device type
N25Q = serial Flash memory, Quad I/O, XiP
Device density
032 = 032 Mbit
Technology
A = 65 nm
Feature set
1 = Byte addressability, Hold pin, Numonyx XiP
2 = Byte addressability, Hold pin, Basic XiP
3 = Byte addressability, Reset pin, Numonyx XiP
4 = Byte addressability, Reset pin, Basic XiP
Operating voltage
3 = VCC = 2.7 V to 3.6 V
Block Structure
E = Uniform (no boot sectors)
Package
F4 = UFDFPN8 4 x 3 mm (MLP8)
F6 = VDFPN8 6 x 5 mm (MLP8)
F8 = VDFPN8 8 x 6 mm (MLP8)
SC = SO8N (SO8 Narrow 150 mils body width)
SE = SO8W (SO8 Wide 208 mils body width)
SF = SO16W (SO16 Wide 300 mils body width)
12 = TBGA24 6 x 8 mm
Temperature and test flow
4 = Industrial temperature range, –40 to 85 °C: Device tested with standard test flow
A = Automotive temperature range, –40 to 125 °C; Device tested with high reliability
certified test flow
H = Industrial temperature range, –40 to 85 °C; Device tested with high reliability
certified test flow
Security features (1)
0 = No extra security
Packing options
E = Tray packing
F = Tape and reel packing
G = Tube packing
1. Additional secure options are available upon request. For security features options please refer to AN:309025
Note:
All packages are RoHS compliant
150/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
N25Q032 - 3 V
Ordering information
Note:
For further information on line items not listed here or on any aspect of this device, please
contact your nearest Numonyx Sales Office.
Table 42.
Valid Order Information Line Items
Part Number
Features
Block
Package
Structure
Temperature and
Security
Test Flow
N25Q032A13E1240E
N25Q032A13E1240F
Byte addressability,
Uniform
Hold pin, Numonyx XiP
TBGA24
6x8 mm
Industrial temp;
Default
Standard test flow
N25Q032A13EF640E
N25Q032A13EF640F
Byte addressability,
Uniform
Hold pin, Numonyx XiP
VDFPN8
6 x 5 mm
Industrial temp;
Default
Standard test flow
N25Q032A13ESC40F Byte addressability,
Uniform
N25Q032A13ESC40G Hold pin, Numonyx XiP
SO8N
Industrial temp;
Default
Standard test flow
N25Q032A13ESE40F Byte addressability,
Uniform
N25Q032A13ESE40G Hold pin, Numonyx XiP
SO8W
Industrial temp;
Default
Standard test flow
Note:
1
Applies to all part numbers: Packing information details: E= tray, F= tape-n-reel, G= tube
(16th digit of part number).
151/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
Revision history
17
N25Q032 - 3 V
Revision history
Table 43.
Document revision history
Date
Revision
Changes
10-May 2010
1
Initial release.
14-Jan-2011
2
Revised package information.
152/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
M25Q032 - 3 V
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
www.micron.com/productsupport Customer Comment Line: 800-932-4992
Micron and the Micron logo are trademarks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
This data sheet contains minimum and maximum limits specified over the power supply and temperature range set
forth herein.
Although considered final, these specifications are subject to change, as further product development and data
characterization sometimes occur.
153/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.