CS44210
Digital PWM Controller with Headphone Monitor
Features
Description
l Up to 100 dB Dynamic Range
l 2.4 V to 5.0 V supply
l Sample rates up to 96 kHz
l Digital Tone Control
The CS44210 is a complete stereo digital-to-PWM Class D audio amplifier system controller including interpolation, volume
control, half bridge PWM driver outputs, and an integrated
CS44L10 headphone amplifier in a 24-pin TSSOP package.
The CS44210 architecture uses a direct-to-digital approach
—3 selectable HPF and LPF corner frequencies that maintains digital signal integrity to the final output filter.
This minimizes analog interference effects that can negatively
—12 dB boost for bass and treble - 1 dB step size affect system performance.
l Programmable Digital volume control
l Peak signal soft limiting
l De-emphasis for 32 kHz, 44.1 kHz, and 48
The CS44210 contains on-chip digital bass and treble boost,
peak signal limiting, and de-emphasis. The PWM amplifier can
achieve greater than 90% efficiency. This efficiency leads to
longer battery life for portable systems, smaller device package, less heat sink requirements, and smaller power supplies.
l Selectable outputs for each channel including
The CS44210 provides all the controls necessary to drive higher voltage output stages for increased power levels.
—+18 to -96 dB in 1 dB steps
kHz
—Channel A: R, L, mono (L + R) / 2, mute
—Channel B: R, L, mono (L + R) / 2, mute
The CS44210 is ideal for integrated, mult-function systems
such as shelf-top audio systems, audio mini systems, audio
video receivers (AVR), boom boxes and powered speakers.
l PWM PopGuard®
ORDERING INFORMATION
CS44210-KZ
-10 to 70 °C
24-pin TSSOP
SCL/CCLK/DIF0
AD1/CDOUT
SDA/CDIN/DEM
AD0/CS/DIF1
VA_HPA
Control Port
Multibit ∆Σ
Modulator with
Correction
VL
SDIN1
SDIN2
SDIN3
SCLK
LRCK
Digital Volume
Control,
Bass/Treble
Boost,
Compression
Limiting,
De-emphasis
Input
MUX
and
Serial
Port
PW M
Conversion
Level
Shifter
HP_A
GND_HPA
DRIVER_A
Interpolation
DRIVER_B
Input Sampling Rate
LRCLK/MCLK Ratio
Multibit ∆Σ
Modulator with
Correction
VA_HPB
PW M
Conversion
Level
Shifter
HP_B
GND_HPB
TSTIN
RST
Advance Product Information
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.cirrus.com
VD
GND
MCLK
SYNC_CLK
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Copyright Cirrus Logic, Inc. 2001
(All Rights Reserved)
MAY ‘01
DS539PP1
1
CS44210
TABLE OF CONTENTS
1.
2.
3.
4.
5.
6.
CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 4
TYPICAL CONNECTION DIAGRAM ...................................................................................... 11
REGISTER QUICK REFERENCE
...................................................................................... 13
REGISTER DESCRIPTIONS .................................................................................................. 14
PIN DESCRIPTION ................................................................................................................. 27
APPLICATIONS ..................................................................................................................... 29
6.1 Grounding and Power Supply Decoupling ...................................................................... 29
6.2 Clock Modes ................................................................................................................... 29
6.3 De-Emphasis .................................................................................................................. 29
6.4 PWM PopGuard Transient Control ................................................................................. 29
6.5 Recommended Power-up Sequence .............................................................................. 30
6.5.1 Stand Alone Mode ................................................................................................ 30
6.5.2 Control Port Mode ................................................................................................ 30
7. CONTROL PORT INTERFACE .............................................................................................. 31
7.1 Format Selection ............................................................................................................. 31
7.2 Two-Wire Format ............................................................................................................ 31
7.2.1 Writing in Two-Wire Format ................................................................................. 31
7.2.2 Reading in Two-Wire Format ............................................................................... 31
7.3 SPI Format ...................................................................................................................... 31
7.3.1 Writing in SPI ....................................................................................................... 31
7.3.2 Reading in SPI ..................................................................................................... 33
7.4 Memory Address Pointer (MAP) ................................................................................... 33
7.4.1 INCR (Auto Map Increment Enable) .................................................................... 33
7.4.2 MAP3-0 (Memory Address Pointer) ..................................................................... 33
8. PARAMETER DEFINITIONS .................................................................................................. 36
9. PACKAGE DIMENSIONS ....................................................................................................... 37
LIST OF FIGURES
Figure 1. Serial Audio Data Interface Timing .................................................................................. 7
Figure 2. Control Port Timing - Two-Wire Format ........................................................................... 9
Figure 3. Control Port Timing - SPI Format ................................................................................... 10
Figure 4. Typical CS44210 Connection Diagram Stand-Alone Mode ........................................... 11
Figure 5. Typical CS44210 Connection Diagram Control Port Mode ............................................ 12
Figure 6. Dynamics Control Block Diagram .................................................................................. 21
Figure 7. De-Emphasis Curve ....................................................................................................... 24
Figure 8. Control Port Timing, Two-Wire Format .......................................................................... 32
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:
http://www.cirrus.com/corporate/contacts/sales.cfm
Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product information describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information
contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of
any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being
relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, including
use of this information as the basis for manufacture or sale of any items, nor for infringements of patents or other rights of third parties. This document is the
property of Cirrus Logic, Inc. and by furnishing this information, Cirrus Logic, Inc. grants no license, express or implied under any patents, mask work rights,
copyrights, trademarks, trade secrets or other intellectual property rights of Cirrus Logic, Inc. Cirrus Logic, Inc., copyright owner of the information contained
herein, gives consent for copies to be made of the information only for use within your organization with respect to Cirrus Logic integrated circuits or other parts
of Cirrus Logic, Inc. The same consent is given for similar information contained on any Cirrus Logic website or disk. This consent does not extend to other
copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. The names of products of Cirrus Logic,
Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some
jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com.
2
DS539PP1
CS44210
Figure 9. Control Port Timing, SPI Format (Write) ........................................................................ 32
Figure 10. Control Port Timing, SPI Format (Read)...................................................................... 33
Figure 11. Single Speed Stopband Rejection ............................................................................... 34
Figure 12. Single Speed Transition Band ..................................................................................... 34
Figure 13. Single Speed Transition Band (Detail)......................................................................... 34
Figure 14. Single Speed Passband Ripple ................................................................................... 34
Figure 15. Double Speed Stopband Rejection.............................................................................. 34
Figure 16. Double Speed Transition Band .................................................................................... 34
Figure 17. Double Speed Transition Band (Detail) ....................................................................... 35
Figure 18. Double Speed Passband Ripple .................................................................................. 35
Figure 19. Left Justified, up to 24-Bit Data.................................................................................... 35
Figure 20. Right Justified, 24-Bit Data ......................................................................................... 35
Figure 21. I2S, Up to 24-Bit Data ................................................................................................. 35
Figure 22. Right Justified, 16-Bit Data .......................................................................................... 36
LIST OF TABLES
Table 1. Register Quick Reference .............................................................................................. 13
Table 2. Example Volume Settings .............................................................................................. 16
Table 3. Example Bass Boost Settings ........................................................................................ 16
Table 4. Example Treble Boost Settings ...................................................................................... 16
Table 5. Base Boost Corner Frequencies in Single Speed Mode ................................................ 17
Table 6. Base Boost Corner Frequencies in Double Speed Mode .............................................. 17
Table 7. Treble Boost Corner Frequencies in Single Speed Mode .............................................. 18
Table 8. Example Limiter Attack Rate Settings ............................................................................ 19
Table 9. Example Limiter Release Rate Settings ......................................................................... 19
Table 10. ATAPI Decode ............................................................................................................. 21
Table 11. Single Speed Clock Modes - Control Port Mode .......................................................... 23
Table 12. Single Speed Clock Modes - Stand-Alone Mode ......................................................... 23
Table 13. Double Speed Clock Modes - Control Port Mode ........................................................ 24
Table 14. Double Speed Clock Modes - Stand-Alone Mode ........................................................ 24
Table 15. Digital Interface Format - DIF1 and DIF0 (Stand-Alone Mode) .................................... 28
DS539PP1
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CS44210
1. CHARACTERISTICS AND SPECIFICATIONS
(TA = 25 °C; GND = 0 V; Logic "1" = VL = 2.4 V; Logic "0" = GND = 0 V; Full-Scale Output Sine Wave, 997 Hz,
MCLK = 12.288 MHz, Measurement Bandwidth 10 Hz to 20 kHz, unless otherwise specified; Fs for Single Speed
Mode = 48 kHz, SCLK = 3.072 MHz; Fs for Double Speed Mode = 96 kHz, SCLK = 6.144 MHz. Test load
RL = 16 Ω, CL = 10pF.) (See Typical CS44210 Connection Diagram.)
Parameter
Symbol
Min
Headphone Output Dynamic Performance for VD = VL = VA_HPx = 2.4 V
Dynamic Range
18 to 24-Bit
A-Weighted
TBD
UnWeighted
TBD
16-Bit
A-Weighted
Unweighted
Total Harmonic Distortion + Noise
0 dBFS THD+N
-20 dBFS
-60 dBFS
Interchannel Isolation
(1 kHz)
Headphone Output Dynamic Performance for VD = VL = VA_HPx = 3.0 V
Dynamic Range
18 to 24-Bit
A-Weighted
TBD
UnWeighted
TBD
16-Bit
A-Weighted
Unweighted
Total Harmonic Distortion + Noise
0 dB THD+N
-20 dB
-60 dB
Interchannel Isolation
(1 kHz)
Headphone Output Dynamic Performance for VD = VL = VA_HPx = 5.0 V
Dynamic Range
18 to 24-Bit
A-Weighted
TBD
UnWeighted
TBD
16-Bit
A-Weighted
Unweighted
Total Harmonic Distortion + Noise
0 dB THD+N
-20 dB
-60 dB
Interchannel Isolation
(1 kHz)
-
4
Typ
Max
Unit
93
91
91
89
-
dB
dB
dB
dB
-62
-71
-31
TBD
-
dB
dB
dB
TBD
-
dB
95
92
92
90
-
dB
dB
dB
dB
-64
-72
-32
TBD
-
dB
dB
dB
TBD
-
dB
99
96
91
93
-
dB
dB
dB
dB
-67
-76
-36
TBD
-
dB
dB
dB
TBD
-
dB
DS539PP1
CS44210
CHARACTERISTICS AND SPECIFICATIONS (Continued)
Parameters
PWM Headphone Output
Symbol
Full Scale Headphone Output Voltage
Headphone Output Quiescent Voltage
Interchannel Gain Mismatch
Modulation Index
VA_HPx=2.4V
VA_HPx=5.0V
Maximum Headphone Output
AC-Current
IHP
Min
Typ
Max
Units
TBD
-
0.85 x VA_HP
0.5 x VA_HP
0.1
45
80
TBD
85
-
Vp
VDC
dB
%
mA
mA
Single Speed Mode
Parameter
Symbol
Digital Filter Response (Note 1)
Passband
to -0.05 dB corner
(Note 2)
to -0.1 dB corner
to -3 dB corner
Frequency Response 10 Hz to 20 kHz
Double Speed Mode
Min
Typ
Max
Min
Typ
Max
Unit
0
0
-
.4535
.4998
0
0
-
.4426
.4984
Fs
Fs
Fs
-.02
-
+.08
0
-
+0.11
dB
.5465
-
-
.577
-
-
Fs
50
-
-
55
-
-
dB
(Note 3)
StopBand
StopBand Attenuation
(Note 4)
Group Delay
Passband Group Delay Deviation
De-emphasis Error
(Relative to 1 kHz)
-
9/Fs
-
-
4/Fs
-
s
0 - 40 kHz
0 - 20 kHz
tgd
-
±0.36/Fs
-
-
±1.39/Fs
±0.23/Fs
-
s
s
Fs = 32 kHz
Fs = 44.1 kHz
Fs = 48 kHz
-
-
+.2/-.1
+.05/-.14
+0/-.22
(Note 5)
dB
dB
dB
Note:
1. Filter response is not tested but is guaranteed by design.
2. Response is clock dependent and will scale with Fs. Note that the response plots (Figures 11-18) have
been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.
3. Referenced to a 1 kHz, full-scale sine wave.
4. For Single Speed Mode, the measurement bandwidth is 0.5465 Fs to 3 Fs.
For Double Speed Mode, the measurement bandwidth is 0.577 Fs to 1.4 Fs.
5. De-emphasis is not available in double speed mode.
DS539PP1
5
CS44210
ABSOLUTE MAXIMUM RATINGS (GND = 0V; all voltages with respect to ground.)
Parameters
Headphone
Interface
Digital
DC Power Supplies:
Input Current, Any Pin Except Supplies
Digital Input Voltage
Ambient Operating Temperature (power applied)
Storage Temperature
Symbol
VA_HPx
VL
VD
Iin
VIND
TA
Tstg
Min
2.4
2.4
2.4
Max
5.5
5.5
5.5
±10
VL + 0.4
125
150
-0.3
-55
-65
Units
V
V
V
mA
V
°C
°C
CAUTION: Operation at or beyond these limits may result in permanent damage to the device. Normal operation
is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS (GND = 0V; all voltages with respect to ground.)
Parameters
Ambient Temperature
Headphone
Interface
Digital
DC Power Supplies:
Symbol
TA
VA_HPx
VL
VD
Min
-10
2.4
2.4
2.4
Typ
-
Max
70
5.0
5.0
5.0
Units
°C
V
V
V
SWITCHING CHARACTERISTICS (TA = -10 to 70°C; VL = 2.4V - 5.0V; Inputs: Logic 0 = GND,
Logic 1 = VL, CL = 20pF)
Parameters
Input Sample Rate
Single Speed Mode
Double Speed Mode
Symbol
Min
Typ
Max
Units
Fs
Fs
8
50
-
50
100
kHz
kHz
40
50
60
%
MCLK Duty Cycle
LRCK Duty Cycle
40
50
60
%
SCLK Pulse Width Low
tsclkl
20
-
-
ns
SCLK Pulse Width High
tsclkh
20
-
-
ns
-
-
ns
Single Speed Mode
tsclkw
1
---------------------( 128 )Fs
Double Speed Mode
tsclkw
1
------------------( 64 )Fs
-
-
ns
SCLK rising to LRCK edge delay
tslrd
20
-
-
ns
SCLK rising to LRCK edge setup time
tslrs
20
-
-
ns
SDIN valid to SCLK rising setup time
tsdlrs
20
-
-
ns
SCLK rising to SDIN hold time
tsdh
20
-
-
ns
SCLK Period
6
DS539PP1
CS44210
LRCK
t sclkh
t slrs
t slrd
t sclkl
SCLK
t sclkw
t sdh
t sdlrs
SDATA
Figure 1. Serial Audio Data Interface Timing
POWER AND THERMAL CHARACTERISTICS
(GND = 0 V; All voltages with respect to
ground. All measurements taken with all zeros input and open outputs, unless otherwise specified.)
Parameters
Symbol
Min
Typ
Max
Units
IVA_HP
ID
IL
IVA_HP
ID
IL
IVA_HP
ID
IL
IVA_HP
ID
IL
-
1
10
1
TBD
TBD
TBD
2
20
2
TBD
TBD
TBD
29
120
0
23
100
75
-
mA
mA
mA
µA
µA
µA
mA
mA
mA
µA
µA
µA
mW
mW
dB
mW
mW
°C/Watt
Power Supplies
Power Supply CurrentNormal Operation
VA_HPx= 2.4 V
VD = 2.4 V
VL= 2.4 V
Power Supply CurrentPower Down Mode (Note 6)
VA_HPx = 2.4V
VD = 2.4V
VL = 2.4V
Power Supply CurrentNormal Operation
VA_HPx = 5.0 V
VD = 5.0 V
VL = 5.0 V
Power Supply CurrentPower Down Mode (Note 6)
VA_HPx = 5.0V
VD = 5.0V
VL = 5.0 V
Total Power DissipationNormal Operation
All Supplies = 2.4 V
All Supplies = 5.0 V
Power Supply Rejection Ratio
Maximum Headphone Power Dissipation
(1 kHz full-scale sine wave into 16 ohm load)
Package Thermal Resistance
PSRR
VA=2.4 V
VA=5.0 V
θJA
Note:
6. Power Down Mode is defined as RST = LO with all clocks and data lines held static.
DS539PP1
7
CS44210
DIGITAL CHARACTERISTICS (TA = 25° C; VL =
Parameters
Symbol
VIH
VIL
Iin
High-Level Input Voltage
Low-Level Input Voltage
Input Leakage Current
Input Capacitance
High-Level Output Voltage (Pin 15)
Low-Level Output Voltage (Pin 15)
High-Level Output Voltage (Pins 11, 13, 14)
Low-Level Output Voltage (Pins 11, 13, 14)
2.4 V - 3.6 V; GND = 0 V)
(Note 7)
(Note 7)
(Note 7)
(Note 7)
VOH
VOL
VOH
VOL
Min
0.7 x VL
0.7 x VL
0.7 x VD
-
Typ
8
-
Max
0.3 x VL
±10
0.3 x VL
0.3 x VD
Units
V
V
µA
pF
V
V
V
V
SWITCHING CHARACTERISTICS- CONTROL PORT- TWO-WIRE FORMAT
(Note 8) (TA = 25° C; VL = 2.4 V - 5.0 V; Inputs: Logic 0 = GND, Logic 1 = VL, C L = 30 pF)
Parameter
Symbol
Min
Max
Unit
SCL Clock Frequency
fscl
-
100
kHz
RST Rising Edge to Start
tirs
500
-
ns
Bus Free Time Between Transmissions
tbuf
4.7
-
µs
Start Condition Hold Time (prior to first clock pulse)
thdst
4.0
-
µs
Clock Low time
tlow
4.7
-
µs
Clock High Time
thigh
4.0
-
µs
Setup Time for Repeated Start Condition
tsust
4.7
-
µs
thdd
0
-
µs
tsud
250
-
ns
Rise Time of SCL and SDA
trc, trc
-
1
µs
Fall Time SCL and SDA
tfc, tfc
-
300
ns
Setup Time for Stop Condition
tsusp
4.7
-
µs
tack
-
(Note 11)
ns
SDA Hold Time from SCL Falling
(Note 9)
SDA Setup time to SCL Rising
Acknowledge Delay from SCL Falling
(Note 10)
Note:
7. VOH and VOL are tested at an output current of TBD mA.
8. The Two-Wire Format is compatible with the I2C protocol.
9. Data must be held for sufficient time to bridge the transition time, tfc, of SCL.
10. The acknowledge delay is based on MCLK and can limit the maximum transaction speed.
11.
8
5 -------------------256 × Fs
for Single-Speed Mode and
5 -------------------128 × Fs
for Double-Speed Mode.
DS539PP1
CS44210
RST
t
irs
Stop
R epe ate d
Start
Start
t rd
t fd
Stop
S DA
t
buf
t
t
hdst
t
high
t fc
hdst
t susp
SCL
t
low
t
hdd
t sud
t ack
t sust
t rc
Figure 2. Control Port Timing - Two-Wire Format
DS539PP1
9
CS44210
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT
(TA = 25° C; VL = 2.4 V - 5.0 V; Inputs: Logic 0 = GND, Logic 1 = VL, C L = 30 pF)
Parameter
Symbol
Min
Max
Unit
CCLK Clock Frequency
fsclk
-
6
MHz
RST Rising Edge to CS Falling
tsrs
500
-
ns
tspi
500
-
ns
CS High Time Between Transmissions
tcsh
1.0
-
µs
CS Falling to CCLK Edge
tcss
20
-
ns
CCLK Low Time
tscl
66
-
ns
CCLK High Time
tsch
66
-
ns
CDIN to CCLK Rising Setup Time
tdsu
40
-
ns
(Note 12)
CCLK Edge to CS Falling
CCLK Rising to DATA Hold Time
(Note 13)
tdh
15
-
ns
Rise Time of CCLK and CDIN
(Note 14)
tr2
-
100
ns
Fall Time of CCLK and CDIN
(Note 15)
tf2
-
100
ns
Transition time from CCLK to CDOUT valid
(Note 15)
tscdov
-
40
ns
Time from CS rising to CDOUT high-Z
(Note 16)
tcscdo
-
20
ns
Note:
12. tspi only needed before first falling edge of CS after RST rising edge. tspi = 0 at all other times.
13. Data must be held for sufficient time to bridge the transition time of CCLK.
14. For FSCK < 1 MHz.
15. CDOUT should not be sampled during this time period.
16. This time is not tested but is guaranteed by design.
RST
t srs
CS
t spi t css
t scl
t sch
t csh
CCLK
t r2
t f2
CDIN
t dsu t
dh
Tri-state
CDOUT
t scdov
t scdov
t cscdo
Figure 3. Control Port Timing - SPI Format
10
DS539PP1
CS44210
2. TYPICAL CONNECTION DIAGRAMS
2.4 to 5.0 V
Supply
+
100 µF
0.1 µ F
19
VA_HPA
12
2.4 to 5.0 V
Supply
2.4 to 5.0 V
Supply
8
+
1.0 µF
TSTIN
VL
HP_A
0.1 µF
Cout
100 µH
18 +
0.15
µF
220 µF
6
+
1.0 µF
VD
HP_B
MCLK
3
LRCK
2
1
*
24
DRIVER_A
SC LK
SDIN1
SDIN2
SDIN3
DRIVER_B
16
23
14
13
DEM
16 Ω
Headphones
0.15
µF
CS44210
5
4
Cout
100 µH
21+
220 µF
0.1 µF
Digital
Audio
Source
MOSFET
Driver
&
Power
Stage
Output
Filter
MOSFET
Driver
&
Power
Stage
Output
Filter
RST
15
Mode
Control
20
VA_HPB
*
9
10
AD1/CDOUT
DIF 0
DIF1
SYNC_CLK 11
GND
GND
GND
17
22
7
Sync Clock
* This feature is unavailable in this mode.
This pin should be grounded.
Figure 4. Typical CS44210 Connection Diagram Stand-Alone Mode
DS539PP1
11
CS44210
2.4 to 5.0 V
Supply
+
100 µF
0.1 µ F
19
VA_HPA
12
2.4 to 5.0 V
Supply
2.4 to 5.0 V
Supply
8
+
1.0 µF
20
VA_HPB
TSTIN
VL
HP_A
0.1 µF
Cout
100 µH
18 +
0.15
µF
220 µ F
6
+
1.0 µF
VD
HP_B
CS44210
5
MCLK
3
LRCK
4
2
1
24
DRIVER_A
µC/
Mode
Control
23
15
9
10
14
SC LK
SDIN1
SDIN2 *
SDIN3 *
DRIVER_B
16
0.15
µF
220 µF
0.1 µF
Digital
Audio
Source
Cout
100 µH
21 +
13
SDA/CDIN
16 Ω
Headphones
MOSFET
Driver
&
Power
Stage
Output
Filter
MOSFET
Driver
&
Power
Stage
Output
Filter
RST
AD1/CDOUT
SCL/CCLK
SYNC_CLK 11
AD0/CS
GND
GND
GND
17
22
7
Sync Clock
* Unused SDIN pins should be connected to GND
Figure 5. Typical CS44210 Connection Diagram Control Port Mode
12
DS539PP1
CS44210
3. REGISTER QUICK REFERENCE
Addr
Function
2h
Power and Muting
Control
3h
Channel A
Volume Control
default
default
4h
Channel B
Volume Control
default
5h
Tone Control
default
6h
Mode Control 1
default
7h
Limiter Attack Rate
default
8h
Limiter Release Rate
default
9h
Volume and Mixing
Control
Ah
Mode Control2
Bh
Mode Control 3
Ch
Revision Indicator
default
default
default
default
7
6
5
4
3
2
1
0
SZC1
SZC0
PDN
FLT
RUPBYP
RDNBYP
Reserved
Reserved
1
0
1
0
0
0
0
0
VOLA7
VOLA6
VOLA5
VOLA4
VOLA3
VOLA2
VOLA1
VOLA0
0
0
0
0
0
0
0
0
VOLB7
VOLB6
VOLB5
VOLB4
VOLB3
VOLB2
VOLB1
VOLB0
0
0
0
0
0
0
0
0
BB3
BB2
BB1
BB0
TB3
TB2
TB1
TB0
0
0
0
0
0
0
0
0
BBCF1
BBCF0
TBCF1
TBCF0
TC1
TC0
TC_EN
LIM_EN
0
0
0
0
0
0
0
0
ARATE7
ARATE6
ARATE5
ARATE4
ARATE3
ARATE2
ARATE1
ARATE0
0
0
0
1
0
0
0
0
RRATE7
RRATE6
RRATE5
RRATE4
RRATE3
RRATE2
RRATE1
RRATE0
0
0
1
0
0
0
0
0
IS1
IS0
ATAPI3
ATAPI2
ATAPI1
ATAPI0
1
0
RMP_SP1 RMP_SP0
0
0
0
1
MCLKDIV
CLKDV1
CLKDV0
DBS
FRQSFT1 FRQSFT0
0
1
DEM1
DEM0
0
0
0
0
0
0
0
0
DIF1
DIF0
A=B
VCBYP
CP_EN
FREEZE
Reserved
Reserved
0
0
0
0
0
0
0
0
Reserved
Reserved
Reserved
Reserved
REV3
REV2
REV1
REV0
0
0
0
0
Read Only Read Only Read Only Read Only
Table 1. Register Quick Reference
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CS44210
4. REGISTER DESCRIPTIONS
4.1 Power and Muting Control (address 02h)
7
SZC1
1
6
SZC0
0
5
PDN
1
4
FLT
0
3
RUPBYP
0
2
RDNBYP
0
1
Reserved
0
0
Reserved
0
4.1.1 SOFT RAMP AND ZERO CROSS CONTROL (SZC)
Default = 10
00 - Immediate Change
01 - Zero Cross Control
10 - Ramped Control
11 - Reserved
Function:
Immediate Change
When Immediate Change is selected, all level changes will take effect immediately in one step.
Zero Cross Control
Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will occur
on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a
time-out period of 512 sample periods (10.7 ms at 48 kHz sample rate) if the signal does not encounter a
zero crossing. The zero cross function is independently monitored and implemented for each channel.
Ramped Control
Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally ramping, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock periods.
Note: Ramped Control is not available in Double Speed Mode.
4.1.2 POWER DOWN (PDN)
Default = 1
0 - Disabled
1 - Enabled
Function:
The entire device will enter a low-power state when this function is enabled, and the contents of the control
registers are retained in this mode. The power-down bit defaults to ‘enabled’ on power-up and must be
disabled before normal operation in Control Port mode can occur.
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CS44210
4.1.3 FLOAT OUTPUT (FLT)
Default = 0
0 - Disabled
1 - Enabled
Function:
When enabled, this bit will cause the headphone output of the CS44210 to float when in the power down
state (PDN=1). The float function can be used in single-ended applications to maintain the charge on the
DC-blocking capacitor during power transients. On power transitions, the output will quickly change to the
bias point, however, if the DC-blocking capacitor still has a full charge, as in short power cycles, the transition will be very small, often inaudible. Refer to Section 6.4.
4.1.4 RAMP UP BYPASS (RUPBYP)
Default = 0
0 - Normal
1 - Bypass
Function:
When in normal mode, the duty cycle of the output PWM signal is increased at a rate determined by the
Ramp Speed variable (RMP_SPx). Normal mode is used in Single Ended applications to reduce pops in
the output caused by the DC-blocking capacitor. When the ramp up function is bypassed in Single Ended
applications, there will be an abrupt change in the output signal. Refer to Section 6.4.
4.1.5 RAMP DOWN BYPASS (RDNBYP)
Default = 0
0 - Disabled
1 - Enabled
Function:
When in normal mode, the duty cycle of the output PWM signal is decreased at a rate determined by the
Ramp Speed variable (RMP_SPx). Normal mode is used in Single Ended applications to reduce pops in
the output caused by the DC-blocking capacitor and changes in bias conditions. When the ramp down
function is bypassed in Single Ended applications, there will be an abrupt change in the output signal. Refer to Section 6.4.
4.2 Channel A Volume Control (address 03h) (VOLA)
4.3 Channel B Volume Control (address 04h) (VOLB)
7
VOLx7
0
6
VOLx6
0
5
VOLx5
0
4
VOLx4
0
3
VOLx3
0
2
VOLx2
0
1
VOLx1
0
0
VOLx0
0
Default = 0 dB (No attenuation)
Function:
The Volume Control registers allow independent control of the signal levels in 1 dB increments from +18
to -96 dB. Volume settings are decoded using a 2’s complement code, as shown in Table 2. The volume
changes are implemented as dictated by the Soft and Zero Cross bits. All volume settings less than -96 dB
are equivalent to muting the channel via the ATAPI bits (see Section 4.8.3).
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CS44210
Note: All volume settings greater than +18 dB are interpreted as +18 dB.
Binary Code
00001010
00000111
00000000
11000100
10100110
Decimal Value
12
7
0
-60
-90
Volume Setting
+12 dB
+7 dB
0 dB
-60 dB
-90 dB
Table 2. Example Volume Settings
4.4 Tone Control (address 05h)
7
BB3
0
6
BB2
0
5
BB1
0
4
BB0
0
3
TB3
0
2
TB2
0
1
TB1
0
0
TB0
0
4.4.1 BASS BOOST LEVEL (BB)
Default = 0 dB (No Bass Boost)
Function:
The level of the shelving bass boost filter is set by Bass Boost Level. The level can be adjusted in 1 dB
increments from 0 to +12 dB of boost. Boost levels are decoded as shown in Table 3. Levels above
+12 dB are interpreted as +12 dB.
Binary Code
0000
0010
1010
1001
1100
Decimal Value
0
2
6
9
12
Boost Setting
0 dB
+2 dB
+6 dB
+9 dB
+12 dB
Table 3. Example Bass Boost Settings
4.4.2 TREBLE BOOST LEVEL (TB)
Default = 0 dB (No Treble Boost)
Function:
The level of the shelving treble boost filter is set by Treble Boost Level. The level can be adjusted in 1 dB
increments from 0 to +12 dB of boost. Boost levels are decoded as shown in Table 4. Levels above
+12 dB are interpreted as +12 dB.
Note: Treble Boost is not available in Double Speed Mode.
Binary Code
0000
0010
1010
1001
1100
Decimal Value
0
2
6
9
12
Boost Setting
0 dB
+2 dB
+6 dB
+9 dB
+12 dB
Table 4. Example Treble Boost Settings
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CS44210
4.5 Mode Control 1 (address 06h)
7
BBCF1
0
6
BBCF0
0
5
TBCF1
0
4
TBCF0
0
3
TC1
0
2
TC0
0
1
TC_EN
0
0
LIM_EN
0
4.5.1 BASS BOOST CORNER FREQUENCY (BBCF)
Default = 00
00 - 50 Hz
01 - 100 Hz
10 - 200 Hz
11 - Reserved
Function:
The bass boost corner frequency is user-selectable. The corner frequency is a function of LRCK (sampling frequency), the DBS bit and the BBCF bits as shown in Table 5 and Table 6.
BBCF
Fs
00
01
10
11
LRCK in Single Speed Mode (DBS=0)
48 kHz
24 kHz
12 kHz
8 kHz
50 Hz
25 Hz
12.5 Hz
8.33 Hz
100 Hz
50 Hz
25 Hz
16.7 Hz
200 Hz
100 Hz
50 Hz
33.3 Hz
Reserved
Reserved
Reserved
Reserved
Table 5. Base Boost Corner Frequencies in Single Speed Mode
BBCF
Fs
00
01
10
11
LRCK in Double Speed Mode (DBS=1)
96 kHz
48 kHz
24 kHz
16 kHz
50 Hz
25 Hz
12.5 Hz
8.33 Hz
100 Hz
50 Hz
25 Hz
16.7 Hz
200 Hz
100 Hz
50 Hz
33.3 Hz
Reserved
Reserved
Reserved
Reserved
Table 6. Base Boost Corner Frequencies in Double Speed Mode
4.5.2 TREBLE BOOST CORNER FREQUENCY (TBCF)
Default = 00
00 - 2 kHz
01 - 4 kHz
10 - 7 kHz
11 - Reserved
Function:
The treble boost corner frequency is user selectable. The corner frequency is a function of LRCK (sampling frequency) and the TBCF bits as shown in Table 7.
Note: Treble Boost is not available in Double Speed Mode.
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CS44210
TBCF
Fs
00
01
10
11
LRCK in Single Speed Mode (DBS=0)
48 kHz
24 kHz
12 kHz
8 kHz
2 kHz
1 kHz
0.5 kHz
0.33 kHz
4 kHz
2 kHz
1 kHz
0.67 kHz
7 kHz
3.5 kHz
1.75 kHz
1.17 kHz
Reserved
Reserved
Reserved
Reserved
Table 7. Treble Boost Corner Frequencies in Single Speed Mode
4.5.3 TONE CONTROL MODE (TC)
Default = 00
00 - All settings are taken from user registers
01 - 12 dB of Bass Boost at 100 Hz and 6 dB of Treble Boost at 7 kHz (at LRCK = 48 kHz)
10 - 8 dB of Bass Boost at 100 Hz and 4 dB of Treble Boost at 7 kHz (at LRCK = 48 kHz)
11 - 4 dB of Bass Boost at 100 Hz and 2 dB of Treble Boost at 7 kHz (at LRCK = 48 kHz)
Function:
The Tone Control Mode bits determine how the Bass Boost and Treble Boost features are configured.
The user-defined settings from the Bass and Treble Boost Level and Corner Frequency registers are used
when these bits are set to ‘00’. Alternately, one of three pre-defined settings may be used (these settings
are a function of LRCK - refer to tables 5, 6, and 7).
Note: Treble boost is not available in Double Speed Mode.
4.5.4 TONE CONTROL ENABLE (TC_EN)
Default = 0
0 - Disabled
1 - Enabled
Function:
The Bass Boost and Treble Boost features are active when this function is enabled.
4.5.5 PEAK SIGNAL LIMITER ENABLE (LIM_EN)
Default = 0
0 - Disabled
1 - Enabled
Function:
The CS44210 will limit the maximum signal amplitude to prevent clipping when this function is enabled.
Peak Signal Limiting is performed by first decreasing the Bass and Treble Boost Levels. If the signal is
still clipping, the digital attenuation is increased. The attack rate is determined by the Limiter Attack Rate
register.
Once the signal has dropped below the clipping level, the attenuation is decreased back to the user selected level followed by the Bass Boost being increased back to the user selected level. The release rate
is determined by the Limiter Release Rate register.
Note: The A=B bit should be set to ‘1’ for optimal limiter performance.
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CS44210
4.6 Limiter Attack Rate (address 07h) (ARATE)
7
ARATE7
0
6
ARATE6
0
5
ARATE5
0
4
ARATE4
1
3
ARATE3
0
2
ARATE2
0
1
ARATE1
0
0
ARATE0
0
Default = 10h - 2 LRCK’s per 1/8 dB
Function:
The limiter attack rate is user-selectable. The rate is a function of sampling frequency, As, and the value
in the Limiter Attack Rate register. Rates are calculated using the function RATE = 32/{value}, where {value} is the decimal value in the Limiter Attack Rate register and RATE is in LRCK’s per 1/8 dB of change.
Note: A value of zero in this register is not recommended, as it will induce erratic behavior of the limiter.
Use the LIM_EN bit to disable the limiter function (see "Peak Signal Limiter Enable (LIM_EN)").
Binary Code
00000001
00010100
00101000
00111100
01011010
Decimal Value
1
20
40
60
90
LRCK’s per 1/8 dB
32
1.6
0.8
0.53
0.356
Table 8. Example Limiter Attack Rate Settings
4.7 Limiter Release Rate (address 08h) (RRATE)
7
RRATE7
0
6
RRATE6
0
5
RRATE5
1
4
RRATE4
0
3
RRATE3
0
2
RRATE2
0
1
RRATE1
0
0
RRATE0
0
Default = 20h - 16 LRCK’s per 1/8 dB
Function:
The limiter release rate is user-selectable. The rate is a function of sampling frequency, Fs, and the value
in the Limiter Release Rate register. Rates are calculated using the function RATE = 512/{value}, where
{value} is the decimal value in the Limiter Release Rate register and RATE is in LRCK’s per 1/8 dB of
change.
Note: A value of zero in this register is not recommended, as it will induce erratic behavior of the limiter.
Use the LIM_EN bit to disable the limiter function (see "Peak Signal Limiter Enable (LIM_EN)").
Binary Code
00000001
00010100
00101000
00111100
01011010
Decimal Value
1
20
40
60
90
LRCK’s per 1/8 dB
512
25
12
8
5
Table 9. Example Limiter Release Rate Settings
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CS44210
4.8 Volume and Mixing Control (address 09h)
7
IS1
0
6
IS0
0
5
RMP_SP1
0
4
RMP_SP0
0
3
ATAPI3
1
2
ATAPI2
0
1
ATAPI1
0
0
ATAPI0
1
4.8.1 INPUT MUX SELECTION (IS)
Default = 00
00 - Selects SDIN1 as input
01 - Selects SDIN2 as input
10 - Selects SDIN3 as input
11 - Reserved
Function:
The Input Mux Selector determines which SDIN input is selected.
4.8.2 RAMP SPEED (RMP_SP)
Default = 01
00 - Ramp speed = approximately 0.1 seconds
01 - Ramp speed = approximately 0.2 seconds
10 - Ramp speed = approximately 0.3 seconds
11 - Ramp speed = approximately 0.65 seconds
Function:
This feature is used in Single Ended applications to reduce pops in the output caused by the DC-blocking
capacitor. When in control port mode, the Ramp Speed sets the time for the PWM signal to linearly ramp
up and down from the bias point (50% PWM duty cycle). Refer to Section 6.4.
4.8.3 ATAPI CHANNEL MIXING AND MUTING (ATAPI)
Default = 1001 - HP_A = L, HP_B = R (Stereo)
Function:
The CS44210 implements the channel mixing functions of the ATAPI CD-ROM specification. Refer to
Table 10 and Figure 6 for additional information.
Note: All mixing functions occur prior to the digital volume control.
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CS44210
ATAPI3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
ATAPI2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
ATAPI1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
ATAPI0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
HP_A
MUTE
MUTE
MUTE
MUTE
R
R
R
R
L
L
L
L
[(L+R)/2]
[(L+R)/2]
[(L+R)/2]
[(L+R)/2]
HP_B
MUTE
R
L
[(L+R)/2]
MUTE
R
L
[(L+R)/2]
MUTE
R
L
[(L+R)/2]
MUTE
R
L
[(L+R)/2]
Table 10. ATAPI Decode
Channel A
Digital
Volume
Control
& Mute
Left Channel
Audio Data
EQ
HP_A
EQ
HP_B
Σ
Right Channel
Audio Data
Channel B
Digital
Volume
Control
& Mute
Figure 6. Dynamics Control Block Diagram
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CS44210
4.9 Mode Control 2 (address 0Ah)
7
MCLKDIV
0
6
CLKDV1
0
5
CLKDV0
0
4
DBS
0
3
FRQSFT1
0
2
FRQSFT0
0
1
DEM1
0
0
DEM0
0
4.9.1 MASTER CLOCK DIVIDE ENABLE (MCLKDIV)
Default = 0
Function:
The MCLKDIV bit enables a circuit which divides the externally applied MCLK signal by 2 prior to all other
internal circuitry. MCLKDIV, DBS, CLKDIV and FRQSFT are set per the user’s MCLK and LRCK requirements. Refer to Tables 11, 12, 13, 14, and Section 6.2.
4.9.2 CLOCK DIVIDE (CLKDIV)
Default = 00
Function:
MCLKDIV, DBS, CLKDIV and FRQSFT are set per the user’s MCLK and LRCK requirements. Refer to
Tables 11, 12, 13, 14, and Section 6.2.
4.9.3 DOUBLE SPEED MODE (DBS)
Default = 0
0 - Single Speed
1 - Double Speed (DBS)
Function:
Single Speed supports 8kHz to 50 kHz sample rates and Double Speed supports 50 kHz to 96kHz sample
rates. MCLKDIV, DBS, CLKDIV and FRQSFT are set per the user’s MCLK and LRCK requirements. Refer
to Tables 11, 12, 13, 14, and Section 6.2.
Note: De-emphasis, ramp control, and treble control are not available in Double Speed Mode.
4.9.4 FREQUENCY SHIFT (FRQSFT)
Default = 00
Function:
MCLKDIV, DBS, CLKDIV and FRQSFT are set per the user’s MCLK and LRCK requirements. Refer to
Tables 11, 12, 13, 14, and Section 6.2.
22
DS539PP1
CS44210
DBS = 0
MCLKDIV = 0
DBS = 0
MCLKDIV = 1
PWM
Switching
FRQSFT1 FRQSFT0 CLKDIV1 CLKDIV0 Freq. (kHz)
LRCK
(kHz)
MCLK/
LRCK
MCLK
(MHz)
MCLK/
LRCK
MCLK
(MHz)
48
256
12.288
512
24.576
0
0
0
0
48
384
18.432
768
36.864
0
0
0
1
48
512
24.576
1024
49.152
0
0
1
0
44.1
256
11.2896
512
22.5792
0
0
0
0
44.1
384
16.9344
768
33.8688
0
0
0
1
44.1
512
22.5792
1024
45.1584
0
0
1
0
32
512
16.384
1024
32.768
0
1
0
0
32
768
24.576
1536
49.152
0
1
0
1
32
1024
32.768
2048
65.536
0
1
1
0
24
512
12.288
1024
24.576
0
1
0
0
24
768
18.432
1536
36.864
0
1
0
1
24
1024
24.576
2048
49.152
0
1
1
0
12
1024
12.288
2048
24.576
1
0
0
0
12
1536
18.432
3072
36.864
1
0
0
1
12
2048
24.576
4096
49.152
1
0
1
0
8
1536
12.288
3072
24.576
1
1
0
0
8
2304
18.432
4608
36.864
1
1
0
1
8
3072
24.576
6144
49.152
1
1
1
0
384
352.8
512
384
384
384
Table 11. Single Speed Clock Modes - Control Port Mode
LRCK
(kHz)
MCLK/
LRCK
MCLK
(MHz)
48
256
12.288
48
384
18.432
48
512
24.576
44.1
256
11.2896
44.1
384
16.9344
44.1
512
22.5792
32
1024
32.768
24
1024
24.576
12
2048
24.576
8
1536
12.288
8
2304
18.432
8
3072
24.576
PWM
Switching
Freq. (kHz)
384
352.8
512
384
Table 12. Single Speed Clock Modes - Stand-Alone Mode
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CS44210
DBS = 1
MCLKDIV = 0
DBS = 1
MCLKDIV = 1
LRCK
(kHz)
MCLK/
LRCK
MCLK
(MHz)
MCLK/
LRCK
MCLK
(MHz)
FRQSFT1
FRQSFT0
CLKDIV1
CLKDIV0
96
128
12.288
256
24.576
0
0
0
0
96
192
18.432
384
36.864
0
0
0
1
96
256
24.576
512
49.152
0
0
1
0
PWM
Switching
Freq. (kHz)
384
Table 13. Double Speed Clock Modes - Control Port Mode
LRCK
(kHz)
MCLK/
LRCK
MCLK
(MHz)
96
128
12.288
96
192
18.432
PWM
Switching
Freq. (kHz)
384
Table 14. Double Speed Clock Modes - Stand-Alone Mode
4.9.5 DE-EMPHASIS CONTROL (DEM)
Default = 00
00 - Disabled
01 - 44.1 kHz
10 - 48 kHz
11 - 32 kHz
Function:
Selects the appropriate digital filter to maintain the standard 15 µs/50 µs digital de-emphasis filter response at 32, 44.1 or 48 kHz sample rates (see Figure 7).
Note: De-emphasis is not available in double speed mode.
Gain
dB
T1=50 µs
0dB
T2 = 15 µs
-10dB
F1
3.183 kHz
F2
Frequency
10.61 kHz
Figure 7. De-Emphasis Curve
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CS44210
4.10 Mode Control 3 (address 0Bh)
7
DIF1
0
6
DIF0
0
5
A=B
0
4
VCBYP
0
3
CP_EN
0
2
FREEZE
0
1
HPSEN
0
0
Reserved
0
4.10.1 DIGITAL INTERFACE FORMATS (DIF)
Default = 00
00 - I2S
01 - Right Justified, 16 bit
10 - Left Justified
11 - Right Justified, 24 bit
Function:
The required relationship between the Left/Right clock, serial clock and serial data is defined by the Digital
Interface Format and the options are detailed in figures 19 through 22.
4.10.2 CHANNEL A VOLUME = CHANNEL B VOLUME (A=B)
Default = 0
0 - Disabled
1 - Enabled
Function:
The HP_A and HP_B volume levels and the DRIVER_x outputs are independently controlled by the A and
the B Channel Volume Control Bytes when this function is disabled. The volume on both HP_A, HP_B,
DRIVER_A and DRIVER_B are determined by the A Channel Volume Control Byte and the B Channel
Byte is ignored when this function is enabled.
4.10.3 VOLUME CONTROL BYPASS (VCBYP)
Default = 0
0 - Disabled
1 - Enabled
Function:
The digital volume control section is bypassed when this function is enabled. This disables the digital volume control, muting, bass boost, treble boost, limiting, and ATAPI functions.
4.10.4 CONTROL PORT ENABLE (CP_EN)
Default = 0
0 - Disabled
1 - Enabled
Function:
This bit defaults to 0, allowing the device to power-up in Stand-Alone mode. The Control port mode can
be accessed by setting this bit to 1. This will allow the operation of the device to be controlled by the registers and the pin definitions will conform to Control Port Mode. Refer to Section 7.1.
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CS44210
4.10.5 FREEZE (FREEZE)
Default = 0
0 - Disabled
1 - Enabled
Function:
This function allows modifications to be made to the registers without the changes being taking effect until
the FREEZE is disabled. To make multiple changes in the Control port registers take effect simultaneously, you will first enable the FREEZE Bit, then make all register changes, then Disable the FREEZE bit.
4.11 Revision Indicator (address 0Ch)[Read Only]
7
Reserved
0
6
Reserved
0
5
Reserved
0
4
Reserved
0
3
REV3
0
2
REV2
0
1
REV1
0
0
REV0
0
Default = none
0000 - Revision A
0001 - Revision B
0010 - Revision C
etc.
Function:
This read-only register indicates the revision level of the device.
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CS44210
5. PIN DESCRIPTION
Serial Data 2
SDIN2
Serial Data 1
SDIN1
Left/Right Clock
LRCK
Serial Clock
SCLK
Master Clock
MCLK
Digital Power
VD
Ground
GND
Interface Power
VL
SCL/CCLK/DIF0 SCL/CCLK/DIF0
Addr0/ChipSel/DIF1
AD0/CS/DIF1
Sync Clock
SYNC_CLK
Test In
TSTIN
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
SDIN3
Serial Data 3
RST
Reset
GND
Headphone B Ground
HP_B
Headphone B Output
VA_HPB
Headphone B Power
VA_HPA
Headphone A Power
HP_A
Headphone A Output
GND
Headphone A Ground
SDA/CDIN/DEM SDA/CDIN/DEM
AD1/CDOUT
Addr1/CDOUT
DRIVER_A
Driver Output A
DRIVER_B
DriverOutput B
SDIN1
SDIN2
SDIN3
2
1
24
Serial Audio Data Input (Input) - Input for two’s complement serial audio data. Unused inputs
should be grounded.
LRCK
3
Left Right Clock (Input) - Determines which channel, Left or Right, is currently active on the
serial audio data line. The frequency of the left/right clock must be at the audio sample rate, Fs.
SCLK
4
Serial Clock (Input) - Serial clock for the serial audio interface.
MCLK
5
Master Clock (Input) - Clock source for the PWM modulator and digital filters. Table 11, 12, 13
and 14 illustrate several standard audio sample rates and the required master clock frequencies.
VD
6
Digital Power (Input) - Positive power supply for the digital section. Refer to "Recommended
Operating Conditions" for appropriate voltages.
GND
7, 17 Ground (Input) - Ground Reference.
& 22
VL
8
Logic Power (Input) - Determines the required signal level for the digital input/output. Refer to
"Recommended Operating Conditions" for appropriate voltages.
Sync Clock
11
SYNC_CLK (Output) - Provides a high frequency clock signal at 32 x PWM switching frequency
to synchronize external circuitry, if needed.
TSTIN
12
Test In (Input) - This pin is not used and must remaing floating.
DRIVER_A
DRIVER_B
14
13
DRIVER OUTPUTS(Outputs) Outputs used to drive external power devices.
HP_A
HP_B
18
21
Headphone Outputs (Output) - PWM Headphone Outputs. An external LC filter should be
added to suppress high frequency switching noise. A DC blocking capacitor is also required.
Refer to Typical Connection Diagrams.
VA_HPA
VA_HPB
19
20
Headphone Amplifier Power (Input) - Positive power supply for the headphone amplifier.
Refer to "Recommended Operating Conditions" for appropriate voltages.
RST
23
Reset (Input) - The device enters a low power mode and all internal registers are reset to their
default settings when low. The control port cannot be accessed when Reset is low. See Section 6.5
9
Serial Control Port Clock (Input) - Serial clock for the serial control port. Requires an external
pull-up resistor to VL in Two-Wire mode.
Control Port
Definitions
SCL/CCLK
DS539PP1
27
CS44210
ADO/CS
10
Address Bit 0 (Two-Wire) / Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin
Two-Wire mode; CS is used to enable the control port interface.
AD1/CDOUT
15
AD1/CDOUT - Address Bit 1 (Two Wire) / Serial Control data out (SPI) (Input/Output) - In
Two- Wire mode, AD1 is a chip address pin. In SPI mode, CDOUT is the output data from the
control port interface.
SDA/CDIN
16
Serial Control Data (Input/Output) - SDA is a data I/O line in Two-Wire mode and requires an
external pull-up resistor to the logic interface voltage. CDIN is the input data line for the control
port interface in SPI mode.
9
10
Digital Interface Format (Input) - The required relationship between the Left/Right clock, serial
clock and serial data is defined by the Digital Interface Format and the options are detailed
below
Stand Alone
Definitions
DIF0
DIF1
.
DIF1
0
0
1
1
DIF0
0
1
0
1
DESCRIPTION
Left Justified, up to 24-bit data
Right Justified, 24 -bit Data
I2S, up to 24-bit data
Right Justified, 16-bit Data
FIGURE
19
20
21
22
Table 15. Digital Interface Format - DIF1 and DIF0
(St d Al
M d )
AD1/CDOUT
15
Non-applicable (input) - non-functional in this mode should be connected to ground.
DEM
16
De-emphasis Control (Input) - Selects the standard 15 µs/50 µs digital de-emphasis filter
response at 44.1 kHz sample rates. NOTE: De-emphasis is not available in Double or Quad
Speed Modes. When DEM is grounded, de-emphasis is disabled.
28
DS539PP1
CS44210
6. APPLICATIONS
6.1 Grounding and Power Supply Decoupling
As with any switching converter, the CS44210 requires careful attention to power supply and
grounding arrangements to optimize performance.
Figures 4 and 5 show the recommended power arrangement with VD, VA_HPx, and VL connected
to clean supplies. Decoupling capacitors should be
located as close to the device package as possible.
If desired, all supply pins may be connected to the
same supply, but a decoupling capacitor should still
be used on each supply pin.
6.2 Clock Modes
One of the characteristics of a PWM amplifier is
that the frequency content of out-of-band noise
generated by the modulator is dependent on the
PWM switching frequency. The systems designer
will specify the external filter based on this switching frequency. The obvious implementation in a
digital PWM system is to directly lock the PWM
switching rate to the incoming data sample rate.
However, this would require a tuneable filter to attentuate the switching frequency across the range
of possible sample rates. To simplify the external
filter design and to accommodate sample rates
ranging from 8 kHz to 96 kHz the CS44210 Controller uses several clock modes that keep the PWM
switching frequency in a small range.
In control port mode, for operation at a particular
sample rate the user selects register settings (refer
to Section 4.9 and Tables 11 and 13) based on their
MCLK and MCLK/LRCK parameters. When using Stand-Alone mode, refer to Tables 12 and 14
for available clock modes.
6.3 De-Emphasis
The CS44210 includes on-chip digital de-emphasis. Figure 7 shows the de-emphasis curve. The frequency response of the de-emphasis curve will
scale proportionally with changes in sample rate,
Fs.
DS539PP1
The de-emphasis feature is included to accommodate older audio recordings that utilize pre-emphasis equalization as a means of noise reduction.
6.4 PWM PopGuard Transient Control
The CS44210 uses PopGuard® technology to minimize the effects of output transients during power-up and power-down. This technique minimizes
the audio transients commonly produced by single-ended, single-supply converters when it is implemented with external DC-blocking capacitors
connected in series with the audio outputs.
When the device is initially powered-up, the
DRIVER_x, and HP_x outputs are clamped to
GND. Following a delay each output begins to increase the PWM duty cycle toward the quiescent
voltage point. By a speed set by the RMP_SP bit,
the DRIVER_x and HP_x outputs will later reach
the bias point (50% PWM duty cycle), and audio
output begins. This gradual voltage ramping allows
time for the external DC-blocking capacitor to
charge to the quiescent voltage, minimizing the
power-up transient.
To prevent transients at power-down, the device
must first enter its power-down state. When this occurs, audio output ceases and the PWM duty cycle
is decreased until the DRIVER_x and HP_x outputs reach GND. The time required to reach GND
is determined by the RMP_SP bits. This allows the
DC-blocking capacitors to slowly discharge. Once
this charge is dissipated, the power to the device
may be turned off, and the system is ready for the
next power-on.
To prevent an audio transient at the next power-on,
the DC-blocking capacitors must fully discharge
before turning off the power or exiting the power-down state. If full discharge does not occur, a
transient will occur when the audio outputs are initially clamped to GND. The time that the device
must remain in the power-down state is related to
the value of the DC-blocking capacitance and the
output load. For example, with a 220 µF capacitor
29
CS44210
and a 16 ohm load on the headphone outputs, the
minimum power-down time will be approximately
0.4 seconds.
Note that ramp up and ramp down period can be set
to zero with the RUPBYP and RDNBYP bits respectively.
6.5 Recommended Power-up Sequence
6.5.1 Stand Alone Mode
1. Hold RST low until the power supply, master,
and left/right clocks are stable. In this state, the
control port is reset to its default settings and the
HP_x and DRIVER_x lines will remain low.
2. Bring RST high. The device will remain in a low
power state and will initiate the Stand-Alone power-up sequence. The control port will be accessible
at this time.
6.5.2 Control Port Mode
1. Hold RST low until the power supply, master,
and left/right clocks are stable. In this state, the
30
control port is reset to its default settings and the
HP_x and DRIVER_x lines will remain low.
2. Bring RST high. The device will remain in a low
power state and will initiate the Stand-Alone power-up sequence. The control port will be accessible
at this time.
3. On the CS44210 the control port pins are shared
with stand-alone configuration pins. To enable the
control port, the user must set the CP_EN bit. This
is done by performing a Two-Wire or SPI write.
Once the control port is enabled, these pins are dedicated to control port functionality.
To prevent audible artifacts the CP_EN bit (see
Section 4.10.4) should be set prior to the completion of the Stand-Alone power-up sequence, approximately 21mS. Writing this bit will halt the
Stand-Alone power-up sequence and initialize the
control port to its default settings. Note, the CP_EN
bit can be set any time after RST goes high; however, setting this bit after the Stand-Alone power-up sequence has completed can cause audible
artifacts.
DS539PP1
CS44210
7. CONTROL PORT INTERFACE
The control port is used to load all the internal settings. The operation of the control port may be
completely asynchronous with the audio sample
rate. However, to avoid potential interference problems, the control port pins should remain static if
no operation is required.
The CS44210 has MAP auto increment capability,
enabled by the INCR bit in the MAP register,
which is the MSB. If INCR is 0, then the MAP will
stay constant for successive writes. If INCR is set
to 1, then MAP will auto increment after each byte
is written, allowing block reads or writes of successive registers.
7.1 Format Selection
The control port has 2 formats: SPI and Two-Wire,
with the CS44210 operating as a slave device.
If Two-Wire operation is desired, AD0/CS should
be tied to VL or GND. If the CS44210 ever detects
a high to low transition on AD0/CS after power-up
and after the control port is activated, SPI format
will be selected.
7.2 Two-Wire Format
In Two-Wire Format, SDA is a bidirectional data
line. Data is clocked into and out of the part by the
clock, SCL, with a clock to data relationship as
shown in Figure 8. The receiving device should
send an acknowledge (ACK) after each byte received. There is no CS pin. Pins AD0 and AD1
forms the partial chip address and should be tied to
VL or GND as required. The upper 6 bits of the 7bit address field must be 001000.
Note: MCLK is required during all two-wire
transactions. The Two-Wire format is compatible
with the I2C protocol.
7.2.1 Writing in Two-Wire Format
To communicate with the CS44210, initiate a
START condition of the bus. Next, send the chip
address. The eighth bit of the address byte is the
DS539PP1
R/W bit (low for a write). The next byte is the
Memory Address Pointer, MAP, which selects the
register to be read or written. The MAP is then followed by the data to be written. To write multiple
registers, continue providing a clock and data,
waiting for the CS44210 to acknowledge between
each byte. To end the transaction, send a STOP
condition.
7.2.2 Reading in Two-Wire Format
To communicate with the CS44210, initiate a
START condition of the bus. Next, send the chip
address. The eighth bit of the address byte is the
R/W bit (high for a read). The contents of the register pointed to by the MAP will be output after the
chip address. To read multiple registers, continue
providing a clock and issue an ACK after each
byte. To end the transaction, send a STOP condition.
7.3 SPI Format
In SPI format, CS is the CS44210 chip select signal, CCLK is the control port bit clock, CDIN is the
input data line from the microcontroller, CDOUT is
the output data line, and the chip address is
0010000. CS, CCLK and CDIN are all inputs and
data is clocked in on the rising edge of CCLK. CDOUT is an output and is three-stated when not actively outputting data.
7.3.1 Writing in SPI
Figure 9 shows the operation of the control port in
SPI format. To write to a register, bring CS low.
The first 7 bits on CDIN form the chip address and
must be 0010000. The eighth bit is a read/write indicator (R/W), which must be low to write. The
next 8 bits form the Memory Address Pointer
(MAP), which is set to the address of the register
that is to be updated. The next 8 bits are the data
which will be placed into register designated by the
MAP. To write multiple registers, keep CS low and
continue providing clocks on CCLK. End the read
transaction by setting CS high.
31
CS44210
Note 1
SDA
001000
ADDR
AD0
R/W
ACK
DATA
1-8
DATA
1-8
ACK
ACK
SCL
Start
Stop
Note: If operation is a write, this byte contains the Memory Address Pointer, MAP.
Figure 8. Control Port Timing, Two-Wire Format
CS
CCLK
CHIP
ADDRESS
CDIN
0010000
MAP
R/W
DATA
MSB
byte 1
LSB
byte n
MAP = Memory Address Pointer
Figure 9. Control Port Timing, SPI Format (Write)
32
DS539PP1
CS44210
7.3.2 Reading in SPI
Figure 10 shows the operation of the control port in
SPI format. To read to a register, bring CS low. The
first 7 bits on CDIN form the chip address and must
be 0010000. The eighth bit is a read/write indicator
(R/W), which must be high to read. The CDOUT
line will then output the data from the register designated by the MAP. To read multiple registers,
keep CS low and continue providing clocks on
CCLK. End the read transaction by setting CS high.
The CDOUT line will tri-state once CS goes high.
CS
CCLK
CHIP
ADDRESS
CDIN
0010000
byte 1
byte n
R/W
DATA
MSB
CDOUT
LSB
Figure 10. Control Port Timing, SPI Format (Read)
7.4 Memory Address Pointer (MAP)
7
INCR
0
6
Reserved
0
5
Reserved
0
4
Reserved
0
3
MAP3
0
2
MAP2
0
1
MAP1
0
0
MAP0
0
7.4.1 INCR (Auto Map Increment Enable)
Default = ‘0’
0 - Disabled
1 - Enabled
7.4.2 MAP3-0 (Memory Address Pointer)
Default = ‘0000’
DS539PP1
33
CS44210
0
-10
-10
-20
-20
-30
-30
Amplitude (dB)
Amplitude (dB)
0
-40
-50
-60
-40
-50
-60
-70
-70
-80
-80
-90
-90
-100
-100
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
0.4
1
0.42
0.44
0
0.5
-1
0.4
-2
0.3
-3
0.2
-4
-5
-6
0.5
0.52
0.54
0.56
0.58
0. 6
0.1
0
-0.1
-7
-0.2
-8
-0.3
-9
-0.4
-10
-0.5
0.45
0.46
0.47
0. 48
0.49
0.5
0.51
0.52
0.53
0.54
0.55
0
0. 05
0.1
Frequency (norm alized to Fs)
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0. 5
Frequency (norm alized to Fs)
Figure 13. Single Speed Transition Band (Detail)
Figure 14. Single Speed Passband Ripple
0
0
-10
-10
-20
-20
-30
-30
Amplitude (dB)
Amplitude (dB)
0.48
Figure 12. Single Speed Transition Band
Amplitude (dB)
Amplitude (dB)
Figure 11. Single Speed Stopband Rejection
-40
-50
-60
-40
-50
-60
-70
-70
-80
-80
-90
-90
-100
-100
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
Frequency (norm alized to Fs)
Figure 15. Double Speed Stopband Rejection
34
0.46
Frequency (norm alized to Fs)
Frequency (norm alized to Fs)
1
0.4
0.42
0.44
0.46
0.48
0.5
0.52
0.54
0.56
0.58
0. 6
Frequency (norm alized to Fs)
Figure 16. Double Speed Transition Band
DS539PP1
CS44210
0
0 .50
-1
0 .40
-2
0 .30
Amplitude (dB)
-3
0 .20
-4
0 .10
-5
0 .00
-6
-0 .10
-7
-0 .20
-8
-0 .30
-9
-0 .40
-10
-0 .50
0.45
0.46
0.47
0. 48
0. 49
0.5
0.51
0.52
0.53
0.54
0.55
0. 00
0 .05
0. 1 0
Fre que ncy (norm alize d to Fs )
Figure 17. Double Speed Transition Band (Detail)
0. 20
0.2 5
0 .30
0. 35
0. 40
0. 45
0.5 0
Figure 18. Double Speed Passband Ripple
Left Channel
LRCK
0. 15
F r equency (no r maliz ed t o F s )
Right Channel
SCLK
SDATA
MSB -1 -2 -3 -4 -5
+5 +4 +3 +2 +1 LSB
MSB -1 -2 -3 -4
+5 +4 +3 +2 +1 LSB
Figure 19. Left Justified, up to 24-Bit Data
LRCK
Right Channel
Left Channel
SCLK
SDATA
0
7 6 5
23 22 21 20 19 18
4 3 2 1 0
23 22 21 20 19 18
7 6 5 4 3 2 1 0
32 clocks
Figure 20. Right Justified, 24-Bit Data
Left Channel
LRCK
Right Channel
SCLK
SDATA
MSB -1 -2 -3 -4 -5
+5 +4 +3 +2 +1 LSB
MSB -1 -2 -3 -4
+5 +4 +3 +2 +1 LSB
Figure 21. I2S, Up to 24-Bit Data
DS539PP1
35
CS44210
LRCK
Right Channel
Left Channel
SCLK
SDATA
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
32 clocks
Figure 22. Right Justified, 16-Bit Data
8. PARAMETER DEFINITIONS
Total Harmonic Distortion + Noise (THD+N)
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified
bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels.
Dynamic Range
The ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the
specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth
made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement
to full scale. This technique ensures that the distortion components are below the noise level and do not
effect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307.
Interchannel Isolation
A measure of crosstalk between the left and right channels. Measured for each channel at the converter’s
output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in
decibels.
Interchannel Gain Mismatch
The gain difference between left and right channels. Units in decibels.
9.0 REFERENCES
1) “The I2C-Bus Specification: Version 2.0” Philips Semiconductors, December 1998.
http://www.semiconductors.philips.com
36
DS539PP1
CS44210
10. PACKAGE DIMENSIONS
24L TSSOP (4.4 mm BODY) PACKAGE DRAWING
N
D
E11
A2
E
A
∝
e
b2
SIDE VIEW
A1
L
END VIEW
SEATING
PLANE
1 2 3
TOP VIEW
DIM
A
A1
A2
b
D
E
E1
e
L
MIN
-0.002
0.03346
0.00748
0.303
0.248
0.169
-0.020
0°
∝
INCHES
NOM
-0.004
0.0354
0.0096
0.307
0.2519
0.1732
0.026 BSC
0.024
4°
MAX
0.043
0.006
0.037
0.012
0.311
0.256
0.177
-0.028
8°
MIN
-0.05
0.85
0.19
7.70
6.30
4.30
-0.50
0°
MILLIMETERS
NOM
--0.90
0.245
7.80
6.40
4.40
0.65 BSC
0.60
4°
NOTE
MAX
1.10
0.15
0.95
0.30
7.90
6.50
4.50
-0.70
8°
2,3
1
1
JEDEC #: MO-153
Controlling Dimension is Millimeters.
Note:
1.“D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold
mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per
side.
2.Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be
0.13 mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not
reduce dimension “b” by more than 0.07 mm at least material condition.
3.These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.
DS539PP1
37