LF147JAN www.ti.com SNOSAJ9A – APRIL 2005 – REVISED MARCH 2013 LF147JAN Wide Bandwidth Quad JFET Input Operational Amplifier Check for Samples: LF147JAN FEATURES DESCRIPTION • • • • • • • • The LF147 is a low cost, high speed quad JFET input operational amplifier with an internally trimmed input offset voltage ( BI-FET™ II technology). The device requires a low supply current and yet maintains a large gain bandwidth product and a fast slew rate. In addition, well matched high voltage JFET input devices provide very low input bias and offset currents. The LF147 is pin compatible with the standard LM148. This feature allows designers to immediately upgrade the overall performance of existing LF148 and LM124 designs. 1 23 • • Internally Trimmed Offset Voltage: 5 mV Max Low Input Bias Current: 50 pA Typ. Low Input Noise Current: 0.01 pA/√Hz Typ. Wide Gain Bandwidth: 4 MHz Typ. High Slew Rate: 13 V/μs Typ. Low Supply Current: 7.2 mA Typ. High Input Impedance: 1012Ω Typ. Low Total Harmonic Distortion: – AV = 10, RL = 10KΩ, VO = 20VP-P – BW = 20Hz — 20KHz ≤0.02% Typ. Low 1/f Noise Corner: 50 Hz Typ. Fast Settling Time to 0.01%: 2 μs Typ. The LF147 may be used in applications such as high speed integrators, fast D/A converters, sample-andhold circuits and many other circuits requiring low input offset voltage, low input bias current, high input impedance, high slew rate and wide bandwidth. The device has low noise and offset voltage drift. Connection Diagram Figure 1. CDIP Package Top View See Package Number J 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. BI-FET is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2005–2013, Texas Instruments Incorporated LF147JAN SNOSAJ9A – APRIL 2005 – REVISED MARCH 2013 www.ti.com Simplified Schematic Figure 2. ¼ Quad Detailed Schematic These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 2 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LF147JAN LF147JAN www.ti.com SNOSAJ9A – APRIL 2005 – REVISED MARCH 2013 Absolute Maximum Ratings (1) Supply Voltage ±18V Differential Input Voltage ±30V Input Voltage Range (2) ±15V Output Short Circuit Duration (3) Continuous Power Dissipation (4) (5) 900 mW TJ max 150°C θJA CDIP 70°C/W Operating Temperature Range −55°C ≤ TA ≤ 125°C Storage Temperature Range −65°C ≤ TA ≤ 150°C Lead Temperature (Soldering, 10 sec.) ESD (1) (2) (3) (4) (5) (6) 260°C (6) 900V Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Unless otherwise specified the absolute maximum negative input voltage is equal to the negative power supply voltage. Any of the amplifier outputs can be shorted to ground indefinitely, however, more than one should not be simultaneously shorted as the maximum junction temperature will be exceeded. The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax (maximum junction temperature), θJA (Package junction to ambient thermal resistance), and TA (ambient temperature). The maximum allowable power dissipation at any temperature is PDmax = (TJmax — TA) / θJA or the number given in the Absolute Maximum Ratings, whichever is lower. Max. Power Dissipation is defined by the package characteristics. Operating the part near the Max. Power Dissipation may cause the part to operate outside specified limits. Human body model, 1.5 kΩ in series with 100 pF. Recommended Operating Conditions Supply Voltage Range ±5V to ±15V Quality Conformance Inspection Mil-Std-883, Method 5005 - Group A Subgroup Description Temp (°C) 1 Static tests at 25 2 Static tests at 125 3 Static tests at -55 4 Dynamic tests at 25 5 Dynamic tests at 125 6 Dynamic tests at -55 7 Functional tests at 25 8A Functional tests at 125 8B Functional tests at -55 9 Switching tests at 25 10 Switching tests at 125 11 Switching tests at -55 12 Settling Time at 25 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LF147JAN 3 LF147JAN SNOSAJ9A – APRIL 2005 – REVISED MARCH 2013 www.ti.com LF147JAN Electrical Characteristics DC Parameters The following conditions apply, unless otherwise specified:VCC = ±15V, VCM = 0V Symbol VIO Parameter Input Offset Voltage ±IIB Input Bias Current IIO Input Offset Current Conditions Notes Subgroups Min Max Unit +VCC = 26V, -VCC = -4V, VCM = -11V -5.0 5.0 mV 1 -7.0 7.0 mV 2, 3 +VCC = 4V, -VCC = -26V, VCM = 11V -5.0 5.0 mV 1 -7.0 7.0 mV 2, 3 +VCC = 15V, -VCC = -15V, VCM = 0V -5.0 5.0 mV 1 -7.0 7.0 mV 2, 3 +VCC = 5V, -VCC = -5V, VCM = 0V -5.0 5.0 mV 1 -7.0 7.0 mV 2, 3 +VCC = 26V, -VCC = -4V, VCM = -11V -0.4 0.2 nA 1 -10 50 nA 2 +VCC = 15V, -VCC = -15V, VCM = 0V -0.2 0.2 nA 1 -10 50 nA 2 +VCC = 4V, -VCC = -26V, VCM = 11V -0.2 1.2 nA 1 -10 70 nA 2 +VCC = 15V, -VCC = -15V, VCM = 0V -0.1 0.1 nA 1 -20 20 nA 2 +PSRR Power Supply Rejection Ratio -VCC = -15V, +VCC = 20V to 10V 80 dB 1, 2, 3 -PSRR Power Supply Rejection Ratio +VCC = 15V, -VCC = -20V to -10V 80 dB 1, 2, 3 CMRR Input Voltage Common Mode Rejection ±VCC = ±4V to ±26V, VCM = -11V to +11V 80 dB 1, 2, 3 +IOS Output Short Circuit Current +VCC = 15V, -VCC = -15V, VCM = -10V, t ≤ 25mS -80 mA 1, 2, 3 −IOS Output Short Circuit Current +VCC = 15V, -VCC = -15V, VCM = 10V, t ≤ 25mS 80 mA 1, 2, 3 ICC Supply Current 14 mA 1, 2 16 mA 3 Delta VIO / Delta T Input Offset Voltage Temp. Sensitivity 25°C ≤ TA ≤ +125°C See (1) -30 30 µV/°C 2 -55°C ≤ TA ≤ 25°C See (1) -30 30 µV/°C 3 +VOP Output Voltage Swing +VCC = 15V, -VCC = -15V, RL=10KΩ, VCM = -15V 12 V 4, 5, 6 +VCC = 15V, -VCC = -15V, RL=2KΩ, VCM = -15V 10 V 4, 5, 6 -VOP +AVS Output Voltage Swing Open Loop Voltage Gain +VCC = 15V, -VCC = -15V +VCC = 15V, -VCC = -15V, RL=10KΩ, VCM = 15V -12 V 4, 5, 6 +VCC = 15V, -VCC = -15V, RL = 2KΩ, VCM = 15V -10 V 4, 5, 6 +VCC = 15V, -VCC = -15V, RL = 2KΩ, VO = 0 to 10V 50 V/mV 4 25 V/mV 5, 6 50 V/mV 4 25 V/mV 5, 6 20 V/mV 4, 5, 6 −AVS Open Loop Voltage Gain +VCC = 15V, -VCC = -15V, RL = 2KΩ, VO = 0 to -10V AVS Open Loop Voltage Gain +VCC = 5V, -VCC = -5V, RL = 10KΩ, VO = ±2V (1) 4 Calculated parameters. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LF147JAN LF147JAN www.ti.com SNOSAJ9A – APRIL 2005 – REVISED MARCH 2013 LF147JAN Electrical Characteristics AC Parameters The following conditions apply, unless otherwise specified:VCC = ±15V Symbol +SR Parameter Slew Rate Conditions Notes VI = -5V to +5V Min Max Unit Subgroups 7 V/µS 7 5 V/µS 8A, 8B 7 V/µS 7 5 V/µS 8A, 8B -SR Slew Rate TRTR Transient Response Rise Time AV=1, VI=50mV, CL= 100pF, RL=2KΩ 200 nS 7, 8A, 8B TROS Transient Response Overshoot AV=1, VI=50mV, CL= 100pF, RL=2KΩ 40 % 7, 8A, 8B NIBB Noise Broadband BW = 10Hz to 15KHz, RS = 0Ω 15 µVRMS 7 NIPC Noise Popcorn BW = 10Hz to 15KHz, RS = 100KΩ 80 µVPK 7 CS Channel Separation RL = 2KΩ 80 dB 7 RL = 2KΩ, VI = ±10V, A to B 80 dB 7 RL = 2KΩ, VI = ±10V, A to C 80 dB 7 RL = 2KΩ, VI = ±10V, A to D 80 dB 7 RL = 2KΩ, VI = ±10V, B to A 80 dB 7 RL = 2KΩ, VI = ±10V, B to C 80 dB 7 RL = 2KΩ, VI = ±10V, B to D 80 dB 7 RL = 2KΩ, VI = ±10V, C to A 80 dB 7 RL = 2KΩ, VI = ±10V, C to B 80 dB 7 RL = 2KΩ, VI = ±10V, C to D 80 dB 7 RL = 2KΩ, VI = ±10V, D to A 80 dB 7 RL = 2KΩ, VI = ±10V, D to B 80 dB 7 RL = 2KΩ, VI = ±10V, D to C 80 dB 7 nS 12 ±tS Settling Time VI = +5V to -5V 1,50 0 AV = 1 LF147JAN Electrical Characteristics Drift Values The following conditions apply, unless otherwise specified: DC ±VCC = ±15V, VCM = 0V, “Delta calculations performed on JAN S and QMLV devices at group B, subgroup 5 only” Min Max Unit Subgroups +VCC = 15V, -VCC = -15V, VCM = 0V -1.0 1.0 mV 1 Input Bias Current +VCC = 15V, -VCC = -15V, VCM = 0V -0.1 0.1 nA 1 Input Bias Current +VCC = 15V, -VCC = -15V, VCM = 0V -0.1 0.1 nA 1 Symbol Parameters Conditions VIO Input Offset Voltage +IIB -IIB Notes Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LF147JAN 5 LF147JAN SNOSAJ9A – APRIL 2005 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics 6 Input Bias Current Input Bias Current Figure 3. Figure 4. Supply Current Positive Common-Mode Input Voltage Limit Figure 5. Figure 6. Negative Common-Mode Input Voltage Limit Positive Current Limit Figure 7. Figure 8. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LF147JAN LF147JAN www.ti.com SNOSAJ9A – APRIL 2005 – REVISED MARCH 2013 Typical Performance Characteristics (continued) Negative Current Limit Output Voltage Swing Figure 9. Figure 10. Output Voltage Swing Gain Bandwidth Figure 11. Figure 12. Bode Plot Slew Rate Figure 13. Figure 14. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LF147JAN 7 LF147JAN SNOSAJ9A – APRIL 2005 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) 8 Distortion vs Frequency Undistorted Output Voltage Swing Figure 15. Figure 16. Open Loop Frequency Response Common-Mode Rejection Ratio Figure 17. Figure 18. Power Supply Rejection Ratio Equivalent Input Noise Voltage Figure 19. Figure 20. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LF147JAN LF147JAN www.ti.com SNOSAJ9A – APRIL 2005 – REVISED MARCH 2013 Typical Performance Characteristics (continued) Open Loop Voltage Gain Output Impedance Figure 21. Figure 22. Inverter Settling Time Figure 23. Pulse Response RL=2 kΩ, CL=10 pF Small Signal Inverting Small Signal Non-Inverting Figure 24. Figure 25. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LF147JAN 9 LF147JAN SNOSAJ9A – APRIL 2005 – REVISED MARCH 2013 www.ti.com Pulse Response (continued) RL=2 kΩ, CL=10 pF Large Signal Inverting Large Signal Non-Inverting Figure 26. Figure 27. Current Limit (RL=100Ω) Figure 28. 10 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LF147JAN LF147JAN www.ti.com SNOSAJ9A – APRIL 2005 – REVISED MARCH 2013 APPLICATION HINTS The LF147 is an op amp with an internally trimmed input offset voltage and JFET input devices (BI-FET II). These JFETs have large reverse breakdown voltages from gate to source and drain eliminating the need for clamps across the inputs. Therefore, large differential input voltages can easily be accommodated without a large increase in input current. The maximum differential input voltage is independent of the supply voltages. However, neither of the input voltages should be allowed to exceed the negative supply as this will cause large currents to flow which can result in a destroyed unit. Exceeding the negative common-mode limit on either input will force the output to a high state, potentially causing a reversal of phase to the output. Exceeding the negative common-mode limit on both inputs will force the amplifier output to a high state. In neither case does a latch occur since raising the input back within the common-mode range again puts the input stage and thus the amplifier in a normal operating mode. Exceeding the positive common-mode limit on a single input will not change the phase of the output; however, if both inputs exceed the limit, the output of the amplifier will be forced to a high state. The amplifiers will operate with a common-mode input voltage equal to the positive supply; however, the gain bandwidth and slew rate may be decreased in this condition. When the negative common-mode voltage swings to within 3V of the negative supply, an increase in input offset voltage may occur. Each amplifier is individually biased by a zener reference which allows normal circuit operation on ±4.5V power supplies. Supply voltages less than these may result in lower gain bandwidth and slew rate. The LF147 will drive a 2 kΩ load resistance to ±10V over the full temperature range. If the amplifier is forced to drive heavier load currents, however, an increase in input offset voltage may occur on the negative voltage swing and finally reach an active current limit on both positive and negative swings. Precautions should be taken to ensure that the power supply for the integrated circuit never becomes reversed in polarity or that the unit is not inadvertently installed backwards in a socket as an unlimited current surge through the resulting forward diode within the IC could cause fusing of the internal conductors and result in a destroyed unit. As with most amplifiers, care should be taken with lead dress, component placement and supply decoupling in order to ensure stability. For example, resistors from the output to an input should be placed with the body close to the input to minimize “pick-up” and maximize the frequency of the feedback pole by minimizing the capacitance from the input to ground. A feedback pole is created when the feedback around any amplifier is resistive. The parallel resistance and capacitance from the input of the device (usually the inverting input) to AC ground set the frequency of the pole. In many instances the frequency of this pole is much greater than the expected 3 dB frequency of the closed loop gain and consequently there is negligible effect on stability margin. However, if the feedback pole is less than approximately 6 times the expected 3 dB frequency a lead capacitor should be placed from the output to the input of the op amp. The value of the added capacitor should be such that the RC time constant of this capacitor and the resistance it parallels is greater than or equal to the original feedback pole time constant. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LF147JAN 11 LF147JAN SNOSAJ9A – APRIL 2005 – REVISED MARCH 2013 www.ti.com Typical Applications Figure 29. Digitally Selectable Precision Attenuator All resistors 1% tolerance 12 • Accuracy of better than 0.4% with standard 1% value resistors No offset adjustment necessary • Expandable to any number of stages • Very high input impedance VO Attenuation A1 A2 A3 0 0 0 0 0 0 1 −1 dB 0 1 0 −2 dB 0 1 1 −3 dB 1 0 0 −4 dB 1 0 1 −5 dB 1 1 0 −6 dB 1 1 1 −7 dB Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LF147JAN LF147JAN www.ti.com SNOSAJ9A – APRIL 2005 – REVISED MARCH 2013 Figure 30. Long Time Integrator with Reset, Hold and Starting Threshold Adjustment • VO starts from zero and is equal to the integral of the input voltage with respect to the threshold voltage: • Output starts when VIN ≥ VTH • Switch S1 permits stopping and holding any output value • Switch S2 resets system to zero Figure 31. Universal State Variable Filter For circuit shown: fO=3 kHz, fNOTCH=9.5 kHz Q=3.4 Passband gain: Highpass – 0.1 Bandpass – 1 Lowpass – 1 Notch – 10 • fo× Q ≤ 200 kHz • 10V peak sinusoidal output swing without slew limiting to 200 kHz • See LM148 data sheet for design equations Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LF147JAN 13 LF147JAN SNOSAJ9A – APRIL 2005 – REVISED MARCH 2013 Date Released Revision 04/18/05 03/20/13 14 www.ti.com Section Originator Changes A New Release into corporate format L. Lytle 1 MDS datasheets converted into one Corp. datasheet format. MJLF147–X rev 1B1 MDS will be archived A All Changed layout of National Data Sheet to TI format Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LF147JAN PACKAGE OPTION ADDENDUM www.ti.com 7-Nov-2014 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty 25 Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) TBD Call TI Call TI -55 to 125 Device Marking (4/5) JL147BCA ACTIVE CDIP J 14 JM38510/11906BCX ACTIVE CDIP J 14 TBD Call TI Call TI -55 to 125 M38510/11906BCX ACTIVE CDIP J 14 TBD Call TI Call TI -55 to 125 JL147BCA JM38510/11906BCA Q (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. 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