ATMEL ATA6626-PGQW Lin bus transceiver with 3.3v (5v) regulator and watchdog Datasheet

Features
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Master and Slave Operation Possible
Supply Voltage up to 40V
Operating voltage VS = 5V to 27V
Typically 10 µA Supply Current During Sleep Mode
Typically 57 µA Supply Current in Silent Mode
Linear Low-drop Voltage Regulator:
– Normal, Fail-safe, and Silent Mode
– ATA6622 VCC = 3.3V ±2%
– ATA6624 VCC = 5.0V ±2%
– ATA6626 VCC = 5.0V ±2%, TXD Time-out Timer Disabled
– In Sleep Mode VCC is Switched Off
VCC- Undervoltage Detection (4 ms Reset Time) and Watchdog Reset Logical
Combined at Open Drain Output NRES
Negative Trigger Input for Watchdog
Boosting the Voltage Regulator Possible with an External NPN Transistor
LIN Physical Layer According to LIN 2.0, 2.1 and SAEJ2602-2
Wake-up Capability via LIN-bus, Wake Pin, or Kl_15 Pin
INH Output to Control an External Voltage Regulator or to Switch off the Master Pull Up
Resistor
TXD Time-out Timer; ATA6626: TXD Time-out Timer Is Disabled
Bus Pin is Overtemperature and Short Circuit Protected versus GND and Battery
Adjustable Watchdog Time via External Resistor
Advanced EMC and ESD Performance
ESD HBM 8 kV at Pins LIN and VS According to STM5.1
Package: QFN 5 mm × 5 mm with 20 Pins
LIN Bus
Transceiver
with 3.3V (5V)
Regulator and
Watchdog
ATA6622
ATA6624
ATA6626
1. Description
The ATA6622 is a fully integrated LIN transceiver, which complies with the LIN 2.0,
2.1 and SAEJ2602-2 specifications. It has a low-drop voltage regulator for
3.3V/50 mA output and a window watchdog. The ATA6624 has the same functionality
as the ATA6622; however, it uses a 5V/50 mA regulator. The ATA6626 has the same
functionality as ATA6624 without a TXD time-out timer. The voltage regulator is able
to source 50 mA, but the output current can be boosted by using an external NPN
transistor. This chip combination makes it possible to develop inexpensive, simple, yet
powerful slave and master nodes for LIN-bus systems. ATA6622/ATA6624/ATA6626
are designed to handle the low-speed data communication in vehicles, e.g., in convenience electronics. Improved slope control at the LIN-driver ensures secure data
communication up to 20 kBaud. Sleep Mode and Silent Mode guarantee very low current consumption. The ATA6626 is able to switch the LIN unlimited to dominant level
via TXD for low data rates.
4986G–AUTO–09/09
Figure 1-1.
Block Diagram
20
VS
Normal and
Fail-safe
Mode
10
INH
PVCC
Normal
Mode
Receiver
-
9
RXD
+
7
RF Filter
LIN
4
WAKE
16
KL_15
PVCC
Edge
Detection
Wake-up
Bus Timer
Slew Rate Control
TXD
Time-out
Timer
11
TXD
Short Circuit and
Overtemperature
Protection
*)
Control Unit
EN
GND
1
5
Debounce
Time
Mode Select
Normal/Silent/
Fail-safe Mode
3.3/5V
/50 mA/±2%
19
Undervoltage
Reset
12
OUT
Internal Testing
Unit
Watchdog
18
VCC
PVCC
NRES
Adjustable
Watchdog
Oscillator
13
WD_OSC
PVCC
15
MODE
14
3
TM
NTRIG
*) Not in ATA6626
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ATA6622/ATA6624/ATA6626
4986G–AUTO–09/09
ATA6622/ATA6624/ATA6626
2. Pin Configuration
EN
VCC
PVCC
GND
KL15
Pinning QFN20
VS
Figure 2-1.
20
19
18
17
16
1
15
MODE
14
TM
13
WD_OSC
12
NRES
11
TXD
ATA6622/24/26
Table 2-1.
4
GND
5
6
7
8
9
10
INH
WAKE
QFN 5 mm × 5 mm
0.65 mm pitch
20 lead
RXD
3
GND
NTRIG
LIN
2
GND
GND
Pin Description
Pin
Symbol
Function
1
EN
2
GND
3
NTRIG
Low-level watchdog trigger input from microcontroller
4
WAKE
High-voltage input for local wake-up request; if not needed, connect to VS
5
GND
System ground (mandatory)
6
GND
System ground (optional)
7
LIN
LIN-bus line input/output
8
GND
System ground (optional)
9
RXD
Receive data output
10
INH
Battery related output for controlling an external voltage regulator
11
TXD
Transmit data input; active low output (strong pull down) after a local wake-up request
Enables the device in Normal Mode
System ground (optional)
12
NRES
13
WD_OSC
14
TM
15
MODE
For debug mode: low, watchdog is on; high, watchdog is off
16
KL_15
Ignition detection (edge sensitive)
17
GND
System ground (optional)
18
PVCC
3.3V/5V regulator sense input pin
19
VCC
3.3V/5V regulator output/driver pin
20
VS
Backside
Output undervoltage and watchdog reset (open drain)
External resistor for adjustable watchdog timing
For factory testing only (tie to ground)
Battery supply
Heat slug is connected to all GND pins
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3. Functional Description
3.1
Physical Layer Compatibility
Since the LIN physical layer is independent from higher LIN layers (e.g., the LIN protocol layer),
all nodes with a LIN physical layer according to revision 2.x can be mixed with LIN physical layer
nodes, which, according to older versions (i.e., LIN 1.0, LIN 1.1, LIN 1.2, LIN 1.3), are without
any restrictions.
3.2
Supply Pin (VS)
The LIN operating voltage is VS = 5V to 27V. An undervoltage detection is implemented to disable data transmission if VS falls below VSth < 4V in order to avoid false bus messages. After
switching on VS, the IC starts in Fail-safe Mode, and the voltage regulator is switched on (i.e.,
3.3V/5V/50 mA output capability).
The supply current is typically 10 µA in Sleep Mode and 57 µA in Silent Mode.
3.3
Ground Pin (GND)
The IC is neutral on the LIN pin in the event of GND disconnection. It is able to handle a ground
shift up to 11.5% of VS. The mandatory system ground is pin 5.
3.4
Voltage Regulator Output Pin (VCC)
The internal 3.3V/5V voltage regulator is capable of driving loads with up to 50 mA. It is able to
supply the microcontroller and other ICs on the PCB and is protected against overloads by
means of current limitation and overtemperature shut-down. Furthermore, the output voltage is
monitored and will cause a reset signal at the NRES output pin if it drops below a defined threshold Vthun. To boost up the maximum load current, an external NPN transistor may be used, with
its base connected to the VCC pin and its emitter connected to PVCC.
3.5
Voltage Regulator Sense Pin (PVCC)
The PVCC is the sense input pin of the 3.3V/5V voltage regulator. For normal applications (i.e.,
when only using the internal output transistor), this pin is connected to the VCC pin. If an external boosting transistor is used, the PVCC pin must be connected to the output of this transistor,
i.e., its emitter terminal.
3.6
Bus Pin (LIN)
A low-side driver with internal current limitation and thermal shutdown and an internal pull-up
resistor compliant with the LIN 2.x specification are implemented. The allowed voltage range is
between –27V and +40V. Reverse currents from the LIN bus to VS are suppressed, even in the
event of GND shifts or battery disconnection. LIN receiver thresholds are compatible with the
LIN protocol specification. The fall time from recessive to dominant bus state and the rise time
from dominant to recessive bus state are slope controlled.
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ATA6622/ATA6624/ATA6626
4986G–AUTO–09/09
ATA6622/ATA6624/ATA6626
3.7
Input/Output Pin (TXD)
In Normal Mode the TXD pin is the microcontroller interface used to control the state of the LIN
output. TXD must be pulled to ground in order to have a low LIN-bus. If TXD is high or unconnected (internal pull-up resistor), the LIN output transistor is turned off, and the bus is in
recessive state. During Fail-safe Mode, this pin is used as output. It is current-limited to < 8 mA.
and is latched to low if the last wake-up event was from pin WAKE or KL_15.
3.8
TXD Dominant Time-out Function
The TXD input has an internal pull-up resistor. An internal timer prevents the bus line from being
driven permanently in dominant state. If TXD is forced to low for longer than tDOM > 6 ms, the
LIN-bus driver is switched to recessive state.
To reactivate the LIN bus driver, switch TXD to high (> 10 µs).
The time-out function is disabled in the ATA6626. Switching to dominant level on the LIN bus
occurs without any time limitations.
3.9
Output Pin (RXD)
The Output pin reports the state of the LIN-bus to the microcontroller. LIN high (recessive state)
is reported by a high level at RXD; LIN low (dominant state) is reported by a low level at RXD.
The output has an internal pull-up resistor with typically 5 kΩ to VCC. The AC characteristics can
be defined with an external load capacitor of 20 pF.
The output is short-circuit protected. RXD is switched off in Unpowered Mode (i.e., VS = 0V).
3.10
Enable Input Pin (EN)
The Enable Input pin controls the operation mode of the device. If EN is high, the circuit is in
Normal Mode, with transmission paths from TXD to LIN and from LIN to RXD both active. The
VCC voltage regulator operates with 3.3V/5V/50 mA output capability.
If EN is switched to low while TXD is still high, the device is forced to Silent Mode. No data transmission is then possible, and the current consumption is reduced to IVS typ. 57 µA. The VCC
regulator has its full functionality.
If EN is switched to low while TXD is low, the device is forced to Sleep Mode. No data transmission is possible, and the voltage regulator is switched off.
3.11
Wake Input Pin (WAKE)
The Wake Input pin is a high-voltage input used to wake up the device from Sleep Mode or
Silent Mode. It is usually connected to an external switch in the application to generate a local
wake-up. A pull-up current source, typically 10 µA, is implemented.
If a local wake-up is not needed for the application, connect the Wake pin directly to the VS pin.
3.12
Mode Input Pin (MODE)
Connect the MODE pin directly or via an external resistor to GND for normal watchdog operation. To debug the software of the connected microcontroller, connect MODE pin to 3.3V/5V and
the watchdog is switched off.
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3.13
TM Input Pin
The TM pin is used for final production measurements at Atmel®. In normal application, it has to
be always connected to GND.
3.14
KL_15 Pin
The KL_15 pin is a high-voltage input used to wake up the device from Sleep or Silent Mode. It
is an edge sensitive pin (low-to-high transition). It is usually connected to ignition to generate a
local wake-up in the application when the ignition is switched on. Although KL_15 pin is at high
voltage (VBatt), it is possible to switch the IC into Sleep or Silent Mode. Connect the KL_15 pin
directly to GND if you do not need it. A debounce timer with a typical Tdb Kl_15 of 160 µs is
implemented.
The input voltage threshold can be adjusted by varying the external resistor due to the input current IKL_15. To protect this pin against voltage transients, a serial resistor of 47 kΩ and a ceramic
capacitor of 100 nF are recommended. With this RC combination you can increase the wake-up
time TwKL_15 and, therefore, the sensitivity against transients on the ignition Kl.15.
You can also increase the wake-up time using external capacitors with higher values.
3.15
INH Output Pin
The INH Output pin is used to switch an external voltage regulator on during Normal or Fail-safe
Mode. The INH pin is switched off in Sleep or Silent Mode. It is possible to switch off the external
1 kΩ master resistor via the INH pin for master node applications. The INH pin is switched off
during VCC undervoltage reset.
3.16
Reset Output Pin (NRES)
The Reset Output pin, an open drain output, switches to low during VCC undervoltage or a
watchdog failure.
3.17
WD_OSC Output Pin
The WD_OSC Output pin provides a typical voltage of 1.2V, which supplies an external resistor
with values between 34 kΩ and 120 kΩ to adjust the watchdog oscillator time.
3.18
NTRIG Input Pin
The NTRIG Input pin is the trigger input for the window watchdog. A pull-up resistor is implemented. A negative edge triggers the watchdog. The trigger signal (low) must exceed a
minimum time ttrigmin to generate a watchdog trigger.
3.19
Wake-up Events from Sleep or Silent Mode
• LIN-bus
• WAKE pin
• EN pin
• KL_15
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ATA6622/ATA6624/ATA6626
4986G–AUTO–09/09
ATA6622/ATA6624/ATA6626
4. Modes of Operation
Figure 4-1.
Modes of Operation
a: VS > 5V
Unpowered Mode
VBatt = 0V
b
b: VS < 4V
c: Bus wake-up event
d: Wake up from WAKE or KL_15 pin
a
e: NRES switches to low
b
Fail-safe Mode
VCC: 3.3V/5V/50 mA
with undervoltage monitoring
Communication: OFF
Watchdog: ON
b
e
EN = 1
b
c+d+e
EN = 1
c+d
Go to silent command
EN = 0
Silent Mode
TXD = 1
VCC: 3.3V/5V/50 mA
with undervoltage monitoring
Communication: OFF
Watchdog: OFF
Local wake-up event
Normal Mode
EN = 1
VCC: 3.3V/5V/50 mA
with undervoltage
monitoring
Go to sleep command
EN = 0
Communication: ON
Watchdog: ON
Sleep Mode
TXD = 0
Table 4-1.
VCC: switched off
Communication: OFF
Watchdog: OFF
Table of Modes
Mode of
Operation
Transceiver
VCC
Fail-safe
Off
3.3V/5V
On
1.23V
On
Normal
On
3.3V/5V
On
1.23V
On
LIN depending
TXD
depending
Silent
Off
3.3V/5V
Off
0V
Off
High
Recessive
Sleep
Off
0V
Off
0V
Off
0V
Recessive
Watchdog WD_OSC INH
RXD
LIN
High,
Recessive
except after wake-up
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4986G–AUTO–09/09
4.1
Normal Mode
This is the normal transmitting and receiving mode of the LIN Interface in accordance with the
LIN specification LIN 2.x. The voltage regulator is active and can source up to 50 mA. The
undervoltage detection is activated. The watchdog needs a trigger signal from NTRIG to avoid
resets at NRES. If NRES is switched to low, the IC changes its state to Fail-safe Mode.
4.2
Silent Mode
A falling edge at EN when TXD is high switches the IC into Silent Mode. The TXD Signal has to
be logic high during the Mode Select window (see Figure 4-2 on page 8). The transmission path
is disabled in Silent Mode. The overall supply current from V Batt is a combination of the
IVSsi = 57 µA plus the VCC regulator output current IVCC.
The 3.3V/5V regulator with 2% tolerance can source up to 50 mA. The internal slave termination
between the LIN pin and the VS pin is disabled in Silent Mode, only a weak pull-up current
(typically 10 µA) between the LIN pin and the VS pin is present. Silent Mode can be activated
independently from the actual level on the LIN, WAKE, or KL_15 pins.
If an undervoltage condition occurs, NRES is switched to low, and the IC changes its state to
Fail-safe Mode.
A voltage less than the LIN Pre_Wake detection VLINL at the LIN pin activates the internal LIN
receiver and switches on the internal slave termination between the LIN pin and the VS pin.
Figure 4-2.
Switch to Silent Mode
Normal Mode
Silent Mode
EN
TXD
Mode select window
td = 3.2 µs
NRES
VCC
Delay time silent mode
td_silent = maximum 20 µs
LIN
LIN switches directly to recessive mode
8
ATA6622/ATA6624/ATA6626
4986G–AUTO–09/09
ATA6622/ATA6624/ATA6626
A falling edge at the LIN pin followed by a dominant bus level maintained for a certain time
period (tbus) and the following rising edge at the LIN pin (see Figure 4-3 on page 9) results in a
remote wake-up request. The device switches from Silent Mode to Fail-safe Mode. The remote
wake-up request is indicated by a low level at the RXD pin to interrupt the microcontroller (see
Figure 4-3 on page 9). EN high can be used to switch directly to Normal Mode.
Figure 4-3.
LIN Wake Up from Silent Mode
Bus wake-up filtering time
tbus
Fail-safe mode
Normal mode
LIN bus
Node in silent mode
RXD
High
Low
High
TXD
Watchdog
VCC
voltage
regulator
Watchdog off
Start watchdog lead time td
Silent mode 3.3V/5V/50 mA
Fail safe mode 3.3V/5V/50 mA
Normal mode
EN High
EN
NRES
4.3
Undervoltage detection active
Sleep Mode
A falling edge at EN when TXD is low switches the IC into Sleep Mode. The TXD Signal has to
be logic low during the Mode Select window (Figure 4-4 on page 10). In order to avoid any influence to the LIN-pin during switching into sleep mode it is possible to switch the EN up to 3.2 µs
earlier to LOW than the TXD. Therefore, the best and easiest way are two falling edges at TXD
and EN at the same time.The transmission path is disabled in Sleep Mode. The supply current
IVSsleep from VBatt is typically 10 µA.
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4986G–AUTO–09/09
The VCC regulator is switched off. NRES and RXD are low. The internal slave termination
between the LIN pin and VS pin is disabled, only a weak pull-up current (typically 10 µA)
between the LIN pin and the VS pin is present. Sleep Mode can be activated independently from
the current level on the LIN, WAKE, or KL_15 pin.
A voltage less than the LIN Pre_Wake detection VLINL at the LIN pin activates the internal LIN
receiver and switches on the internal slave termination between the LIN pin and the VS pin.
A falling edge at the LIN pin followed by a dominant bus level maintained for a certain time
period (tbus) and a following rising edge at pin LIN results in a remote wake-up request. The
device switches from Sleep Mode to Fail-safe Mode.
The VCC regulator is activated, and the remote wake-up request is indicated by a low level at
the RXD pin to interrupt the microcontroller (see Figure 4-5 on page 11).
EN high can be used to switch directly from Sleep/Silent to Fail-safe Mode. If EN is still high after
VCC ramp up and undervoltage reset time, the IC switches to the Normal Mode.
Figure 4-4.
Switch to Sleep Mode
Normal Mode
Sleep Mode
EN
Mode select window
TXD
td = 3.2 µs
NRES
VCC
Delay time sleep mode
td_sleep = maximum 20 µs
LIN
LIN switches directly to recessive mode
4.4
Fail-safe Mode
The device automatically switches to Fail-safe Mode at system power-up. The voltage regulator
is switched on (VCC = 3.3V/5V/2%/50 mA) (see Figure 5-1 on page 14). The NRES output
switches to low for tres = 4 ms and gives a reset to the microcontroller. LIN communication is
switched off. The IC stays in this mode until EN is switched to high. The IC then changes to Normal Mode. A power down of VBatt (VS < 4V) during Silent or Sleep Mode switches the IC into
Fail-safe Mode after power up. A low at NRES switches into Fail-safe Mode directly. During
Fail-safe Mode the TXD pin is an output and signals the last wake-up source.
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ATA6622/ATA6624/ATA6626
4986G–AUTO–09/09
ATA6622/ATA6624/ATA6626
4.5
Unpowered Mode
If you connect battery voltage to the application circuit, the voltage at the VS pin increases
according to the block capacitor (see Figure 5-1 on page 14). After VS is higher than the VS
undervoltage threshold VSth, the IC mode changes from Unpowered Mode to Fail-safe Mode.
The VCC output voltage reaches its nominal value after tVCC. This time, tVCC, depends on the
VCC capacitor and the load.
The NRES is low for the reset time delay treset . During this time, treset, no mode change is
possible.
Figure 4-5.
LIN Wake Up from Sleep Mode
Bus wake-up filtering time
tbus
Fail-safe Mode
Low or floating
Low
Normal Mode
LIN bus
RXD
TXD
VCC
voltage
regulator
On state
Off state
Regulator wake-up time
EN High
EN
Reset
time
NRES
Floating
Microcontroller
start-up time delay
Watchdog
Watchdog off
Start watchdog lead time td
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4986G–AUTO–09/09
5. Wake-up Scenarios from Silent or Sleep Mode
5.1
Remote Wake-up via Dominant Bus State
A voltage less than the LIN Pre_Wake detection VLINL at the LIN pin activates the internal LIN
receiver.
A falling edge at the LIN pin followed by a dominant bus level VBUSdom maintained for a certain
time period (tBUS) and a rising edge at pin LIN result in a remote wake-up request. The device
switches from Silent or Sleep Mode to Fail-safe Mode. The VCC voltage regulator is/remains
activated, the INH pin is switched to high, and the remote wake-up request is indicated by a low
level at the RXD pin to generate an interrupt for the microcontroller. A low level at the LIN pin in
the Normal Mode starts the bus wake-up filtering time, and if the IC is switched to Silent or Sleep
Mode, it will receive a wake-up after a positive edge at the LIN pin.
5.2
Local Wake-up via Pin WAKE
A falling edge at the WAKE pin followed by a low level maintained for a certain time period
(tWAKE) results in a local wake-up request. The device switches to Fail-safe Mode. The local
wake-up request is indicated by a low level at the RXD pin to generate an interrupt in the microcontroller and a strong pull down at TXD. When the Wake pin is low, it is possible to switch to
Silent or Sleep Mode via pin EN. In this case, the wake-up signal has to be switched to high
> 10 µs before the negative edge at WAKE starts a new local wake-up request.
5.3
Local Wake-up via Pin KL_15
A positive edge at pin KL_15 followed by a high voltage level for a certain time period (> tKL_15)
results in a local wake-up request. The device switches into the Fail-safe Mode. The extra long
wake-up time ensures that no transients at KL_15 create a wake up. The local wake-up request
is indicated by a low level at the RXD pin to generate an interrupt for the microcontroller and a
strong pull down at TXD. During high-level voltage at pin KL_15, it is possible to switch to Silent
or Sleep Mode via pin EN. In this case, the wake-up signal has to be switched to low > 250 µs
before the positive edge at KL_15 starts a new local wake-up request. With external RC combination, the time is even longer.
5.4
Wake-up Source Recognition
The device can distinguish between a local wake-up request (Wake or KL_15 pins) and a
remote wake-up request (dominant LIN bus state). The wake-up source can be read on the TXD
pin in Fail-safe Mode. A high level indicates a remote wake-up request (weak pull up at the TXD
pin); a low level indicates a local wake-up request (strong pull down at the TXD pin). The
wake-up request flag (signalled on the RXD pin), as well as the wake-up source flag (signalled
on the TXD pin), is immediately reset if the microcontroller sets the EN pin to high (see Figure
4-2 on page 8 and Figure 4-3 on page 9) and the IC is in Normal Mode. The last wake-up source
flag is stored and signalled in Fail-safe Mode at the TXD pin.
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ATA6622/ATA6624/ATA6626
5.5
Fail-safe Features
• During a short-circuit at LIN to VBattery, the output limits the output current to IBUS_lim. Due to
the power dissipation, the chip temperature exceeds TLINoff, and the LIN output is switched
off. The chip cools down and after a hysteresis of Thys, switches the output on again. RXD
stays on high because LIN is high. During LIN overtemperature switch-off, the VCC regulator
works independently.
• During a short-circuit from LIN to GND the IC can be switched into Sleep or Silent Mode. If
the short-circuit disappears, the IC starts with a remote wake-up.
• The reverse current is very low < 2 µA at the LIN pin during loss of VBatt. This is optimal
behavior for bus systems where some slave nodes are supplied from battery or ignition.
• During a short circuit at VCC, the output limits the output current to IVCClim. Because of
undervoltage, NRES switches to low and sends a reset to the microcontroller. The IC
switches into Fail-safe Mode. If the chip temperature exceeds the value TVCCoff, the VCC
output switches off. The chip cools down and after a hysteresis of Thys, switches the output on
again. Because of the Fail-safe Mode, the VCC voltage will switch on again although EN is
switched off from the microcontroller. The microcontroller can start with its normal operation.
• EN pin provides a pull-down resistor to force the transceiver into recessive mode if EN is
disconnected.
• RXD pin is set floating if VBatt is disconnected.
• TXD pin provides a pull-up resistor to force the transceiver into recessive mode if TXD is
disconnected.
• If TXD is short-circuited to GND, it is possible to switch to Sleep Mode via ENABLE after
tdom > 20 ms (only for ATA6622/ATA6624).
• If the WD_OSC pin has a short-circuit to GND or the resistor is disconnected, the watchdog
runs with an internal oscillator and guarantees a reset after the second NTRIG signal at the
latest.
5.6
Voltage Regulator
The voltage regulator needs an external capacitor for compensation and for smoothing the disturbances from the microcontroller. It is recommended to use an electrolythic capacitor with
C > 1.8 µF and a ceramic capacitor with C = 100 nF. The values of these capacitors can be varied by the customer, depending on the application.
The main power dissipation of the IC is created from the VCC output current IVCC , which is
needed for the application. In Figure 5-2 on page 14 the safe operating area of the
ATA6622/ATA6624/ATA6626 is shown.
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4986G–AUTO–09/09
Figure 5-1.
VCC Voltage Regulator: Ramp-up and Undervoltage Detection
VS
12V
5.5V/3.8V
t
VCC
5V/3.3V
Vthun
TVCC
Tres_f
TReset
t
NRES
5V/3.3V
t
Figure 5-2.
Power Dissipation: Safe Operating Area versus VCC Output Current and Supply
Voltage VS at Different Ambient Temperatures Due to Rthja = 35 K/W
60
Tamb = 105°C
50
IVCC (mA)
Tamb = 125°C
40
30
20
10
0
3
5
7
9
11
13
15
17
19
VS (V)
For programming purposes of the microcontroller it is potentially necessary to supply the VCC
output via an external power supply while the VS Pin of the system basis chip is disconnected.
This behavior is no problem for the system basis chip.
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6. Watchdog
The watchdog anticipates a trigger signal from the microcontroller at the NTRIG (negative edge)
input within a time window of T w d . The trigger signal must exceed a minimum time
ttrigmin > 200 ns. If a triggering signal is not received, a reset signal will be generated at output
NRES. The timing basis of the watchdog is provided by the internal oscillator. Its time period,
Tosc, is adjustable via the external resistor Rwd_osc (34 kΩ to 120 kΩ).
During Silent or Sleep Mode the watchdog is switched off to reduce current consumption.
The minimum time for the first watchdog pulse is required after the undervoltage reset at NRES
disappears. It is defined as lead time td. After wake up from Sleep or Silent Mode, the lead time
td starts with the negative edge of the RXD output.
6.1
Typical Timing Sequence with RWD_OSC = 51 kΩ
The trigger signal T wd is adjustable between 20 ms and 64 ms using the external resistor
RWD_OSC.
For example, with an external resistor of RWD_OSC = 51 kΩ ±1%, the typical parameters of the
watchdog are as follows:
tosc = 0.405 × RWD_OSC – 0.0004 × (RWD_OSC)2 (RWD_OSC in kΩ; tosc in µs)
tOSC = 19.6 µs due to 51 kΩ
td = 7895 × 19.6 µs = 155 ms
t1 = 1053 × 19.6 µs = 20.6 ms
t2 = 1105 × 19.6 µs = 21.6 ms
tnres = constant = 4 ms
After ramping up the battery voltage, the 3.3V/5V regulator is switched on. The reset output
NRES stays low for the time treset (typically 4 ms), then it switches to high, and the watchdog
waits for the trigger sequence from the microcontroller. The lead time, td, follows the reset and is
td = 155 ms. In this time, the first watchdog pulse from the microcontroller is required. If the trigger pulse NTRIG occurs during this time, the time t1 starts immediately. If no trigger signal
occurs during the time td, a watchdog reset with tNRES = 4 ms will reset the microcontroller after
td = 155 ms. The times t1 and t2 have a fixed relationship between each other. A triggering signal
from the microcontroller is anticipated within the time frame of t2 = 21.6 ms. To avoid false triggering from glitches, the trigger pulse must be longer than tTRIG,min > 200 ns. This slope serves to
restart the watchdog sequence. If the triggering signal fails in this open window t2, the NRES
output will be drawn to ground. A triggering signal during the closed window t1 immediately
switches NRES to low.
15
4986G–AUTO–09/09
Figure 6-1.
Timing Sequence with RWD_OSC = 51 kΩ
VCC
3.3V/5V
Undervoltage Reset
NRES
Watchdog Reset
tnres = 4 ms
treset = 4 ms
td = 155 ms
t1
t1 = 20.6 ms
t2
t2 = 21 ms
twd
NTRIG
ttrig > 200 ns
6.2
Worst Case Calculation with RWD_OSC = 51 kΩ
The internal oscillator has a tolerance of 20%. This means that t1 and t2 can also vary by 20%.
The worst case calculation for the watchdog period twd is calculated as follows.
The ideal watchdog time twd is between the maximum t1 and the minimum t1 plus the minimum
t2.
t1,min = 0.8 × t1 = 16.5 ms, t1,max = 1.2 × t1 = 24.8 ms
t2,min = 0.8 × t2 = 17.3 ms, t2,max = 1.2 × t2 = 26 ms
twdmax = t1min + t2min = 16.5 ms + 17.3 ms = 33.8 ms
twdmin = t1max = 24.8 ms
twd = 29.3 ms ±4.5 ms (±15%)
A microcontroller with an oscillator tolerance of ±15% is sufficient to supply the trigger inputs
correctly.
Table 6-1.
16
Typical Watchdog Timings
RWD_OSC
kΩ
Oscillator
Period
tosc/µs
Lead
Time
td/ms
Closed
Window
t1/ms
Open Window
t2/ms
Trigger Period from
Microcontroller
Reset Time
twd/ms
tnres/ms
34
13.3
105
14.0
14.7
19.9
4
51
19.61
154.8
20.64
21.67
29.32
4
91
33.54
264.80
35.32
37.06
50.14
4
120
42.84
338.22
45.11
47.34
64.05
4
ATA6622/ATA6624/ATA6626
4986G–AUTO–09/09
ATA6622/ATA6624/ATA6626
7. Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Parameters
Symbol
Min.
Supply voltage VS
VS
–0.3
Pulse time ≤ 500 ms; Ta = 25°C
Output current IVCC ≤ 50 mA
Pulse time ≤ 2 min; Ta = 25°C
Output current IVCC ≤ 50 mA
Max.
Unit
+40
V
VS
+40
V
VS
27
V
–1
–150
+40
+100
V
V
INH
- DC voltage
–0.3
VS + 0.3
V
LIN
- DC voltage
–27
+40
V
Logic pins (RxD, TxD, EN, NRES, NTRIG,
WD_OSC, MODE, TM)
–0.3
+5.5
WAKE (with 33 kΩ serial resistor)
KL_15 (with 50 kΩ/100 nF)
DC voltage
Transient voltage due to ISO7637 (coupling 1 nF)
Output current NRES
Typ.
INRES
PVCC DC voltage
VCC DC voltage
–0.3
–0.3
ESD according to IBEE LIN EMC
Test Spec. 1.0 following IEC 61000-4-2
- Pin VS, LIN to GND
- Pin WAKE (33 kΩ serial resistor) to GND
V
+2
mA
+5.5
+6.5
V
V
±6
±5
KV
KV
ESD HBM following STM5.1 with 1.5 kΩ 100 pF
- Pin VS, LIN, WAKE to GND
±8
KV
HBM ESD
ANSI/ESD-STM5.1
JESD22-A114
AEC-Q100 (002)
±3
KV
CDM ESD STM 5.3.1
±750
V
Machine Model ESD AEC-Q100-RevF(003)
±200
V
Junction temperature
Tj
–40
+150
°C
Storage temperature
Ts
–55
+150
°C
Symbol
Min.
Max.
Unit
10
K/W
8. Thermal Characteristics
Parameters
Thermal resistance junction to heat slug
Rthjc
Thermal resistance junction to ambient, where
heat slug is soldered to PCB
Rthja
Typ.
35
K/W
Thermal shutdown of VCC regulator
150
165
170
°C
Thermal shutdown of LIN output
150
165
170
°C
Thermal shutdown hysteresis
10
°C
17
4986G–AUTO–09/09
9. Electrical Characteristics
5V < VS < 27V, -40°C < Tj < 150°C, unless otherwise specified. All values refer to GND pins
No.
1
1.1
1.2
1.3
Parameters
Test Conditions
Pin
Symbol
Min.
VS
VS
5
Sleep Mode
VLIN > VS – 0.5V
VS < 14V (Tj = 25°C)
VS
IVSsleep
3
Sleep Mode
VLIN > VS – 0.5V
VS < 14V (Tj = 125°C)
VS
IVSsleep
Bus recessive
VS < 14V (Tj = 25°C)
Without load at VCC
VS
Bus recessive
VS < 14V (Tj = 125°C)
Without load at VCC
Typ.
Max.
Unit
Type*
27
V
A
10
14
µA
A
5
11
16
µA
A
IVSsi
47
57
67
µA
A
VS
IVSsi
56
66
76
µA
A
VS Pin
Nominal DC voltage
range
Supply current in Sleep
Mode
Supply current in Silent
Mode
1.4
Bus recessive
Supply current in Normal
VS < 14V
Mode
Without load at VCC
VS
IVSrec
0.3
0.8
mA
A
1.5
Bus dominant
Supply current in Normal
VS < 14V
Mode
VCC load current 50 mA
VS
IVSdom
50
53
mA
A
1.6
Supply current in
Fail-safe Mode
VS
IVSfail
250
550
µA
A
1.7
VS undervoltage
threshold
VS
VSth
4.0
5
V
A
1.8
VS undervoltage
threshold hysteresis
VS
VSth_hys
V
A
RXD
IRXD
8
mA
A
0.4
V
A
7
kΩ
A
2
Bus recessive
VS < 14V
Without load at VCC
4.5
0.2
RXD Output Pin
Normal Mode
VLIN = 0V
VRXD = 0.4V
2.1
Low-level output sink
current
2.2
Low-level output voltage IRXD = 1 mA
RXD
VRXDL
2.3
Internal resistor to VCC
RXD
RRXD
3
3
TXD Input/Output Pin
3.1
Low-level voltage input
TXD
VTXDL
–0.3
+0.8
V
A
3.2
High-level voltage input
TXD
VTXDH
2
VCC +
0.3V
V
A
3.3
Pull-up resistor
VTXD = 0V
TXD
RTXD
125
400
kΩ
A
3.4
High-level leakage
current
VTXD = VCC
TXD
ITXD
–3
+3
µA
A
1.3
2.5
5
250
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
18
ATA6622/ATA6624/ATA6626
4986G–AUTO–09/09
ATA6622/ATA6624/ATA6626
9. Electrical Characteristics (Continued)
5V < VS < 27V, -40°C < Tj < 150°C, unless otherwise specified. All values refer to GND pins
No.
Parameters
3.5
Fail-safe Mode
Low-level output sink
VLIN = VS
current at local wake-up
VWAKE = 0V
request
VTXD = 0.4V
4
4.1
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
TXD
ITXDwake
2
2.5
8
mA
A
EN
VENL
–0.3
+0.8
V
A
VCC +
0.3V
V
A
200
kΩ
A
EN Input Pin
Low-level voltage input
4.2
High-level voltage input
4.3
Pull-down resistor
4.4
Low-level input current
5
Test Conditions
EN
VENH
2
VEN = VCC
EN
REN
50
VEN = 0V
EN
IEN
–3
+3
µA
A
125
NTRIG Watchdog Input Pin
5.1
Low-level voltage input
NTRIG
VNTRIGL
–0.3
+0.8
V
A
5.2
High-level voltage input
NTRIG
VNTRIGH
2
VCC +
0.3V
V
A
5.3
Pull-up resistor
VNTRIG = 0V
NTRIG
RNTRIG
125
400
kΩ
A
5.4
High-level leakage
current
VNTRIG = VCC
NTRIG
INTRIG
–3
+3
µA
A
6
250
Mode Input Pin
6.1
Low-level voltage input
MODE
VMODEL
–0.3
+0.8
V
A
6.2
High-level voltage input
MODE
VMODEH
2
VCC +
0.3V
V
A
6.3
Leakage current
MODE
IMODE
–3
+3
µA
A
7
INH Output Pin
INH
VINHH
VS – 0.8
VS
V
A
INH
RINH
50
Ω
A
INH
IINHL
+3
µA
A
7.1
High-level voltage
7.2
Switch-on resistance
between VS and INH
7.3
Leakage current
8
VMODE = VCC or
VMODE = 0V
IINH = –15 mA
Sleep Mode
VINH = 0V/27V, VS = 27V
30
–3
LIN Bus Driver: Bus Load Conditions:
Load 1 (Small): 1 nF, 1 kΩ; Load 2 (Large): 10 nF, 500Ω; Internal Pull-up RRXD = 5 kΩ; CRXD = 20 pF
Load 3 (Medium): 6.8 nF, 660Ω, Characterized on Samples
10.6 and 10.7 Specifies the Timing Parameters for Proper Operation at 20 kBit/s and 10.8 and 10.9 at 10.4 kBit/s
8.1
Driver recessive output
voltage
Load1/Load2
LIN
VBUSrec
8.2
Driver dominant voltage
VVS = 7V
Rload = 500 Ω
LIN
8.3
Driver dominant voltage
VVS = 18V
Rload = 500 Ω
8.4
Driver dominant voltage
8.5
Driver dominant voltage
0.9 × VS
VS
V
A
V_LoSUP
1.2
V
A
LIN
V_HiSUP
2
V
A
VVS = 7.0V
Rload = 1000 Ω
LIN
V_LoSUP_1k
0.6
V
A
VVS = 18V
Rload = 1000 Ω
LIN
V_HiSUP_1k
0.8
V
A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
19
4986G–AUTO–09/09
9. Electrical Characteristics (Continued)
5V < VS < 27V, -40°C < Tj < 150°C, unless otherwise specified. All values refer to GND pins
No.
Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
8.6
Pull-up resistor to VS
The serial diode is
mandatory
LIN
RLIN
20
30
60
kΩ
A
8.7
Voltage drop at the serial In pull-up path with Rslave
diodes
ISerDiode = 10 mA
LIN
VSerDiode
0.4
1.0
V
D
8.8
LIN current limitation
VBUS = VBatt_max
LIN
IBUS_LIM
40
120
200
mA
A
8.9
Input leakage current at
the receiver including
pull-up resistor as
specified
Input leakage current
Driver off
VBUS = 0V
VBatt = 12V
LIN
IBUS_PAS_dom
–1
–0.35
mA
A
8.10
Leakage current LIN
recessive
Driver off
8V < VBatt < 18V
8V < VBUS < 18V
VBUS ≥ VBatt
LIN
IBUS_PAS_rec
8.11
Leakage current when
control unit disconnected
from ground.
GNDDevice = VS
VBatt = 12V
Loss of local ground
0V < VBUS < 18V
must not affect
communication in the
residual network.
LIN
IBUS_NO_gnd
8.12
Leakage current at a
disconnected battery.
Node has to sustain the VBatt disconnected
current that can flow
VSUP_Device = GND
under this condition. Bus 0V < VBUS < 18V
must remain operational
under this condition.
LIN
IBUS_NO_bat
LIN
VBUS_CNT
–10
10
20
µA
A
+0.5
+10
µA
A
0.1
2
µA
A
0.5 ×
VS
0.525 ×
VS
V
A
0.4 × VS
V
A
V
A
0.175 ×
VS
V
A
9
LIN Bus Receiver
9.1
Center of receiver
threshold
9.2
Receiver dominant state VEN = 5V
LIN
VBUSdom
9.3
Receiver recessive state VEN = 5V
LIN
VBUSrec
0.6 × VS
9.4
Receiver input
hysteresis
LIN
VBUShys
0.028 ×
VS
9.5
Pre_Wake detection LIN
High-level input voltage
LIN
VLINH
VS – 2V
VS +
0.3V
V
A
9.6
Pre_Wake detection LIN
Activates the LIN receiver
Low-level input voltage
LIN
VLINL
–27
VS –
3.3V
V
A
10
Internal Timers
VBUS_CNT =
(Vth_dom + Vth_rec)/2
Vhys = Vth_rec – Vth_dom
0.475 ×
VS
0.1 × VS
10.1
Dominant time for
wake-up via LIN bus
VLIN = 0V
LIN
tbus
30
90
150
µs
A
10.2
Time delay for mode
change from Fail-safe
into Normal Mode via
EN pin
VEN = 5V
EN
tnorm
5
15
20
µs
A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
20
ATA6622/ATA6624/ATA6626
4986G–AUTO–09/09
ATA6622/ATA6624/ATA6626
9. Electrical Characteristics (Continued)
5V < VS < 27V, -40°C < Tj < 150°C, unless otherwise specified. All values refer to GND pins
No.
Parameters
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
10.3
Time delay for mode
change from Normal
V = 0V
Mode to Sleep Mode via EN
EN pin
EN
tsleep
2
7
12
µs
A
10.4
TXD dominant time-out
= 0V
V
time (ATA6626 disabled) TXD
TXD
tdom
6
13
20
ms
A
10.5
Time delay for mode
change from Silent
V = 5V
Mode into Normal Mode EN
via EN
EN
ts_n
5
15
40
µs
A
Duty cycle 1
THRec(max) = 0.744 × VS
THDom(max) = 0.581 × VS
VS = 7.0V to 18V
tBit = 50 µs
D1 = tbus_rec(min)/(2 × tBit)
LIN
D1
0.396
Duty cycle 2
THRec(min) = 0.422 × VS
THDom(min) = 0.284 × VS
VS = 7.6V to 18V
tBit = 50 µs
D2 = tbus_rec(max)/(2 × tBit)
LIN
D2
Duty cycle 3
THRec(max) = 0.778 × VS
THDom(max) = 0.616 × VS
VS = 7.0V to 18V
tBit = 96 µs
D3 = tbus_rec(min)/(2 × tBit)
LIN
D3
10.9
Duty cycle 4
THRec(min) = 0.389 × VS
THDom(min) = 0.251 × VS
VS = 7.6V to 18V
tBit = 96 µs
D4 = tbus_rec(max)/(2 × tBit)
LIN
D4
10.10
Slope time falling and
rising edge at LIN
VS = 7.0V to 18V
LIN
tSLOPE_fall
tSLOPE_rise
10.6
10.7
10.8
11
Test Conditions
0.581
A
0.417
A
0.590
3.5
A
22.5
µs
A
6
µs
A
+2
µs
A
Receiver Electrical AC Parameters of the LIN Physical Layer
LIN Receiver, RXD Load Conditions: CRXD = 20 pF
11.1
Propagation delay of
receiver (Figure 9-1 on
page 24)
11.2
Symmetry of receiver
VS = 7.0V to 18V
propagation delay rising
=t
–t
t
edge minus falling edge rx_sym rx_pdr rx_pdf
12
A
VS = 7.0V to 18V
trx_pd = max(trx_pdr , trx_pdf)
RXD
trx_pd
RXD
trx_sym
NRES
VNRESL
0.2
0.14
V
V
A
0.2
V
A
6
ms
A
–2
NRES Open Drain Output Pin
12.1
VS ≥ 5.5V
Low-level output voltage INRES = 1 mA
INRES = 250 µA
12.2
Low-level output low
10 kΩ to VCC
VCC = 0V
NRES
VNRESLL
12.3
Undervoltage reset time
VS ≥ 5.5V
CNRES = 20 pF
NRES
treset
2
4
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
21
4986G–AUTO–09/09
9. Electrical Characteristics (Continued)
5V < VS < 27V, -40°C < Tj < 150°C, unless otherwise specified. All values refer to GND pins
No.
Parameters
Test Conditions
12.4
Reset debounce time for VS ≥ 5.5V
falling edge
CNRES = 20 pF
Pin
Symbol
Min.
NRES
tres_f
1.5
WD_
OSC
VWD_OSC
1.13
WD_
OSC
ROSC
34
Typ.
Max.
Unit
Type*
10
µs
A
1.33
V
A
120
kΩ
A
13
Watchdog Oscillator
13.1
Voltage at WD_OSC in
Normal Mode
13.2
Possible values of
resistor
13.3
Oscillator period
ROSC = 34 kΩ
tOSC
10.65
13.3
15.97
µs
A
13.4
Oscillator period
ROSC = 51 kΩ
tOSC
15.68
19.6
23.52
µs
A
13.5
Oscillator period
ROSC = 91 kΩ
tOSC
26.83
33.5
40.24
µs
A
13.6
Oscillator period
ROSC = 120 kΩ
tOSC
34.2
42.8
51.4
µs
A
14
IWD_OSC = –200 µA
VVS ≥ 4V
1.23
Watchdog Timing Relative to tOSC
14.1
Watchdog lead time after
Reset
td
7895
cycles
A
14.2
Watchdog closed
window
t1
1053
cycles
A
14.3
Watchdog open window
t2
1105
cycles
A
14.4
Watchdog reset time
NRES
4.8
ms
A
15
NRES
tnres
3.2
4
KL_15
VKL_15H
4
VS +
0.3V
V
A
KL_15
VKL_15L
–1
+2
V
A
50
65
µA
A
KL_15 Pin
Positive edge initializes a
wake-up
15.1
High-level input voltage
RV = 47 kΩ
15.2
Low-level input voltage
RV = 47 kΩ
15.3
KL_15 pull-down current
VS < 27V
VKL_15 = 27V
KL_15
IKL_15
15.4
Internal debounce time
Without external capacitor
KL_15
TdbKL_15
80
160
250
µs
A
15.5
KL_15 wake-up time
RV = 47 kΩ, C = 100 nF
KL_15
TwKL_15
0.4
2
4.5
ms
C
WAKE
VWAKEH
VS – 1V
VS +
0.3V
V
A
VS –
3.3V
V
A
µA
A
+5
µA
A
150
µs
A
16
WAKE Pin
16.1
High-level input voltage
16.2
Low-level input voltage
Initializes a wake-up signal
WAKE
VWAKEL
–1
16.3
WAKE pull-up current
VS < 27V
VWAKE = 0V
WAKE
IWAKE
–30
16.4
High-level leakage
current
VS = 27V
VWAKE = 27V
WAKE
IWAKEL
–5
16.5
Time of low pulse for
wake-up via WAKE pin
VWAKE = 0V
WAKE
IWAKEL
30
–10
70
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
22
ATA6622/ATA6624/ATA6626
4986G–AUTO–09/09
ATA6622/ATA6624/ATA6626
9. Electrical Characteristics (Continued)
5V < VS < 27V, -40°C < Tj < 150°C, unless otherwise specified. All values refer to GND pins
No.
Parameters
Test Conditions
17
VCC Voltage Regulator ATA6622, PVCC = VCC
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
17.1
Output voltage VCC
4V < VS < 18V
(0 mA to 50 mA)
VCC
VCCnor
3.234
3.366
V
A
17.2
Output voltage VCC at
low VS
3V < VS < 4V
VCC
VCClow
VS – VD
3.366
V
A
17.3
Regulator drop voltage
VS > 3V
IVCC = –15 mA
VS,
VCC
VD1
200
mV
A
17.4
Regulator drop voltage
VS > 3V
IVCC = –50 mA
VS,
VCC
VD2
500
700
mV
A
17.5
Line regulation
4V < VS < 18V
VCC
VCCline
1
%
A
17.6
Load regulation
5 mA < IVCC < 50 mA
VCC
VCCload
0.5
2
%
A
17.7
Power supply ripple
rejection
10 Hz to 100 kHz
CVCC = 10 µF
VS = 14V, IVCC = –15 mA
VCC
dB
A
17.8
Output current limitation VS > 4V
17.9
Load capacity
17.10
50
VCC
IVCClim
–240
–160
mA
A
0.2Ω < ESR < 5Ω at
100 kHz
VCC
Cload
1.8
10
µF
D
VCC undervoltage
threshold
Referred to VCC
VS > 4V
VCC
VthunN
2.8
V
A
17.11
Hysteresis of
undervoltage threshold
Referred to VCC
VS > 4V
VCC
Vhysthun
150
mV
A
17.12
Ramp-up time VS > 4V to CVCC = 2.2 µF
VCC = 3.3V
Iload = –5 mA at VCC
VCC
TVCC
100
250
µs
A
18
3.2
VCC Voltage Regulator ATA6624/ATA6626, PVCC = VCC
18.1
Output voltage VCC
5.5V < VS < 18V
(0 mA to 50 mA)
VCC
VCCnor
4.9
5.1
V
A
18.2
Output voltage VCC at
low VS
4V < VS < 5.5V
VCC
VCClow
VS – VD
5.1
V
A
18.3
Regulator drop voltage
VS > 4V
IVCC = –20 mA
VS,
VCC
VD1
250
mV
A
18.4
Regulator drop voltage
VS > 4V
IVCC = –50 mA
VS,
VCC
VD2
600
mV
A
18.5
Regulator drop voltage
VS > 3.3V
IVCC = –15 mA
VS,
VCC
VD3
200
mV
A
18.6
Line regulation
5.5V < VS < 18V
VCC
VCCline
1
%
A
18.7
Load regulation
5 mA < IVCC < 50 mA
VCC
VCCload
2
%
A
18.8
Power supply ripple
rejection
10 Hz to 100 kHz
CVCC = 10 µF
VS = 14V, IVCC = –15 mA
VCC
dB
A
18.9
Output current limitation VS > 5.5V
18.10 Load capacity
0.2Ω < ESR < 5Ω at
100 kHz
400
0.5
50
VCC
IVCClim
–240
–130
mA
A
VCC
VthunN
1.8
10
µF
D
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
23
4986G–AUTO–09/09
9. Electrical Characteristics (Continued)
5V < VS < 27V, -40°C < Tj < 150°C, unless otherwise specified. All values refer to GND pins
No.
Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
18.11
VCC undervoltage
threshold
Referred to VCC
VS > 5.5V
VCC
VthunN
4.2
18.12
Hysteresis of
undervoltage threshold
Referred to VCC
VS > 5.5V
VCC
Vhysthun
250
18.13
Ramp-up time VS > 5.5V CVCC = 2.2 µF
to VCC = 5V
Iload = –5 mA at VCC
VCC
tVCC
130
Max.
Unit
Type*
4.8
V
A
mV
A
µs
A
300
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Figure 9-1.
Definition of Bus Timing Characteristics
tBit
tBit
tBit
TXD
(Input to transmitting node)
tBus_dom(max)
tBus_rec(min)
Thresholds of
receiving node1
THRec(max)
VS
(Transceiver supply
of transmitting node)
THDom(max)
LIN Bus Signal
Thresholds of
receiving node2
THRec(min)
THDom(min)
tBus_dom(min)
tBus_rec(max)
RXD
(Output of receiving node1)
trx_pdf(1)
trx_pdr(1)
RXD
(Output of receiving node2)
trx_pdr(2)
24
trx_pdf(2)
ATA6622/ATA6624/ATA6626
4986G–AUTO–09/09
ATA6622/ATA6624/ATA6626
Figure 9-2.
Application Circuit
Ignition
KL15
VBattery
KL30
22 µF +
100 nF
47 kΩ
Master node
pull-up
KL_15
10 kΩ
PVCC
VS
+
VCC
100 nF
1 kΩ
Debug
100 nF 10 µF
20
Microcontroller
NTRIG
33 kΩ
WAKE
GND
EN
Wake
switch
15
2
ATA6622/24/26
14
3
MLP 5 mm 5 mm
0.65 mm pitch
20 lead
13
4
12
5
11
6
NTRIG
16
7
8
9
MODE
10 kΩ
TM
WD_OSC
NRES
51 kΩ
TXD
LIN sub bus
10 kΩ
17
10
RXD
VCC
18
1
LIN
EN
19
RXD
220 pF
TXD
GND
RESET
INH
25
4986G–AUTO–09/09
Figure 9-3.
Application Circuit with External NPN
Ignition
KL15
VBattery
KL30
22 µF +
100 nF
MJD31C
47 kΩ
Master node
pull-up
+
2.2 µF
10 kΩ
PVCC
VS
VCC
3.3Ω
+
KL_15
100 nF
1 kΩ
Debug
100 nF 10 µF
20
Microcontroller
NTRIG
33 kΩ
WAKE
GND
EN
Wake
switch
16
15
2
ATA6622/24/26
14
3
MLP 5 mm 5 mm
0.65 mm pitch
20 lead
13
4
12
5
11
6
NTRIG
7
8
9
MODE
10 kΩ
TM
WD_OSC
NRES
51 kΩ
TXD
LIN sub bus
10 kΩ
17
10
RXD
VCC
18
1
LIN
EN
19
RXD
220 pF
TXD
GND
RESET
INH
26
ATA6622/ATA6624/ATA6626
4986G–AUTO–09/09
ATA6622/ATA6624/ATA6626
10. Ordering Information
Extended Type Number
Package
Remarks
ATA6622-PGPW
QFN20
3.3V LIN system-basis-chip, Pb-free, 1.5k, taped and reeled
ATA6624-PGPW
QFN20
5V LIN system-basis-chip, Pb-free, 1.5k, taped and reeled
ATA6622-PGQW
QFN20
3.3V LIN system-basis-chip, Pb-free, 6k, taped and reeled
ATA6624-PGQW
QFN20
5V LIN system-basis-chip, Pb-free, 6k, taped and reeled
ATA6626-PGQW
QFN20
5V LIN system-basis-chip, Pb-free, 6k, taped and reeled
11. Package Information
Package: VQFN_5 x 5_20L
Exposed pad 3.1 x 3.1
Dimensions in mm
Not indicated tolerances ±0.05
Bottom
0
0.05-0.05
3.1±0.15
Top
20
Pin 1 identification
16
20
1
15
1
5
11
5
10
0.2
5
6
0.65 nom.
0.9±0.1
0.6±0.1
2.6
Drawing-No.: 6.543-5129.01-4
Issue: 2; 09.02.07
0.28±0.07
technical drawings
according to DIN
specifications
27
4986G–AUTO–09/09
12. Revision History
Please note that the following page numbers referred to in this section refer to the specific revision
mentioned, not to this document.
Revision No.
History
4986G-AUTO-08/09
• complete datasheet:
“LIN 2.0 specicfication” changed in “LIN 2.1 specicfication”
• Figures changed: 1-1, 4-2, 4-3, 4-4, 4-5, 5-1, 9-2, 9-3
• Sections changed:
3.1, 3.6, 3.8, 3.9, 3.10, 3.14, 4.1, 4.2, 4,3, 5.1, 5.2, 5.3, 5.5, 5.6
• Features and Description changed
• Table 4-1 changed
• Abs. Max. Ratings table changed
• Thermal Characteristics table inserted
• El. Characteristics table changed
4986F-AUTO-05/08
• Section 3.15 “INH Output Pin” on page 6 changed
• Section 5.5 “Fail-safe Features” on page 13 changed
• Section 6.1 “Typical Timing Sequence with RWD_OSC = 51 kΩ” on page 15
changed
• Section 8 “Electrical Characteristics” numbers 1.6 to 1.8 on page 18
changed
4986E-AUTO-02/08
• Figure 2-1 on page 3 renamed
• Figure 6-1 “Timing Sequence with RWD_OSC = 51 kΩ” on page 16
changed
• Figure 8-3 “Application Circuit with External NPN” on page 26 added
4986D-AUTO-10/07
• Section 9 “Ordering Information” on page 26 changed
4986C-AUTO-09/07
•
•
•
•
•
4986B-AUTO-06/07
28
Features changed
Sections 4.2, 4.3, 4.4 and 4.5 changed
Figures 4-2, 4-3, 4-4, 5-1, 5-2, 5-3, 5-6, 6-1 and 6-2 changed
Section 7 “Absolute Maximum Ratings” changed”
Section 8 “Electrical Characteristics”: numbers 17.9 and 18.9 changed
•
•
•
•
•
•
•
•
•
•
•
Put datasheet into a new template
Part number ATA6626 added
Features changed
Description text changed
Figure 1-1 “Block Diagram” changed
Figure 2-1 “Pinning SO8 changed”
Figure 4-3 “LIN Wake Up from Silent Mode” changed
Figure 4-5 “LIN Wake Up from Sleep Mode” changed
Sections 3.2, 3.4, 3.7, 3.8, 3.9, 3.10, 3.11, 3.12, 3.13 and 3.14 changed
Sections 4.2, 4.3, 4.4, 4.5, 5.1, 5.2, 5.3, 5.5, 5.6, 6.1 and 6.2 changed
Section 8 “Electrical Characteristics”: numbers 1.3, 3.5, 8.4, 12.1, 15.5,
17.9, 18 and 18.9 changed
• Figure 8-2 “Application Circuit” changed
• Section 9 “Ordering Information” changed
• Section 10 “Package Information” changed
ATA6622/ATA6624/ATA6626
4986G–AUTO–09/09
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4986G–AUTO–09/09