AD AD7862ARS-10 Simultaneous sampling dual 250 ksps 12-bit adc Datasheet

Simultaneous Sampling
Dual 250 kSPS 12-Bit ADC
AD7862
a
FEATURES
Two Fast 12-Bit ADCs
Four Input Channels
Simultaneous Sampling & Conversion
4 ms Throughput Time
Single Supply Operation
Selection of Input Ranges:
610 V for AD7862-10
62.5 V for AD7862-3
0 V to 2.5 V for AD7862-2
High Speed Parallel Interface
Low Power, 60 mW typ
Power Saving Mode, 50 mW typ
Overvoltage Protection on Analog Inputs
14-Bit Pin Compatible Upgrade (AD7863)
APPLICATIONS
AC Motor Control
Uninterrupted Power Supplies
Data Acquisition Systems
Communications
GENERAL DESCRIPTION
The AD7862 is a high speed, low power, dual 12-bit A/D
converter that operates from a single +5 V supply. The part
contains two 4 µs successive approximation ADCs, two track/
hold amplifiers, an internal +2.5 V reference and a high speed
parallel interface. There are four analog inputs that are grouped
into two channels (A & B) selected by the A0 input. Each
channel has two inputs (VA1 & VA2 or VB1 & VB2) that can be
sampled and converted simultaneously thus preserving the
relative phase information of the signals on both analog inputs.
The part accepts an analog input range of ± 10 V (AD7862-10),
± 2.5 V (AD7862-3) and 0–2.5 V (AD7862-2). Overvoltage
protection on the analog inputs for the part allows the input
voltage to go to ± 17 V, ± 7 V or +7 V, respectively, without
causing damage.
A single conversion start signal (CONVST) places both track/
holds into hold simultaneously and initiates conversion on both
inputs. The BUSY signal indicates the end of conversion, and
at this time the conversion results for both channels are available to be read. The first read after a conversion accesses the
result from VA1 or VB1, while the second read accesses the result
from VA2 or VB2, depending on whether the multiplexer select
A0 is low or high, respectively. Data is read from the part via a
12-bit parallel data bus with standard CS and RD signals.
In addition to the traditional dc accuracy specifications such as
linearity, full-scale and offset errors, the part is also specified for
dynamic performance parameters including harmonic distortion
and signal-to-noise ratio.
FUNCTIONAL BLOCK DIAGRAM
VREF
VDD
2kΩ
+2.5V
REFERENCE
AD7862
VA1
SIGNAL
SCALING
VB1
SIGNAL
SCALING
VA2
SIGNAL
SCALING
VB2
SIGNAL
SCALING
MUX
MUX
TRACK/
HOLD
TRACK/
HOLD
12-BIT
ADC
DB0
OUTPUT
LATCH
DB11
12-BIT
ADC
CS
CONVERSION
CONTROL LOGIC
A0
BUSY CONVST
CLOCK
AGND
AGND
RD
DGND
The AD7862 is fabricated in Analog Devices’ Linear Compatible CMOS (LC2MOS) process, a mixed technology process
that combines precision bipolar circuits with low power CMOS
logic. It is available in 28-lead SSOP, SOIC and DIP.
PRODUCT HIGHLIGHTS
1. The AD7862 features two complete ADC functions allowing
simultaneous sampling and conversion of two channels. Each
ADC has a 2-channel input mux. The conversion result for
both channels is available 3.6 µs after initiating conversion.
2. The AD7862 operates from a single +5 V supply and
consumes 60 mW typ. The automatic power-down mode,
where the part goes into power down once conversion is
complete and “wakes up” before the next conversion cycle,
makes the AD7862 ideal for battery-powered or portable
applications.
3. The part offers a high speed parallel interface for easy connection to microprocessors, microcontrollers and digital
signal processors.
4. The part is offered in three versions with different analog
input ranges. The AD7862-10 offers the standard industrial
input range of ± 10 V; the AD7862-3 offers the common
signal processing input range of ±2.5 V; while the AD7862-2
can be used in unipolar 0 V – +2.5 V applications.
5. The part features very tight aperture delay matching between
the two input sample-and-hold amplifiers.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
World Wide Web Site: http://www.analog.com
Fax: 617/326-8703
© Analog Devices, Inc., 1996
AD7862* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
COMPARABLE PARTS
DESIGN RESOURCES
View a parametric search of comparable parts.
• AD7862 Material Declaration
• PCN-PDN Information
DOCUMENTATION
• Quality And Reliability
Data Sheet
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• AD7862: Simultaneous Sampling Dual 250 kSPS 12-Bit
ADC Data Sheet
DISCUSSIONS
Product Highlight
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• AD7862 IBIS Models
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REFERENCE MATERIALS
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number.
Technical Articles
• MS-2210: Designing Power Supplies for High Speed ADC
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V 6 5%, AGND = DGND = 0 V, REF = Internal. All Specifications T
AD7862–SPECIFICATIONS (Vunless= +5otherwise
noted.)
DD
Parameter
A
Version1
B
Version
S
Version
Units
SAMPLE AND HOLD
–3 dB Small Signal Bandwidth
Aperture Delay
Aperture Jitter
Aperture Delay Matching
3
20
100
200
3
20
100
200
3
20
100
200
MHz typ
ns typ
ps typ
ps typ
DYNAMIC PERFORMANCE2
Signal to (Noise+Distortion) Ratio3
@ +25°C
TMIN to TMAX
Total Harmonic Distortion3
Peak Harmonic or Spurious Noise3
Intermodulation Distortion3
2nd Order Terms
3rd Order Terms
Channel to Channel Isolation3
fIN = 100.0 kHz, fS = 250 kSPS
71
70
–78
–85
70
70
–78
–85
dB min
dB min
dB max
dB typ
–85
–85
–80
–85
–85
–80
–85
–85
–80
dB typ
dB typ
dB max
12
12
12
Bits
12
±1
±1
±4
4
12
±1
±1
±3
3
12
±1
±1
±4
4
Bits
LSB max
LSB max
LSB max
LSB max
±4
±4
4
±3
±3
3
±4
±4
4
LSB max
LSB max
LSB max
±4
±4
4
±3
±3
3
±4
±4
4
LSB max
LSB max
LSB max
+4
4
+3
3.5
+4
4
LSB max
LSB max
± 10
24
± 10
24
± 10
24
Volts
kΩ min
Input
± 2.5
6
± 2.5
6
± 2.5
6
Volts
kΩ min
Input
+2.5
500
+2.5
500
+2.5
500
Volts
nA max
Input
REFERENCE INPUT/OUTPUT
REF IN Input Voltage Range
REF IN Input Capacitance4
REF OUT Output Voltage
REF OUT Error @ +25°C
REF OUT Error TMIN to TMAX
REF OUT Temperature Coefficient
REF OUT Output Impedance
2.375/2.625
10
2.5
± 10
± 25
25
2
2.375/2.625
10
2.5
± 10
± 25
25
2
2.375/2.625
10
2.5
± 10
± 25
25
2
V min/V max 2.5 V ± 5%
pF max
V nom
mV max
mV max
ppm/°C typ
kΩ nom
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
Input Capacitance, CIN4
2.4
0.8
± 10
10
2.4
0.8
± 10
10
2.4
0.8
± 10
10
V min
V max
µA max
pF max
ANALOG INPUTS
AD7862-10
Input Voltage Range
Input Resistance
AD7862-3
Input Voltage Range
Input Resistance
AD7862-2
Input Voltage Range
Input Current
to TMAX
Test Conditions/Comments
70
70
–78
–85
DC ACCURACY
Resolution
Minimum Resolution for which
No Missing Codes are Guaranteed
Relative Accuracy3
Differential Nonlinearity3
Positive Gain Error3
Positive Gain Error Match3
AD7862-10
Negative Gain Error3
Bipolar Zero Error
Bipolar Zero Error Match
AD7862-3
Negative Gain Error3
Bipolar Zero Error
Bipolar Zero Error Match
AD7862-2
Unipolar Offset Error
Unipolar Offset Error Match
MIN
fa = 49 kHz, fb = 50 kHz
fIN = 100 kHz Sine Wave
Any Channel
–2–
Typically 0.4 LSB
VDD = 5 V ± 5%
VDD = 5 V ± 5%
REV. 0
AD7862
Parameter
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
DB11–DB0
Floating-State Leakage Current
Floating-State Capacitance4
Output Coding
AD7862-10, AD7862-3
AD7863-2
A
Version1
B
Version
S
Version
Units
Test Conditions/Comments
4.0
0.4
4.0
0.4
4.0
0.4
V min
V max
ISOURCE = 200 µA
ISINK = 1.6 mA
± 10
10
± 10
10
± 10
10
µA max
pF max
Twos Complement
Straight (Natural) Binary
CONVERSION RATE
Conversion Time
Track/Hold Acquisition Time2, 3
3.6
0.3
3.6
0.3
3.6
0.3
µs max
µs max
For Both Channels
POWER REQUIREMENTS
VDD
+5
+5
+5
V nom
± 5% for Specified Performance
15
25
15
25
15
25
mA max
µA max
Logic Inputs = 0 V or VDD
75
125
75
125
75
125
mW max
µW max
Typically 60 mW
Typically 75 µW
IDD
Normal Mode
Standby Mode
Power Dissipation
Normal Mode
Standby Mode
NOTES
1
Temperature ranges are as follows: A, B Versions: –40°C to +85°C;
S Version: –55°C to +125°C.
2
Performance measured through full channel (multiplexer, SHA and ADC).
3
See Terminology.
4
Sample tested @ +25°C to ensure compliance.
Specifications subject to change without notice.
Lead Temperature, (Soldering 10 sec) . . . . . . . . . . +260°C
Ceramic DIP Package, Power Dissipation . . . . . . . . . 670 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 116°C/W
Lead Temperature, (Soldering 10 sec) . . . . . . . . . . +260°C
SOIC Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 110°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
SSOP Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 110°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
ABSOLUTE MAXIMUM RATINGS*
(TA = +25°C unless otherwise noted)
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 0.3 V
Analog Input Voltage to AGND
AD7862-10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 17 V
AD7862-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 7 V
AD7862-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7 V
Reference Input Voltage to AGND . . . –0.3 V to VDD + 0.3 V
Digital Input Voltage to DGND . . . . . –0.3 V to VDD + 0.3 V
Digital Output Voltage to DGND . . . . –0.3 V to VDD + 0.3 V
Operating Temperature Range
Commercial (A, B Version) . . . . . . . . . . . –40°C to +85°C
Extended (S Version) . . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Plastic DIP Package, Power Dissipation . . . . . . . . . . 670 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 116°C/W
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ORDERING GUIDE
Model
Input
Input
Relative
Accuracy
Temperature
Range
Package
Description
Package
Option
AD7862AR-10
AD7862BR-10
AD7862ARS-10
AD7862AN-10
AD7862SQ-10
± 10 V
± 10 V
± 10 V
± 10 V
± 10 V
± 1 LSB
± 1 LSB
± 1 LSB
± 1 LSB
± 1 LSB
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
28-Bit Small Outline Package
28-Bit Small Outline Package
28-Bit Shrink Small Outline Package
28-Bit Plastic DIP
28-Bit Cerdip
R-28
R-28
RS-28
N-28
Q-28
AD7862AR-3
AD7862BR-3
AD7862ARS-3
AD7862AN-3
± 2.5 V
± 2.5 V
± 2.5 V
± 2.5 V
± 1 LSB
± 1 LSB
± 1 LSB
± 1 LSB
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
28-Bit Small Outline Package
28-Bit Small Outline Package
28-Bit Shrink Small Outline Package
28-Plastic DIP
R-28
R-28
RS-28
N-28
AD7862AR-2
AD7862ARS-2
0 V to 2.5 V
0 V to 2.5 V
± 1 LSB
± 1 LSB
–40°C to +85°C
–40°C to +85°C
28-Bit Small Outline Package
28-Bit Shrink Small Outline Package
R-28
RS-28
REV. 0
–3–
AD7862
TIMING CHARACTERISTICS1, 2
(VDD = +5 V 6 5%, AGND = DGND = 0 V, REF = Internal. All Specifications TMIN to TMAX unless
otherwise noted.)
Parameter
A, B
Versions
S
Version
Units
Test Conditions/Comments
tCONV
tACQ
3.6
0.3
3.6
0.3
µs max
us max
Conversion Time
Acquisition Time
0
0
35
35
12
60
5
30
40
0
0
45
45
12
70
5
40
40
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns max
ns min
CS to RD Setup Time
CS to RD Hold Time
CONVST Pulse Width
Read Pulse Width
Data Access Time After Falling Edge of RD
Parallel Interface
t1
t2
t3
t4
t5 3
t6 4
t7
Bus Relinquish Time After Rising Edge of RD
Time Between Consecutive Reads
NOTES
1
Sample tested at +25°C to ensure compliance. All input signals are measured with tr = tf = 1 ns (10% to 90% of +5 V) and timed from a voltage level of +1.6 V.
2
See Figure 1.
3
Measured with the load circuit of Figure 2 and defined as the time required for an output to cross 0.8 V or 2.0 V.
4
These times are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and as such are independent of external bus loading capacitances.
Specifications subject to change without notice.
CONVST
t3
BUSY
tCONV
A0
CS
.........
.........
t1
t4
RD
t5
DATA
t7
t2
t6
VA1
VA2
VB1
VB2
Figure 1. Timing Diagram
1.6mA
TO
OUTPUT
PIN
+1.6V
50pF
200µA
Figure 2. Load Circuit for Access Time and Bus Relinquish Time
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7862 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
–4–
WARNING!
ESD SENSITIVE DEVICE
REV. 0
AD7862
PIN FUNCTION DESCRIPTION
Pin
Mnemonic
Description
1
2
NC
DB11
3–6
7
8
DB10–DB7
DGND
CONVST
9–15
16
17
DB6–DB0
AGND
VB2
18
VA2
19
VREF
20
A0
21
22
CS
RD
23
BUSY
24
25
VDD
VA1
26
VB1
27
28
AGND
NC
No Connect
Data Bit 11 (MSB). Three-state TTL output. Output coding is twos complement for the AD786210 and AD7862-3. Output coding is straight (natural) binary for the AD7862-2.
Data Bit 10 to Data Bit 7. Three-state TTL outputs.
Digital Ground. Ground reference for digital circuitry.
Convert Start Input. Logic Input. A high to low transition on this input puts both track/holds into
their hold mode and starts conversion on both channels.
Data Bit 6 to Data Bit 0. Three-state TTL outputs.
Analog Ground. Ground reference for mux, track/hold, reference and DAC circuitry.
Input Number 2 of Channel B. Analog Input voltage ranges of ± 10 V (AD7862-10), ± 2.5 V
(AD7862-3) and 0 V–2.5 V (AD7862-2).
Input Number 2 of Channel A. Analog Input voltage ranges of ± 10 V (AD7862-10), ± 2.5 V
(AD7862-3) and 0 V–2.5 V (AD7862-2).
Reference Input/Output. This pin is connected to the internal reference through a series resistor and is
the output reference source for the analog-to-digital converter. The nominal reference voltage is 2.5 V,
and this appears at the pin.
Multiplexer Select. This input is used in conjunction with RD and CS low to enable the data outputs.
With A0 logic low, one read after a conversion will read the data from each of the ADCs in the sequence,
VA1, VA2, and a subsequent read, when A0 goes high, reads the data from VB1, VB2.
Chip Select Input. Active low logic input. The device is selected when this input is active.
Read Input. Active low logic input. This input is used in conjunction with A0 and CS low to enable
the data outputs. With A0 logic low, one read after a conversion will read the data from each of the
ADCs in the sequence, VA1, VA2, and a subsequent read, when A0 goes high, reads the data from VB1,
VB2.
Busy Output. The busy output is triggered high by the falling edge of CONVST and remains high
until conversion is completed.
Analog and Digital Positive Supply Voltage, +5.0 V ± 5%.
Input Number 1 of Channel A. Analog Input voltage ranges of ± 10 V (AD7862-10), ± 2.5 V
(AD7862-3) and 0 V–2.5 V (AD7862-2).
Input Number 1 of Channel B. Analog Input voltage ranges of ± 10 V (AD7862-10), ± 2.5 V
(AD7862-3) and 0 V–2.5 V (AD7862-2).
Analog Ground. Ground reference for mux, track/hold, reference and DAC circuitry.
No Connect
PIN CONFIGURATION
28 NC
NC 1
DB11 2
27 AGND
DB10 3
26 VB1
DB9 4
25 VA1
DB8 5
AD7862
24 VDD
DB7 6
TOP VIEW 23 BUSY
DGND 7 (Not to Scale) 22 RD
CONVST 8
21 CS
DB6 9
20 A0
DB5 10
19 VREF
DB4 11
18 VA2
DB3 12
17 VB2
DB2 13
16 AGND
DB1 14
15 DB0
NC = NO CONNECT
REV. 0
–5–
AD7862
TERMINOLOGY
Signal to (Noise + Distortion) Ratio
Channel-to-Channel Isolation
This is the measured ratio of signal to (noise + distortion) at the
output of the A/D converter. The signal is the rms amplitude of
the fundamental. Noise is the rms sum of all nonfundamental
signals up to half the sampling frequency (fS/2), excluding dc.
The ratio is dependent upon the number of quantization levels
in the digitization process; the more levels, the smaller the
quantization noise. The theoretical signal to (noise + distortion)
ratio for an ideal N-bit converter with a sine wave input is given
by:
Channel-to-Channel isolation is a measure of the level of
crosstalk between channels. It is measured by applying a fullscale 100 kHz sine wave signal to each of the four inputs
individually. These, in turn, are individually referenced to the
other three channels whose inputs are grounded, and the ADC
output is measured to determine the level of crosstalk from the
other channel. The figure given is the worst case across all four
channels.
Relative Accuracy
Thus for a 12-bit converter, this is 74 dB.
Relative accuracy or endpoint nonlinearity is the maximum
deviation from a straight line passing through the endpoints of
the ADC transfer function.
Total Harmonic Distortion
Differential Nonlinearity
Signal to (Noise + Distortion) = (6.02 N + 1.76) dB
This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Total harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7862 it is defined as:
Positive Full-Scale Error
THD ( dB ) = 20 log
V 22 + V 32 + V 42 + V 52
This is the deviation of the last code transition (01 . . . 110 to
01 . . . 111) from the ideal 4 × VREF – 3/2 LSB (AD7862-10
± 10 V range) or VREF – 3/2 LSB (AD7862-3, ± 2.5 V range)
after the Bipolar Offset Error has been adjusted out.
V1
where V1 is the rms amplitude of the fundamental and V2, V3, V4
and V5 are the rms amplitudes of the second through the fifth
harmonics.
Positive Full-Scale Error (AD7862-2, 0 V to 2.5 V)
This is the deviation of the last code transition (01 . . . 110 to
01 . . . 111) from the ideal VREF – 3/2 LSB after the unipolar
offset error has been adjusted out.
Peak Harmonic or Spurious Noise
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fS/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for parts
where the harmonics are buried in the noise floor, it will be a
noise peak.
Bipolar Zero Error (AD7862-10, 610 V, AD7862-3, 62.5 V)
This is the deviation of the midscale transition (all 1s to all 0s)
from the ideal AGND – 1/2 LSB.
Unipolar Offset Error (AD7862-2, 0 V to 2.5 V)
This is the deviation of the first code transition (00 . . . 000 to
00 . . . 001) from the ideal AGND + 1/2 LSB.
Intermodulation Distortion
Negative Full-Scale Error (AD7862-1, 610 V; AD7862-3,
62.5 V)
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for
which neither m nor n are equal to zero. For example, the
second order terms include (fa + fb) and (fa – fb), while the
third order terms include (2 fa + fb), (2 fa – fb), (fa + 2 fb) and
(fa – 2 fb).
This is the deviation of the first code transition (10 . . . 000 to
10 . . . 001) from the ideal –4 × VREF + 1/2 LSB (AD7862-10
± 10 V range) or –VREF + 1/2 LSB (AD7862-3, ± 2.5 V range)
after Bipolar Zero Error has been adjusted out.
Track/Hold Acquisition Time
The AD7862 is tested using the CCIF standard where two input
frequencies near the top end of the input bandwidth are used.
In this case, the second and third order terms are of different
significance. The second order terms are usually distanced in
frequency from the original sine waves, while the third order
terms are usually at a frequency close to the input frequencies.
As a result, the second and third order terms are specified
separately. The calculation of the intermodulation distortion is
as per the THD specification where it is the ratio of the rms sum
of the individual distortion products to the rms amplitude of the
fundamental expressed in dBs.
–6–
Track/Hold acquisition time is the time required for the output
of the track/hold amplifier to reach its final value, within
± 1/2 LSB, after the end of conversion (the point at which the
track/hold returns to track mode). It also applies to situations
where a change in the selected input channel takes place or
where there is a step input change on the input voltage applied
to the selected VAX/BX input of the AD7862. It means that the
user must wait for the duration of the track/hold acquisition
time, after the end of conversion or after a channel change/step
input change to VAX/BX, before starting another conversion to
ensure that the part operates to specification.
REV. 0
AD7862
CONVERTER DETAILS
The AD7862 is a high speed, low power, dual 12-bit A/D
converter that operates from a single +5 V supply. The part
contains two 4 µs successive approximation ADCs, two track/
hold amplifiers, an internal +2.5 V reference and a high speed
parallel interface. There are four analog inputs that are grouped
into two channels (A & B) selected by the A0 input. Each
channel has two inputs (VA1 & VA2 or VB1 & VB2) that can be
sampled and converted simultaneously thus preserving the
relative phase information of the signals on both analog inputs.
The part accepts an analog input range of ± 10 V (AD7862-10),
± 2.5 V (AD7862-3) and 0 V–2.5 V (AD7862-2). Overvoltage
protection on the analog inputs for the part allows the input
voltage to go to ± 17 V, ± 7 V or +7 V, respectively, without
causing damage. The AD7862 has two operating modes, the
high sampling mode and the auto sleep mode where the part
automatically goes into sleep after the end of conversion. These
modes are discussed in more detail in the Timing and Control
Section.
Conversion is initiated on the AD7862 by pulsing the CONVST
input. On the falling edge of CONVST, both on-chip track/
holds are placed into hold simultaneously, and the conversion
sequence is started on both channels. The conversion clock for
the part is generated internally using a laser-trimmed clock
oscillator circuit. The BUSY signal indicates the end of
conversion, and at this time the conversion results for both
channels are available to be read. The first read after a conversion accesses the result from VA1 or VB1 while the second read
accesses the result from VA2 or VB2, depending on whether the
multiplexer select A0 is low or high, respectively. Data is read
from the part via a 12-bit parallel data bus with standard CS
and RD signals.
Conversion time for the AD7862 is 3.6 µs in the high sampling
mode (6 µs for the auto sleep mode), and the track/hold
acquisition time is 0.3 µs. To obtain optimum performance
from the part, the read operation should not occur during the
conversion or during 300 ns prior to the next conversion. This
allows the part to operate at throughput rates up to 250 kHz
and achieve data sheet specifications.
The acquisition time of the track/hold amplifiers begins at
this point.
Reference Section
The AD7862 contains a single reference pin, labelled VREF,
which either provides access to the part’s own +2.5 V reference
or to which an external +2.5 V reference can be connected to
provide the reference source for the part. The part is specified
with a +2.5 V reference voltage. Errors in the reference source
will result in gain errors in the AD7862’s transfer function and
will add to the specified full-scale errors on the part. On the
AD7862-10 and the AD7862-3, it will also result in an offset
error injected in the attenuator stage.
The AD7862 contains an on-chip +2.5 V reference. To use this
reference as the reference source for the AD7862, simply
connect a 0.1 µF disc ceramic capacitor from the VREF pin to
AGND. The voltage that appears at this pin is internally
buffered before being applied to the ADC. If this reference is
required for use external to the AD7862, it should be buffered
as the part has a FET switch in series with the reference output,
resulting in a source impedance for this output of 3 kΩ nominal.
The tolerance on the internal reference is ± 10 mV at 25°C with
a typical temperature coefficient of 25 ppm/°C and a maximum
error over temperature of ± 25 mV.
If the application requires a reference with a tighter tolerance or
the AD7862 needs to be used with a system reference, the user
has the option of connecting an external reference to this VREF
pin. The external reference will effectively overdrive the internal
reference and provide the reference source for the ADC. The
reference input is buffered before being applied to the ADC
with the maximum input current of ± 100 µA. Suitable reference
sources for the AD7862 include the AD680, AD780 and
REF43 precision +2.5 V references.
CIRCUIT DESCRIPTION
Analog Input Section
The AD7862 is offered as three part types; the AD7862-10,
which handles a ± 10 V input voltage range; the AD7862-3,
which handles input voltage range ± 2.5 V; and the AD7862-2,
which handles a 0 V to +2.5 V input voltage range.
Track/Hold Section
The track/hold amplifiers on the AD7862 allow the ADCs to
accurately convert an input sine wave of full-scale amplitude to
12-bit accuracy. The input bandwidth of the track/hold is
greater than the Nyquist rate of the ADC even when the ADC
is operated at its maximum throughput rate of 250 kHz (i.e.,
the track/hold can handle input frequencies in excess of 125 kHz).
The track/hold amplifiers acquire input signals to 12-bit
accuracy in less than 400 ns. The operation of the track/holds is
essentially transparent to the user. The two track/hold amplifiers sample their respective input channels simultaneously on the
falling edge of CONVST. The aperture time for the track/holds
(i.e., the delay time between the external CONVST signal and
the track/hold actually going into hold) is typically 15 ns and,
more importantly, is well matched across the two track/holds on
one device and also well matched from device to device. This
allows the relative phase information between different input
channels to be accurately preserved. It also allows multiple
AD7862s to sample more than two channels simultaneously. At
the end of conversion, the part returns to its tracking mode.
REV. 0
+2.5V
REFERENCE
2kΩ
VREF
TO ADC
REFERENCE
CIRCUITRY
R2
R1
VAX
R3
AGND
TO INTERNAL
COMPARATOR
MUX
TRACK/
HOLD
AD7862-10/AD7862-3
Figure 3. AD7862-10/-3 Analog Input Structure
Figure 3 shows the analog input section for the AD7862-10 and
AD7862-3. The analog input range of the AD7862-10 is ± 10 V
into an input resistance of typically 33 kΩ. The analog input
range of the AD7862-3 is ± 2.5 V into an input resistance of
typically 12 kΩ. This input is benign with no dynamic charging
–7–
AD7862
applications, offset and full-scale error will have to be adjusted
to zero.
currents, as the resistor stage is followed by a high input
impedance stage of the track/hold amplifier. For the AD7862-10,
R1 = 30 kΩ, R2 = 7.5 kΩ, and R3 = 10 kΩ. For the AD7862-3,
R1 = R2 = 6.5 kΩ and R3 is open circuit.
Figure 4 shows a circuit that can be used to adjust the offset and
full-scale errors on the AD7862 (VA1 on the AD7862-10 version
is shown for example purposes only). Where adjustment is
required, offset error must be adjusted before full-scale error.
This is achieved by trimming the offset of the op amp driving
the analog input of the AD7862 while the input voltage is a
1/2 LSB below analog ground. The trim procedure is as follows:
apply a voltage of –2.44 mV (–1/2 LSB) at VA1 (see Figure 4)
and adjust the op amp offset voltage until the ADC output code
flickers between 1111 1111 1111 and 0000 0000 0000.
For the AD7862-10 and AD7862-3, the designed code transitions occur on successive integer LSB values (i.e., 1 LSB,
2 LSBs, 3 LSBs . . .). Output coding is twos complement
binary with 1 LSB = FS/4096. The ideal input/output transfer
function for the AD7862-10 and AD7862-3 is shown in Table I.
Table I. Ideal Input/Output Code Table for the AD7862-10/-3
Analog Inputl
Digital Output Code Transition
2
+FSR/2 – 1 LSB
+FSR/2 – 2 LSBs
+FSR/2 – 3 LSBs
GND + 1 LSB
GND
GND – 1 LSB
–FSR/2 + 3 LSBs
–FSR/2 + 2 LSBs
–FSR/2 + 1 LSB
INPUT
RANGE = ±10V
V1
011 . . . 110 to 011 . . . 111
011 . . . 101 to 011 . . . 110
011 . . . 100 to 011 . . . 101
000 . . . 000 to 000 . . . 001
111 . . . 111 to 000 . . . 000
111 . . . 110 to 111 . . . 111
100 . . . 010 to 100 . . . 011
100 . . . 001 to 100 . . . 010
100 . . . 000 to 100 . . . 001
R1
10kΩ
R2
500Ω
VA1
R4
R3
10kΩ
10kΩ
R5
10kΩ
AD7862*
AGND
NOTES
1
FSR is full-scale range = 20 V (AD7862-10) and = 5 V (AD7862-3) with
REF IN = +2.5 V.
2
1 LSB = FSR/4096 = 4.883 mV (AD7862-10) and 1.22 mV (AD7862-3) with
REF IN = +2.5 V.
*ADDITIONAL PINS OMITTED FOR CLARITY
The analog input section for the AD7862-2 contains no biasing
resistors, and the VAX/BX pin drives the input to the multiplexer
and track/hold amplifier circuitry directly. The analog input
range is 0 V to +2.5 V into a high impedance stage with an
input current of less than 500 nA. This input is benign with no
dynamic charging currents. Once again, the designed code
transitions occur on successive integer LSB values. Output
coding is straight (natural) binary with 1 LSB = FS/4096 =
2.5 V/4096 = 0.61 mV. Table II shows the ideal input/output
transfer function for the AD7862-2.
Figure 4. Full-Scale Adjust Circuit
Gain error can be adjusted at either the first code transition
(ADC negative full scale) or the last code transition (ADC
positive full scale). The trim procedures for both cases are as
follows:
Positive Full-Scale Adjust
Apply a voltage of +9.9927 V (FS/2 – 3/2 LSBs) at VA1. Adjust
R2 until the ADC output code flickers between 0111 1111 1110
and 0111 1111 1111.
Negative Full-Scale Adjust
Table II. Ideal Input/Output Code Table for the AD7862-2
Analog Input1
Digital Output Code Transition
+FSR – 1 LSB2
+FSR – 2 LSB
+FSR – 3 LSB
GND + 3 LSB
GND + 2 LSB
GND + 1 LSB
Apply a voltage of –9.9976 V (–FS + 1/2 LSB) at VA1 and adjust
R2 until the ADC output code flickers between 1000 0000 0000
and 1000 0000 0001.
111 . . . 110 to 111 . . . 111
111 . . . 101 to 111 . . . 110
111 . . . 100 to 111 . . . 101
000 . . . 010 to 000 . . . 011
000 . . . 001 to 000 . . . 010
000 . . . 000 to 000 . . . 001
An alternative scheme for adjusting full-scale error in systems
that use an external reference is to adjust the voltage at the
VREF pin until the full-scale error for any of the channels is
adjusted out. The good full-scale matching of the channels will
ensure small full-scale errors on the other channels.
TIMING AND CONTROL
NOTES
1
FSR is full-scale range and is 2.5 V for AD7862-2 with VREF = +2.5 V.
2
1 LSB = FSR/4096 and is 0.61 mV for AD7862-2 with VREF = +2.5 V.
Figure 5a shows the timing and control sequence required to
obtain optimum performance (Mode 1) from the AD7862. In
the sequence shown, a conversion is initiated on the falling edge
of CONVST. This places both track/holds into hold simultaneously, and new data from this conversion is available in the
output register of the AD7862 3.6 µs later. The BUSY signal
indicates the end of conversion, and at this time the conversion
results for both inputs are available to be read. A second
conversion is then initiated. If the multiplexer select A0 is low,
the first and second read pulses after the first conversion accesses
the result from channel A (VA1 and VA2 respectively). The third
OFFSET AND FULL-SCALE ADJUSTMENT
In most digital signal processing (DSP) applications, offset and
full-scale errors have little or no effect on system performance.
Offset error can always be eliminated in the analog domain by
ac coupling. Full-scale error effect is linear and does not cause
problems as long as the input signal is within the full dynamic
range of the ADC. Invariably, some applications will require the
input signal to span the full analog input dynamic range. In such
–8–
REV. 0
AD7862
400ns
300ns
CONVST
t3
BUSY
A0
tCONV = 3.6µs
CS
t1
t7
t2
t4
RD
t5
t6
VA1
DATA
VA2
VB2
VB1
Figure 5a. Mode 1 Timing Operation Diagram for High Sampling Performance
and fourth read pulses, after the second conversion and A0 high,
access the result from Channel B (VB1 and VB2 respectively). A0’s
state can be changed any time after the CONVST goes high,
i.e., track/holds into hold, and 400 ns prior to the next falling
edge of CONVST. Data is read from the part via a 12-bit
parallel data bus with standard CS and RD signal, i.e., the read
operation consists of a negative going pulse on the CS pin
combined with two negative going pulses on the RD pin (while
the CS is low), accessing the two 12-bit results. Once the read
operation has taken place, a further 300 ns should be allowed
before the next falling edge of CONVST to optimize the settling
of the track/hold amplifier before the next conversion is initiated.
With the internal clock frequency at its maximum (3.7 MHz—not
accessible externally), the achievable throughput rate for the
part is 3.6 µs (conversion time) plus 100 ns (read time) plus
0.3 µs (acquisition time). This results in a minimum throughput
time of 4 µs (equivalent to a throughput rate of 250 kHz).
CS
RD
VA1
DATA
VA2
VA1
Figure 5c. Read Option B
A0
CS
Read Options
Apart from the read operation described above and displayed in
Figure 5a, other CS and RD combinations can result in
different channels/inputs being read in different combinations.
Suitable combinations are shown in Figures 5b through 5d.
RD
DATA
VA1
VB1
Figure 5d. Read Option C
CS
OPERATING MODES
Mode 1 Operation (High Sampling Performance)
RD
DATA
VA1
VA2
Figure 5b. Read Option A
REV. 0
The timing diagram in Figure 5a is for optimum performance in
operating mode 1 where the falling edge of CONVST starts
conversion and puts the track/hold amplifiers into their hold
mode. This falling edge of CONVST also causes the BUSY
signal to go high to indicate that a conversion is taking place.
The BUSY signal goes low when the conversion is complete,
which is 3.6 µs max after the falling edge of CONVST, and new
data from this conversion is available in the output latch of the
AD7862. A read operation accesses this data. If the multiplexer
select A0 is low, the first and second read pulses after the first
conversion access the result from Channel A (VA1 and VA2
–9–
AD7862
respectively). The third and fourth read pulses, after the second
conversion and A0 high, access the result from Channel B (VB1
and VB2 respectively). Data is read from the part via a 12-bit
parallel data bus with standard CS and RD signals. This data
read operation consists of negative going pulse on the CS pin
combined with a negative going pulse on the RD pin; this repeated
twice will access the two 12-bit results. For the fastest throughput
rate (with an internal clock of 3.7 MHz), the read operation will
take 100 ns. The read operation must be complete at least 300 ns
before the falling edge of the next CONVST, and this gives a total
time of 4 µs for the full throughput time (equivalent to 250 kHz).
This mode of operation should be used for high sampling
applications.
because the track/hold amplifiers go into their hold mode on
the falling edge of CONVST, and the conversion will not be
complete for a further 3.6 µs. In this case the BUSY will be the
best indicator for when the conversion is complete. Even though
the part is in sleep mode, data can still be read from the part.
The read operation is identical to Mode 1 operation and must
also be complete at least 300 ns before the falling edge of the
next CONVST to allow the track/hold amplifiers to have enough
time to settle. This mode is very useful when the part is converting at a slow rate, as the power consumption will be significantly
reduced from that of Mode 1 operation.
Mode 2 Operation (Auto Sleep After Conversion)
The AD7862 is specified and 100% tested for dynamic performance specifications as well as traditional dc specifications such
as Integral and Differential Nonlinearity. These ac specifications
are required for the signal processing applications such as phased
array sonar, adaptive filters and spectrum analysis. These applications require information on the ADC’s effect on the spectral
content of the input signal. Hence, the parameters for which the
AD7862 is specified include SNR, harmonic distortion, intermodulation distortion and peak harmonics. These terms are
discussed in more detail in the following sections.
DYNAMIC SPECIFICATIONS
The timing diagram in Figure 6 is for optimum performance in
Operating Mode 2 where the part automatically goes into sleep
mode once BUSY goes low after conversion and “wakes-up”
before the next conversion takes place. This is achieved by keeping
CONVST low at the end of the second conversion, whereas it
was high at the end of the second conversion for Mode 1 operation. The operation shown in Figure 6 shows how to access data
from both Channels A and B followed by the Auto Sleep mode.
One can also setup the timing to access data from Channel A
only or Channel B only (see Read Options section on previous
page) and then go into Auto-Sleep mode. The rising edge of
CONVST “wakes-up” the part. This wake-up time is 2.5 µs
when using an external reference and 5 ms when using the
internal reference at which point the Track/Hold amplifier’s go
into their hold mode, provided the CONVST has gone low. The
conversion takes 3.6 µs after this, giving a total of 6 µs (external
reference, 5.0035 ms for internal reference) from the rising edge
of CONVST to the conversion being complete, which is
indicated by the BUSY going low. Note that since the wake-up
time from the rising edge of CONVST is 2.5 µs, if the CONVST
pulse width is greater than 2.5 µs, the conversion will take more
than the 6 µs (2.5 µs wake-up time + 3.6 µs conversion time)
shown in the diagram from the rising edge of CONVST. This is
Signal-to-Noise Ratio (SNR)
SNR is the measured signal-to-noise ratio at the output of the
ADC. The signal is the rms magnitude of the fundamental.
Noise is the rms sum of all the nonfundamental signals up to
half the sampling frequency (fS/2) excluding dc. SNR is dependent upon the number of quantization levels used in the
digitization process; the more levels, the smaller the quantization noise. The theoretical signal to noise ratio for a sine wave
input is given by
SNR = (6.02N + 1.76) dB
(1)
where N is the number of bits.
Thus for an ideal 12-bit converter, SNR = 74 dB.
2.5µs*/5ms**
WAKE-UP
TIME
400ns
300ns
CONVST
t3
t3
BUSY
tCONV = 3.5µs
A0
tCONV = 3.6µs
CS
RD
DATA
VA1
VA2
VB1
VB2
**WHEN USING AN EXTERNAL REFERENCE, WAKE-UP TIME = 2.5µs
**WHEN USING AN INTERNAL REFERENCE, WAKE-UP TIME = 5ms
Figure 6. Mode 2 Timing Where Automatic Sleep Function Is Initiated
–10–
REV. 0
AD7862
–0
Figure 7 shows a histogram plot for 8192 conversions of a dc
input using the AD7862 with 5 V supply. The analog input was
set at the center of a code transition. It can be seen that all the
codes appear in the one output bin indicating very good noise
performance from the ADC.
FSAMPLE = 245760
FIN = 10kHz
SNR = –72.95dB
THD = –89.99dB
–10
–20
–30
–40
–50
9000
–60
8000
–70
–80
7000
–90
6000
–100
5000
–110
–120
4000
0
10k
30k
50k
70k
90k
100k 12.2k
3000
Figure 9. AD7862 FFT Plot
2000
Effective Number of Bits
1000
0
746
747
748
749
750
751
752
753
754
755
756
Figure 7. Histogram of 8192 Conversions of a DC Input
The same data is presented in Figure 8 as in Figure 7 except
that in this case the output data read for the device occurs
during conversion. This has the effect of injecting noise onto the
die while bit decisions are being made and this increases the
noise generated by the AD7862. The histogram plot for 8192
conversions of the same dc input now shows a larger spread of
codes. This effect will vary depending on where the serial clock
edges appear with respect to the bit trials of the conversion
process. It is possible to achieve the same level of performance
when reading during conversion as when reading after conversion depending on the relationship of the serial clock edges to
the bit trial points.
The formula given in Equation 1 relates the SNR to the number
of bits. Rewriting the formula, as in Equation 2, it is possible to
get a measure of performance expressed in effective number of
bits (N).
N=
SNR − 1.76
6.02
(2)
The effective number of bits for a device can be calculated
directly from its measured SNR.
Figure 10 shows a typical plot of effective number of bits versus
frequency for an AD7862BN with a sampling frequency of
245.76 kHz. The effective number of bits typically falls between
11.6 and 10.6 corresponding to SNR figures of 71.59 dB and
65.57 dB.
12.0
11.8
The output spectrum from the ADC is evaluated by applying a
sine wave signal of very low distortion to the VAX/BX input that is
sampled at a 245.76 kHz sampling rate. A Fast Fourier Transform (FFT) plot is generated from which the SNR data can be
obtained. Figure 9 shows a typical 2048 point FFT plot of the
AD7862 with an input signal of 10 kHz and a sampling frequency of 245.76 kHz. The SNR obtained from this graph is
72.95 dB. It should be noted that the harmonics are taken into
account when calculating the SNR.
11.6
ENOB
11.4
11.2
11.0
10.8
10.6
10.4
7000
10.2
0
6000
5000
400
600
FREQUENCY – kHz
800
1000
Figure 10. Effective Numbers of Bits vs. Frequency
4000
Total Harmonic Distortion (THD)
3000
Total Harmonic Distortion (THD) is the ratio of the rms sum
of harmonics to the rms value of the fundamental. For the
AD7862, THD is defined as
2000
THD ( dB ) = 20 log
1000
0
745
746
747
748
749
750
751
752
753
754
755
Figure 8. Histogram of the 8192 Conversions with Read
During Conversion
REV. 0
200
V 22 + V 32 + V 42 + V 52
V1
where V1 is the rms amplitude of the fundamental and V2, V3,
V4 and V5 are the rms amplitudes of the second through the
sixth harmonic. The THD is also derived from the FFT plot of
the ADC output spectrum.
–11–
AD7862
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3 . . ., etc. Intermodulation terms are those for
which neither m or n are equal to zero. For example, the second
order terms include (fa + fb) and (fa – fb) while the third order
terms include (2 fa + fb), (2 fa – fb), (fa + 2 fb) and (fa – 2 fb).
Using the CCIF standard where two input frequencies near the
top end of the input bandwidth are used, the second and third
order terms are of different significance. The second order terms
are usually distanced in frequency from the original sine waves
while the third order terms are usually at a frequency close to
the input frequencies. As a result, the second and third order
terms are specified separately. The calculation of the intermodulation distortion is as per the THD specification where it is
the ratio of the rms sum of the individual distortion products to
the rms amplitude of the fundamental expressed in dBs. In this
case the input consists of two, equal amplitude, low distortion
sine waves. Figure 11 shows a typical IMD plot for the AD7862.
where INL(i) is the integral linearity at code i. V(fS) and V(o)
are the estimated full-scale and offset transitions, and V(i) is the
estimated transition for the ith code.
V(i), the estimated code transition point is derived as follows:
 π × cum ( i ) 
V (i ) = − A × Cos 

N


where A is the peak signal amplitude, N is the number of
histogram samples
and cum ( i ) =
i
∑ V (n ) occurrences
n =0
LSB
0.5
FIN = 10 kHz
FIN = 245.760 kHz
TA = 25°C
0.4
0.3
0.2
–0
INPUT FREQUENCIES
F1 = 50010 Hz
F2 = 49110 Hz
FSAMPLE = 245760 Hz
SNR = –60.62dB
THD = –89.22dB
–10
–20
–30
0.1
0
–40
IMD:
2ND ORDER TERM –88.44 dB
3RD ORDER TERM –66.20 dB
–50
–60
–0.1
–0.2
–70
–80
–0.3
–90
–0.4
–100
–110
–120
–0.5
0
10k
30k
50k
70k
90k
100k 12.3k
Figure 12. AD7862 AC INL Plot
Power Considerations
Figure 11. AD7862 IMD Plot
Peak Harmonic or Spurious Noise
Harmonic or spurious noise is defined as the ratio of the rms
value of the next largest component in the ADC output spectrum (up to fS/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this specification will be
determined by the largest harmonic in the spectrum, but for
parts where the harmonics are buried in the noise floor, the peak
will be a noise peak.
In the automatic power-down mode the part may be operated at
a sample rate that is considerably less than 200 kHz. In this
case, the power consumption will be reduced and will depend
on the sample rate. Figure 13 shows a graph of the power
consumption versus sampling rates from 100 Hz to 90 kHz in
the automatic power-down mode. The conditions are 5 V
supply 25°C, and the data was read after conversion.
40
AC Linearity Plot
35
(
 V ( i ) − V ( o ) × 4096
INL(i ) = 
V ( f S ) − V (o)


)  − i


30
POWER – mW
When a sine wave of specified frequency is applied to the VIN
input of the AD7862, and several million samples are taken, a
histogram showing the frequency of occurrence of each of the
4096 ADC codes can be generated. From this histogram data, it
is possible to generate an ac integral linearity plot as shown in
Figure 12. This shows very good integral linearity performance
from the AD7862 at an input frequency of 10 kHz. The absence
of large spikes in the plot shows good differential linearity. Simplified versions of the formulas used are outlined below.
25
20
15
10
5
0
0.1
10
20
30
40
50
60
FREQUENCY – kHz
70
80
90
Figure 13. Power vs. Sample Rate in Auto Power-Down
Mode
REV. 0
–12–
AD7862
MICROPROCESSOR INTERFACING
OPTIONAL
The AD7862 high speed bus timing allows direct interfacing to
DSP processors as well as modern 16-bit microprocessors.
Suitable microprocessor interfaces are shown in Figures 14
through 18.
PA2
ADDRESS BUS
PA0
CONVST
AD7862–ADSP-2100 Interface
Figure 14 shows an interface between the AD7862 and the
ADSP-2100. The CONVST signal can be supplied from the
ADSP-2100 or from an external source. The AD7862 BUSY
line provides an interrupt to the ADSP-2100 when conversion is
completed on all four channels. The four conversion results can
then be read from the AD7862 using four successive reads to
the same memory address. The following instruction reads one
of the four results (this instruction is repeated four times to read
all four results in sequence):
MEN
ADDR
DECODE
A0
EN
CS
TMS32010
AD7862*
INT
BUSY
RD
DEN
DB11
DB0
MR0 = DM(ADC)
D15
where MR0 is the ADSP-2100 MR0 register, and ADC is the
AD7862 address.
DMA13
* ADDITIONAL PINS OMITTED FOR CLARITY
Figure 15. AD7862–TMS32010 Interface
OPTIONAL
ADDRESS BUS
DMA0
AD7862–TMS320C25 Interface
CONVST
DMS
DATA BUS
D0
ADDR
DECODE
CS
EN
A0
AD7862*
ADSP-2100
(ADSP-2101/
ADSP-2102)
IRQn
BUSY
RD
DMRD (RD)
DB11
DB0
Figure 16 shows an interface between the AD7862 and the
TMS320C25. As with the two previous interfaces, conversion
can be initiated from the TMS320C25 or from an external
source, and the processor is interrupted when the conversion
sequence is completed. The TMS320C25 does not have a
separate RD output to drive the AD7862 RD input directly.
This has to be generated from the processor STRB and R/W
outputs with the addition of some logic gates. The RD signal is
OR-gated with the MSC signal to provide the one WAIT state
required in the read cycle for correct interface timing. Conversion results are read from the AD7862 using the following
instruction:
IN D,ADC
DMD15
DATA BUS
DMD0
* ADDITIONAL PINS OMITTED FOR CLARITY
where D is Data Memory address and ADC is the AD7862
address.
OPTIONAL
Figure 14. AD7862–ADSP-2100 Interface
A15
ADDRESS BUS
AD7862–ADSP-2101/ADSP-2102 INTERFACE
A0
The interface outlined in Figure 14 also forms the basis for an
interface between the AD7862 and the ADSP-2101/ADSP-2102.
The READ line of the ADSP-2101/ADSP-2102 is labeled RD.
In this interface, the RD pulse width of the processor can be
programmed using the Data Memory Wait State Control Register.
The instruction used to read one of the four results is outlined
for the ADSP-2100.
ADDR
DECODE
IS
EN
AD7862*
TMS320C25
BUSY
INTn
AD7862–TMS32010 Interface
STRB
An interface between the AD7862 and the TMS32010 is shown
in Figure 15. Once again, the CONVST signal can be supplied
from the TMS32010 or from an external source, and the
TMS32010 is interrupted when both conversions have been
completed. The following instruction is used to read the conversion results from the AD7862:
CONVST
A0
CS
RD
R/W
READY
DB11
MSC
DB0
D15
IN D,ADC
DATA BUS
D0
where D is Data Memory address, and ADC is the AD7862
address.
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 16. AD7862–TMS320C25 Interface
REV. 0
–13–
AD7862
Some applications may require that the conversion be initiated
by the microprocessor rather than an external timer. One option
is to decode the AD7862 CONVST from the address bus so
that a write operation starts a conversion. Data is read at the
end of the conversion sequence as before. Figure 18 shows an
example of initiating conversion using this method. Note that
for all interfaces, it is preferred that a read operation not be
attempted during conversion.
A15
ADDRESS BUS
A1
AD7862*
MOVE.W ADC,D0
OPTIONAL
A15
ADDRESS BUS
A0
MC68000
ADDR
DECODE
A0
EN
CS
CONVST
AD7862*
DTACK
AS
RD
R/W
DB11
DB0
D15
DATA BUS
D0
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 17. AD7862–MC68000 Interface
AD7862–80C196 Interface
Figure 18 shows an interface between the AD7862 and the
80C196 microprocessor. Here, the microprocessor initiates
conversion. This is achieved by gating the 80C196 WR signal
with a decoded address output (different to the AD7862 CS
address). The AD7862 BUSY line is used to interrupt the
microprocessor when the conversion sequence is completed.
CONVST
WR
An interface between the AD7862 and the MC68000 is shown
in Figure 17. As before, conversion can be supplied from the
MC68000 or from an external source. The AD7862 BUSY line
can be used to interrupt the processor or, alternatively, software
delays can ensure that conversion has been completed before a
read to the AD7862 is attempted. Because of the nature of its
interrupts, the 68000 requires additional logic (not shown in
Figure 18) to allow it to be interrupted correctly. For further
information on 68000 interrupts, consult the 68000 user’s manual.
where D0 is the 68000 D0 register, and ADC is the AD7862
address.
A0
CS
AD7862–MC68000 Interface
The MC68000 AS and R/W outputs are used to generate a
separate RD input signal for the AD7862. CS is used to drive
the 68000 DTACK input to allow the processor to execute a
normal read operation to the AD7862. The conversion results
are read using the following 68000 instruction:
ADDR
DECODE
80C196
RD
RD
DB11
DB0
D15
ADDRESS/DATA BUS
D0
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 18. AD7862–8086 Interface
Vector Motor Control
The current drawn by a motor can be split into two components: one produces torque, and the other produces magnetic
flux. For optimal performance of the motor, these two components should be controlled independently. In conventional
methods of controlling a three-phase motor, the current (or
voltage) supplied to the motor and the frequency of the drive are
the basic control variables; however, both the torque and flux
are functions of current (or voltage) and frequency. This
coupling effect can reduce the performance of the motor
because, if the torque is increased by increasing the frequency,
for example, the flux tends to decrease.
Vector control of an ac motor involves controlling phase in
addition to drive and current frequency. Controlling the phase
of the motor requires feedback information on the position of
the rotor relative to the rotating magnetic field in the motor.
Using this information, a vector controller mathematically
transforms the three phase drive currents into separate torque
and flux components. The AD7862, with its four-channel
simultaneous sampling capability, is ideally suited for use in
vector motor control applications.
A block diagram of a vector motor control application using the
AD7862 is shown in Figure 19. The position of the field is
derived by determining the current in each phase of the motor.
Only two phase currents need to be measured because the third
can be calculated if two phases are known. VA1 and VA2 of the
AD7862 are used to digitize this information.
Simultaneous sampling is critical to maintain the relative phase
information between the two channels. A current sensing
isolation amplifier, transformer or Hall effect sensor is used
between the motor and the AD7862. Rotor information is
obtained by measuring the voltage from two of the inputs to the
motor. VB1 and VB2 of the AD7862 are used to obtain this
information. Once again, the relative phase of the two channels
is important. A DSP microprocessor is used to perform the
mathematical transformations and control loop calculations on
the information fed back by the AD7862.
–14–
REV. 0
AD7862
DSP
MICROPROCESSOR
TORQUE & FLUX
CONTROL LOOP
CALCULATIONS &
TWO TO THREE
PHASE
INFORMATION
IC
DAC
DAC
DRIVE
CIRCUITRY
IB
VB
VA
3
PHASE
MOTOR
IA
DAC
of AD7862 number 1 is used to drive the reference input of all
other AD7862s in the circuit shown in Figure 20. One VREF
pin can drive several AD7862 REF IN pins. Alternatively, an
external or system reference can be used to drive all VREF
inputs. A common reference ensures good full-scale tracking
between all channels.
TORQUE
SETPOINT
VA1
FLUX
SETPOINT
VA2
VA1
TRANSFORMATION
TO TORQUE &
FLUX CURRENT
COMPONENTS
RD
VB1
ISOLATION
AMPLIFIERS
RD
AD7862(1)
VB2
CS
VREF
VA2
AD7862*
VB1
VA1
VB2
*ADDITIONAL PINS OMITTED FOR CLARITY
RD
VB1
VOLTAGE
ATTENUATORS
VA2
Figure 19. Vector Motor Control Using the AD7862
AD7862(2)
CS
VB2
ADDRESS
DECODE
ADDRESS
REF IN
MULTIPLE AD7862S
Figure 20 shows a system where a number of AD7862s can be
configured to handle multiple input channels. This type of
configuration is common in applications such as sonar, radar,
etc. The AD7862 is specified with typical limits on aperture
delay. This means that the user knows the difference in the
sampling instant between all channels. This allows the user to
maintain relative phase information between the different
channels.
REF IN
VA1
VB1
AD7862(n)
VA2
VB2
A common read signal from the microprocessor drives the RD
input of all AD7862s. Each AD7862 is designated a unique
address selected by the address decoder. The reference output
REV. 0
RD
CS
Figure 20. Multiple AD7862s in Multichannel System
–15–
AD7862
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28-Pin Small Outline Package
(R-28)
28-Pin Plastic DIP
(N-28)
0.580 (14.73)
0.485 (12.32)
1
28
15
1
14
14
PIN 1
0.060 (1.52)
0.015 (0.38)
0.250
(6.35)
MAX
0.625 (15.87)
0.600 (15.24)
0.150
(3.81)
MIN
0.200 (5.05)
0.022 (0.558)
0.125 (3.18)
0.014 (0.356)
0.100
(2.54)
BSC
0.070
(1.77)
MAX
0.195 (4.95)
0.125 (3.18)
PIN 1
0.0118 (0.30)
0.0040 (0.10)
8°
0.0192 (0.49)
0°
SEATING 0.0125 (0.32)
0.0138 (0.35)
PLANE 0.0091 (0.23)
0.0500 (1.27)
0.0157 (0.40)
0.407 (10.34)
0.397 (10.08)
0.100 (2.54) MAX
15
14
PIN 1
1.490 (37.85) MAX
0.620 (15.75)
0.590 (14.99)
0.015
(0.38)
MIN
0.150
(3.81)
MIN
0.200 (5.08) 0.026 (0.66) 0.110 (2.79) 0.070 (1.78) SEATING
0.125 (3.18) 0.014 (0.36) 0.090 (2.29) 0.030 (0.76) PLANE
15
1
14
0.018 (0.46)
0.008 (0.20)
0.07 (1.79)
0.066 (1.67)
0.078 (1.98) PIN 1
0.068 (1.73)
15°
0°
0.008 (0.203) 0.0256
(0.65)
0.002 (0.050) BSC
0.015 (0.38)
0.010 (0.25)
SEATING 0.009 (0.229)
PLANE
0.005 (0.127)
8°
0°
0.03 (0.762)
0.022 (0.558)
PRINTED IN U.S.A.
1
28
0.311 (7.9)
0.301 (7.64)
0.610 (15.49)
0.500 (12.70)
0.212 (5.38)
0.205 (5.21)
28
0.225
(5.72)
MAX
0.0500
(1.27)
BSC
0.0291 (0.74)
x 45°
0.0098 (0.25)
28-Pin Shrink Small Outline Package
(RS-28)
28-Pin Cerdip
(Q-28)
0.005 (0.13) MIN
0.1043 (2.65)
0.0926 (2.35)
0.015 (0.381)
0.008 (0.204)
SEATING
PLANE
0.4193 (10.65)
0.3937 (10.00)
15
0.2992 (7.60)
0.2914 (7.40)
28
C2211–12–10/96
0.7125 (18.10)
0.6969 (17.70)
1.565 (39.70)
1.380 (35.10)
–16–
REV. 0