AD AD743 Ultralow noise bifet op amp Datasheet

Ultralow Noise
BiFET Op Amp
AD743
Excellent DC Performance
0.5 mV Max Offset Voltage
250 pA Max Input Bias Current
1000 V/mV Min Open-Loop Gain
AC Performance
2.8 V/␮s Slew Rate
4.5 MHz Unity-Gain Bandwidth
THD = 0.0003% @ 1 kHz
Available in Tape and Reel in Accordance with
EIA-481A Standard
APPLICATIONS
Sonar Preamplifiers
High Dynamic Range Filters (>140 dB)
Photodiode and IR Detector Amplifiers
Accelerometers
GENERAL DESCRIPTION
The AD743 is an ultralow noise, precision, FET input, monolithic
operational amplifier. It offers a combination of the ultralow voltage noise generally associated with bipolar input op amps and
the very low input current of a FET input device. Furthermore,
the AD743 does not exhibit an output phase reversal when the
negative common-mode voltage limit is exceeded.
The AD743’s guaranteed, maximum input voltage noise of
4.0 nV/√Hz at 10 kHz is unsurpassed for a FET input monolithic op amp, as is the maximum 1.0 µV p-p, 0.1 Hz to 10 Hz
noise. The AD743 also has excellent dc performance with 250 pA
maximum input bias current and 0.5 mV maximum offset voltage.
The AD743 is specifically designed for use as a preamp in capacitive sensors, such as ceramic hydrophones. The AD743J is rated
over the commercial temperature range of 0°C to 70°C.
The AD743 is available in a 16-lead SOIC and 8-lead PDIP.
CONNECTION DIAGRAMS
8-Lead PDIP (N)
NULL
–IN
1
2
+IN
3
–VS
4
TOP VIEW
NC
8 NC
16
1
+VS
OFFSET
NULL
2
6
OUT
–IN
3
14 NC
5
NULL
NC
4
13
+IN
5
12 OUTPUT
–VS
6
11
NC
7
10 NC
NC
8
7
NC = NO CONNECT
AD743
15 NC
TOP VIEW
+VS
OFFSET
NULL
9 NC
NC = NO CONNECT
2. The combination of low voltage and low current noise make
the AD743 ideal for charge sensitive applications such as
accelerometers and hydrophones.
3. The low input offset voltage and low noise level of the AD743
provide >140 dB dynamic range.
4. The typical 10 kHz noise level of 2.9 nV/√Hz permits a three
op amp instrumentation amplifier, using three AD743s, to be
built which exhibits less than 4.2 nV/√Hz noise at 10 kHz
and which has low input bias currents.
1000
R SOURCE
OP27 AND
RESISTOR
(—)
EO
R SOURCE
100
AD743 AND RESISTOR
OR
OP27 AND RESISTOR
AD743 AND
RESISTOR
(
)
10
PRODUCT HIGHLIGHTS
1. The low offset voltage and low input offset voltage drift of the
AD743 coupled with its ultralow noise performance mean
that the AD743 can be used for upgrading many applications
now using bipolar amplifiers.
16-Lead SOIC (R)
8 NC
AD743
INPUT VOLTAGE NOISE (nV/ Hz)
FEATURES
Ultralow Noise Performance
2.9 nV/√Hz at 10 kHz
0.38 ␮V p-p, 0.1 Hz to 10 Hz
6.9 fA/√Hz Current Noise at 1 kHz
RESISTOR NOISE ONLY
(– – –)
1
100
1k
10k
100k
1M
10M
SOURCE RESISTANCE (⍀)
Figure 1. Input Voltage Noise vs. Source Resistance
REV. E
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© 2003 Analog Devices, Inc. All rights reserved.
AD743–SPECIFICATIONS
Parameter
INPUT OFFSET VOLTAGE
Initial Offset
Initial Offset
vs. Temperature
vs. Supply (PSRR)
vs. Supply (PSRR)
(@ 25ⴗC and ⴞ15 V dc, unless otherwise noted.)
Conditions
Min
Typ
Max
Unit
0.25
1.0
1.5
mV
mV
µV/°C
dB
dB
400
8.8
600
200
pA
nA
pA
pA
150
2.2
pA
nA
1
TMIN to TMAX
TMIN to TMAX
12 V to 18 V2
TMIN to TMAX
90
88
2
96
INPUT BIAS CURRENT 3
Either Input
Either Input @ TMAX
Either Input
Either Input, VS = ± 5 V
VCM = 0 V
VCM = 0 V
VCM = 10 V
VCM = 0 V
150
INPUT OFFSET CURRENT
Offset Current @ TMAX
VCM = 0 V
VCM = 0 V
40
G = –1
VO = 20 V p-p
G = –1
4.5
25
2.8
6
MHz
kHz
V/µs
µs
0.0003
%
1 10 10储20
3 10 11储18
Ω储pF
Ω储pF
± 20
+13.3, –10.7
V
V
V
dB
dB
FREQUENCY RESPONSE
Gain BW, Small Signal
Full Power Response
Slew Rate, Unity Gain
Settling Time to 0.01%
Total Harmonic Distortion4
(TPC 16)
250
30
f = 1 kHz
G = –1
INPUT IMPEDANCE
Differential
Common Mode
INPUT VOLTAGE RANGE
Differential5
Common-Mode Voltage
Over Maximum Operating Range 6
Common-Mode Rejection Ratio
INPUT VOLTAGE NOISE
VCM = ± 10 V
TMIN to TMAX
–10
80
78
+12
95
µV p-p
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
0.1 Hz to 10 Hz
f = 10 Hz
f = 100 Hz
f = 1 kHz
f = 10 kHz
0.38
5.5
3.6
3.2
2.9
INPUT CURRENT NOISE
f = 1 kHz
6.9
fA/√Hz
OPEN-LOOP GAIN
VO = ± 10 V,
RLOAD ≥ 2 kΩ
TMIN to TMAX
RLOAD = 600 Ω
4000
V/mV
V/mV
V/mV
OUTPUT CHARACTERISTICS
Voltage
Current
RLOAD ≥ 600 Ω
RLOAD ≥ 600 Ω
TMIN to TMAX
RLOAD ≥ 2 kΩ
Short Circuit
POWER SUPPLY
Rated Performance
Operating Range
Quiescent Current
TRANSISTOR COUNT
1000
800
1200
5.0
4.0
+13, –12
V
V
V
V
mA
+13.6, –12.6
+12, –10
± 12
20
± 4.8
+13.8, –13.1
40
± 15
8.1
No. of Transistors
± 18
10.0
V
V
mA
50
NOTES
1
Input offset voltage specifications are guaranteed after five minutes of operation at T A = 25°C.
2
Test conditions: +V S = 15 V, –VS = 12 V to 18 V; and +V S = 12 V to 18 V, –V S = 15 V.
3
Bias current specifications are guaranteed maximum at either input after 5 minutes of operation at T A = 25°C. For higher temperature, the current doubles every 10°C.
4
Gain = –1, R L = 2 kΩ, CL = 10 pF.
5
Defined as voltage between inputs, such that neither exceeds ± 10 V from common.
6
The AD743 does not exhibit an output phase reversal when the negative common-mode limit is exceeded.
All min and max specifications are guaranteed.
Specifications subject to change without notice.
–2–
REV. E
AD743
ABSOLUTE MAXIMUM RATINGS 1
ORDERING GUIDE
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V
Internal Power Dissipation2
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± VS
Output Short Circuit Duration . . . . . . . . . . . . . . . . Indefinite
Differential Input Voltage . . . . . . . . . . . . . . . . . . +VS and –VS
Storage Temperature Range (N, R) . . . . . . . –65°C to +125°C
Operating Temperature Range
AD743J . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Lead Temperature Range (Soldering 60 sec) . . . . . . . . . 300°C
Model
Temperature
Range
Package
Option*
AD743JN
AD743JR-16
AD743JR-16-REEL
AD743JR-16-REEL7
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
N-8
R-16
Tape and Reel
Tape and Reel
*N = PDIP; R = SOIC.
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; and functional operation
of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2
8-lead PDIP: JA = 100°C/W, JC = 30°C/W.
16-lead SOIC: JA = 100°C/W, JC = 30°C/W.
ESD SUSCEPTIBILITY
An ESD classification per method 3015.6 of MIL-STD-883C has
been performed on the AD743. The AD743 is a Class 1 device,
passing at 1000 V and failing at 1500 V on null Pins 1 and 5,
when tested, using an IMCS 5000 automated ESD tester. Pins
other than null pins fail at greater than 2500 V.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD743 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
REV. E
–3–
AD743–Typical Performance Characteristics
(@ 25ⴗC, VS = 15 V)
20
20
35
15
+VIN
10
–VIN
5
0
0
5
10
15
SUPPLY VOLTAGE (ⴞV)
TPC 1. Input Voltage Swing vs.
Supply Voltage
POSITIVE
SUPPLY
15
10
NEGATIVE
SUPPLY
50
0
20
OUTPUT VOLTAGE SWING (V p-p)
RLOAD = 10k⍀
OUTPUT VOLTAGE SWING (V)
INPUT VOLTAGE SWING (V)
RLOAD = 10k⍀
0
5
10
15
SUPPLY VOLTAGE (ⴞV)
25
20
15
10
5
0
10
20
TPC 2. Output Voltage Swing
vs. Supply Voltage
12
30
10k
100
1k
LOAD RESISTANCE (⍀)
TPC 3. Output Voltage Swing
vs. Load Resistance
200
10–6
9
6
3
OUTPUT IMPEDANCE (⍀)
INPUT BIAS CURRENT (A)
10–8
10–9
10–10
0
0
5
10
15
SUPPLY VOLTAGE (ⴞV)
10–12
–60 –40 –20 0 20 40 60 80 100 120 140
TEMPERATURE (ⴗC)
20
TPC 4. Quiescent Current vs.
Supply Voltage
TPC 5. Input Bias Current vs.
Temperature
300
1
0.1
CURRENT LIMIT (mA)
200
100
60
+ OUTPUT
CURRENT
50
40
30
0
–9 –6 –3
3
6
9
COMMON-MODE VOLTAGE (V)
TPC 7. Input Bias Current vs.
Common-Mode Voltage
12
100k
1M
10M
FREQUENCY (Hz)
100M
TPC 6. Output Impedance vs.
Frequency (Closed-Loop Gain = –1)
7.0
– OUTPUT
CURRENT
20
10
0
–12
0.01
10k
80
70
INPUT BIAS CURRENT (pA)
10
10–11
0
–60 –40 –20 0 20 40 60 80 100 120 140
TEMPERATURE (ⴗC)
TPC 8. Short Circuit Current
Limit vs. Temperature
–4–
GAIN BANDWIDTH PRODUCT (MHz)
QUIESCENT CURRENT (mA)
100
10–7
6.0
5.0
4.0
3.0
2.0
–60 –40 –20 0 20 40 60 80 100 120 140
TEMPERATURE (ⴗC)
TPC 9. Gain Bandwidth Product
vs. Temperature
REV. E
AD743
100
80
40
40
GAIN
20
20
0
0
1k
10k
1M
100k
10M
3.0
2.5
–20
100M
TPC 11. Slew Rate vs. Temperature
(Gain = –1)
POWER SUPPLY REJECTION (dB)
COMMON-MODE REJECTION (dB)
120
100
VCM = ⴞ10V
80
60
40
20
0
100
1k
10k
100k
35
100
30
80
+ SUPPLY
60
40
– SUPPLY
20
1k
THD (dB)
–90
–100
GAIN = +10
–110
–120
GAIN = –1
–130
100k
TPC 16. Total Harmonic Distortion
vs. Frequency
REV. E
VOLTAGE NOISE (PREFERRED TO INPUT) (nV/ Hz)
–80
1k
10k
FREQUENCY (Hz)
10k
100k
1M
10M
RL = 2k⍀
20
15
10
0
10
100M
TPC 14. Power Supply Rejection
vs. Frequency
–70
100
25
100
CLOSED-LOOP GAIN = ⴙ1
10
CLOSED-LOOP GAIN = ⴙ10
1
0.1
1
10
100
1k
10k 100k
FREQUENCY (Hz)
1M
TPC 17. Input Voltage Noise
Spectral Density
–5–
10M
10k
100
1k
FREQUENCY (Hz)
FREQUENCY (Hz)
TPC 13. Common-Mode
Rejection vs. Frequency
20
5
0
100
1M
15
5
10
SUPPLY VOLTAGE (ⴞV)
0
TPC 12. Open-Loop Gain vs.
Supply Voltage, RLOAD = 2 kΩ
120
FREQUENCY (Hz)
–140
10
120
80
2.0
–60 –40 –20 0 20 40 60 80 100 120 140
TEMPERATURE (ⴗC)
FREQUENCY (Hz)
TPC 10. Open-Loop Gain and
Phase vs. Frequency
130
100
TPC 15. Large Signal Frequency
Response
CURRENT NOISE SPECTRAL DENSITY (fA/ Hz)
–20
100
OPEN-LOOP GAIN (dB)
60
OUTPUT VOLTAGE (V p-p)
60
140
SLEW RATE (V/␮s)
PHASE
PHASE MARGIN (Degrees)
OPEN-LOOP GAIN (dB)
80
150
3.5
100
1k
100
10
1
1
10
100
1k
FREQUENCY (Hz)
10k
100k
TPC 18. Input Current Noise
Spectral Density
AD743
69
63
NUMBER OF UNITS
57
51
45
39
33
27
21
15
9
3
2.5
2.7
2.9
3.3
3.1
3.8
3.5
INPUT VOLTAGE NOISE (nV/ Hz)
TPC 23. Unity-Gain Follower Small
Signal Pulse Response
TPC 19. Typical Noise Distribution @ 10 kHz (602 Units)
100pF
2k⍀
+VS
1␮F
2
7
AD743
4
3
0.1␮F
0.1␮F
+VS
6
1 5
2k⍀
VIN
2M⍀
VOS ADJUST
1␮F
7
AD743
1M⍀
3
–VS
1␮F
2
0.1␮F
6
CL
100pF
4
VOUT
–VS
SQUARE WAVE
INPUT
TPC 20. Offset Null Configuration
1␮F
0.1␮F
TPC 24. Unity-Gain Inverter
+VS
2
VIN
300⍀
* 3
1␮F
7
AD743
0.1␮F
6
RL
2k⍀
4
CL
10pF
VOUT
–VS
SQUARE WAVE
INPUT
1␮F
0.1␮F
*OPTIONAL, NOT REQUIRED
TPC 21. Unity-Gain Follower
TPC 25. Unity-Gain Inverter Large Signal Pulse Response
TPC 22. Unity-Gain Follower Large Signal Pulse Response
TPC 26. Unity-Gain Inverter Small Signal Pulse Response
–6–
REV. E
AD743
low frequency noise performance. Random air currents can generate varying thermocouple voltages that appear as low frequency
noise; therefore, sensitive circuitry should be well shielded from
air flow. Keeping absolute chip temperature low also reduces low
frequency noise in two ways. First, the low frequency noise is
strongly dependent on the ambient temperature and increases
above +25°C. Second, since the gradient of temperature from the
IC package to ambient is greater, the noise generated by random
air currents, as previously mentioned, will be larger in magnitude.
Chip temperature can be reduced both by operation at reduced
supply voltages and by the use of a suitable clip-on heat sink,
if possible.
OP AMP PERFORMANCE: JFET VS. BIPOLAR
The AD743 is the first monolithic JFET op amp to offer the low
input voltage noise of an industry-standard bipolar op amp without
its inherent input current errors. This is demonstrated in Figure 2,
which compares input voltage noise versus input source resistance of the OP27 and AD743 op amps. From this figure, it is
clear that at high source impedance the low current noise of the
AD743 also provides lower total noise. It is also important to
note that with the AD743 this noise reduction extends all the
way down to low source impedances. The lower dc current errors
of the AD743 also reduce errors due to offset and drift at high
source impedances (Figure 3).
Low frequency current noise can be computed from the magnitude of the dc bias current
1000
INPUT VOLTAGE NOISE (nV/ Hz)
R SOURCE
OP27 AND
RESISTOR
(—)
EO
Ĩ n = 2qI B ∆f
and increases below approximately 100 Hz with a 1/f power spectral
density. For the AD743, the typical value of current noise is
6.9 fA/√Hz at 1 kHz. Using the formula
R SOURCE
100
AD743 AND RESISTOR
OR
OP27 AND RESISTOR
AD743 AND
RESISTOR
(
)
I˜ n = 4kT / R∆f
to compute the Johnson noise of a resistor, expressed as a current,
one can see that the current noise of the AD743 is equivalent to
that of a 3.45 108 Ω source resistance.
10
RESISTOR NOISE ONLY
(– – –)
1
100
1k
10k
100k
1M
At high frequencies, the current noise of a FET increases proportionately to frequency. This noise is due to the “real” part of
the gate input impedance, which decreases with frequency. This
noise component usually is not important, since the voltage noise
of the amplifier impressed upon its input capacitance is an apparent current noise of approximately the same magnitude.
10M
SOURCE RESISTANCE (⍀)
Figure 2. Total Input Noise Spectral Density @ 1 kHz
vs. Source Resistance
In any FET input amplifier, the current noise of the internal
bias circuitry can be coupled externally via the gate-to-source
capacitances and appears as input current noise. This noise is
totally correlated at the inputs, so source impedance matching will tend to cancel out its effect. Both input resistance and
input capacitance should be balanced whenever dealing with
source capacitances of less than 300 pF in value.
100
INPUT OFFSET VOLTAGE (mV)
OP27
10
LOW NOISE CHARGE AMPLIFIERS
As stated, the AD743 provides both low voltage and low current
noise. This combination makes this device particularly suitable
in applications requiring very high charge sensitivity, such as
capacitive accelerometers and hydrophones. When dealing with
a high source capacitance, it is useful to consider the total input
charge uncertainty as a measure of system noise.
1
AD743
0.1
100
1k
10k
100k
1M
10M
Charge (Q) is related to voltage and current by the simply stated
fundamental relationships
SOURCE RESISTANCE (⍀)
Figure 3. Input Offset Voltage vs. Source Resistance
Q = CV and I =
DESIGNING CIRCUITS FOR LOW NOISE
An op amp’s input voltage noise performance is typically divided
into two regions: flatband and low frequency noise. The AD743
offers excellent performance with respect to both. The figure of
2.9 nV/√Hz @ 10 kHz is excellent for a JFET input amplifier. The
0.1 Hz to 10 Hz noise is typically 0.38 µV p-p. The user should
pay careful attention to several design details in order to optimize
REV. E
dQ
dt
As shown, voltage, current, and charge noise can all be directly
related. The change in open circuit voltage (∆V) on a capacitor
will equal the combination of the change in charge (∆Q/C) and
the change in capacitance with a built in charge (Q/∆C).
–7–
AD743
Figures 4 and 5 show two ways to buffer and amplify the output of
a charge output transducer. Both require using an amplifier that
has a very high input impedance, such as the AD743. Figure 4
shows a model of a charge amplifier circuit. Here, amplification depends on the principle of conservation of charge at the
input of amplifier A1, which requires that the charge on capacitor CS be transferred to capacitor CF, thus yielding an output
voltage of ∆Q/CF. The amplifier’s input voltage noise will appear at
the output amplified by the noise gain (1 + (CS/CF)) of the circuit.
–100
DECIBELS REFERENCED TO 1V/ Hz
–110
CF
RB*
R1
–120
TOTAL
OUTPUT
NOISE
–130
–140
–150
–160
NOISE
DUE TO
RB ALONE
–170
–180
–190
NOISE
DUE TO
IB ALONE
–200
–210
–220
R2
0.01
CS
A1
CB*
1
10
100
FREQUENCY (Hz)
1k
10k
100k
Figure 6. Noise at the Outputs of the Circuits of
Figures 4 and 5. Gain = +10, CS = 3000 pF, RB = 22 MΩ
R1 = CS
R2
CF
RB*
0.1
However, this does not change the noise contribution of RB which,
in this example, dominates at low frequencies. The graph of
Figure 7 shows how to select an RB large enough to minimize
this resistor’s contribution to overall circuit noise. When the
equivalent current noise of RB ((√4kT)/R equals the noise of IB
(√2qIB), there is diminishing return in making RB larger.
*OPTIONAL, SEE TEXT
Figure 4. Charge Amplifier Circuit
R1
CB*
5.2 ⴛ 1010
CS
A2
RB
5.2 ⴛ 109
RESISTANCE (⍀)
R2
RB*
*OPTIONAL, SEE TEXT
Figure 5. Model for a High Z Follower with Gain
The circuit in Figure 5 is simply a high impedance follower with
gain. Here the noise gain (1 + (R1/R2)) is the same as the gain
from the transducer to the output. In both circuits, resistor RB is
required as a dc bias current return.
5.2 ⴛ 107
There are three important sources of noise in these circuits.
Amplifiers A1 and A2 contribute both voltage and current noise,
while resistor RB contributes a current noise of
Ñ = 4k
5.2 ⴛ 108
5.2 ⴛ 106
1pA
T
∆f
RB
10pA
100pA
INPUT BIAS CURRENT
1nA
10nA
Figure 7. Graph of Resistance vs. Input Bias Current
Where the Equivalent Noise √4kT/R, Equals the Noise
of the Bias Current √2qIB
where
To maximize dc performance over temperature, the source
resistances should be balanced on each input of the amplifier.
This is represented by the optional resistor RB in Figures 4 and 5.
As previously mentioned, for best noise performance, care should
be taken to also balance the source capacitance designated by CB.
The value for CB in Figure 4 would be equal to CS in Figure 5.
At values of CB over 300 pF, there is a diminishing impact on
noise; capacitor CB can then be simply a large bypass of 0.01 µF
or greater.
k = Boltzman’s Constant = 1.381 × 10–23 joules/kelvin
T = Absolute Temperature, kelvin (0°C = 273.2 kelvin)
f = Bandwidth—in Hz (assuming an ideal “brick wall” filter)
This must be root-sum-squared with the amplifier’s own
current noise.
Figure 6 shows that these circuits in Figures 4 and 5 have an
identical frequency response and noise performance (provided
that CS/CF = R1/ R2). One feature of the first circuit is that a “T”
network is used to increase the effective resistance of RB and to
improve the low frequency cutoff point by the same factor.
–8–
REV. E
AD743
300
HOW CHIP PACKAGE TYPE AND POWER DISSIPATION
AFFECT INPUT BIAS CURRENT
INPUT BIAS CURRENT (pA)
As with all JFET input amplifiers, the input bias current of
the AD743 is a direct function of device junction temperature,
IB approximately doubling every 10°C. Figure 8 shows the relationship between the bias current and the junction temperature
for the AD743. This graph shows that lowering the junction
temperature will dramatically improve IB.
10–6
TA = +25 C
␪JA = 165 C/W
200
␪JA = 115 C/W
␪JA = 0 C/W
100
INPUT BIAS CURRENT (A)
10–7
0
10–8
TA = 25ⴗC
VS = ±15V
10–9
5
10
SUPPLY VOLTAGE ( V)
15
Figure 10. Input Bias Current vs. Supply Voltage
for Various Values of JA
10–10
TJ
␪A
(J TO
DIE MOUNT)
10–11
10–12
–60
–40
–20
0
20
40
60
80
100
120
␪B
(DIE MOUNT
TO CASE)
140
JUNCTION TEMPERATURE (ⴗC)
Figure 8. Input Bias Current vs. Junction Temperature
TA
The dc thermal properties of an IC can be closely approximated
by using the simple model of Figure 9, where current represents
power dissipation, voltage represents temperature, and resistors
represent thermal resistance ( in °C/W).
TJ ␪JC
PIN
␪A + ␪B = ␪JC
CASE
Figure 11. Breakdown of Various Package Thermal
Resistances
␪CA
REDUCED POWER SUPPLY OPERATION FOR LOWER I B
Reduced power supply operation lowers IB in two ways: first, by
lowering both the total power dissipation and second, by reducing the basic gate-to-junction leakage (Figure 10). Figure 12
shows a 40 dB gain piezoelectric transducer amplifier, which
operates without an ac-coupling capacitor over the –40°C to
+85°C temperature range. If the optional coupling capacitor is
used, this circuit will operate over the entire –55°C to +125°C
military temperature range.
␪JA
TA
PIN = DEVICE DISSIPATION
TA = AMBIENT TEMPERATURE
TJ = JUNCTION TEMPERATURE
␪JC = THERMAL RESISTANCE—JUNCTION TO CASE
␪CA = THERMAL RESISTANCE—CASE TO AMBIENT
Figure 9. Device Thermal Model
100⍀
From this model, TJ = TA + JA PIN. Therefore, IB can be determined in a particular application by using Figure 8 together with
the published data for JA and power dissipation. The user can
modify JA by using of an appropriate clip-on heat sink, such as
the Aavid No. 5801. JA is also a variable when using the AD743
in chip form. Figure 10 shows the bias current versus the supply
voltage with JA as the third variable. This graph can be used to
predict bias current after JA has been computed. Again, bias current will double for every 10°C. The designer using the AD743
in chip form (Figure 11) must also be concerned with both
JC and CA, since JC can be affected by the type of die mount
technology used.
C1*
108⍀**
CT** +5V
AD743
TRANSDUCER
CT
108⍀
–5V
*OPTIONAL DC BLOCKING CAPACITOR
**OPTIONAL, SEE TEXT
Figure 12. Piezoelectric Transducer
Typically, JC will be in the 3°C/W to 5°C/W range; therefore,
for normal packages, this small power dissipation level may be
ignored. But, with a large hybrid substrate, JC will dominate
proportionately more of the total JA.
REV. E
10k⍀
–9–
AD743
AN INPUT IMPEDANCE COMPENSATED, SALLEN-KEY
FILTER
C1
1250pF
The simple high-pass filter of Figure 13 has an important source
of error which is often overlooked. Even 5 pF of input capacitance
in amplifier A will contribute an additional 1% of pass-band amplitude error, as well as distortion, proportional to the C/V characteristics
of the input junction capacitance. The addition of the network
designated Z will balance the source impedance—as seen by
A—and thus eliminate these errors.
R1
110M⍀
(5 ⴛ 22M⍀)
R3
1k⍀
R2
9k⍀
C2
2.2␮F
R4
18M⍀
AD711
+VS
Z
500k⍀
R5
18M⍀
C3
2.2␮F
A
1000pF
1000pF
500k⍀
–VS
1000pF
B AND K MODEL
4370 OR
EQUIVALENT
500k⍀
1000pF
Figure 14b. Accelerometer Circuit Using a DC
Servo Amplifier
Figure 13. Input Impedance Compensated
Sallen-Key Filter
TWO HIGH PERFORMANCE ACCELEROMETER
AMPLIFIERS
Two of the most popular charge-out transducers are hydrophones
and accelerometers. Precision accelerometers are typically calibrated for a charge output (pC/g).* Figures 14a and 14b show
two ways in which to configure the AD743 as a low noise charge
amplifier for use with a wide variety of piezoelectric accelerometers. The input sensitivity of these circuits will be determined
by the value of capacitor C1 and is equal to
∆VOUT =
∆QOUT
C1
The ratio of capacitor C1 to the internal capacitance (CT) of the
transducer determines the noise gain of this circuit (1 + CT/C1).
The amplifier’s voltage noise will appear at its output amplified
by this amount. The low frequency bandwidth of these circuits
will be dependent on the value of resistor R1. If a T network is
used, the effective value is R1(1 + R2/R3).
A dc servo loop (Figure 14b) can be used to assure a dc output
which is <10 mV, without the need for a large compensating
resistor when dealing with bias currents as large as 100 nA. For
optimal low frequency performance, the time constant of the
servo loop (R4C2 = R5C3) should be
R2 

Time Constant ≥ 10 R11 +
 C1

R3 
LOW NOISE HYDROPHONE AMPLIFIER
Hydrophones are usually calibrated in the voltage out mode.
The circuits of Figures 15a and 15b can be used to amplify the
output of a typical hydrophone. Figure 15a shows a typical
dc-coupled circuit. The optional resistor and capacitor serve
to counteract the dc offset caused by bias currents flowing through
resistor R1. Figure 15b, a variation of the original circuit, has a
low frequency cutoff determined by an RC time constant equal to
Time Constant =
C1
1250pF
R1
110M⍀
(5 ⴛ 22M⍀)
R2
9k⍀
R2
1900⍀
C1*
R4*
108⍀
R3
1k⍀
B AND K MODEL
4370 OR
EQUIVALENT
1
2 π × CC × 100 Ω
R3
100⍀
AD743
OUTPUT
0.8mV/pC
AD743
500k⍀
Z
AD743
B AND K TYPE 8100
HYDROPHONE
OUTPUT
0.8mV/pC*
CT
OUTPUT
R1
108⍀
INPUT SENSITIVITY = –179 dB re. 1V/␮Pa**
*pC = PICOCOULOMBS
g = EARTH’S GRAVITATIONAL CONSTANT
*OPTIONAL, SEE TEXT
**1V PER MICROPASCAL
Figure 14a. Basic Accelerometer Circuit
Figure 15a. Basic Hydrophone Amplifier
–10–
REV. E
AD743
where the dc gain is 1 and the gain above the low frequency cutoff
(1/(2πCC(100 Ω))) is the same as the circuit of Figure 15a. The
circuit of Figure 15c uses a dc servo loop to keep the dc output
at 0 V and to maintain full dynamic range for IB up to 100 nA.
The time constant of R7 and C2 should be larger than that of
R1 and CT for a smooth low frequency response.
R2
1900⍀
R3
100⍀
CC
C1*
R4*
AD743
B AND K TYPE 8100
HYDROPHONE
OUTPUT
The transducer shown has a source capacitance of 7500 pF. For
smaller transducer capacitances (≤300 pF), the lowest noise can
be achieved by adding a parallel RC network (R4 = R1, C1 = CT)
in series with the inverting input of the AD743.
R1
108⍀
CT
INPUT SENSITIVITY = –179 dB re. 1V/␮Pa**
*OPTIONAL, SEE TEXT
**1V PER MICROPASCAL
BALANCING SOURCE IMPEDANCES
As mentioned previously, it is good practice to balance the
source impedances (both resistive and reactive) as seen by the
inputs of the AD743. Balancing the resistive components will
optimize dc performance over temperature because balancing
will mitigate the effects of any bias current errors. Balancing
input capacitance will minimize ac response errors due to the
amplifier’s input capacitance and, as shown in Figure 16, noise
performance will be optimized. Figure 17 shows the required
external components for noninverting (A) and inverting (B)
configurations.
Figure 15b. AC-Coupled, Low Noise
Hydrophone Amplifier
R2
1900⍀
R3
100⍀
R4*
108⍀
C1*
OUTPUT
R7
16M⍀
AD743
40
B AND K
TYPE 8100
HYDROPHONE
CT
R1
108⍀
RTI VOLTAGE NOISE (nV/√Hz)
C2
0.27␮F
R5
100k⍀
AD711K
R6
1M⍀
16M⍀
DC OUTPUT 1mV FOR IB (AD743) 100nA
*OPTIONAL, SEE TEXT
Figure 15c. Hydrophone Amplifier Incorporating a
DC Servo Loop
30
20
UNBALANCED
10
BALANCED
2.9nV/√Hz
10
100
INPUT CAPACITORS (pF)
1000
Figure 16. RTI Voltage Noise vs. Input Capacitance
R1
CF
CB
R1
A
RB
B
OUTPUT
R2
CS
RS
RS
OUTPUT
CS
CB
NONINVERTING
CONNECTION
A
CB = CS
RB = RS
FOR
RS >> R1 OR R2
RB
INVERTING
CONNECTION
B
CB = C F 储 CS
RB = R1 储 RS
Figure 17. Optional External Components for Balancing Source Impedances
REV. E
–11–
AD743
OUTLINE DIMENSIONS
8-Lead Plastic Dual In-Line Package [PDIP]
(N-8)
16-Lead Standard Small Outline Package [SOIC]
Wide Body
(R-16)
Dimensions shown in inches and (millimeters)
Dimensions shown in millimeters and (inches)
0.375 (9.53)
0.365 (9.27)
0.355 (9.02)
5
1
4
0.295 (7.49)
0.285 (7.24)
0.275 (6.98)
0.100 (2.54)
BSC
0.180
(4.57)
MAX
0.150 (3.81)
0.130 (3.30)
0.110 (2.79)
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.015
(0.38)
MIN
SEATING
PLANE
0.060 (1.52)
0.050 (1.27)
0.045 (1.14)
9
16
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
C00830–0–7/03(E)
8
10.50 (0.4134)
10.10 (0.3976)
7.60 (0.2992)
7.40 (0.2913)
0.150 (3.81)
0.135 (3.43)
0.120 (3.05)
0.015 (0.38)
0.010 (0.25)
0.008 (0.20)
1.27 (0.0500)
BSC
0.30 (0.0118)
0.10 (0.0039)
COPLANARITY
0.10
10.65 (0.4193)
10.00 (0.3937)
8
1
0.51 (0.0201)
0.33 (0.0130)
0.75 (0.0295)
ⴛ 45ⴗ
0.25 (0.0098)
2.65 (0.1043)
2.35 (0.0925)
SEATING
PLANE
0.32 (0.0126)
0.23 (0.0091)
8ⴗ
0ⴗ
1.27 (0.0500)
0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-013AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MO-095AA
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
Revision History
Location
Page
7/03—Data Sheet changed from REV. D to REV. E.
Deleted K Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal
Changes to GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2/02—Data Sheet changed from REV. C to REV. D.
Edits to PRODUCT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Edits to CONNECTION DIAGRAMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Deleted AD7435 column from SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Deleted METALLIZATION PHOTOGRAPH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Edits to REDUCE POWER SUPPLY OPERATION FOR LOWER IB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Deleted 8-Pin CERDIP (Q) package drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
–12–
REV. E