PHILIPS OQ2538HP Sdh/sonet stm16/oc48 main amplifier Datasheet

INTEGRATED CIRCUITS
DATA SHEET
OQ2538HP; OQ2538U
SDH/SONET STM16/OC48 main
amplifiers
Product specification
Supersedes data of 1997 Nov 26
File under Integrated Circuits, IC19
1998 Oct 14
Philips Semiconductors
Product specification
SDH/SONET STM16/OC48 main amplifiers
OQ2538HP; OQ2538U
FEATURES
GENERAL DESCRIPTION
• Differential 100 Ω outputs for direct connection to
Current-Mode Logic (CML) inputs
The OQ2538HP is a limiting amplifier IC intended for use
as the main amplifier in 2.5 Gbits/s Non-Return to Zero
(NRZ) transmission systems (SDH/SONET).
• Wide bandwidth (3 GHz)
• 48.5 dB limiting gain
Comprised of four amplifier stages with a total gain of
48.5 dB, it provides for a wide input signal dynamic range
at a constant CML-compatible output level.
• Noise figure typically 11 dB
• Automatic offset compensation
Two level-detection circuits are provided for monitoring
AGC and LOS input signal levels. An internal automatic
offset compensation circuit eliminates offset in the
amplifier chain.
• Input level-detection circuits for Automatic Gain Control
(AGC) and Loss Of Signal (LOS) detection
• Low power dissipation (typically 270 mW)
• Single −4.5 V supply voltage
• Low cost LQFP48 plastic package.
APPLICATIONS
• Main amplifier in Synchronous Digital Hierarchy (SDH)
and Synchronous Optical Network (SONET) systems for
short, medium and long haul optical transmission
• Level detector for laser diode control loops
• Wideband RF gain block with internal level detectors.
ORDERING INFORMATION
TYPE
NUMBER
OQ2538HP
OQ2538U
1998 Oct 14
PACKAGE
NAME
DESCRIPTION
VERSION
LQFP48
plastic low profile quad flat package; 48 leads; body 7 × 7 × 1.4 mm
SOT313-2
−
bare die; dimensions 2070 × 2070 × 380 µm
2
−
Philips Semiconductors
Product specification
SDH/SONET STM16/OC48 main amplifiers
OQ2538HP; OQ2538U
BLOCK DIAGRAM
VEE
handbook, full pagewidth
3
A
43
19
B
IN
INQ
8
6
18
32
AMP A
BAND GAP
21
AMP B
AMP C
reference
voltage
for all cells
AMP D
30
OQ2538HP
45 44
22
MGE745
REF CAPA
COFF
COFFQ
Fig.1 Block diagram.
1998 Oct 14
3
GND
AGC
AGCDC
LOS
LOSDC
OUT
OUTQ
Philips Semiconductors
Product specification
SDH/SONET STM16/OC48 main amplifiers
OQ2538HP; OQ2538U
PINNING
PIN
(OQ2538HP)
PAD
(OQ2538U)
VEE
1, 12, 13, 24, 25,
36, 37, 48
2, 3, 11, 12, 28,
29(2)
S
negative power supply
n.c.
2, 11, 14, 15, 23,
26, 27, 35, 38,
40, 46, 47
20, 22(3)
−
not connected
AGC
3
30
O
rectifier A output
S
ground
SYMBOL
GND
4, 5, 7, 9, 10, 16, 1, 4, 5, 8, 13, 14,
17, 20, 28, 29,
16, 18, 19, 21,
31, 33, 34, 39,
23, 24, 31, 32,
41, 42
34, 36(2)
TYPE(1)
DESCRIPTION
INQ
6
33
I
main amplifier inverting input
IN
8
35
I
main amplifier input
LOSDC
18
6
O
rectifier B reference output
LOS
19
7
O
rectifier B output
REF
21
9
O
band gap reference
CAPA
22
10
A
pin for connecting band gap reference decoupling
capacitor
OUTQ
30
15
O
main amplifier inverted output
OUT
32
17
O
main amplifier output
AGCDC
43
25
O
rectifier A reference output
COFFQ
44
26
A
pin for connecting automatic offset control capacitor
(return)
COFF
45
27
A
pin for connecting automatic offset control capacitor
Notes
1. Pin type abbreviations: O = Output, I = Input, S = power Supply and A = Analog function.
2. All GND and VEE pads must be bonded; do not leave one single GND or VEE pad unconnected!
3. Pads denoted ‘n.c.’ should not be connected. Connections to these pads degrade device performance.
1998 Oct 14
4
Philips Semiconductors
Product specification
37 VEE
VEE
1
36 VEE
n.c.
2
35 n.c.
AGC
3
34 GND
GND
4
33 GND
GND
5
32 OUT
INQ
6
GND
7
30 OUTQ
IN
8
29 GND
GND
9
28 GND
31 GND
OQ2538HP
5
n.c. 23
VEE 24
CAPA 22
REF 21
GND 20
LOS 19
LOSDC 18
25 VEE
GND 17
VEE 12
GND 16
26 n.c.
n.c. 15
n.c. 11
n.c. 14
27 n.c.
VEE 13
GND 10
Fig.2 Pin configuration.
1998 Oct 14
38 n.c.
OQ2538HP; OQ2538U
39 GND
40 n.c.
41 GND
42 GND
43 AGCDC
44 COFFQ
46 n.c.
47 n.c.
48 VEE
handbook, full pagewidth
45 COFF
SDH/SONET STM16/OC48 main amplifiers
MGE744
Philips Semiconductors
Product specification
SDH/SONET STM16/OC48 main amplifiers
FUNCTIONAL DESCRIPTION
REF and CAPA band gap output and decoupling
capacitance
The OQ2538HP is comprised of four DC-coupled amplifier
stages along with additional circuitry for offset
compensation and level detection.
To reduce band gap noise levels, a 1 nF decoupling
capacitor on CAPA is recommended. Since the band gap
is referenced to the negative power supply, the decoupling
capacitor should be connected between CAPA and VEE.
The first amplifier stage contains a modified
Cherry/Hooper amplifying cell with high gain
(approximately 20 dB) and a wide bandwidth. Special
attention is paid to minimizing the equivalent input noise at
this stage, thus reducing the overall noise level. Additional
feedback is applied at the second and third stages,
improving isolation and reducing the gain to 14 dB per
stage. The last stage is an output buffer, a unity gain
amplifier, with an output impedance of 100 Ω.
The band gap voltage is present on pin REF for test
purposes only. It is not intended to serve as an external
reference.
RF input and output connections
Striplines, or microstrips, with an odd mode characteristic
impedance of Zo(odd) = 50 Ω must be used for the
differential RF connections on the PCB. This applies to
both the input signal pair IN and INQ and to the output
signal pair OUT and OUTQ. The two lines in each pair
should have the same length.
The total gain of the OQ2538HP amounts to 48.5 dB, thus
providing a constant CML-compatible output signal over a
wide input signal range.
Two rectifier circuits are used to measure the input signal
level. Two separate RF preamplifiers are used to generate
the voltage gain needed to obtain a suitable rectifier output
voltage. For rectifier A the gain is approximately 18 dB, for
rectifier B it is about 14 dB. The output of rectifier A can be
used for AGC at the preamplifier stage in front of the
OQ2538HP. The output of rectifier B can be used for LOS
detection. There is a linear relationship between the
rectifier output voltage and the input signal level provided
the amplifiers are not saturated.
RF input matching circuit
The input circuit for pins IN and INQ contains internal
100 Ω resistors decoupled to ground via an internal
common mode 6 pF capacitor. The topology is depicted in
Fig.3.
Because the four gain stages are DC-coupled and provide
a high overall gain, the effect of the input offset can be
considerable. The OQ2538HP features an internal offset
compensation circuit for eliminating the input offset.
The bandwidth of the offset control loop is determined by
an external capacitor.
GND
handbook, halfpage
6 pF
100 Ω
100 Ω
IN
COFF and COFFQ offset compensation
Automatic offset compensation eliminates the input offset
of the OQ2538HP. This offset cancellation influences the
low frequency gain of the amplifier stages. With a
capacitance of 100 nF between COFF and COFFQ the
loop bandwidth will be less than 1.5 kHz, small enough to
have no influence on amplifier gain over the frequencies of
interest. If the capacitor was omitted, the loop bandwidth
would be greater than 30 MHz, which would influence the
input signal gain. The loop bandwidth can be calculated
from the following formula:
1
f loop = -----------------------------------------------(1)
2π × 1250 Ω × C ext
INQ
MGM114
Fig.3 RF input topology.
where Cext is the capacitance connected between COFF
and COFFQ.
1998 Oct 14
OQ2538HP; OQ2538U
6
Philips Semiconductors
Product specification
SDH/SONET STM16/OC48 main amplifiers
An external 200 Ω resistor between IN and INQ is
recommended in order to match the inputs to a differential
transmission line, coupled microstrip or stripline with an
odd mode impedance Zo(odd) = 50 Ω, as shown in Fig.4.
RF output matching circuit
Matching of the main amplifier outputs, OUT and OUTQ, is
not mandatory. In most applications, the receiving end of
the transmission line will be properly matched, so very little
reflection will occur. Matching the transmitting end to
absorb these reflections is only recommended for very
sensitive applications. In such cases, 100 Ω pull-up
resistors should be connected from OUT and OUTQ to
ground, as close as possible to the IC pins. These
matching resistors will not be needed in most applications,
however. The output circuit of the OQ2538HP is depicted
in Fig.6. For more information see “Application Note
AN96051” describing the OM5801 STM16 demo board.
22 nF
handbook, halfpage
IN
differential line
Zo(odd) = 50 Ω
OQ2538HP; OQ2538U
200 Ω
INQ
22 nF
MGM115
GND
handbook, halfpage
Fig.4 Differential input matching.
100 Ω
OUT
For single-ended excitation, separate matching networks
on IN and INQ, as depicted in Fig.5, achieve optimum
matching. Care should be taken to avoid DC loading, since
the OQ2538HP controls its own DC input voltage.
The resistors on the unused input INQ may be combined
for convenience.
100 Ω
OUTQ
MGM117
Fig.6 RF output topology.
handbook, halfpage
22 nF
100 Ω
transmission line
22 nF
IN
Zo = 50 Ω
INQ
50 Ω
22 nF
100 Ω
22 nF
MGM116
Fig.5 Single-ended input matching.
In both cases, the essence of good matching is the equity
of the circuitry on both input pins. The impedance seen on
pins IN and INQ should be as equal as possible. For more
information see “Application Note AN96051” describing
the OM5801 STM16 demo board.
1998 Oct 14
7
Philips Semiconductors
Product specification
SDH/SONET STM16/OC48 main amplifiers
OQ2538HP; OQ2538U
When performing S21 measurements make sure the input
power level is around −50 dBm, as indicated in Fig.7
(port 1 of the network analyzer). For correct measurement
results the OQ2538 should not be limiting the input signal,
but operate in its linear region. This can be achieved by
using a very small input signal level of −50 dBm.
RF gain and group delay measurements
The measurement set-up shown in Fig.7 was used to
measure the single-ended small signal gain as specified in
Chapter “Characteristics”. Since the network analyzer can
only perform single-ended measurements, the
single-ended matching scheme described above is used
to match the inputs of the OQ2538HP to 50 Ω. For greater
accuracy, the outputs are also matched. The gain
measured with this set-up is denoted by S21. Graphs of
typical S21 and group delay characteristics are shown in
Figs 8 and 9. The OQ2538HP test PCB used for these
measurements can be supplied on request.
Although the differential voltage gain of the OQ2538HP
cannot be measured directly, it can be calculated from S21.
The differential voltage gain is 6 dB greater than the
measured S21 value, typically 46 dB (40 + 6 dB). If the
100 Ω matching resistors on the output are omitted, the
differential voltage gain is increased by a further 2.4 dB,
typically to 48.4 dB. This is due to the fact that the output
load is increased from 25 to 33 Ω, so the output voltage is
increased by a factor of 1.32 (2.4 dB).
handbook, full pagewidth
6 GHz NETWORK ANALYZER
S-PARAMETER TEST SET
P = 50 dBm
PORT 1
PORT 2
Zo = 50 Ω
50 Ω semi rigid
50 Ω semi rigid
100 pF
IN
50 Ω semi rigid
OUT
50 Ω semi rigid
100 pF
INQ
50 Ω SMA
termination
Zo = 50 Ω
OQ2538HP
test PCB
100 Ω
OUTQ
100 Ω
100 Ω
100 Ω
VEE = −4.5 V
Fig.7 S21 and group delay measurement set-up.
1998 Oct 14
8
50 Ω SMA
termination
MGM111
Philips Semiconductors
Product specification
SDH/SONET STM16/OC48 main amplifiers
S21
OQ2538HP; OQ2538U
log MAG
MGM160
handbook, full pagewidth
(2)
40 dB
(1)
(3)
(4)
stop: 6 GHz
start: 30 kHz
Vertical scale 6 dB/division.
Linear frequency sweep; start: 30 kHz; stop: 6 GHz.
(1) 41.603 dB; 1 GHz.
(2) 38.633 dB; 3.45 GHz.
(3) 41.291 dB; 2 GHz.
(4) 41.386 dB; 2.5 GHz.
Fig.8 S21 characteristic, measured on the OQ2538HP test PCB.
1998 Oct 14
9
Philips Semiconductors
Product specification
SDH/SONET STM16/OC48 main amplifiers
S21
OQ2538HP; OQ2538U
delay
MGM161
handbook, full pagewidth
(2)
(1)
(3)
(4)
0 ps
stop: 6 GHz
start: 30 kHz
Vertical scale 200 ps/division.
Linear frequency sweep; start: 30 kHz; stop: 6 GHz.
(1) 832.91 ps; 1 GHz.
(2) 1007.4 ps; 3.45 GHz.
(3) 834 ps; 2 GHz.
(4) 860.93 ps; 2.5 GHz.
Fig.9 Group delay characteristic, measured on the OQ2538HP test PCB.
1998 Oct 14
10
Philips Semiconductors
Product specification
SDH/SONET STM16/OC48 main amplifiers
OQ2538HP; OQ2538U
whereas the differential power gain is applicable in this
situation. Ni can be replaced with the available noise
power at the input, which is kT under matched conditions
(k is Boltzmann’s constant). The formula expressed in
dBm makes calculation easier:
F = N o – ( S 21 + 3 ) + 173.8 [ dB ] ,
Noise figure measurements
The noise figure is the ratio of signal-to-noise ratio at the
input (Si/Ni) to signal-to-noise ratio at the output (So/No) of
the amplifier. This definition is true for both single-ended
and differential amplifiers, provided the correct values for
Si/Ni and So/No are substituted in the formula. The noise
figure is measured using the differential set-up shown in
Fig.10. The total noise on the output (No in dBm) is
measured using the spectrum analyzer at the frequency of
interest. From this value, the actual (differential) noise
figure for that frequency (spot noise figure) can be
calculated using the following formula:
Si ⁄ Ni
No
No
F = ----------------= -------------------------- = ---------------------------2 ⋅ S 21 ⋅ N i
2 ⋅ S 21 ⋅ kT
So ⁄ No
assuming log(kT) is −173.8 dBm (T = 298 K) and
No measured in 1 Hz bandwidth and expressed in dBm.
For the OQ2538HP, in the differential configuration
(including the 100 Ω matching resistors), this yields a
typical noise figure of 11 dB.
While the performance of this measurement set-up cannot
match that of a dedicated noise analysis system, the
results are comparable for an amplifier with a noise figure
of 11 dB.
The factor 2 in the denominator is present to compensate
for the fact that S21 is the single-ended power gain,
handbook, full pagewidth
SPECTRUM
ANALYZER
IN
Zo = 50 Ω
OQ2538HP
test PCB
50 Ω semi rigid
50 Ω semi rigid
100 pF
IN
50 Ω SMA
termination
50 Ω semi rigid
50 Ω semi rigid
100 pF
INQ
50 Ω SMA
termination
OUT
100 Ω
OUTQ
100 Ω
100 Ω
100 Ω
VEE = −4.5 V
Fig.10 Noise figure measurement set-up.
1998 Oct 14
11
50 Ω SMA
termination
MGM112
Philips Semiconductors
Product specification
SDH/SONET STM16/OC48 main amplifiers
OQ2538HP; OQ2538U
MGE747
MGE746
VAGC − VAGCDC
(mV)
VLOS − VLOSDC
(mV)
200
200
(2)
(2)
(1)
(1)
(3)
100
0
0
10
20
30
40
(3)
100
50
60
VIN (mV p-p)
0
80
(1) Tamb = −20 °C.
(2) Tamb = +25 °C.
(3) Tamb = +85 °C.
0
1
2
3
4
5
6
7 8 9 10 11
VIN (mV p-p)
(1) Tamb = −20 °C.
(2) Tamb = +25 °C.
(3) Tamb = +85 °C.
Fig.11 AGC transfer characteristics.
Fig.12 LOS detection characteristics.
AGC and AGCDC level detection
Grounding and power supply decoupling
When using rectifier A as an input signal level detector, the
AGC and AGCDC pins must be decoupled to ground with
100 nF capacitors. The AGCDC output is intended as a
reference voltage against which the actual AGC output
voltage can be compared. This voltage difference,
VAGC − VAGCDC, can be used as a control input in an AGC
loop. A graph depicting output voltage difference as a
function of the input signal level (typical) is shown in
Fig.11. Note that an input signal with the specified
peak-to-peak value is applied to both IN and INQ inputs,
but with complementary phase.
The ground connection on the PCB needs to be a large
copper area fill connected to a common ground plane with
as low inductance as possible, preferably positioned
directly underneath the LQFP48 package. The large area
fill will improve heat transfer to the PCB and thus aid IC
cooling.
All VEE pins (two at each corner) need to be connected to
a common supply plane with as low inductance as
possible. This plane should be decoupled to ground.
To avoid high frequency resonance, multiple bypass
capacitors should not be mounted at the same location.
To minimize low frequency switching noise in the vicinity of
the OQ2538HP, the power supply line should be filtered
once using an LC-circuit with a low cut-off frequency
(see Fig.14).
LOS and LOSDC level detection
The output of rectifier B can be used for LOS detection.
The LOSDC output provides a reference voltage against
which the voltage at the LOS output can be compared.
The voltage difference VLOS − VLOSDC can be used as
input to a LOS detection circuit. Both outputs need to be
decoupled using 100 nF capacitors. A graph depicting
VLOS − VLOSDC as a function of the input signal level
(typical) is shown in Fig.12. Note that an input signal with
the specified peak-to-peak value is applied to both IN and
INQ inputs, but with complementary phase.
1998 Oct 14
12
Philips Semiconductors
Product specification
SDH/SONET STM16/OC48 main amplifiers
OQ2538HP; OQ2538U
Using alternative supply voltages
ESD protection
Although the OQ2538HP is intended to be used with a
single −4.5 V supply voltage, a slightly modified −5 V
supply can also be used. By connecting a Schottky diode
between the VEE power supply line and the IC, an
additional 0.5 V voltage drop is obtained, bringing the
supply voltage on the pins of the OQ2538HP within the
specified range. A BAS85 Schottky diode is
recommended. A −5 V application schematic is shown in
Fig.15.
Exceptions have been made to the standard ESD
protection scheme in order to achieve high frequency
performance. The inputs IN and INQ and the outputs OUT
and OUTQ have no protection against ESD. All other pins
have a standard ESD protection structure, capable of
withstanding 2 kV Human Body Model (HBM) zappings.
Extrapolating from this case, a +5 V application is also
possible. However, care should be taken with the RF
transmission lines. The on-chip signals refer to the GND
pins, which become the positive supply pins in a +5 V
application. The external transmission lines will most likely
be referenced to system ground (VEE pins). The RF signals
will change from one reference plane to another at the
interface to the RF input and output pins. The positive
supply application is very vulnerable to interference at this
point. For a successful +5 V application, special care
should be taken when designing board layout to reduce
the influence of interference and keep the positive supply
as clean as possible.
1998 Oct 14
13
Philips Semiconductors
Product specification
SDH/SONET STM16/OC48 main amplifiers
OQ2538HP; OQ2538U
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
−6.0
+0.5
V
−600
+600
mV
−2.0
+2.0
mA
pins 30 and 32
−6
+10
mA
pins 3, 18, 19 and 43
−3
+3
mA
pin 21
−2
+2
mA
pins 44 and 45
−1
+1
mA
pin 22
−0.1
+0.1
mA
VEE
negative supply voltage
∆VI
input voltage difference
IIN, IINQ
input current
In
DC current
note 1
Ptot
total power dissipation
−
380
mW
Tj
junction temperature
−
150
°C
Tstg
storage temperature
−65
+150
°C
Note
1. ∆VI = VIN − VINQ (AC only). The DC level is internally controlled.
HANDLING
Precautions should be taken to avoid damage through electrostatic discharge. This is particularly important during
assembly and handling of the bare die. Additional safety can be obtained by bonding the VEE and GND pads first, the
remaining pads may then be bonded to their external connections in any order (see also Section “ESD protection”).
THERMAL CHARACTERISTICS
SYMBOL
DESCRIPTION
CONDITIONS
Rth(j-s)
thermal resistance from junction to solder point
Rth(j-a)
thermal resistance from junction to ambient
note 1
Note
1. Rth(j-a) will be in the application from 15 to 65 K/W, dependent on the PCB layout.
1998 Oct 14
14
VALUE
UNIT
15
K/W
65
K/W
Philips Semiconductors
Product specification
SDH/SONET STM16/OC48 main amplifiers
OQ2538HP; OQ2538U
CHARACTERISTICS
At nominal supply voltages; Tamb = −40 to +85 °C; 50 Ω measuring environment.
SYMBOL
PARAMETER
CONDITIONS
VEE
negative supply voltage
IEE
negative supply current
Ptot
total power dissipation
note 1
Tamb
operating ambient temperature
note 2
Tj
operating junction temperature
MIN.
TYP.
MAX.
UNIT
−4.725
−4.5
−4.275
V
−
60
80
mA
−
270
380
mW
−40
−
+85
°C
−40
−
+120
°C
Main amplifier inputs: IN and INQ; note 3
Vi(sens)
input sensitivity
note 4
−
0.5
2.5
mV
Vi(p-p)
signal voltage swing (peak-to-peak
value)
note 4
2.5
−
600
mV
VI
DC input voltage
note 5
−2.4
−2.1
−1.7
V
VIO
input offset voltage
note 6
−
0.2
−
mV
Zi
single-ended input impedance
note 7
−
100
−
Ω
S21
single-ended small signal gain
note 8
34
40
−
dB
Gv(dif)
differential voltage gain
note 9
−
48.5
−
dB
No
output noise power
note 10
−
−120
−
dBm
F
noise figure
note 10
−
11
−
dB
B−3dB
3 dB bandwidth
2.4
3.0
−
GHz
−3.3
−3.0
−2.5
V
12.5
−
60
mV
Rectifier outputs: AGC and AGCDC; note 11
VO(ref)
DC reference voltage
Vi(p-p)
input voltages on pins IN and INQ for
linear rectifier output (peak-to-peak
value)
∆V
maximum input signal level related
voltage difference
note 12
−
400
−
mV
VOO
output offset voltage
note 13
−5
−
+5
mV
open output
−3.4
−3.1
−2.6
V
2.5
−
9
mV
open output
Rectifier outputs: LOS and LOSDC; note 11
VO(ref)
DC reference voltage
Vi(p-p)
input voltages on pins IN and INQ for
linear recitifier output (peak-to-peak
value)
∆V
maximum input signal level related
voltage difference
note 12
−
450
−
mV
VOO
output offset voltage
note 13
−15
−
+15
mV
−2.4
−2.1
−1.7
V
−
1250
−
Ω
1.1
1.3
1.5
V
Automatic offset compensation lowpass filter: COFF and COFFQ
VO
DC output voltage
R
offset compensation filter resistance
open output
Band gap reference: REF
VO
1998 Oct 14
band gap voltage
referenced to VEE;
open output; note 14
15
Philips Semiconductors
Product specification
SDH/SONET STM16/OC48 main amplifiers
SYMBOL
PARAMETER
OQ2538HP; OQ2538U
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Band gap reference decoupling: CAPA
VO
decoupling voltage
referenced to VEE;
open output
−
2.9
−
V
−20
−5
0
mV
Main amplifier outputs: OUT and OUTQ; note 15
VOH
HIGH-level output voltage
VOL
LOW-level output voltage
note 16
−280
−200
−140
mV
tr
differential output rise time
input signal >2.5 mV (p-p)
−
100
150
ps
tf
differential output fall time
input signal >2.5 mV (p-p)
−
100
150
ps
Zo
single-ended output impedance
see Fig.6
83
100
117
Ω
Notes
1. No special cooling is required in the application if the total thermal resistance Rth(j-a) is less than 90 K/W.
2. The temperature of the PCB in the vicinity of the IC is taken to be the ambient temperature.
3. The input signal must be AC-coupled to the inputs through a coupling capacitance >22 nF.
4. Vi(p-p) is the input signal on IN and INQ for full output clipping. It is assumed that both inputs carry a complementary
signal of the specified peak-to-peak value. The lower specified limit is usually called the input sensitivity. This value
is defined as a 20% increase in rise and fall times when compared to rise and fall times with a complementary input
signal of 10 mV (p-p) applied to IN and INQ.
5. The DC voltage is fixed internally; only AC-coupling of the input signal is allowed.
6. VIO = V IN − V INQ
7. See Section “RF input matching circuit” for detailed information.
8. All signal ports are AC-matched to 50 Ω and are measured at 1 GHz (see Fig.7). Flatness deviations are within ±3 dB
over the entire bandwidth.
9. See Section “RF gain and group delay measurements”.
10. F is the noise figure for a differential application and is measured at 1 GHz. See Section “Noise figure
measurements”.
11. An external 100 nF capacitor is connected at each output to remove any spurious high frequency signals.
Any circuitry driven from these pins must have an input impedance >50 kΩ.
12. Voltage difference between AGC (LOS) and AGCDC (LOSDC), measured with a differential square wave input
signal of 600 mV (p-p) on IN and INQ.
13. The offset is measured with inputs IN and INQ shorted together.
14. The band gap voltage may not be used as an external reference.
15. Both outputs are connected to ground through a 50 Ω load resistance and carry complementary signals.
16. The output levels are dependent on load impedance. The specified values assume an external load impedance of
50 Ω. If the external 100 Ω matching resistors are connected at pins OUT and OUTQ, the output levels will fall to
75% of the specified values (see also Section “RF gain and group delay measurements”).
1998 Oct 14
16
Philips Semiconductors
Product specification
SDH/SONET STM16/OC48 main amplifiers
OQ2538HP; OQ2538U
APPLICATION INFORMATION
handbook, full pagewidth
CGY2100
OQ2541HP
OQ2538HP
RFB
data
IPHOTO
to data and
clock recovery unit
FILTER
Vbias
TRANSIMPEDANCE
AMPLIFIER
DATA AND
CLOCK
RECOVERY
LIMITING
AMPLIFIER
recovered
clock
MGE748
PHOTODIODE
Fig.13 System application diagram.
handbook, full pagewidth
CIN
IN
IN
>22 nF
CINQ
32
8
30
200 Ω
INQ
INQ
16
45
>22 nF
OUT
OUTQ
COFF
OQ2538HP
AGC
GAIN
REGULATION
AGCDC
100
nF
100
nF
44
3
21
43
22
19
18
LOS
LOSDC
COFFQ
REF
CAPA
1 nF
VEE
LOSS OF SIGNAL
DETECTION
GND
VEE
10 µH
100
nF
100
nF
100
nF
33
nF
−4.5 V
4.7
µF
MGE749
Fig.14 Typical application schematic.
1998 Oct 14
17
Philips Semiconductors
Product specification
SDH/SONET STM16/OC48 main amplifiers
handbook, full pagewidth
CIN
IN
IN
>22 nF
CINQ
OQ2538HP; OQ2538U
32
8
30
200 Ω
INQ
INQ
16
45
>22 nF
OUT
OUTQ
COFF
OQ2538HP
AGC
GAIN
REGULATION
AGCDC
100
nF
100
nF
44
3
21
43
22
19
18
LOS
LOSDC
REF
CAPA
GND
10 µH
100
nF
100
nF
1 nF
VEE
LOSS OF SIGNAL
DETECTION
100
nF
COFFQ
33
nF
VEE
BAS85
−5.0 V
4.7
µF
MGM113
Fig.15 −5 V application schematic.
1998 Oct 14
18
Philips Semiconductors
Product specification
SDH/SONET STM16/OC48 main amplifiers
OQ2538HP; OQ2538U
VEE
COFF
COFFQ
AGCDC
GND
GND
n.c.
GND
BONDING PAD LOCATIONS
28
27
26
25
24
23
22
21
handbook, full pagewidth
2.07(1)
mm
VEE
29
AGC
20
n.c.
30
19
GND
GND
31
18
GND
GND
32
17
OUT
INQ
33
16
GND
15
OUTQ
14
GND
x
0
GND
34
IN
35
0
y
OQ2538U
VEE
2
11
VEE
3
4
5
6
7
8
9
10
CAPA
VEE
REF
12
GND
1
LOS
GND
LOSDC
GND
GND
13
GND
36
VEE
GND
2.07 mm(1)
MGR525
(1) Typical value.
Fig.16 Bonding pad locations of OQ2538U.
1998 Oct 14
19
Philips Semiconductors
Product specification
SDH/SONET STM16/OC48 main amplifiers
Table 1
OQ2538HP; OQ2538U
Bonding pad locations. All x/y coordinates
represent the position of the centre of the pad
with respect to the centre of the die (see
Fig.16).
COORDINATES
COORDINATES
SYMBOL
SYMBOL
PAD
x
y
GND
1
−900
−700
GND
PAD
19
x
y
+900
+700
VEE
2
−900
−900
n.c.
20
+900
+900
VEE
3
−700
−900
GND
21
+700
+900
GND
4
−500
−900
n.c.
22
+500
+900
GND
5
−300
−900
GND
23
+300
+900
LOSDC
6
−100
−900
GND
24
+100
+900
LOS
7
+100
−900
AGCDC
25
−100
+900
GND
8
+300
−900
COFFQ
26
−300
+900
REF
9
+500
−900
COFF
27
−500
+900
CAPA
10
+700
−900
VEE
28
−700
+900
VEE
11
+900
−900
VEE
29
−900
+900
VEE
12
+900
−700
AGC
30
−900
+700
GND
13
+900
−500
GND
31
−900
+500
GND
14
+900
−300
GND
32
−900
+300
OUTQ
15
+900
−100
INQ
33
−900
+100
GND
16
+900
+100
GND
34
−900
−100
OUT
17
+900
+300
IN
35
−900
−300
GND
18
+900
+500
GND
36
−900
−500
Table 2
Physical characteristics of bare die
PARAMETER
VALUE
Glass passivation
0.8 µm silicon nitride on top of 0.9 µm PSG (PhosphoSilicate Glass)
Bonding pad dimension
minimum dimension of exposed metallization is 90 × 90 µm (pad size = 100 × 100 µm)
Metallization
1.8 µm AlCu (1% Cu)
Thickness
380 µm nominal
Size
2.070 × 2.070 mm (4.285 mm2)
Backing
silicon; electrically connected to VEE potential through substrate contacts
Attache temperature
<440 °C; recommended die attache is glue
Attache time
<15 s
1998 Oct 14
20
Philips Semiconductors
Product specification
SDH/SONET STM16/OC48 main amplifiers
OQ2538HP; OQ2538U
PACKAGE OUTLINE
LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm
SOT313-2
c
y
X
36
25
A
37
24
ZE
e
E HE
A A2
(A 3)
A1
w M
pin 1 index
θ
bp
Lp
L
13
48
detail X
12
1
ZD
e
v M A
w M
bp
D
B
HD
v M B
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HD
HE
L
Lp
v
w
y
mm
1.60
0.20
0.05
1.45
1.35
0.25
0.27
0.17
0.18
0.12
7.1
6.9
7.1
6.9
0.5
9.15
8.85
9.15
8.85
1.0
0.75
0.45
0.2
0.12
0.1
Z D (1) Z E (1)
θ
0.95
0.55
7
0o
0.95
0.55
o
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
EIAJ
ISSUE DATE
94-12-19
97-08-01
SOT313-2
1998 Oct 14
EUROPEAN
PROJECTION
21
Philips Semiconductors
Product specification
SDH/SONET STM16/OC48 main amplifiers
If wave soldering cannot be avoided, for LQFP
packages with a pitch (e) larger than 0.5 mm, the
following conditions must be observed:
SOLDERING
Introduction
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
• The footprint must be at an angle of 45° to the board
direction and must incorporate solder thieves
downstream and at the side corners.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(order code 9398 652 90011).
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
Reflow soldering
Reflow soldering techniques are suitable for all LQFP
packages.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Repairing soldered joints
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 50 and 300 seconds depending on heating
method. Typical reflow peak temperatures range from
215 to 250 °C.
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
Wave soldering
Wave soldering is not recommended for LQFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.
CAUTION
Wave soldering is NOT applicable for all LQFP
packages with a pitch (e) equal or less than 0.5 mm.
1998 Oct 14
OQ2538HP; OQ2538U
22
Philips Semiconductors
Product specification
SDH/SONET STM16/OC48 main amplifiers
OQ2538HP; OQ2538U
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
BARE DIE DISCLAIMER
All die are tested and are guaranteed to comply with all data sheet limits up to the point of wafer sawing for a period of
ninety (90) days from the date of Philips' delivery. If there are data sheet limits not guaranteed, these will be separately
indicated in the data sheet. There is no post waffle pack testing performed on individual die. Although the most modern
processes are utilized for wafer sawing and die pick and place into waffle pack carriers, Philips Semiconductors has no
control of third party procedures in the handling, packing or assembly of the die. Accordingly, Philips Semiconductors
assumes no liability for device functionality or performance of the die or systems after handling, packing or assembly of
the die. It is the responsibility of the customer to test and qualify their application in which the die is used.
1998 Oct 14
23
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For all other countries apply to: Philips Semiconductors,
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Internet: http://www.semiconductors.philips.com
© Philips Electronics N.V. 1998
SCA60
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
425102/400/02/pp24
Date of release: 1998 Oct 14
Document order number:
9397 750 04257