TI1 MSP430FR2533IRHBR Mixed-signal microcontroller Datasheet

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MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532
SLAS942A – NOVEMBER 2015 – REVISED DECEMBER 2015
MSP430FR263x, MSP430FR253x Mixed-Signal Microcontrollers
1 Device Overview
1.1
Features
1
• Embedded Microcontroller
– 16-Bit RISC Architecture
– Clock Supports Frequencies up to 16 MHz
– Wide Supply Voltage Range From 1.8 V to
3.6 V (1)
• Optimized Ultra-Low-Power Modes
– Active Mode: 126 µA/MHz (Typical)
– Standby
• 1.7 µA/Button Average (Typical) (16 SelfCapacitance Buttons, 8-Hz Scanning)
• 1.7 µA/Button Average (Typical) (64 MutualCapacitance Buttons, 8-Hz Scanning)
– LPM3.5 Real-Time Clock (RTC) Counter With
32768-Hz Crystal: 770 nA (Typical)
– Shutdown (LPM4.5): 15 nA (Typical)
• Low-Power Ferroelectric RAM (FRAM)
– Up to 15.5KB of Nonvolatile Memory
– Built-In Error Correction Code (ECC)
– Configurable Write Protection
– Unified Memory of Program, Constants, and
Storage
– 1015 Write Cycle Endurance
– Radiation Resistant and Nonmagnetic
– High FRAM-to-SRAM Ratio, up to 4:1
• Intelligent Digital Peripherals
– Four 16-Bit Timers
• Two Timers With Three Capture/Compare
Registers Each (Timer_A3)
• Two Timers With Two Capture/Compare
Registers Each (Timer_A2)
– One 16-Bit Timer Associated With CapTIvate™
Technology
– One 16-Bit Counter-Only RTC
– 16-Bit Cyclic Redundancy Check (CRC)
• Enhanced Serial Communications
– Two Enhanced Universal Serial Communication
Interfaces (eUSCI_A) Support UART, IrDA, and
SPI
– One eUSCI (eUSCI_B) Supports SPI and I2C
• High-Performance Analog
– 8-Channel 10-Bit Analog-to-Digital Converter
(ADC)
• Internal 1.5-V Reference
• Sample-and-Hold 200 ksps
(1)
1
Minimum supply voltage is restricted by SVS levels (see
VSVSH- and VSVSH+ in Table 5-2)
– CapTIvate Technology – Capacitive Touch
• Performance
– Fast Electrode Scanning With Four
Simultaneous Scans
– Support for High-Resolution Sliders With
>1024 Points
– 30-cm Proximity Sensing
• Reliability
– Increased Immunity to Power Line, RF,
and Other Environmental Noise
– Built-in Spread Spectrum, Automatic
Tuning, Noise Filtering, and Debouncing
Algorithms
– Enables Reliable Touch Solutions With
10-V RMS Common-Mode Noise, 4-kV
Electrical Fast Transients, and 15-kV
Electrostatic Discharge, Allowing for
IEC‑61000-4-6, IEC-61000-4-4, and
IEC‑61000-4-2 Compliance
– Reduced RF Emissions to Simplify
Electrical Designs
– Support for Metal Touch and Water
Rejection Designs
• Flexibility
– Up to 16 Self-Capacitance and 64
Mutual-Capacitance Electrodes
– Mix and Match Self- and MutualCapacitive Electrodes in the Same
Design
– Supports Multitouch Functionality
– Wide Range of Capacitance Detection,
Wide Electrode Range of 0 to 300 pF
• Low Power
– <0.9 µA/Button in Wake-on-Touch Mode,
Where Capacitive Measurement and
Touch Detection is Done by Hardware
State Machine While CPU is Asleep
– Wake-on-Touch State Machine Allows
Electrode Scanning While CPU is Asleep
– Hardware Acceleration for Environmental
Compensation, Filtering, and Threshold
Detection
• Ease of Use
– CapTIvate Design Center, PC GUI Lets
Engineers Design and Tune Capacitive
Buttons in Real Time Without Having to
Write Code
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532
SLAS942A – NOVEMBER 2015 – REVISED DECEMBER 2015
– CapTIvate Software Library in ROM
Provides Ample FRAM for Customer
Application
• Clock System (CS)
– On-Chip 32-kHz RC Oscillator (REFO)
– On-Chip 16-MHz Digitally Controlled Oscillator
(DCO) With Frequency-Locked Loop (FLL)
• ±1% Accuracy With On-Chip Reference at
Room Temperature
– On-Chip Very Low-Frequency 10-kHz Oscillator
(VLO)
– On-Chip High-Frequency Modulation Oscillator
(MODOSC)
– External 32-kHz Crystal Oscillator (LFXT)
– Programmable MCLK Prescalar of 1 to 128
– SMCLK Derived from MCLK With
Programmable Prescalar of 1, 2, 4, or 8
• General Input/Output and Pin Functionality
– Total of 19 I/Os on TSSOP-32 Package
– 16 Interrupt Pins (P1 and P2) Can Wake MCU
From Low-Power Modes
• Development Tools and Software
– Ease-of-Use Ecosystem
• CapTIvate Design Center – Code
Generation, Customizable GUI, Real-Time
Tuning
1.2
•
•
•
•
– Free Professional Development Environments
• 12-KB ROM Library Includes CapTIvate Touch
Libraries and Driver Libraries
• Family Members (Also See Section 3)
– MSP430FR2633: 15KB of Program FRAM +
512B of Information FRAM + 4KB of RAM
up to 16 Self-Capacitive and 64 MutualCapacitive Sensors
– MSP430FR2533: 15KB of Program FRAM +
512B of Information FRAM + 2KB of RAM
up to 16 Self-Capacitive or 16 Mutual-Capacitive
Sensors
– MSP430FR2632: 8KB of Program FRAM +
512B of Information FRAM + 2KB of RAM
up to 8 Self-Capacitive or 16 Mutual-Capacitive
Sensors
– MSP430FR2532: 8KB of Program FRAM +
512B of Information FRAM + 1KB of RAM
up to 8 Self-Capacitive or 8 Mutual-Capacitive
Sensors
• Package Options
– 32-Pin: VQFN (RHB)
– 32-Pin: TSSOP (DA)
– 24-Pin: VQFN (RGE)
• For Complete Module Descriptions, See the
MSP430FR4xx and MSP430FR2xx Family User's
Guide (SLAU445)
Applications
Thermostats
Electronic Access Control
Lighting Control
Electronic Door Locks
1.3
www.ti.com
•
•
•
White Goods
Small Appliances
Personal Electronics
Description
The MSP430FR263x and MSP430FR253x are FRAM-based ultra-low-power MSP microcontrollers that
feature CapTIvate touch technology for buttons, sliders, wheels (BSW), and proximity applications.
CapTIvate technology provides the highest resolution capacitive-touch solution in the market with high
reliability and noise immunity at the lowest power. CapTIvate technology supports concurrent selfcapacitance and mutual-capacitance electrodes on the same design for maximum flexibility. Using the
CapTIvate Design Center, engineers can quickly develop BSW applications with an easy-to-use GUI.
The TI MSP family of low-power microcontrollers consists of several devices that feature different sets of
peripherals targeted for various applications. The architecture, combined with extensive low-power modes,
is optimized to achieve extended battery life in portable measurement applications. The MCU features a
powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code
efficiency. The digitally controlled oscillator (DCO) allows the MCU to wake up from low-power modes to
active mode typically in less than 10 µs.
2
Device Overview
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SLAS942A – NOVEMBER 2015 – REVISED DECEMBER 2015
Device Information (1)
PART NUMBER
MSP430FR2633IRHB
PACKAGE
BODY SIZE (2)
VQFN (32)
5 mm × 5 mm
MSP430FR2533IRHB
VQFN (32)
5 mm × 5 mm
MSP430FR2633IDA
TSSOP (32)
11 mm × 6.2 mm
MSP430FR2533IDA
TSSOP (32)
11 mm × 6.2 mm
MSP430FR2632IRGE
VQFN (24)
4 mm × 4 mm
MSP430FR2532IRGE
VQFN (24)
4 mm × 4 mm
(1)
(2)
For the most current part, package, and ordering information, see the Package Option Addendum in
Section 9, or see the TI website at www.ti.com.
The sizes shown here are approximations. For the package dimensions with tolerances, see the
Mechanical Data in Section 9.
CAUTION
System-level ESD protection must be applied in compliance with the devicelevel ESD specification to prevent electrical overstress or disturbing of data or
code memory. See the application report MSP430 System-Level ESD
Considerations (SLAA530) for more information.
Device Overview
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SLAS942A – NOVEMBER 2015 – REVISED DECEMBER 2015
1.4
www.ti.com
Functional Block Diagram
Figure 1-1 shows the functional block diagram.
XIN
DVCC
DVSS
RST/NMI
VREG
Power
Management
Module
P1.x/P2.x
XOUT
LFXT
ADC
FRAM
RAM
Clock
System
Up to 8-ch
Single-end
10-bit
200ksps
15KB+512B
8KB+512B
4KB
2KB
2×TA
2×TA
MPY32
32-bit
Hardware
Multiplier
I/O Ports
P1/P2
2×8 IOs
Interrupt
& Wakeup
PA
1×16 IOs
P3.x
I/O Ports
P3
1×3 IOs
PB
1×3 IOs
CapTIvate
16-ch
8-ch
MAB
16-MHZ CPU
inc.
16 Registers
MDB
EEM
CRC16
SYS
TCK
TMS
TDI/TCLK
TDO
SBWTCK
SBWTDIO
•
•
•
•
•
•
4
JTAG
Watchdog
16-bit
Cyclic
Redundancy
Check
Timer_A3
3 CC
Registers
Timer_A2
2 CC
Registers
2×eUSCI_A
(UART,
IrDA, SPI)
eUSCI_B0
(SPI, I2C)
RTC
Counter
BAKMEM
16-bit
Real-Time
Clock
32-bytes
Backup
Memory
LPM3.5 Domain
SBW
Figure 1-1. Functional Block Diagram
The MCU has one main power pair of DVCC and DVSS that supplies digital and analog modules.
Recommended bypass and decoupling capacitors are 4.7 µF to 10 µF and 0.1 µF, respectively, with
±5% accuracy.
VREG is the decoupling capacitor of the CapTIvate regulator. The recommended value for the required
decoupling capacitor is 1 µF, with a maximum ESR of ≤200 mΩ.
P1 and P2 feature the pin interrupt function and can wake the MCU from all LPMs, including LPM3.5
and LPM4.
Each Timer_A3 has three capture/compare registers. Only CCR1 and CCR2 are externally connected.
CCR0 registers can be used only for internal period timing and interrupt generation.
Each Timer_A2 has two capture/compare registers. Both registers can be used only for internal period
timing and interrupt generation.
In LPM3 mode, the CapTIvate module can be functional while the rest of the peripherals are off.
Device Overview
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SLAS942A – NOVEMBER 2015 – REVISED DECEMBER 2015
Table of Contents
1
2
3
4
Device Overview ......................................... 1
7.2
17
Active Mode Supply Current Into VCC Excluding
External Current ..................................... 18
75
Peripheral- and Interface-Specific Design
Information .......................................... 78
7.3
Typical Applications ................................. 84
1.2
Applications ........................................... 2
1.3
Description ............................................ 2
1.4
Functional Block Diagram ............................ 4
Revision History ......................................... 5
Device Comparison ..................................... 6
Terminal Configuration and Functions .............. 7
4.1
Pin Diagrams ......................................... 7
4.2
Pin Attributes ........................................ 10
4.3
Signal Descriptions .................................. 13
.....................................
4.5
Buffer Types.........................................
4.6
Connection of Unused Pins .........................
Specifications ...........................................
5.1
Absolute Maximum Ratings .........................
5.2
ESD Ratings ........................................
5.3
Recommended Operating Conditions ...............
Pin Multiplexing
5.4
Active Mode Supply Current Per MHz ..............
Low-Power Mode LPM0 Supply Currents Into VCC
Excluding External Current..........................
Low-Power Mode LPM3 Supply Currents (Into VCC)
Excluding External Current..........................
Low-Power Mode LPMx.5 Supply Currents (Into
VCC) Excluding External Current ....................
Typical Characteristics - Low-Power Mode Supply
Currents .............................................
5.5
5.6
5.7
5.8
5.9
6
17
17
Features .............................................. 1
4.4
5
............................................
.................................................
6.3
Operating Modes ....................................
6.4
Interrupt Vector Addresses..........................
6.5
Bootloader (BSL) ....................................
6.6
JTAG Standard Interface............................
6.7
Spy-Bi-Wire Interface (SBW)........................
6.8
FRAM................................................
6.9
Memory Protection ..................................
6.10 Peripherals ..........................................
6.11 Input/Output Schematics ............................
6.12 Device Descriptors ..................................
6.13 Memory ..............................................
6.14 Identification .........................................
Applications, Implementation, and Layout........
7.1
Device Connection and Layout Fundamentals ......
1.1
16
16
16
17
7
8
18
18
19
20
21
5.10
Thermal Resistance Characteristics ................ 23
5.11
Timing and Switching Characteristics ............... 24
9
6.1
Overview
6.2
CPU
43
43
43
45
46
47
47
47
47
48
58
65
66
74
75
Device and Documentation Support ............... 85
8.1
Device Support ...................................... 85
8.2
Documentation Support ............................. 88
8.3
Related Links ........................................ 89
8.4
Community Resources .............................. 89
8.5
Trademarks.......................................... 89
8.6
Electrostatic Discharge Caution ..................... 89
8.7
Export Control Notice
8.8
Glossary ............................................. 89
...............................
89
Mechanical, Packaging, and Orderable
Information .............................................. 90
Detailed Description ................................... 43
2 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from November 10, 2015 to December 8, 2015
•
•
•
•
•
•
•
•
Page
Changed document status from Preview to Production Data ................................................................... 1
Added note to list item that starts "Wide Supply Voltage Range..." ........................................................... 1
Changed list item that starts "Enables Reliable Touch Solutions..." ........................................................... 1
In the note that starts "Low-power mode 3, VLO, excludes SVS test conditions...", changed "fXT1 = 0 Hz" to
"fXT1 = 32768 Hz" .................................................................................................................... 19
Added note that starts "The VLO clock frequency is reduced by 15%...".................................................... 28
Added note to "Clock" in Table 6-1, Operating Modes ......................................................................... 44
Added note that starts "XT1CLK and VLOCLK can be active during LPM4..." ............................................. 44
Corrected description in Section 6.10.10, Backup Memory (BKMEM) ....................................................... 55
Revision History
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SLAS942A – NOVEMBER 2015 – REVISED DECEMBER 2015
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3 Device Comparison
Table 3-1 summarizes the features of the available family members.
Table 3-1. Device Comparison (1) (2)
PROGRAM FRAM
+ INFORMATION
FRAM (bytes)
SRAM
(bytes)
TA0 TO TA3
MSP430FR2633IRHB
15360 + 512
4096
MSP430FR2533IRHB
15360 + 512
MSP430FR2633IDA
DEVICE
eUSCI_B
10-BIT ADC
CHANNELS
CapTIvate™
CHANNELS
GPIOs
PACKAGE
TYPE
up to 2
1
8
16 (4)
19
32 RHB
(VQFN)
up to 2
up to 2
1
8
16 (4)
19
32 RHB
(VQFN)
2, 3 × CCR (3)
2, 2 × CCR
up to 2
up to 2
1
8
16 (4)
19
32 DA
(TSSOP)
2048
2, 3 × CCR (3)
2, 2 × CCR
up to 2
up to 2
1
8
16 (4)
19
32 DA
(TSSOP)
8192 + 512
2048
2, 3 × CCR (3)
2, 2 × CCR
up to 2
1
1
8
8 (5)
15
24 RGE
(VQFN)
8192 + 512
1,024
2, 3 × CCR (3)
2, 2 × CCR
up to 2
1
1
8
8 (5)
15
24 RGE
(VQFN)
SPI
2, 3 × CCR (3)
2, 2 × CCR
up to 2
2048
2, 3 × CCR (3)
2, 2 × CCR
15360 + 512
4096
MSP430FR2533IDA
15360 + 512
MSP430FR2632IRGE
MSP430FR2532IRGE
(1)
(2)
(3)
(4)
(5)
6
eUSCI_A
UART
For the most current package and ordering information, see the Package Option Addendum in Section 9, or see the TI website at
www.ti.com
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/packaging
A CCR register is a configurable register that provides internal and external capture or compare inputs, or internal and external PWM
outputs.
Eight dedicated CapTIvate channels are included.
Four dedicated CapTIvate channels are included.
Device Comparison
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SLAS942A – NOVEMBER 2015 – REVISED DECEMBER 2015
4 Terminal Configuration and Functions
4.1
Pin Diagrams
CAP3.1
P2.7/CAP3.0
CAP3.3
P3.2/CAP3.2
P2.1/XIN
P2.0/XOUT
DVCC
DVSS
Figure 4-1 shows the pinout for the 24-pin RHB package.
RST/NMI/SBWTDIO
1
32 31 30 29 28 27 26 25
24
CAP2.3
TEST/SBWTCK
2
23
CAP2.2
P1.4/UCA0TXD/UCA0SIMO/TA1.2/TCK/A4/VREF+
3
22
CAP2.1
4 MSP430FR2633IRHB 21
5 MSP430FR2533IRHB 20
CAP2.0
P1.5/UCA0RXD/UCA0SOMI/TA1.1/TMS/A5
P1.6/UCA0CLK/TA1CLK/TDI/TCLK/A6
VREG
8
17
9 10 11 12 13 14 15 16
P2.4/UCA1CLK/CAP1.1
P3.1/UCA1STE/CAP1.0
CAP0.3
P2.5/UCA1RXD/UCA1SOMI/CAP1.2
P1.1/UCB0CLK/TA0.1/A1
CAP0.1
18
P2.3/CAP0.2
7
P3.0/CAP0.0
P2.6/UCA1TXD/UCA1SIMO/CAP1.3
P1.0/UCB0STE/TA0CLK/A0/Veref+
P2.2/SYNC/ACLK
19
P1.3/UCB0SOMI/UCB0SCL/MCLK/A3
6
P1.2/UCB0SIMO/UCB0SDA/TA0.2/A2/Veref-
P1.7/UCA0STE/SMCLK/TDO/A7
Figure 4-1. 32-Pin RHB Package (Top View)
Terminal Configuration and Functions
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Figure 4-2 shows the pinout for the 32-pin DA package.
P2.0/XOUT
1
32
CAP3.3
P2.1/XIN
2
31
P3.2/CAP3.2
DVSS
3
30
CAP3.1
DVCC
4
29
P2.7/CAP3.0
RST/NMI/SBWTDIO
5
28
CAP2.3
TEST/SBWTCK
6
27
CAP2.2
P1.4/UCA0TXD/UCA0SIMO/TA1.2/TCK/A4/VREF+
7
26
CAP2.1
P1.5/UCA0RXD/UCA0SOMI/TA1.1/TMS/A5
8
25
CAP2.0
MSP430FR2633IDA
MSP430FR2533IDA
P1.6/UCA0CLK/TA1CLK/TDI/TCLK/A6
9
24
VREG
P1.7/UCA0STE/SMCLK/TDO/A7
10
23
P2.6/UCA1TXD/UCA1SIMO/CAP1.3
P1.0/UCB0STE/TA0CLK/A0/Veref+
11
22
P2.5/UCA1RXD/UCA1SOMI/CAP1.2
P1.1/UCB0CLK/TA0.1/A1
12
21
P2.4/UCA1CLK/CAP1.1
P1.2/UCB0SIMO/UCB0SDA/TA0.2/A2/Veref-
13
20
P3.1/UCA1STE/CAP1.0
P1.3/UCB0SOMI/UCB0SCL/MCLK/A3
14
19
CAP0.3
P2.2/SYNC/ACLK
15
18
P2.3/CAP0.2
P3.0/CAP0.0
16
17
CAP0.1
Figure 4-2. 32-Pin DA Package (Top View)
8
Terminal Configuration and Functions
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SLAS942A – NOVEMBER 2015 – REVISED DECEMBER 2015
CAP3.1
P2.7/CAP3.0
P2.1/XIN
P2.0/XOUT
DVCC
DVSS
Figure 4-3 shows the pinout for the 24-pin RGE package.
24 23 22 21 20 19
RST/NMI/SBWTDIO
1
18
CAP2.1
TEST/SBWTCK
2
17
CAP2.0
P1.4/UCA0TXD/UCA0SIMO/TA1.2/TCK/A4/VREF+
3
16
VREG
P1.5/UCA0RXD/UCA0SOMI/TA1.1/TMS/A5
4
15
P2.6/UCA1TXD/UCA1SIMO/CAP1.3
P1.6/UCA0CLK/TA1CLK/TDI/TCLKA6
5
14
P2.5/UCA1RXD/UCA1SOMI/CAP1.2
P1.7/UCA0STE/SMCLK/TDO/A7
6
13
CAP0.3
P1.1/UCB0CLK/TA0.1/A1
P1.2/UCB0SIMO/UCB0SDA/TA0.2/A2/Veref-
P2.3/CAP0.2
9 10 11 12
P2.2/SYNC/ACLK
8
P1.3/UCB0SOMI/UCB0SCL/MCLK/A3
7
P1.0/UCB0STE/TA0CLK/A0/Veref+
MSP430FR2632IRGE
MSP430FR2532IRGE
Figure 4-3. 24-Pin RGE Package (Top View)
Terminal Configuration and Functions
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4.2
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Pin Attributes
Table 4-1 lists the attributes of all pins.
Table 4-1. Pin Attributes
PIN NUMBER
RHB
DA
RGE
SIGNAL NAME (1)
RST (RD)
1
2
3
4
5
6
5
6
7
8
9
10
1
2
3
4
5
6
NMI
(1)
(2)
(3)
(4)
(5)
(6)
10
11
7
SIGNAL
TYPE (3)
BUFFER TYPE (4)
POWER
SOURCE (5)
RESET STATE
AFTER BOR (6)
I
LVCMOS
DVCC
OFF
–
I
LVCMOS
DVCC
SBWTDIO
I/O
LVCMOS
DVCC
–
TEST (RD)
I
LVCMOS
DVCC
OFF
SBWTCK
I
LVCMOS
DVCC
–
P1.4 (RD)
I/O
LVCMOS
DVCC
OFF
UCA0TXD
O
LVCMOS
DVCC
–
UCA0SIMO
I/O
LVCMOS
DVCC
–
TA1.2
I/O
LVCMOS
DVCC
–
TCK
I
LVCMOS
DVCC
–
A4
I
Analog
DVCC
–
VREF+
O
Power
DVCC
–
P1.5 (RD)
I/O
LVCMOS
DVCC
OFF
UCA0RXD
I
LVCMOS
DVCC
–
UCA0SOMI
I/O
LVCMOS
DVCC
–
TA1.1
I/O
LVCMOS
DVCC
–
TMS
I
LVCMOS
DVCC
–
A5
I
Analog
DVCC
–
P1.6 (RD)
I/O
LVCMOS
DVCC
OFF
UCA0CLK
I/O
LVCMOS
DVCC
–
TA1CLK
I
LVCMOS
DVCC
–
TDI
I
LVCMOS
DVCC
–
TCLK
I
LVCMOS
DVCC
–
A6
I
Analog
DVCC
–
P1.7 (RD)
I/O
LVCMOS
DVCC
OFF
UCA0STE
I/O
LVCMOS
DVCC
–
SMCLK
O
LVCMOS
DVCC
–
TDO
O
LVCMOS
DVCC
–
A7
7
(2)
I
Analog
DVCC
–
P1.0 (RD)
I/O
LVCMOS
DVCC
OFF
UCB0STE
I/O
LVCMOS
DVCC
–
TA0CLK
I
LVCMOS
DVCC
–
A0
I
Analog
DVCC
–
Veref+
I
Power
DVCC
–
Signals names with (RD) denote the reset default pin name.
To determine the pin mux encodings for each pin, see Section 6.11, Input/Output Schematics.
Signal Types: I = Input, O = Output, I/O = Input or Output
Buffer Types: LVCMOS, Analog, or Power (see Table 4-3)
The power source shown in this table is the I/O power source, which may differ from the module power source.
Reset States:
OFF = High-impedance with Schmitt trigger and pullup or pulldown (if available) disabled
N/A = Not applicable
Terminal Configuration and Functions
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SLAS942A – NOVEMBER 2015 – REVISED DECEMBER 2015
Table 4-1. Pin Attributes (continued)
PIN NUMBER
RHB
8
DA
12
RGE
8
SIGNAL
TYPE (3)
BUFFER TYPE (4)
POWER
SOURCE (5)
RESET STATE
AFTER BOR (6)
P1.1 (RD)
I/O
LVCMOS
DVCC
OFF
UCB0CLK
I/O
LVCMOS
DVCC
–
TA0.1
I/O
LVCMOS
DVCC
–
SIGNAL NAME (1)
A1
9
10
13
14
9
10
I
Analog
DVCC
–
P1.2 (RD)
I/O
LVCMOS
DVCC
OFF
UCB0SIMO
I/O
LVCMOS
DVCC
–
UCB0SDA
I/O
LVCMOS
DVCC
–
TA0.2
I/O
LVCMOS
DVCC
–
A2
I
Analog
DVCC
–
Veref-
I
Power
DVCC
–
P1.3 (RD)
I/O
LVCMOS
DVCC
OFF
UCB0SOMI
I/O
LVCMOS
DVCC
–
UCB0SCL
I/O
LVCMOS
DVCC
–
MCLK
O
LVCMOS
DVCC
–
A3
I
Analog
DVCC
–
I/O
LVCMOS
DVCC
OFF
SYNC
I
LVCMOS
DVCC
–
ACLK
I/O
LVCMOS
DVCC
–
P3.0 (RD)
I/O
LVCMOS
DVCC
OFF
CAP0.0
I/O
Analog
VREG
–
CAP0.1
I/O
Analog
VREG
OFF
P2.3 (RD)
I/O
LVCMOS
DVCC
OFF
CAP0.2
I/O
Analog
VREG
–
CAP0.3
I/O
Analog
VREG
OFF
P3.1 (RD)
I/O
LVCMOS
DVCC
OFF
UCA1STE
I/O
LVCMOS
DVCC
–
CAP1.0
I/O
Analog
VREG
–
P2.4 (RD)
I/O
LVCMOS
DVCC
OFF
UCA1CLK
I/O
LVCMOS
DVCC
–
CAP1.1
I/O
Analog
VREG
–
P2.5 (RD)
I/O
LVCMOS
DVCC
OFF
UCA1RXD
I
LVCMOS
DVCC
–
UCA1SOMI
I/O
LVCMOS
DVCC
–
CAP1.2
I/O
Analog
VREG
–
P2.6 (RD)
I/O
LVCMOS
DVCC
OFF
UCA1TXD
O
LVCMOS
DVCC
–
UCA1SIMO
I/O
LVCMOS
DVCC
–
CAP1.3
I/O
Analog
VREG
–
P
Power
VREG
N/A
P2.2 (RD)
11
15
12
16
13
17
11
14
18
12
15
19
13
16
17
18
19
20
21
22
23
14
15
(2)
20
24
16
VREG
21
25
17
CAP2.0
I/O
Analog
VREG
OFF
22
26
18
CAP2.1
I/O
Analog
VREG
OFF
23
27
CAP2.2
I/O
Analog
VREG
OFF
24
28
CAP2.3
I/O
Analog
VREG
OFF
25
29
19
P2.7 (RD)
I/O
LVCMOS
DVCC
OFF
CAP3.0
I/O
Analog
VREG
–
26
30
20
CAP3.1
I/O
Analog
VREG
OFF
Terminal Configuration and Functions
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Table 4-1. Pin Attributes (continued)
PIN NUMBER
12
RHB
DA
27
31
28
32
29
1
RGE
21
SIGNAL
TYPE (3)
BUFFER TYPE (4)
POWER
SOURCE (5)
RESET STATE
AFTER BOR (6)
P3.2 (RD)
I/O
LVCMOS
DVCC
OFF
CAP3.2
I/O
Analog
VREG
–
CAP3.3
I/O
Analog
VREG
OFF
P2.0 (RD)
I/O
LVCMOS
DVCC
OFF
XOUT
O
LVCMOS
DVCC
–
P2.1 (RD)
I/O
LVCMOS
DVCC
OFF
SIGNAL NAME (1)
(2)
30
2
22
XIN
I
LVCMOS
DVCC
–
31
3
23
DVSS
P
Power
DVCC
N/A
32
4
24
DVCC
P
Power
DVCC
N/A
Terminal Configuration and Functions
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4.3
SLAS942A – NOVEMBER 2015 – REVISED DECEMBER 2015
Signal Descriptions
Table 4-2 describes the signals for all device variants and package options.
Table 4-2. Signal Descriptions
ADC
CapTIvate
Clock
Debug
(1)
PIN NUMBER
RHB
DA
RGE
PIN
TYPE (1)
A0
7
11
7
I
Analog input A0
A1
8
12
8
I
Analog input A1
A2
9
13
9
I
Analog input A2
A3
10
14
10
I
Analog input A3
A4
3
7
3
I
Analog input A4
A5
4
8
4
I
Analog input A5
A6
5
9
5
I
Analog input A6
A7
6
10
6
I
Analog input A7
Veref+
7
11
7
I
ADC positive reference
Veref-
9
13
9
I
ADC negative reference
CAP0.0
12
16
CAP0.1
13
17
CAP0.2
14
18
12
CAP0.3
15
19
13
CAP1.0
16
CAP1.1
17
CAP1.2
18
22
CAP1.3
19
CAP2.0
CAP2.1
FUNCTION
SIGNAL NAME
DESCRIPTION
I/O
CapTIvate channel
I/O
CapTIvate channel
I/O
CapTIvate channel
I/O
CapTIvate channel
20
I/O
CapTIvate channel
21
I/O
CapTIvate channel
14
I/O
CapTIvate channel
23
15
I/O
CapTIvate channel
21
25
17
I/O
CapTIvate channel
22
26
18
I/O
CapTIvate channel
CAP2.2
23
27
I/O
CapTIvate channel
CAP2.3
24
28
I/O
CapTIvate channel
CAP3.0
25
29
19
I/O
CapTIvate channel
CAP3.1
26
30
20
I/O
CapTIvate channel
CAP3.2
27
31
I/O
CapTIvate channel
CAP3.3
28
32
I/O
CapTIvate channel
SYNC
11
15
11
I
ACLK
11
15
11
I/O
ACLK output
MCLK
10
14
10
O
MCLK output
SMCLK
6
10
6
O
SMCLK output
XIN
30
2
22
I
Input terminal for crystal oscillator
XOUT
29
1
21
O
Output terminal for crystal oscillator
SBWTCK
2
6
2
I
Spy-Bi-Wire input clock
SBWTDIO
1
5
1
I/O
TCK
3
7
3
I
Test clock
TCLK
5
9
5
I
Test clock input
TDI
5
9
5
I
Test data input
TDO
6
10
6
O
Test data output
TEST
2
6
2
I
Test Mode pin – selected digital I/O on JTAG pins
TMS
4
8
4
I
Test mode select
CapTIvate synchronous trigger input for processing and
conversion
Spy-Bi-Wire data input/output
Pin Types: I = Input, O = Output, I/O = Input or Output, P = Power
Terminal Configuration and Functions
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Table 4-2. Signal Descriptions (continued)
FUNCTION
GPIO
I2C
Power
SPI
System
(2)
14
PIN NUMBER
RHB
DA
RGE
PIN
TYPE (1)
P1.0
7
11
7
I/O
General-purpose I/O
P1.1
8
12
8
I/O
General-purpose I/O
P1.2
9
13
9
I/O
General-purpose I/O
P1.3
10
14
10
I/O
General-purpose I/O
P1.4
3
7
3
I/O
General-purpose I/O (2)
P1.5
4
8
4
I/O
General-purpose I/O (2)
P1.6
5
9
5
I/O
General-purpose I/O (2)
P1.7
6
10
6
I/O
General-purpose I/O (2)
P2.0
29
1
21
I/O
General-purpose I/O
P2.1
30
2
22
I/O
General-purpose I/O
P2.2
11
15
11
I/O
General-purpose I/O
P2.3
14
18
12
I/O
General-purpose I/O
P2.4
17
21
I/O
General-purpose I/O
P2.5
18
22
14
I/O
General-purpose I/O
P2.6
19
23
15
I/O
General-purpose I/O
P2.7
25
29
19
I/O
General-purpose I/O
P3.0
12
16
I/O
General-purpose I/O
P3.1
16
20
I/O
General-purpose I/O
P3.2
27
31
I/O
General-purpose I/O
UCB0SCL
10
14
10
I/O
eUSCI_B0 I2C clock
UCB0SDA
9
13
9
I/O
eUSCI_B0 I2C data
DVCC
32
4
24
P
Power supply
DVSS
31
3
23
P
Power ground
SIGNAL NAME
DESCRIPTION
VREF+
3
7
3
P
Output of positive reference voltage with ground as reference
VREG
20
24
16
O
CapTIvate regulator external decoupling capacitor
UCA0CLK
5
9
5
I/O
eUSCI_A0 SPI clock input/output
UCA0SIMO
3
7
3
I/O
eUSCI_A0 SPI slave in/master out
UCA0SOMI
4
8
4
I/O
eUSCI_A0 SPI slave out/master in
UCA0STE
6
10
6
I/O
eUSCI_A0 SPI slave transmit enable
UCA1CLK
17
21
I/O
eUSCI_A1 SPI clock input/output
UCA1SIMO
19
23
15
I/O
eUSCI_A1 SPI slave in/master out
UCA1SOMI
18
22
14
I/O
eUSCI_A1 SPI slave out/master in
UCA1STE
16
20
I/O
eUSCI_A1 SPI slave transmit enable
UCB0CLK
8
12
8
I/O
eUSCI_B0 clock input/output
UCB0SIMO
9
13
9
I/O
eUSCI_B0 SPI slave in/master out
UCB0SOMI
10
14
10
I/O
eUSCI_B0 SPI slave out/master in
UCB0STE
7
11
7
I/O
eUSCI_B0 slave transmit enable
NMI
1
5
1
I
Nonmaskable interrupt input
RST
1
5
1
I
Active-low reset input
Because this pin is multiplexed with the JTAG function, TI recommends disabling the pin interrupt function while in JTAG debug to
prevent collisions.
Terminal Configuration and Functions
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SLAS942A – NOVEMBER 2015 – REVISED DECEMBER 2015
Table 4-2. Signal Descriptions (continued)
FUNCTION
Timer_A
UART
PIN NUMBER
RHB
DA
RGE
PIN
TYPE (1)
TA0.1
8
12
8
I/O
Timer TA0 CCR1 capture: CCI1A input, compare: Out1
outputs
TA0.2
9
13
9
I/O
Timer TA0 CCR2 capture: CCI2A input, compare: Out2
outputs
TA0CLK
7
11
7
I
TA1.1
4
8
4
I/O
Timer TA1 CCR1 capture: CCI1A input, compare: Out1
outputs
TA1.2
3
7
3
I/O
Timer TA1 CCR2 capture: CCI2A input, compare: Out2
outputs
TA1CLK
5
9
5
I
Timer clock input TACLK for TA1
UCA0RXD
4
8
4
I
eUSCI_A0 UART receive data
UCA0TXD
3
7
3
O
eUSCI_A0 UART transmit data
UCA1RXD
18
22
14
I
eUSCI_A1 UART receive data
UCA1TXD
19
23
15
O
eUSCI_A1 UART transmit data
SIGNAL NAME
DESCRIPTION
Timer clock input TACLK for TA0
Terminal Configuration and Functions
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4.4
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Pin Multiplexing
Pin multiplexing for these MCUs is controlled by both register settings and operating modes (for example,
if the MCU is in test mode). For details of the settings for each pin and schematics of the multiplexed
ports, see Section 6.11.
4.5
Buffer Types
Table 4-3 defines the pin buffer types that are listed in Table 4-1.
Table 4-3. Buffer Types
NOMINAL
VOLTAGE
HYSTERESIS
PU OR PD
NOMINAL
PU OR PD
STRENGTH
(µA)
OUTPUT
DRIVE
STRENGTH
(mA)
LVCMOS
3.0 V
Y (1)
Programmable
See
Section 5.11.4
See
Section 5.11.4
Analog
3.0 V
N
N/A
N/A
N/A
See analog modules in
Section 5 for details.
Power (DVCC)
3.0 V
N
N/A
N/A
N/A
SVS enables hysteresis on
DVCC.
Power (AVCC)
3.0 V
N
N/A
N/A
N/A
BUFFER TYPE
(STANDARD)
(1)
OTHER
CHARACTERISTICS
Only for input pins.
4.6
Connection of Unused Pins
Table 4-4 lists the correct termination of unused pins.
Table 4-4. Connection of Unused Pins (1)
PIN
POTENTIAL
COMMENT
Px.0 to Px.7
Open
Switched to port function, output direction (PxDIR.n = 1)
RST/NMI
DVCC
47-kΩ pullup or internal pullup selected with 10-nF (or 1.1-nF) pulldown (2)
TEST
Open
This pin always has an internal pulldown enabled.
CAP2.x, CAPx.1, CAPx.3
Open
These pins have internal pullup and pulldown resistors, and high impedance is their
default setting.
(1)
(2)
16
Any unused pin with a secondary function that is shared with general-purpose I/O should follow the Px.0 to Px.7 unused pin connection
guidelines.
The pulldown capacitor should not exceed 1.1 nF when using MCUs with Spy-Bi-Wire interface in Spy-Bi-Wire mode with TI tools like
FET interfaces or GANG programmers.
Terminal Configuration and Functions
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SLAS942A – NOVEMBER 2015 – REVISED DECEMBER 2015
5 Specifications
Absolute Maximum Ratings (1)
5.1
over operating free-air temperature range (unless otherwise noted)
Voltage applied at DVCC pin to VSS
Voltage applied to any dedicated CapTIvate pin or pin in CapTIvate mode
Voltage applied to any other pin
(2)
(3)
MIN
MAX
–0.3
4.1
V
–0.3
VREG
V
–0.3
VCC + 0.3
(4.1 V Max)
V
Diode current at any device pin
Maximum junction temperature, TJ
Storage temperature, Tstg (4) (5)
(1)
(2)
(3)
(4)
(5)
–40
UNIT
±2
mA
85
°C
125
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
This applies to dedicated CapTIvate I/Os only or I/Os worked in CapTIvate mode.
All voltages referenced to VSS.
Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
Data retention on FRAM cannot be ensured when exceeding the specified maximum storage temperature, Tstg. Therefore, programming
of devices with user application code should only be performed after soldering.
5.2
ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS‑001
(1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22‑C101 (2)
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as
±2000 V may actually have higher performance.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±500 V
may actually have higher performance.
Recommended Operating Conditions
VCC
Supply voltage applied at DVCC pin (1) (2) (3)
VSS
Supply voltage applied at DVSS pin
TA
Operating free-air temperature
–40
TJ
Operating junction temperature
–40
CDVCC
Recommended capacitor at DVCC (4)
4.7
10
CREG
External buffer capacitor, ESR ≤ 200 mΩ
0.8
1
CELECTRODE
Maximum capacitance of all external electrodes on all
CapTIvate blocks
fSYSTEM
Processor frequency (maximum MCLK frequency) (3) (5)
MIN
fACLK
Maximum ACLK frequency
fSMCLK
Maximum SMCLK frequency
(7)
V
±500
5.3
(1)
(2)
(3)
(4)
(5)
(6)
UNIT
NOM
1.8
MAX
UNIT
3.6
V
85
°C
0
V
85
°C
µF
1.2
µF
300
pF
No FRAM wait states
(NWAITSx = 0)
0
8
With FRAM wait states
(NWAITSx = 1) (6)
0
16 (7)
MHz
40
kHz
16 (7)
MHz
Supply voltage changes faster than 0.2 V/µs can trigger a BOR reset even within the recommended supply voltage range.
Modules may have a different supply voltage range specification. See the specification of the respective module in this data sheet.
The minimum supply voltage is defined by the SVS levels. Refer to the SVS threshold parameters in Table 5-2.
A capacitor tolerance of ±20% or better is required.
Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.
Wait states only occur on actual FRAM accesses (that is, on FRAM cache misses). RAM and peripheral accesses are always executed
without wait states.
If clock sources such as HF crystals or the DCO with frequencies >16 MHz are used, the clock must be divided in the clock system to
comply with this operating condition.
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5.4
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Active Mode Supply Current Into VCC Excluding External Current
(1)
FREQUENCY (fMCLK = fSMCLK)
EXECUTION
MEMORY
PARAMETER
TEST
CONDITION
1 MHz
0 WAIT STATES
(NWAITSx = 0)
TYP
IAM,
FRAM(0%)
IAM,
FRAM(100%)
IAM,
RAM
(1)
(2)
(2)
8 MHz
0 WAIT STATES
(NWAITSx = 0)
MAX
TYP
16 MHz
1 WAIT STATE
(NWAITSx = 1)
MAX
TYP
MAX
3480
FRAM
0% cache hit ratio
3 V, 25°C
504
2772
3047
3 V, 85°C
516
2491
2871
FRAM
100% cache hit
ratio
3 V, 25°C
203
625
1000
3 V, 85°C
212
639
1016
RAM
3 V, 25°C
229
818
1377
UNIT
µA
1215
µA
µA
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current. Characterized with program executing typical data
processing.
fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO at specified frequency
Program and data entirely reside in FRAM. All execution is from FRAM.
Program and data reside entirely in RAM. All execution is from RAM. No access to FRAM.
5.5
Active Mode Supply Current Per MHz
VCC = 3 V, TA = 25°C (unless otherwise noted)
PARAMETER
dIAM,FRAM/df
5.6
TEST CONDITIONS
Active mode current consumption per MHz,
execution from FRAM, no wait states
TYP
UNIT
126
µA/MHz
[IAM (75% cache hit rate) at 8 MHz –
IAM (75% cache hit rate) at 1 MHz) / 7 MHz
Low-Power Mode LPM0 Supply Currents Into VCC Excluding External Current
VCC = 3 V, TA = 25°C (unless otherwise noted) (1) (2)
FREQUENCY (fSMCLK)
PARAMETER
VCC
1 MHz
TYP
ILPM0
(1)
(2)
18
8 MHz
MAX
TYP
16 MHz
MAX
TYP
2V
156
328
420
3V
166
342
433
UNIT
MAX
µA
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
Current for watchdog timer clocked by SMCLK included.
fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK at specified frequency.
Specifications
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5.7
SLAS942A – NOVEMBER 2015 – REVISED DECEMBER 2015
Low-Power Mode LPM3 Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
ILPM3,XT1
Low-power mode 3, 12.5-pF crystal, includes SVS (2) (3) (4)
ILPM3,VLO
Low-power mode 3, VLO, excludes SVS (5)
ILPM3,
Low-power mode 3, RTC, excludes SVS (6)
RTC
VCC
–40°C
TYP
MAX
25°C
(1)
85°C
TYP
MAX
TYP
1.65
3.24
3V
0.98
1.18
2V
0.96
1.16
3V
0.78
0.98
2V
0.76
0.96
3.01
3V
0.93
1.13
3.19
MAX
3.21
1.40
3.04
UNIT
µA
µA
µA
ILPM3,
CapTIvate, 1
proximity,
wake on touch
Low-power mode 3, CapTIvate , excludes SVS (7)
3.3 V
5
µA
Low-power mode 3, CapTIvate , excludes SVS (8)
3.3 V
3.4
µA
Low-power mode 3, CapTIvate, excludes SVS (9)
3.3 V
3.6
µA
Low-power mode 3, CapTIvate, excludes SVS (10)
3.3 V
27.2
µA
Low-power mode 3, CapTIvate, excludes SVS (11)
3.3 V
109.2
µA
ILPM3,
CapTIvate, 1
button, wake
on touch
ILPM3,
CapTIvate, 4
button, wake
on touch
ILPM3,
CapTIvate, 16
button
ILPM3,
CapTIvate, 64
button
ILPM4,
ILPM4
SVS
Low-power mode 4, includes SVS
Low-power mode 4, excludes SVS
3V
0.51
0.65
2.65
2V
0.49
0.64
2.63
3V
0.35
0.49
2.49
2V
0.34
0.48
2.46
µA
µA
(1)
(2)
(3)
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
Not applicable for MCUs with HF crystal oscillator only.
Characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load capacitance are
chosen to closely match the required 12.5-pF load.
(4) Low-power mode 3, 12.5-pF crystal, includes SVS test conditions:
Current for watchdog timer clocked by ACLK and RTC clocked by XT1 included. Current for brownout and SVS included (SVSHE = 1).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3),
fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz
(5) Low-power mode 3, VLO, excludes SVS test conditions:
Current for watchdog timer clocked by VLO included. RTC disabled. Current for brownout included. SVS disabled (SVSHE = 0).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3)
fXT1 = 32768 Hz, fACLK = fMCLK = fSMCLK = 0 MHz
(6) RTC periodically wakes up every second with external 32768-Hz input as source.
(7) CapTIvate technology works in LPM3 with one proximity sensor for wake on touch. CapTIvate BSWP demo panel with 1.5-mm overlay.
Current for brownout included. SVS disabled (SVSHE = 0).
fSCAN = 8 Hz, fCONVER = 2 MHz, COUNTS = 800
(8) CapTIvate technology works in LPM3 with one button, wake on touch. CapTIvate BSWP demo panel with 1.5-mm overlay, Current for
brownout included. SVS disabled (SVSHE = 0).
fSCAN = 8 Hz, fCONVER = 2 MHz, COUNTS = 250
(9) CapTIvate technology works in LPM3 with four self-capacitance buttons, wake on touch. CapTIvate BSWP demo panel with 1.5-mm
overlay. Current for brownout included. SVS disabled (SVSHE = 0).
fSCAN = 8 Hz, fCONVER = 2 MHz, COUNTS = 250
(10) CapTIvate technology works in LPM3 with 16 self-capacitance buttons, process only, CapTIvate BSWP demo panel with 1.5-mm
overlay. Current for brownout included. SVS disabled (SVSHE = 0).
fSCAN = 8 Hz, fCONVER = 2 MHz, COUNTS = 250.
(11) CapTIvate technology works in LPM3 with 64 mutual-capacitance buttons, process only. CapTIvate BSWP demo panel with 1.5-mm
overlay. Current for brownout included. SVS disabled (SVSHE = 0).
fSCAN = 8 Hz, fCONVER = 2 MHz, COUNTS = 250.
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19
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SLAS942A – NOVEMBER 2015 – REVISED DECEMBER 2015
5.8
www.ti.com
Low-Power Mode LPMx.5 Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
ILPM3.5,
XT1
Low-power mode 3.5, 12.5-pF crystal, includes
SVS (1) (2) (3)
(also see Figure 5-2)
ILPM4.5,
SVS
Low-power mode 4.5, includes SVS (4)
ILPM4.5
(1)
(2)
(3)
(4)
(5)
20
Low-power mode 4.5, excludes SVS (5)
VCC
–40°C
TYP
25°C
MAX
85°C
TYP
MAX
TYP
MAX
0.95
0.99
1.42
3V
0.65
0.73
2V
0.63
0.71
3V
0.22
0.24
2V
0.21
0.23
3V
0.012
0.016
2V
0.002
0.007
µA
0.87
0.31
0.30
0.38
0.28
0.055
0.061
0.044
UNIT
0.120
µA
µA
Not applicable for MCUs with HF crystal oscillator only.
Characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load capacitance are
chosen to closely match the required 12.5-pF load.
Low-power mode 3.5, 12.5-pF crystal, includes SVS test conditions:
Current for RTC clocked by XT1 included. Current for brownout and SVS included (SVSHE = 1). Core regulator disabled.
PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),
fXT1 = 32768 Hz, fACLK = 0, fMCLK = fSMCLK = 0 MHz
Low-power mode 4.5, includes SVS test conditions:
Current for brownout and SVS included (SVSHE = 1). Core regulator disabled.
PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5)
fXT1 = 0 Hz, fACLK = fMCLK = fSMCLK = 0 MHz
Low-power mode 4.5, excludes SVS test conditions:
Current for brownout included. SVS disabled (SVSHE = 0). Core regulator disabled.
PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5)
fXT1 = 0 Hz, fACLK = fMCLK = fSMCLK = 0 MHz
Specifications
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5.9
SLAS942A – NOVEMBER 2015 – REVISED DECEMBER 2015
Typical Characteristics - Low-Power Mode Supply Currents
3.0
LPM3.5 Supply Current (µA)
LPM3 Supply Current (µA)
10
9
8
7
6
5
4
3
2
1
0
2.5
2.0
1.5
1.0
0.5
0.0
-40 -30 -20 -10
VCC = 3 V
0
10 20 30 40
Temperature (°C)
LPM3
RTC
50
60
70
80
SVS Disabled
Figure 5-1. LPM3 Supply Current vs Temperature
-40 -30 -20 -10
0
VCC = 3 V
10 20 30 40
Temperature (°C)
LPM3.5
XT1
50
60
70
80
SVS Enabled
Figure 5-2. LPM3.5 Supply Current vs Temperature
LPM4.5 Supply Current (µA)
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
-40 -30 -20 -10
LPM4.5
0
10 20 30 40
Temperature (°C)
VCC = 3 V
50
60
70
80
SVS Enabled
Figure 5-3. LPM4.5 Supply Current vs Temperature
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Specifications
21
MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532
SLAS942A – NOVEMBER 2015 – REVISED DECEMBER 2015
www.ti.com
Table 5-1. Typical Characteristics – Current Consumption Per Module
MODULE
TEST CONDITIONS
Timer_A
REFERENCE CLOCK
MIN
TYP
MAX
UNIT
Module input clock
5
µA/MHz
eUSCI_A
UART mode
Module input clock
7
µA/MHz
eUSCI_A
SPI mode
Module input clock
5
µA/MHz
eUSCI_B
SPI mode
Module input clock
5
µA/MHz
eUSCI_B
I2C mode, 100 kbaud
Module input clock
5
µA/MHz
RTC
CRC
22
From start to end of operation
Specifications
32 kHz
85
nA
MCLK
8.5
µA/MHz
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SLAS942A – NOVEMBER 2015 – REVISED DECEMBER 2015
5.10 Thermal Resistance Characteristics
VALUE
RθJA
RθJC
RθJB
(1)
(2)
Junction-to-ambient thermal resistance, still air (1)
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
(2)
VQFN 32 pin (RHB)
33.5
TSSOP 32 pin (DA)
69.4
VQFN 24 pin (RGE)
32.6
VQFN 32 pin (RHB)
25.7
TSSOP 32 pin (DA)
18.1
VQFN 24 pin (RGE)
32.4
VQFN 32 pin (RHB)
7.6
TSSOP 32 pin (DA)
33.1
VQFN 24 pin (RGE)
10.1
UNIT
ºC/W
ºC/W
ºC/W
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold place test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
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Specifications
23
MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532
SLAS942A – NOVEMBER 2015 – REVISED DECEMBER 2015
www.ti.com
5.11 Timing and Switching Characteristics
5.11.1 Power Supply Sequencing
Table 5-2. PMM, SVS and BOR
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
(1)
TYP
MAX
VBOR, safe
Safe BOR power-down level
tBOR, safe
Safe BOR reset delay (2)
ISVSH,AM
SVSH current consumption, active mode
VCC = 3.6 V
ISVSH,LPM
SVSH current consumption, low-power modes
VCC = 3.6 V
VSVSH-
SVSH power-down level
1.71
1.80
1.86
VSVSH+
SVSH power-up level
1.74
1.89
1.99
VSVSH_hys
SVSH hysteresis
tPD,SVSH, AM
SVSH propagation delay, active mode
tPD,SVSH, LPM
SVSH propagation delay, low-power modes
VREF,
1.2-V REF voltage (3)
(1)
(2)
(3)
1.2V
UNIT
0.1
V
10
ms
1.5
240
nA
80
1.158
1.20
µA
V
V
mV
10
µs
100
µs
1.242
V
A safe BOR can be correctly generated only if DVCC drops below this voltage before it rises.
When an BOR occurs, a safe BOR can be correctly generated only if DVCC is kept low longer than this period before it reaches VSVSH+.
This is a characterized result with external 1-mA load to ground from –40°C to 85°C.
V
Power Cycle Reset
SVS Reset
V SVS+
BOR Reset
V SVS–
V BOR
t BOR
t
Figure 5-4. Power Cycle, SVS, and BOR Reset Conditions
24
Specifications
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SLAS942A – NOVEMBER 2015 – REVISED DECEMBER 2015
5.11.2 Reset Timing
Table 5-3. Wake-Up Times From Low-Power Modes and Reset
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TEST
CONDITIONS
PARAMETER
VCC
MIN
TYP
MAX
UNIT
tWAKE-UP FRAM
Additional wake-up time to activate the FRAM in
AM if previously disabled by the FRAM controller or
from a LPM if immediate activation is selected for
wakeup (1)
tWAKE-UP LPM0
Wake-up time from LPM0 to active mode
(1)
3V
tWAKE-UP LPM3
Wake-up time from LPM3 to active mode
(2)
3V
10
µs
tWAKE-UP LPM4
Wake-up time from LPM4 to active mode
3V
10
µs
tWAKE-UP LPM3.5
Wake-up time from LPM3.5 to active mode
(2)
3V
350
µs
tWAKE-UP LPM4.5
Wake-up time from LPM4.5 to active mode
(2)
tWAKE-UP-RESET
Wake-up time from RST or BOR event to active
mode (2)
3V
tRESET
Pulse duration required at RST/NMI pin to accept a
reset
3V
(1)
(2)
3V
SVSHE = 1
SVSHE = 0
10
µs
200 +
2.5 / fDCO
3V
ns
350
µs
1
ms
1
ms
2
µs
The wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt or wake-up event) to the first
externally observable MCLK clock edge.
The wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt or wake-up event) until the first
instruction of the user program is executed.
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Specifications
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MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532
SLAS942A – NOVEMBER 2015 – REVISED DECEMBER 2015
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5.11.3 Clock Specifications
Table 5-4. XT1 Crystal Oscillator (Low Frequency)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
fXT1, LF
XT1 oscillator crystal, low
frequency
LFXTBYPASS = 0
DCXT1, LF
XT1 oscillator LF duty cycle
Measured at MCLK,
fLFXT = 32768 Hz
fXT1,SW
XT1 oscillator logic-level squarewave input frequency
LFXTBYPASS = 1
DCXT1, SW
LFXT oscillator logic-level squareLFXTBYPASS = 1
wave input duty cycle
OALFXT
Oscillation allowance for
LF crystals (4)
LFXTBYPASS = 0, LFXTDRIVE = {3},
fLFXT = 32768 Hz, CL,eff = 12.5 pF
CL,eff
Integrated effective load
capacitance (5)
See
tSTART,LFXT Start-up time
fFault,LFXT
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
MIN
TYP
(8)
MAX
32768
30%
(2) (3)
Hz
32.768
40%
kHz
60%
(6)
XTS = 0 (9)
UNIT
70%
fOSC = 32768 Hz,
LFXTBYPASS = 0, LFXTDRIVE = {3},
TA = 25°C, CL,eff = 12.5 pF
(7)
Oscillator fault frequency
VCC
200
kΩ
1
pF
1000
ms
0
3500
Hz
To improve EMI on the LFXT oscillator, observe the following guidelines:
• Keep the trace between the device and the crystal as short as possible.
• Design a good ground plane around the oscillator pins.
• Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
• Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
• Use assembly materials and processes that avoid any parasitic load on the oscillator XIN and XOUT pins.
• If conformal coating is used, make sure that it does not induce capacitive or resistive leakage between the oscillator pins.
When LFXTBYPASS is set, LFXT circuits are automatically powered down. Input signal is a digital square wave with parametrics
defined in the Schmitt-trigger inputs section of this data sheet. Duty cycle requirements are defined by DCLFXT, SW.
Maximum frequency of operation of the entire device cannot be exceeded.
Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the
LFXTDRIVE settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following
guidelines, but should be evaluated based on the actual crystal selected for the application:
• For LFXTDRIVE = {0}, CL,eff = 3.7 pF
• For LFXTDRIVE = {1}, 6 pF ≤ CL,eff ≤ 9 pF
• For LFXTDRIVE = {2}, 6 pF ≤ CL,eff ≤ 10 pF
• For LFXTDRIVE = {3}, 6 pF ≤ CL,eff ≤ 12 pF
Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
Includes start-up counter of 1024 clock cycles.
Frequencies above the MAX specification do not set the fault flag. Frequencies between the MIN and MAX specifications might set the
flag. A static condition or stuck at fault condition sets the flag.
Measured with logic-level input frequency but also applies to operation with crystals.
Table 5-5. DCO FLL, Frequency
over recommended operating free-air temperature (unless otherwise noted)
PARAMETER
FLL lock frequency, 16 MHz, 25°C
fDCO,
FLL lock frequency, 16 MHz, –40°C to 85°C
TEST CONDITIONS
Measured at MCLK, Internal
trimmed REFO as reference
VCC
MIN
3V
–1.0%
TYP
1.0%
MAX
3V
–2.0%
2.0%
3V
–0.5%
0.5%
40%
UNIT
FLL
FLL lock frequency, 16 MHz, –40°C to 85°C
Measured at MCLK, XT1
crystal as reference
fDUTY
Duty cycle
3V
Jittercc
Cycle-to-cycle jitter, 16 MHz
3V
0.25%
Jitterlong
Long term jitter, 16 MHz
3V
0.022%
tFLL, lock
FLL lock time
3V
280
ms
tstart-up
DCO start-up time, 2 MHz
3V
16
µs
26
Specifications
Measured at MCLK, XT1
crystal as reference
Measured at MCLK
50%
60%
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SLAS942A – NOVEMBER 2015 – REVISED DECEMBER 2015
Table 5-6. DCO Frequency
over recommended operating free-air temperature (unless otherwise noted) (see Figure 5-5)
PARAMETER
TEST CONDITIONS
VCC
DCORSEL = 101b, DISMOD = 1b, DCOFTRIMEN = 1b,
DCOFTRIM = 000b, DCO = 0
fDCO,
fDCO,
fDCO,
fDCO,
fDCO,
fDCO,
16MHz
12MHz
8MHz
4MHz
2MHz
1MHz
DCO frequency, 16 MHz
DCO frequency, 12 MHz
DCO frequency, 8 MHz
DCO frequency, 4 MHz
DCO frequency, 2 MHz
DCO frequency, 1 MHz
DCORSEL = 101b, DISMOD = 1b, DCOFTRIMEN = 1b,
DCOFTRIM = 000b, DCO = 511
DCORSEL = 101b, DISMOD = 1b, DCOFTRIMEN = 1b,
DCOFTRIM = 111b, DCO = 0
TYP
7.46
12.26
3V
MHz
17.93
DCORSEL = 101b, DISMOD = 1b, DCOFTRIMEN = 1b,
DCOFTRIM = 111b, DCO = 511
29.1
DCORSEL = 100b, DISMOD = 1b, DCOFTRIMEN = 1b,
DCOFTRIM = 000b, DCO = 0
5.75
DCORSEL = 100b, DISMOD = 1b, DCOFTRIMEN = 1b,
DCOFTRIM = 000b, DCO = 511
DCORSEL = 100b, DISMOD = 1b, DCOFTRIMEN = 1b,
DCOFTRIM = 111b, DCO = 0
9.5
3V
MHz
13.85
DCORSEL = 100b, DISMOD = 1b, DCOFTRIMEN = 1b,
DCOFTRIM = 111b, DCO = 511
22.5
DCORSEL = 011b, DISMOD = 1b, DCOFTRIMEN = 1b,
DCOFTRIM = 000b, DCO = 0
3.91
DCORSEL = 011b, DISMOD = 1b, DCOFTRIMEN = 1b,
DCOFTRIM = 000b, DCO = 511
DCORSEL = 011b, DISMOD = 1b, DCOFTRIMEN = 1b,
DCOFTRIM = 111b, DCO = 0
6.49
3V
MHz
9.5
DCORSEL = 011b, DISMOD = 1b, DCOFTRIMEN = 1b,
DCOFTRIM = 111b, DCO = 511
15.6
DCORSEL = 010b, DISMOD = 1b, DCOFTRIMEN = 1b,
DCOFTRIM = 000b, DCO = 0
2.026
DCORSEL = 010b, DISMOD = 1b, DCOFTRIMEN = 1b,
DCOFTRIM = 000b, DCO = 511
DCORSEL = 010b, DISMOD = 1b, DCOFTRIMEN = 1b,
DCOFTRIM = 111b, DCO = 0
3.407
3V
MHz
4.95
DCORSEL = 010b, DISMOD = 1b, DCOFTRIMEN = 1b,
DCOFTRIM = 111b, DCO = 511
8.26
DCORSEL = 001b, DISMOD = 1b, DCOFTRIMEN = 1b,
DCOFTRIM = 000b, DCO = 0
1.0225
DCORSEL = 001b, DISMOD = 1b, DCOFTRIMEN = 1b,
DCOFTRIM = 000b, DCO = 511
DCORSEL = 001b, DISMOD = 1b, DCOFTRIMEN = 1b,
DCOFTRIM = 111b, DCO = 0
1.729
3V
MHz
2.525
DCORSEL = 001b, DISMOD = 1b, DCOFTRIMEN = 1b,
DCOFTRIM = 111b, DCO = 511
4.25
DCORSEL = 000b, DISMOD = 1b, DCOFTRIMEN = 1b,
DCOFTRIM = 000b, DCO = 0
0.5319
DCORSEL = 000b, DISMOD = 1b, DCOFTRIMEN = 1b,
DCOFTRIM = 000b, DCO = 511
DCORSEL = 000b, DISMOD = 1b, DCOFTRIMEN = 1b,
DCOFTRIM = 111b, DCO = 0
UNIT
0.9029
3V
DCORSEL = 000b, DISMOD = 1b, DCOFTRIMEN = 1b,
DCOFTRIM = 111b, DCO = 511
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MHz
1.307
2.21
Specifications
27
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SLAS942A – NOVEMBER 2015 – REVISED DECEMBER 2015
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30
DCOFTRIM = 7
25
Frequency (MHz)
DCOFTRIM = 7
20
DCOFTRIM = 7
15
10
DCOFTRIM = 7
DCOFTRIM = 7
5
DCOFTRIM = 0
DCOFTRIM = 0
DCOFTRIM = 7
DCOFTRIM = 0
DCOFTRIM = 0
0
DCOFTRIM = 0
0
DCO
511
0
DCORSEL
DCOFTRIM = 0
511
0
511
0
1
VCC = 3 V
511
0
2
3
511
0
4
511
0
5
TA = –40°C to 85°C
Figure 5-5. Typical DCO Frequency
Table 5-7. REFO
over recommended operating free-air temperature (unless otherwise noted)
PARAMETER
IREFO
TEST CONDITIONS
VCC
REFO oscillator current consumption
TA = 25°C
REFO calibrated frequency
Measured at MCLK
REFO absolute calibrated tolerance
–40°C to 85°C
dfREFO/dT
REFO frequency temperature drift
Measured at MCLK (1)
dfREFO/
dVCC
REFO frequency supply voltage drift
Measured at MCLK at 25°C (2)
1.8 V to 3.6 V
fDC
REFO duty cycle
Measured at MCLK
1.8 V to 3.6 V
tSTART
REFO start-up time
40% to 60% duty cycle
fREFO
(1)
(2)
MIN
TYP
3V
3V
1.8 V to 3.6 V
MAX
15
µA
32768
–3.5%
3V
40%
UNIT
Hz
+3.5%
0.01
%/°C
1
%/V
50%
60%
50
µs
Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C))
Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)
Table 5-8. Internal Very-Low-Power Low-Frequency Oscillator (VLO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
VCC
TYP
fVLO
VLO frequency
PARAMETER
Measured at MCLK
3V
10
kHz
dfVLO/dT
VLO frequency temperature drift
Measured at MCLK (1)
3V
0.5
%/°C
dfVLO/dVCC
VLO frequency supply voltage drift
Measured at MCLK (2)
1.8 V to 3.6 V
4
%/V
fVLO,DC
Duty cycle
Measured at MCLK
(1)
(2)
TEST CONDITIONS
3V
UNIT
50%
Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C))
Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)
NOTE
The VLO clock frequency is reduced by 15% (typical) when the device switches from active mode to
LPM3 or LPM4, because the reference changes. This lower frequency is not a violation of the VLO
specifications (see Table 5-8).
28
Specifications
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SLAS942A – NOVEMBER 2015 – REVISED DECEMBER 2015
Table 5-9. Module Oscillator (MODOSC)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fMODOSC
MODOSC frequency
fMODOSC/dT
MODOSC frequency temperature drift
fMODOSC/dVCC
MODOSC frequency supply voltage drift
fMODOSC,DC
Duty cycle
VCC
MIN
TYP
MAX
UNIT
3V
3.8
4.8
5.8
MHz
3V
0.102
1.8 V to 3.6 V
1.02
3V
40%
%/℃
%/V
50%
60%
TYP
MAX
5.11.4 Digital I/Os
Table 5-10. Digital Inputs
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
2V
0.90
1.50
3V
1.35
2.25
2V
0.50
1.10
3V
0.75
1.65
2V
0.3
0.8
3V
0.4
1.2
UNIT
VIT+
Positive-going input threshold voltage
VIT–
Negative-going input threshold voltage
Vhys
Input voltage hysteresis (VIT+ – VIT–)
RPull
Pullup or pulldown resistor
For pullup: VIN = VSS
For pulldown: VIN = VCC
CI,dig
Input capacitance, digital only port pins
VIN = VSS or VCC
3
pF
CI,ana
Input capacitance, port pins with shared analog
VIN = VSS or VCC
functions
5
pF
Ilkg(Px.y)
High-impedance leakage current
(1)
(2)
See
(1) (2)
20
2 V, 3 V
35
–20
V
V
V
50
kΩ
20
nA
The leakage current is measured with VSS or VCC applied to the corresponding pins, unless otherwise noted.
The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup or pulldown resistor is
disabled.
Table 5-11. Digital Outputs
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
(1)
2V
1.4
2.0
I(OHmax) = –5 mA (1)
3V
2.4
3.0
I(OLmax) = 3 mA (1)
2V
0.0
0.60
I(OHmax) = 5 mA (1)
3V
0.0
0.60
2V
16
3V
16
I(OHmax) = –3 mA
VOH
High-level output voltage
VOL
Low-level output voltage
fPort_CLK
Clock output frequency
CL = 20 pF (2)
trise,dig
Port output rise time, digital only port pins
CL = 20 pF
tfall,dig
Port output fall time, digital only port pins
CL = 20 pF
(1)
(2)
TYP
MAX
UNIT
V
V
MHz
2V
10
3V
7
2V
10
3V
5
ns
ns
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop
specified.
The port can output frequencies at least up to the specified limit and might support higher frequencies.
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SLAS942A – NOVEMBER 2015 – REVISED DECEMBER 2015
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5.11.4.1 Typical Characteristics – Outputs at 3 V and 2 V
10
Low-Level Output Current (mA)
Low-Level Output Current (mA)
25
20
15
10
5
85°C
0
25°C
0.5
1
1.5
2
2.5
5
85°C
2.5
25°C
–40°C
–40°C
0
-5
0
7.5
0
3
0.25
0.5
Low-Level Output Voltage (V)
DVCC = 3 V
2
Figure 5-7. Typical Low-Level Output Current vs Low-Level
Output Voltage
5
0
85°C
0
25°C
-5
–40°C
85°C
High-Level Output Current (mA)
High-Level Output Current (mA)
1.75
DVCC = 2 V
Figure 5-6. Typical Low-Level Output Current vs Low-Level
Output Voltage
-10
-15
-20
-25
25°C
-2.5
–40°C
-5
-7.5
-10
-30
0
0.5
1
1.5
2
High-Level Output Voltage (V)
2.5
DVCC = 3 V
Specifications
3
0
0.25
0.5
0.75
1
1.25
1.5
High-Level Output Voltage (V)
1.75
2
DVCC = 2 V
Figure 5-8. Typical High-Level Output Current vs High-Level
Output Voltage
30
0.75
1
1.25
1.5
Low-Level Output Voltage (V)
Figure 5-9. Typical High-Level Output Current vs High-Level
Output Voltage
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SLAS942A – NOVEMBER 2015 – REVISED DECEMBER 2015
5.11.5 VREF+ Built-in Reference
Table 5-12. VREF+
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VREF+
Positive built-in reference voltage
TCREF+
Temperature coefficient of built-in
reference voltage
EXTREFEN = 1 with 1-mA load current
VCC
MIN
TYP
MAX
UNIT
2 V, 3 V
1.15
1.19
1.23
V
30
µV/°C
5.11.6 Timer_A
Table 5-13. Timer_A
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
fTA
TEST CONDITIONS
Internal: SMCLK, ACLK
External: TACLK
Duty cycle = 50% ±10%
Timer_A input clock frequency
VCC
MIN
TYP
MAX
UNIT
16
MHz
2 V, 3 V
tTIMR
Timer Clock
Timer
CCR0-1
CCR0
0h
CCR0-1
1h
CCR0
tVALID,PWM
0h
tHD,PWM
TAx.1
Figure 5-10. Timer PWM Mode
Capture
tTIMR
Timer Clock
tSU,CCIA
t,HD,CCIA
TAx.CCIA
Figure 5-11. Timer Capture Mode
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SLAS942A – NOVEMBER 2015 – REVISED DECEMBER 2015
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5.11.7 eUSCI
Table 5-14. eUSCI (UART Mode) Clock Frequency
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
feUSCI
eUSCI input clock frequency
fBITCLK
BITCLK clock frequency
(equals baud rate in Mbaud)
Internal: SMCLK, MODCLK
External: UCLK
Duty cycle = 50% ±10%
VCC
MIN
MAX
UNIT
2 V, 3 V
16
MHz
2 V, 3 V
5
MHz
Table 5-15. eUSCI (UART Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TYP
UCGLITx = 0
tt
UART receive deglitch time
12
UCGLITx = 1
(1)
40
2 V, 3 V
UCGLITx = 2
68
UCGLITx = 3
(1)
UNIT
ns
110
Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are
correctly recognized, their duration should exceed the maximum specification of the deglitch time.
Table 5-16. eUSCI (SPI Master Mode) Clock Frequency
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
feUSCI
TEST CONDITIONS
MIN
MAX
UNIT
8
MHz
Internal: SMCLK, MODCLK
Duty cycle = 50% ±10%
eUSCI input clock frequency
Table 5-17. eUSCI (SPI Master Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
tSTE,LEAD
STE lead time, STE active to clock
tSTE,LAG
STE lag time, last clock to STE inactive
tSU,MI
SOMI input data setup time
tHD,MI
SOMI input data hold time
tVALID,MO
SIMO output data valid time (2)
UCLK edge to SIMO valid,
CL = 20 pF
tHD,MO
SIMO output data hold time (3)
CL = 20 pF
(1)
(2)
(3)
32
VCC
UCSTEM = 0, UCMODEx = 01 or 10
UCSTEM = 1, UCMODEx = 01 or 10
UCSTEM = 0, UCMODEx = 01 or 10
UCSTEM = 1, UCMODEx = 01 or 10
MIN
MAX
UNIT
1
UCxCLK
cycles
1
UCxCLK
cycles
2V
45
3V
35
2V
0
3V
0
ns
ns
2V
20
3V
20
2V
0
3V
0
ns
ns
fUCxCLK = 1/2tLO/HI with tLO/HI = max(tVALID,MO(eUSCI) + tSU,SI(Slave), tSU,MI(eUSCI) + tVALID,SO(Slave)).
For the slave parameters tSU,SI(Slave) and tVALID,SO(Slave), see the SPI parameters of the attached slave.
Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. Refer to the timing
diagrams in Figure 5-12 and Figure 5-13.
Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data
on the SIMO output can become invalid before the output changing clock edge observed on UCLK. Refer to the timing diagrams in
Figure 5-12 and Figure 5-13.
Specifications
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SLAS942A – NOVEMBER 2015 – REVISED DECEMBER 2015
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tSU,MI
tHD,MI
SOMI
tVALID,MO
SIMO
Figure 5-12. SPI Master Mode, CKPH = 0
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tSU,MI
tHD,MI
SOMI
tVALID,MO
SIMO
Figure 5-13. SPI Master Mode, CKPH = 1
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Table 5-18. eUSCI (SPI Slave Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
tSTE,LEAD
STE lead time, STE active to clock
tSTE,LAG
STE lag time, Last clock to STE inactive
tSTE,ACC
STE access time, STE active to SOMI data out
tSTE,DIS
STE disable time, STE inactive to SOMI high
impedance
tSU,SI
SIMO input data setup time
tHD,SI
SIMO input data hold time
tVALID,SO
SOMI output data valid time (2)
tHD,SO
SOMI output data hold time
(1)
(2)
(3)
34
(3)
TEST CONDITIONS
UCLK edge to SOMI valid,
CL = 20 pF
CL = 20 pF
VCC
MIN
2V
55
3V
45
2V
20
3V
20
MAX
ns
ns
2V
65
3V
40
2V
40
3V
35
2V
6
3V
4
2V
12
3V
12
65
40
3V
5
ns
ns
3V
5
ns
ns
2V
2V
UNIT
ns
ns
fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(Master) + tSU,SI(eUSCI), tSU,MI(Master) + tVALID,SO(eUSCI)).
For the master parameters tSU,MI(Master) and tVALID,MO(Master), see the SPI parameters of the attached master.
Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. Refer to the timing
diagrams in Figure 5-14 and Figure 5-15.
Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. Refer to the timing diagrams in
Figure 5-14 and Figure 5-15.
Specifications
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tSTE,LAG
tSTE,LEAD
STE
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tSU,SIMO
tLOW/HIGH
tHD,SIMO
SIMO
tACC
tDIS
tVALID,SOMI
SOMI
Figure 5-14. SPI Slave Mode, CKPH = 0
tSTE,LAG
tSTE,LEAD
STE
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tHD,SI
tSU,SI
SIMO
tACC
tVALID,SO
tDIS
SOMI
Figure 5-15. SPI Slave Mode, CKPH = 1
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Table 5-19. eUSCI (I2C Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-16)
PARAMETER
TEST CONDITIONS
feUSCI
eUSCI input clock frequency
fSCL
SCL clock frequency
VCC
MIN
TYP
Internal: SMCLK, MODCLK
External: UCLK
Duty cycle = 50% ±10%
2 V, 3 V
fSCL = 100 kHz
UNIT
16
MHz
400
kHz
4.0
tHD,STA
Hold time (repeated) START
tSU,STA
Setup time for a repeated START
tHD,DAT
Data hold time
2 V, 3 V
0
ns
tSU,DAT
Data setup time
2 V, 3 V
250
ns
tSU,STO
tSP
fSCL > 100 kHz
fSCL = 100 kHz
fSCL > 100 kHz
fSCL = 100 kHz
Setup time for STOP
fSCL > 100 kHz
Pulse duration of spikes suppressed by
input filter
2 V, 3 V
0
MAX
2 V, 3 V
2 V, 3 V
µs
0.6
4.7
µs
0.6
4.0
µs
0.6
UCGLITx = 0
50
600
UCGLITx = 1
25
300
12.5
150
UCGLITx = 2
2 V, 3 V
UCGLITx = 3
6.3
75
UCCLTOx = 1
tTIMEOUT Clock low time-out
UCCLTOx = 2
27
2 V, 3 V
30
UCCLTOx = 3
tSU,STA
tHD,STA
ns
ms
33
tHD,STA
tBUF
SDA
tLOW
tHIGH
tSP
SCL
tSU,DAT
tSU,STO
tHD,DAT
Figure 5-16. I2C Mode Timing
36
Specifications
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SLAS942A – NOVEMBER 2015 – REVISED DECEMBER 2015
5.11.8 ADC
Table 5-20. ADC, Power Supply and Input Range Conditions
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
DVCC
ADC supply voltage
V(Ax)
Analog input voltage range
All ADC pins
IADC
Operating supply current into DVCC
terminal, reference current not
included, repeat-single-channel
mode
fADCCLK = 5 MHz, ADCON = 1,
REFON = 0, SHT0 = 0, SHT1 = 0,
ADCDIV = 0, ADCCONSEQx = 10b
CI
Input capacitance
Only one terminal Ax can be selected at one
time, from the pad to the ADC capacitor
array, including wiring and pad
RI
Input MUX ON resistance
DVCC = 2 V, 0 V = VAx = DVCC
VCC
MIN
TYP
MAX
UNIT
2.0
3.6
V
0
DVCC
V
2V
185
3V
207
2.2 V
1.6
µA
2.0
pF
2
kΩ
Table 5-21. ADC, 10-Bit Timing Parameters
over operating free-air temperature range (unless otherwise noted)
PARAMETER
VCC
MIN
TYP
MAX
UNIT
For specified performance of ADC linearity
parameters
2 V to
3.6 V
0.45
5
5.5
MHz
Internal ADC oscillator
(MODOSC)
ADCDIV = 0, fADCCLK = fADCOSC
2 V to
3.6 V
4.5
5.0
5.5
MHz
2 V to
3.6 V
2.18
Conversion time
REFON = 0, Internal oscillator,
10 ADCCLK cycles, 10-bit mode,
fADCOSC = 4.5 MHz to 5.5 MHz
External fADCCLK from ACLK or SMCLK,
ADCSSEL ≠ 0
2 V to
3.6 V
fADCCLK
fADCOSC
tCONVERT
TEST CONDITIONS
tADCON
Turnon settling time of the
ADC
The error in a conversion started after tADCON
is less than ±0.5 LSB,
Reference and input signal already settled
tSample
Sampling time
RS = 1000 Ω, RI = 36000 Ω, CI = 3.5 pF,
Approximately 8 Tau (t) are required for an
error of less than ±0.5 LSB
(1)
2.67
µs
See
(1)
100
2V
1.5
3V
2.0
ns
µs
12 × ADCDIV × 1 / fADCCLK
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Table 5-22. ADC, 10-Bit Linearity Parameters
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Integral linearity error (10-bit mode)
EI
Veref+ as reference
Integral linearity error (8-bit mode)
Differential linearity error (10-bit mode)
ED
Veref+ as reference
Differential linearity error (8-bit mode)
Offset error (10-bit mode)
EO
Veref+ as reference
Offset error (8-bit mode)
Gain error (10-bit mode)
EG
Gain error (8-bit mode)
Total unadjusted error (10-bit mode)
ET
Total unadjusted error (8-bit mode)
VSENSOR
See
(1)
TCSENSOR
See
(2)
tSENSOR
(sample)
(1)
(2)
(3)
38
Sample time required if channel 12 is
selected (3)
Veref+ as reference
Internal 1.5-V reference
Veref+ as reference
Internal 1.5-V reference
Veref+ as reference
Internal 1.5-V reference
Veref+ as reference
Internal 1.5-V reference
VCC
MIN
TYP
MAX
2.4 V to
3.6 V
–2
2
2 V to
3.6 V
–2
2
2.4 V to
3.6 V
–1
1
2 V to
3.6 V
–1
1
2.4 V to
3.6 V
–6.5
6.5
2 V to
3.6 V
–6.5
6.5
LSB
LSB
mV
2.4 V to
3.6 V
–2.0
2.0
–3.0%
3.0%
2 V to
3.6 V
–2.0
2.0
–3.0%
3.0%
2.4 V to
3.6 V
–2.0
2.0
–3.0%
3.0%
–2.0
2.0
–3.0%
3.0%
2 V to
3.6 V
UNIT
LSB
LSB
LSB
LSB
ADCON = 1, INCH = 0Ch,
TA = 0°C
3V
913
mV
ADCON = 1, INCH = 0Ch
3V
3.35
mV/°C
ADCON = 1, INCH = 0Ch, Error
of conversion result ≤1 LSB,
AM and all LPMs above LPM3
3V
ADCON = 1, INCH = 0Ch, Error
of conversion result ≤1 LSB,
LPM3
3V
30
µs
100
The temperature sensor offset can vary significantly. TI recommends a single-point calibration to minimize the offset error of the built-in
temperature sensor.
The device descriptor structure contains calibration values for 30°C ±3°C and 85°C ±3°C for each of the available reference voltage
levels. The sensor voltage can be computed as VSENSE = TCSENSOR × (Temperature, °C) + VSENSOR , where TCSENSOR and VSENSOR
can be computed from the calibration values for higher accuracy.
The typical equivalent impedance of the sensor is 700 kΩ. The sample time required includes the sensor on time, tSENSOR(on).
Specifications
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SLAS942A – NOVEMBER 2015 – REVISED DECEMBER 2015
5.11.9 CapTIvate
Table 5-23. CapTIvate Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
1.5
1.55
1.6
UNIT
VREG
Reference voltage output
tWAKEUP,COLD
Voltage regulator wake-up time: LDO completely off then
turned on
1
ms
tWAKEUP,WARM
Voltage regulator wake-up time: LDO in low-power mode
then turned on
300
us
fCAPCLK
Captivate oscillator frequency, nominal
TA = 25ºC, CAPCLK0,
FREQSHFT = 00b
–3%
16
+3%
MHz
fCAPCLK,DC
Duty cycle
Duty cycle (excluding first
clock cycle, DC = thigh × f)
40%
50%
60%
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V
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5.11.10 FRAM
Table 5-24. FRAM
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
tRetention
Data retention duration
IWRITE
Current to write into FRAM
IERASE
Erase current
tWRITE
TJ = 25°C
100
TJ = 70°C
40
TJ = 85°C
10
Write time
Read time
NWAITSx = 1
(1)
(2)
(3)
(4)
40
TYP
MAX
UNIT
cycles
years
IREAD (1)
nA
N/A (2)
nA
(3)
ns
tREAD
NWAITSx = 0
tREAD
MIN
1015
Read and write endurance
1/
fSYSTEM (4)
2/
fSYSTEM
ns
(4)
Writing to FRAM does not require a setup sequence or additional power when compared to reading from FRAM. The FRAM read
current IREAD is included in the active mode current consumption parameter IAM,FRAM.
FRAM does not require a special erase sequence.
Writing into FRAM is as fast as reading.
The maximum read (and write) speed is specified by fSYSTEM using the appropriate wait state settings (NWAITSx).
Specifications
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SLAS942A – NOVEMBER 2015 – REVISED DECEMBER 2015
5.11.11 Debug and Emulation
Table 5-25. JTAG, Spy-Bi-Wire Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-17)
MAX
UNIT
fSBW
Spy-Bi-Wire input frequency
PARAMETER
2 V, 3 V
0
10
MHz
tSBW,Low
Spy-Bi-Wire low clock pulse duration
2 V, 3 V
0.028
15
µs
tSU, SBWTDIO
SBWTDIO setup time (before falling edge of SBWTCK in TMS and
TDI slot, Spy-Bi-Wire)
2 V, 3 V
4
ns
tHD,
SBWTDIO hold time (after rising edge of SBWTCK in TMS and TDI
slot, Spy-Bi-Wire)
2 V, 3 V
19
ns
tValid, SBWTDIO
SBWTDIO data valid time (after falling edge of SBWTCK in TDO
slot, Spy-Bi-Wire)
2 V, 3 V
31
ns
tSBW, En
Spy-Bi-Wire enable time (TEST high to acceptance of first clock
edge) (1)
2 V, 3 V
110
µs
tSBW,Ret
Spy-Bi-Wire return to normal operation time (2)
2 V, 3 V
15
Rinternal
Internal pulldown resistance on TEST
2 V, 3 V
20
(1)
(2)
SBWTDIO
VCC
MIN
TYP
35
100
µs
50
kΩ
Tools that access the Spy-Bi-Wire interface must wait for the tSBW,En time after pulling the TEST/SBWTCK pin high before applying the
first SBWTCK clock edge.
Maximum tSBW,Ret time after pulling or releasing the TEST/SBWTCK pin low until the Spy-Bi-Wire pins revert from their Spy-Bi-Wire
function to their application function. This time applies only if the Spy-Bi-Wire mode is selected.
tSBW,EN
1/fSBW
tSBW,Low
tSBW,High
tSBW,Ret
TEST/SBWTCK
tEN,SBWTDIO
tValid,SBWTDIO
RST/NMI/SBWTDIO
tSU,SBWTDIO
tHD,SBWTDIO
Figure 5-17. JTAG Spy-Bi-Wire Timing
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Table 5-26. JTAG, 4-Wire Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-18)
PARAMETER
VCC
MIN
TYP
MAX
UNIT
10
MHz
fTCK
TCK input frequency (1)
2 V, 3 V
0
tTCK,Low
TCK low clock pulse duration
2 V, 3 V
15
ns
tTCK,High
TCK high clock pulse duration
2 V, 3 V
15
ns
tSU,TMS
TMS setup time (before rising edge of TCK)
2 V, 3 V
11
ns
tHD,TMS
TMS hold time (after rising edge of TCK)
2 V, 3 V
3
ns
tSU,TDI
TDI setup time (before rising edge of TCK)
2 V, 3 V
13
ns
tHD,TDI
TDI hold time (after rising edge of TCK)
2 V, 3 V
5
tZ-Valid,TDO
TDO high impedance to valid output time (after falling edge of TCK)
2 V, 3 V
26
ns
tValid,TDO
TDO to new valid output time (after falling edge of TCK)
2 V, 3 V
26
ns
tValid-Z,TDO
TDO valid to high-impedance output time (after falling edge of TCK)
2 V, 3 V
26
ns
tJTAG,Ret
Spy-Bi-Wire return to normal operation time
100
µs
Rinternal
Internal pulldown resistance on TEST
50
kΩ
(1)
ns
15
2 V, 3 V
20
35
fTCK may be restricted to meet the timing requirements of the module selected.
1/fTCK
tTCK,Low
tTCK,High
TCK
TMS
tSU,TMS
tHD,TMS
TDI
(or TDO as TDI)
tSU,TDI
tHD,TDI
TDO
tZ-Valid,TDO
tValid,TDO
tValid-Z,TDO
tJTAG,Ret
TEST
Figure 5-18. JTAG 4-Wire Timing
42
Specifications
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SLAS942A – NOVEMBER 2015 – REVISED DECEMBER 2015
6 Detailed Description
6.1
Overview
The MSP430FR263x and MSP430FR253x ultra-low-power MCUs are the first FRAM-based MCUs with
integrated high-performance charge-transfer CapTIvate technology in ultra-low-power high-reliability highflexibility MCUs. The MSP430FR263x and MSP430FR253x MCU features up to 16 self-capacitance or 64
mutual-capacitance electrodes, 30-cm proximity sensing, and high accuracy up to 1-fF detection. The
MCUs also include four 16-bit timers, eUSCIs that support UART, SPI, and I2C, a hardware multiplier, an
RTC module with alarm capabilities, and a high-performance 10-bit ADC.
6.2
CPU
The MSP430™ CPU has a 16-bit RISC architecture that is highly transparent to the application. All
operations, other than program-flow instructions, are performed as register operations in conjunction with
seven addressing modes for source operand and four addressing modes for destination operand.
The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-toregister operation execution time is one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as program counter (PC), stack pointer (SP), status register
(SR), and constant generator (CG), respectively. The remaining registers are general-purpose registers.
Peripherals are connected to the CPU using data, address, and control buses. Peripherals can be handled
with all instructions.
6.3
Operating Modes
The MSP430 has one active mode and several software-selectable low-power modes of operation (see
Table 6-1). An interrupt event can wake the MCU from low-power mode LPM0 or LPM3, service the
request, and restore the MCU back to the low-power mode on return from the interrupt program. Lowpower modes LPM3.5 and LPM4.5 disable the core supply to minimize power consumption.
Table 6-1. Operating Modes
MODE
AM
LPM0
LPM3
LPM4
LPM3.5
LPM4.5
ACTIVE
MODE
(FRAM ON)
CPU OFF
STANDBY
OFF
ONLY RTC
SHUTDOWN
16 MHz
16 MHz
40 kHz
0
40 kHz
0
126 µA/MHz
40 µA/MHz
1.7 µA/button
average with
8-Hz scan
0.49 µA
without SVS
0.73 µA with
RTC counter
only in LFXT
16 nA without
SVS
N/A
Instant
10 µs
10 µs
350 µs
350 µs
I/O
Maximum system clock
Power consumption at 25°C, 3 V
Wake-up time
N/A
All
All
I/O
RTC
CapTIvate
I/O
Full
Regulation
Full
Regulation
Partial Power
Down
Partial Power
Down
Partial Power
Down
Power Down
SVS
On
On
Optional
Optional
Optional
Optional
Brownout
On
On
On
On
On
On
Wake-up events
Regulator
Power
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Table 6-1. Operating Modes (continued)
Clock (1)
Core
Peripherals
I/O
(1)
(2)
AM
LPM0
LPM3
LPM4
LPM3.5
LPM4.5
MODE
ACTIVE
MODE
(FRAM ON)
CPU OFF
STANDBY
OFF
ONLY RTC
SHUTDOWN
MCLK
Active
Off
Off
Off
Off
Off
SMCLK
Optional
Optional
Off
Off
Off
Off
FLL
Optional
Optional
Off
Off
Off
Off
DCO
Optional
Optional
Off
Off
Off
Off
MODCLK
Optional
Optional
Off
Off
Off
Off
REFO
Optional
Optional
Optional
Off
Off
Off
ACLK
Optional
Optional
Optional
Off
Off
Off
XT1CLK
Optional
Optional
Optional
Off
Optional
Off
VLOCLK
Optional
Optional
Optional
Off
Optional
Off
CapTIvate MODCLK
Optional
Optional
Optional
Off
Off
Off
CPU
On
Off
Off
Off
Off
Off
FRAM
On
On
Off
Off
Off
Off
RAM
On
On
On
On
Off
Off
Backup memory (2)
On
On
On
On
On
Off
Timer0_A3
Optional
Optional
Optional
Off
Off
Off
Timer1_A3
Optional
Optional
Optional
Off
Off
Off
Timer2_A2
Optional
Optional
Optional
Off
Off
Off
Timer3_A2
Optional
Optional
Optional
Off
Off
Off
WDT
Optional
Optional
Optional
Off
Off
Off
eUSCI_A0
Optional
Optional
Off
Off
Off
Off
eUSCI_A1
Optional
Optional
Off
Off
Off
Off
eUSCI_B0
Optional
Optional
Off
Off
Off
Off
CRC
Optional
Optional
Off
Off
Off
Off
ADC
Optional
Optional
Optional
Off
Off
Off
RTC
Optional
Optional
Optional
Off
Optional
Off
CapTIvate
Optional
Optional
Optional
Off
Off
Off
On
Optional
State Held
State Held
State Held
State Held
General-purpose
digital input/output
The status shown for LPM4 applies to internal clocks only.
Backup memory contains 32 bytes of register space in peripheral memory. See Table 6-24 and Table 6-43 for its memory allocation.
NOTE
XT1CLK and VLOCLK can be active during LPM4 if requested by low-frequency peripherals.
44
Detailed Description
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6.4
SLAS942A – NOVEMBER 2015 – REVISED DECEMBER 2015
Interrupt Vector Addresses
The interrupt vectors and the power-up start address are in the address range 0FFFFh to 0FF80h. The
vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
Table 6-2. Interrupt Sources, Flags, and Vectors
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM
INTERRUPT
WORD
ADDRESS
PRIORITY
System Reset
Power up, Brownout, Supply supervisor
External reset RST
Watchdog time-out, Key violation
FRAM uncorrectable bit error detection
Software POR, BOR
FLL unlock error
SVSHIFG
PMMRSTIFG
WDTIFG
PMMPORIFG, PMMBORIFG
SYSRSTIV
FLLUNLOCKIFG
Reset
FFFEh
63, Highest
System NMI
Vacant memory access
JTAG mailbox
FRAM access time error
FRAM bit error detection
VMAIFG
JMBINIFG, JMBOUTIFG
CBDIFG, UBDIFG
Nonmaskable
FFFCh
62
User NMI
External NMI
Oscillator fault
NMIIFG
OFIFG
Nonmaskable
FFFAh
61
Timer0_A3
TA0CCR0 CCIFG0
Maskable
FFF8h
60
Timer0_A3
TA0CCR1 CCIFG1, TA0CCR2 CCIFG2,
TA0IFG (TA0IV)
Maskable
FFF6h
59
Timer1_A3
TA1CCR0 CCIFG0
Maskable
FFF4h
58
Timer1_A3
TA1CCR1 CCIFG1, TA1CCR2 CCIFG2,
TA1IFG (TA1IV)
Maskable
FFF2h
57
Timer2_A2
TA2CCR0 CCIFG0
Maskable
Timer2_A2
TA2CCR1 CCIFG1, TA2IFG (TA2IV)
Maskable
FFF0h
56
FFEEh
55
FFECh
54
FFEAh
53
Timer3_A2
TA3CCR0 CCIFG0
Timer3_A2
TA3CCR1 CCIFG1, TA3IFG (TA3IV)
RTC
RTCIFG
Maskable
FFE8h
52
Watchdog timer interval mode
WDTIFG
Maskable
FFE6h
51
eUSCI_A0 receive or transmit
UCTXCPTIFG, UCSTTIFG, UCRXIFG,
UCTXIFG (UART mode)
UCRXIFG, UCTXIFG (SPI mode)
(UCA0IV)
Maskable
FFE4h
50
eUSCI_A1 receive or transmit
UCTXCPTIFG, UCSTTIFG, UCRXIFG,
UCTXIFG (UART mode)
UCRXIFG, UCTXIFG (SPI mode)
(UCA1IV)
Maskable
FFE2h
49
eUSCI_B0 receive or transmit
UCB0RXIFG, UCB0TXIFG (SPI mode)
UCALIFG, UCNACKIFG, UCSTTIFG,
UCSTPIFG, UCRXIFG0, UCTXIFG0,
UCRXIFG1, UCTXIFG1, UCRXIFG2,
UCTXIFG2, UCRXIFG3, UCTXIFG3,
UCCNTIFG, UCBIT9IFG (I2C mode)
(UCB0IV)
Maskable
FFE0h
48
ADC
ADCIFG0, ADCINIFG, ADCLOIFG,
ADCHIIFG, ADCTOVIFG, ADCOVIFG
(ADCIV)
Maskable
FFDEh
47
P1
P1IFG.0 to P1IFG.7 (P1IV)
Maskable
FFDCh
46
P2
P2IFG.0 to P2IFG.7 (P2IV)
Maskable
FFDAh
45
CapTIvate
(See CapTivate Design Center for
details )
Maskable
FFD8h
44, Lowest
Reserved
Reserved
Maskable
FFD6h–FF88h
Detailed Description
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Table 6-2. Interrupt Sources, Flags, and Vectors (continued)
INTERRUPT SOURCE
Signatures
6.5
SYSTEM
INTERRUPT
INTERRUPT FLAG
WORD
ADDRESS
BSL Signature 2
0FF86h
BSL Signature 1
0FF84h
JTAG Signature 2
0FF82h
JTAG Signature 1
0FF80h
PRIORITY
Bootloader (BSL)
The BSL lets users program the FRAM or RAM using either the UART serial interface or the I2C interface.
Access to the MCU memory through the BSL is protected by an user-defined password. Use of the BSL
requires four pins (see Table 6-3 and Table 6-4). The BSL entry requires a specific entry sequence on the
RST/NMI/SBWTDIO and TEST/SBWTCK pins. For the complete description of the feature of the BSL, see
the MSP430FR4xx and MSP430FR2xx Bootloader (BSL) User's Guide (SLAU610).
Table 6-3. UART BSL Pin Requirements and Functions
DEVICE SIGNAL
BSL FUNCTION
RST/NMI/SBWTDIO
Entry sequence signal
TEST/SBWTCK
Entry sequence signal
P1.4
Data transmit
P1.5
Data receive
VCC
Power supply
VSS
Ground supply
Table 6-4. I2C BSL Pin Requirements and Functions
46
Detailed Description
DEVICE SIGNAL
BSL FUNCTION
RST/NMI/SBWTDIO
Entry sequence signal
TEST/SBWTCK
Entry sequence signal
P1.2
Data transmit and receive
P1.3
Clock
VCC
Power supply
VSS
Ground supply
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6.6
SLAS942A – NOVEMBER 2015 – REVISED DECEMBER 2015
JTAG Standard Interface
The MSP low-power microcontrollers support the standard JTAG interface, which requires four signals for
sending and receiving data. The JTAG signals are shared with general-purpose I/O. The TEST/SBWTCK
pin enables the JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO is required to interface
with MSP430 development tools and device programmers. Table 6-5 lists the JTAG pin requirements. For
further details on interfacing to development tools and device programmers, see the MSP430 Hardware
Tools User's Guide (SLAU278). For details on using the JTAG interface, see the MSP430 Programming
Via the JTAG Interface User's Guide (SLAU320).
Table 6-5. JTAG Pin Requirements and Function
6.7
DEVICE SIGNAL
DIRECTION
P1.4/UCA0TXD/UCA0SIMO/TA1.2/TCK/A4/VREF+
IN
JTAG FUNCTION
JTAG clock input
P1.5/UCA0RXD/UCA0SOMI/TA1.1/TMS/A5
IN
JTAG state control
P1.6/UCA0CLK/TA1CLK/TDI/TCLK/A6
IN
JTAG data input, TCLK input
P1.7/UCA0STE/SMCLK/TDO/A7
OUT
JTAG data output
TEST/SBWTCK
IN
Enable JTAG pins
RST/NMI/SBWTDIO
IN
External reset
DVCC
Power supply
DVSS
Ground supply
Spy-Bi-Wire Interface (SBW)
The MSP low-power microcontrollers support the 2-wire SBW interface. SBW can be used to interface
with MSP development tools and device programmers. Table 6-6 lists the SBW interface pin requirements.
For further details on interfacing to development tools and device programmers, see the MSP430
Hardware Tools User's Guide (SLAU278). For details on using the SBW interface, see the MSP430
Programming Via the JTAG Interface User's Guide (SLAU320).
Table 6-6. Spy-Bi-Wire Pin Requirements and Functions
DEVICE SIGNAL
6.8
DIRECTION
SBW FUNCTION
TEST/SBWTCK
IN
Spy-Bi-Wire clock input
RST/NMI/SBWTDIO
IN, OUT
Spy-Bi-Wire data input and output
DVCC
Power supply
DVSS
Ground supply
FRAM
The FRAM can be programmed using the JTAG port, SBW, the BSL, or in-system by the CPU. Features
of the FRAM include:
• Byte and word access capability
• Programmable wait state generation
• Error correction coding (ECC)
6.9
Memory Protection
The device features memory protection for user access authority and write protection, including options to:
• Secure the whole memory map to prevent unauthorized access from JTAG port or BSL, by writing
JTAG and BSL signatures using the JTAG port, SBW, the BSL, or in-system by the CPU.
• Enable write protection to prevent unwanted write operation to FRAM contents by setting the control
bits in the System Configuration 0 register. For detailed information, see the SYS chapter in the
MP430FR4xx and MP430FR2xx Family User's Guide (SLAU445).
Detailed Description
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6.10 Peripherals
Peripherals are connected to the CPU through data, address, and control buses. All peripherals can be
handled by using all instructions in the memory map. For complete module description, see the
MP430FR4xx and MP430FR2xx Family User's Guide (SLAU445).
6.10.1 Power-Management Module (PMM)
The PMM includes an integrated voltage regulator that supplies the core voltage to the device. The PMM
also includes supply voltage supervisor (SVS) and brownout protection. The brownout reset circuit (BOR)
is implemented to provide the proper internal reset signal to the device during power on and power off.
The SVS circuitry detects if the supply voltage drops below a user-selectable safe level. SVS circuitry is
available on the primary supply.
The device contains two on-chip reference: 1.5 V for internal reference and 1.2 V for external reference.
The 1.5-V reference is internally connected to ADC channel 13. DVCC is internally connected to ADC
channel 15. When DVCC is set as the reference voltage for ADC conversion, the DVCC can be easily
represent as Equation 1 by using ADC sampling 1.5-V reference without any external components
support.
DVCC = (1023 × 1.5 V) ÷ 1.5-V reference ADC result
(1)
A 1.2-V reference voltage can be buffered and output to P1.4/MCLK/TCK/A4/VREF+, when
EXTREFEN = 1 in the PMMCTL1 register. ADC channel 4 can also be selected to monitor this voltage.
For more detailed information, see the MP430FR4xx and MP430FR2xx Family User's Guide (SLAU445).
6.10.2 Clock System (CS) and Clock Distribution
The clock system includes a 32-kHz crystal oscillator (XT1), an internal very-low-power low-frequency
oscillator (VLO), an integrated 32-kHz RC oscillator (REFO), an integrated internal digitally controlled
oscillator (DCO) that may use frequency-locked loop (FLL) locking with internal or external 32-kHz
reference clock, and an on-chip asynchronous high-speed clock (MODOSC). The clock system is
designed for cost-effective designs with minimal external components. A fail-safe mechanism is included
for XT1. The clock system module offers the following clock signals.
• Main Clock (MCLK): The system clock used by the CPU and all relevant peripherals accessed by the
bus. All clock sources except MODOSC can be selected as the source with a predivider of 1, 2, 4, 8,
16, 32, 64, or 128.
• Sub-Main Clock (SMCLK): The subsystem clock used by the peripheral modules. SMCLK derives from
the MCLK with a predivider of 1, 2, 4, or 8. This means SMCLK is always equal to or less than MCLK.
• Auxiliary Clock (ACLK): This clock is derived from the external XT1 clock or internal REFO clock up to
40 kHz.
48
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SLAS942A – NOVEMBER 2015 – REVISED DECEMBER 2015
All peripherals may have one or several clock sources depending on specific functionality. Table 6-7 lists
the clock distribution used in this device.
Table 6-7. Clock Distribution
CLOCK
SOURCE
SELECT
BITS
Frequency
Range
MCLK
SMCLK
ACLK
MODCLK
XT1CLK
VLOCLK
DC to
16 MHz
DC to
16 MHz
DC to
40 kHz
5 MHz
±10%
DC to
40 kHz
10 kHz
±50%
EXTERNAL PIN
CPU
N/A
Default
FRAM
N/A
Default
RAM
N/A
Default
CRC
N/A
Default
I/O
N/A
Default
TA0
TASSEL
10b
01b
00b (TA0CLK pin)
TA1
TASSEL
10b
01b
00b (TA1CLK pin)
TA2
TASSEL
10b
01b
01b
TA3
TASSEL
10b
eUSCI_A0
UCSSEL
10b or 11b
01b
00b (UCA0CLK pin)
eUSCI_A1
UCSSEL
10b or 11b
01b
00b (UCA1CLK pin)
eUSCI_B0
UCSSEL
10b or 11b
01b
00b (UCB0CLK pin)
WDT
WDTSSEL
00b
01b
ADC
ADCSSEL
11b
01b
CapTIvate
RTC
CAPTSSEL
10b or 11b
00b
00b
CAPCLKSEL
1b
RTCSS
01b
01b
10b
11b
6.10.3 General-Purpose Input/Output Port (I/O)
Up to 19 I/O ports are implemented.
• P1 and P2 are full 8-bit ports; P3 has 3 bits implemented.
• All individual I/O bits are independently programmable.
• Any combination of input, output, and interrupt conditions is possible.
• Programmable pullup or pulldown on all ports.
• Edge-selectable interrupt and LPM3.5 and LPM4.5 wake-up input capability is available for P1 and P2.
• Read and write access to port-control registers is supported by all instructions.
• Ports can be accessed byte-wise or word-wise in pairs.
• CapTIvate functionality is supported on all CAPx.y pins.
NOTE
Configuration of digital I/Os after BOR reset
To prevent any cross currents during start-up of the device, all port pins are high-impedance
with Schmitt triggers and module functions disabled. To enable the I/O functions after a BOR
reset, the ports must be configured first and then the LOCKLPM5 bit must be cleared. For
details, see the Configuration After Reset section in the Digital I/O chapter of the
MP430FR4xx and MP430FR2xx Family User's Guide (SLAU445)
Detailed Description
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6.10.4 Watchdog Timer (WDT)
The primary function of the WDT module is to perform a controlled system restart after a software problem
occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not
needed in an application, the module can be configured as interval timer and can generate interrupts at
selected time intervals. Table 6-8 lists the system clocks that can be used to source the WDT.
Table 6-8. WDT Clocks
50
Detailed Description
WDTSSEL
NORMAL OPERATION
(WATCHDOG AND INTERVAL TIMER MODE)
00
SMCLK
01
ACLK
10
VLOCLK
11
Reserved
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SLAS942A – NOVEMBER 2015 – REVISED DECEMBER 2015
6.10.5 System (SYS) Module
The SYS module handles many of the system functions within the device. These features include poweron reset (POR) and power-up clear (PUC) handling, NMI source selection and management, reset
interrupt vector generators, bootloader entry mechanisms, and configuration management (device
descriptors). The SYS module also includes a data exchange mechanism through SBW called a JTAG
mailbox mail box that can be used in the application. Table 6-9 summarizes the interrupts that are
managed by the SYS module.
Table 6-9. System Module Interrupt Vector Registers
INTERRUPT VECTOR
REGISTER
SYSRSTIV, System Reset
SYSSNIV, System NMI
SYSUNIV, User NMI
ADDRESS
015Eh
015Ch
015Ah
INTERRUPT EVENT
VALUE
No interrupt pending
00h
Brownout (BOR)
02h
RSTIFG RST/NMI (BOR)
04h
PMMSWBOR software BOR (BOR)
06h
LPMx.5 wake up (BOR)
08h
Security violation (BOR)
0Ah
Reserved
0Ch
SVSHIFG SVSH event (BOR)
0Eh
Reserved
10h
Reserved
12h
PMMSWPOR software POR (POR)
14h
WDTIFG watchdog time-out (PUC)
16h
WDTPW password violation (PUC)
18h
FRCTLPW password violation (PUC)
1Ah
Uncorrectable FRAM bit error detection
1Ch
Peripheral area fetch (PUC)
1Eh
PMMPW PMM password violation (PUC)
20h
FLL unlock (PUC)
24h
Reserved
22h, 26h to 3Eh
No interrupt pending
00h
SVS low-power reset entry
02h
Uncorrectable FRAM bit error detection
04h
Reserved
06h
Reserved
08h
Reserved
0Ah
Reserved
0Ch
Reserved
0Eh
Reserved
10h
VMAIFG Vacant memory access
12h
JMBINIFG JTAG mailbox input
14h
JMBOUTIFG JTAG mailbox output
16h
Correctable FRAM bit error detection
18h
Reserved
1Ah to 1Eh
No interrupt pending
00h
NMIIFG NMI pin or SVSH event
02h
OFIFG oscillator fault
04h
Reserved
06h to 1Eh
PRIORITY
Highest
Lowest
Highest
Lowest
Highest
Lowest
Detailed Description
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6.10.6 Cyclic Redundancy Check (CRC)
The 16-bit cyclic redundancy check (CRC) module produces a signature based on a sequence of data
values and can be used for data checking purposes. The CRC generation polynomial is compliant with
CRC-16-CCITT standard of x16 + x12 + x5 + 1.
6.10.7 Enhanced Universal Serial Communication Interface (eUSCI_A0, eUSCI_B0)
The eUSCI modules are used for serial data communications. The eUSCI_A module supports either
UART or SPI communications. The eUSCI_B module supports either SPI or I2C communications.
Additionally, eUSCI_A supports automatic baud-rate detection and IrDA. Table 6-10 lists the pin
configurations that are required for each eUSCI mode.
Table 6-10. eUSCI Pin Configurations
eUSCI_A0
eUSCI_A1
eUSCI_B0
52
Detailed Description
PIN
UART
SPI
P1.4
TXD
SIMO
P1.5
RXD
SOMI
P1.6
–
SCLK
P1.7
–
STE
P2.6
TXD
SIMO
P2.5
RXD
SOMI
P2.4
–
SCLK
P3.1
–
STE
PIN
2
I C
SPI
P1.0
–
STE
P1.1
–
SCLK
P1.2
SDA
SIMO
P1.3
SCL
SOMI
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6.10.8 Timers (Timer0_A3, Timer1_A3, Timer2_A2 and Timer3_A2)
The Timer0_A3 and Timer1_A3 modules are 16-bit timers and counters with three capture/compare
registers each. Each timer supports multiple captures or compares, PWM outputs, and interval timing (see
Table 6-11 and Table 6-12). Each timer has extensive interrupt capabilities. Interrupts may be generated
from the counter on overflow conditions and from each of the capture/compare registers. The CCR0
registers on both Timer0_A3 and Timer1_A3 are not externally connected and can only be used for
hardware period timing and interrupt generation. In Up mode, they can be used to set the overflow value
of the counter.
Table 6-11. Timer0_A3 Signal Connections
PORT PIN
DEVICE INPUT
SIGNAL
MODULE INPUT
NAME
P1.0
TA0CLK
TACLK
ACLK (internal)
ACLK
SMCLK (internal)
SMCLK
MODULE BLOCK
MODULE OUTPUT
SIGNAL
DEVICE OUTPUT
SIGNAL
Timer
N/A
CCR0
TA0
Timer1_A3 CCI0B
input
CCI0A
CCI0B
P1.1
P1.2
DVSS
GND
DVCC
VCC
TA0.1
CCI1A
TA0.1
from RTC (internal)
CCI1B
TA1
Timer1_A3 CCI1B
input
DVSS
GND
TA2
CCR1
DVCC
VCC
TA0.2
CCI2A
TA0.2
CCI2B
Timer1_A3 CCI2B
input,
IR Input
DVSS
GND
DVCC
VCC
CCR2
Detailed Description
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Table 6-12. Timer1_A3 Signal Connections
PORT PIN
DEVICE INPUT
SIGNAL
MODULE INPUT
NAME
P1.6
TA1CLK
TACLK
ACLK (internal)
ACLK
SMCLK (internal)
SMCLK
MODULE BLOCK
MODULE OUTPUT
SIGNAL
Timer
N/A
CCR0
TA0
DEVICE OUTPUT
SIGNAL
CCI0A
Timer0_A3 CCR0B
output (internal)
CCI0B
DVSS
GND
DVCC
VCC
TA1.1
CCI1A
Timer0_A3 CCR1B
output (internal)
CCI1B
DVSS
GND
P1.5
DVCC
VCC
TA1.2
CCI2A
Timer0_A3 CCR2B
output (internal)
CCI2B
DVSS
GND
DVCC
VCC
P1.4
TA1.1
CCR1
to ADC trigger
TA1
TA1.2
CCR2
IR Input
TA2
The interconnection of Timer0_A3 and Timer1_A3 can be used to modulate the eUSCI_A pin of
UCA0TXD/UCA0SIMO in either ASK or FSK mode, with which a user can easily acquire a modulated
infrared command for directly driving an external IR diode. The IR functions are fully controlled by SYS
configuration registers 1 including IREN (enable), IRPSEL (polarity select), IRMSEL (mode select),
IRDSEL (data select), and IRDATA (data) bits. For more information, see the SYS chapter in the
MP430FR4xx and MP430FR2xx Family User's Guide (SLAU445).
The Timer2_A2 and Timer3_A2 modules are 16-bit timers and counters with two capture/compare
registers each. Each timer supports multiple captures or compares and interval timing (see Table 6-13 and
Table 6-14). Each timer has extensive interrupt capabilities. Interrupts may be generated from the counter
on overflow conditions and from each of the capture registers. The CCR0 registers on both Timer2_TA2
and Timer3_TA2 are not externally connected and can only be used for hardware period timing and
interrupt generation. In Up mode, they can be used to set the overflow value of the counter. The
Timer2_A2 and Timer3_A2 are only internal connected and do not support PWM output.
Table 6-13. Timer2_A2 Signal Connections
DEVICE INPUT SIGNAL
MODULE INPUT NAME
ACLK (internal)
ACLK
SMCLK (internal)
SMCLK
MODULE BLOCK
MODULE OUTPUT
SIGNAL
Timer
N/A
CCR0
TA0
CCR1
CCR1
DEVICE OUTPUT SIGNAL
CCI0A
CCI0B
DVSS
GND
DVCC
Timer3_A3 CCI0B input
VCC
CCI1A
CCI1B
54
DVSS
GND
DVCC
VCC
Detailed Description
Timer3_A3 CCI1B input
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SLAS942A – NOVEMBER 2015 – REVISED DECEMBER 2015
Table 6-14. Timer3_A2 Signal Connections
DEVICE INPUT SIGNAL
MODULE INPUT NAME
ACLK (internal)
ACLK
SMCLK (internal)
SMCLK
MODULE BLOCK
MODULE OUTPUT
SIGNAL
Timer
N/A
CCR0
TA0
CCR1
CCR1
DEVICE OUTPUT SIGNAL
CCI0A
Timer3_A3 CCI0B input
CCI0B
DVSS
GND
DVCC
VCC
CCI1A
Timer3_A3 CCI1B input
CCI1B
DVSS
GND
DVCC
VCC
6.10.9 Hardware Multiplier (MPY)
The multiplication operation is supported by a dedicated peripheral module. The module performs
operations with 32-, 24-, 16-, and 8-bit operands. The MPY module supports signed multiplication,
unsigned multiplication, signed multiply-and-accumulate, and unsigned multiply-and-accumulate
operations.
6.10.10 Backup Memory (BKMEM)
The BKMEM supports data retention during LPM3.5. This device provides up to 32 bytes that are retained
during LPM3.5.
6.10.11 Real-Time Clock (RTC)
The RTC is a 16-bit modulo counter that is functional in AM, LPM0, LPM3, and LPM3.5. This module may
periodically wake up the CPU from LPM0, LPM3 and LPM3.5 based on timing from a low-power clock
source such as the XT1 and VLO clocks. In AM, RTC can be driven by SMCLK to generate highfrequency timing events and interrupts. The RTC overflow events trigger:
• Timer0_A3 CCR1B
• ADC conversion trigger when ADCSHSx bits are set as 01b
Detailed Description
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6.10.12 10-Bit Analog-to-Digital Converter (ADC)
The 10-bit ADC module supports fast 10-bit analog-to-digital conversions with single-ended input. The
module implements a 10-bit SAR core, sample select control, reference generator and a conversion result
buffer. A window comparator with lower and upper limits allows CPU-independent result monitoring with
three window comparator interrupt flags.
The ADC supports 10 external inputs and 4 internal inputs (see Table 6-15).
Table 6-15. ADC Channel Connections
ADCSHSx
ADC CHANNELS
EXTERNAL PINOUT
0
A0/Veref+
P1.0
1
A1
P1.1
2
A2/Veref-
P1.2
3
A3
P1.3
4
(1)
A4
(1)
P1.4
5
A5
P1.5
6
A6
P1.6
7
A7
P1.7
8
A8
NA
9
A9
NA
10
Not used
N/A
11
Not used
N/A
12
On-chip temperature sensor
N/A
13
Reference voltage (1.5 V)
N/A
14
DVSS
N/A
15
DVCC
N/A
When A4 is used, the PMM 1.2-V reference voltage can be output to this pin by setting the PMM
control register. The 1.2-V voltage can be directly measured by A4 channel.
The analog-to-digital conversion can be started by software or a hardware trigger. Table 6-16 lists the
trigger sources that are available.
Table 6-16. ADC Trigger Signal Connections
ADCINCHx
56
Detailed Description
TRIGGER SOURCE
BINARY
DECIMAL
00
0
ADCSC bit (software trigger)
01
1
RTC event
10
2
TA1.1B
11
3
TA1.2B
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6.10.13 CapTIvate
The CapTIvate module detects the capacitance changed with a charge-transfer method and is functional
in AM, LPM0, and LPM3. The CapTIvate module can periodically wake the CPU from LPM0 or LPM3
based on a timer source such as the ACLK and VLO clocks. The CapTIvate module supports the following
touch-sensing capability:
• Up to 64 CapTIvate sense channels composed of 4 CapTIvate blocks. Each block consists of 4 I/Os,
and these blocks scan in parallel of 4 electrodes.
• Each block can be individually configured in self or mutual mode. Each CapTIvate I/O can be used for
either self or mutual electrodes.
• Supports a wake-on-touch state machine.
• Supports synchronized conversion on a zero-crossing event trigger.
• Processing logic to perform filter calculation and threshold detection.
6.10.14 Embedded Emulation Module (EEM)
The EEM supports real-time in-system debugging. The EEM on these devices has the following features:
• Three hardware triggers or breakpoints on memory access
• One hardware trigger or breakpoint on CPU register write access
• Up to four hardware triggers can be combined to form complex triggers or breakpoints
• One cycle counter
• Clock control on module level
• EEM version: S
Detailed Description
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6.11 Input/Output Schematics
6.11.1 Port P1 Input/Output With Schmitt Trigger
Figure 6-1 shows the port schematic. Table 6-17 summarizes the selection of pin function.
A0..A7
From SYS (ADCPCTLx)
P1REN.x
P1DIR.x
From Module1
00
01
10
11
2 bit
DVSS
0
DVCC
1
00
01
10
11
P1OUT.x
From Module1
From Module2
DVSS
2 bit
P1SEL.x
EN
D
To module
P1IN.x
P1IE.x
P1 Interrupt
Q
D
S
P1IFG.x
Edge
Select
P1IES.x
From JTAG
Bus
Keeper
P1.0/UCB0STE/TA0CLK/A0/Veref+
P1.1/UCB0CLK/TA0.1/A1
P1.2/UCB0SIMO/UCB0SDA/TA0.2/A2/VerefP1.3/UCB0SOMI/UCB0SCL/MCLK/A3
P1.4/UCA0TXD/UCA0SIMO/TA1.2/TCK/A4/VREF+
P1.5/UCA0RXD/UCA0SOMI/TA1.1/TMS/A5
P1.6/UCA0CLK/TA1CLK/TDI/TCLK/A6
P1.7/UCA0STE/SMCLK/TDO/A7
To JTAG
Figure 6-1. Port P1 (P1.0 to P1.7) Input/Output With Schmitt Trigger
58
Detailed Description
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SLAS942A – NOVEMBER 2015 – REVISED DECEMBER 2015
Table 6-17. Port P1 (P1.0 to P1.7) Pin Functions
PIN NAME (P1.x)
x
P1.0/UCB0STE/
TA0CLK/A0
0
P1.1/UCB0CLK/TA0.1/
A1
1
FUNCTION
P1DIR.x
P1SELx
ADCPCTLx (2)
JTAG
P1.0 (I/O)
I: 0; O: 1
00
0
N/A
UCB0STE
X
01
0
N/A
TA0CLK
0
10
0
N/A
A0/Veref+
X
X
1 (x = 0)
N/A
P1.1 (I/O)
I: 0; O: 1
00
0
N/A
UCB0CLK
X
01
0
N/A
TA0.CCI1A
0
TA0.1
1
10
0
N/A
A1
X
X
1 (x = 1)
N/A
I: 0; O: 1
00
0
N/A
UCB0SIMO/UCB0SDA
X
01
0
N/A
TA0.CCI2A
0
TA0.2
1
10
0
N/A
P1.2 (I/O)
P1.2/UCB0SIMO/
UCB0SDA/TA0.2/A2
2
P1.3/UCB0SOMI/
UCB0SCL/MCLK/A3
3
A2/Veref-
X
X
1 (x = 2)
N/A
P1.3 (I/O)
I: 0; O: 1
00
0
N/A
UCB0SOMI/UCB0SCL
X
01
0
N/A
MCLK
1
10
0
N/A
A3
X
X
1 (x = 3)
N/A
P1.4 (I/O)
P1.4/UCA0TXD/
UCA0SIMO/TA1.2/TCK/
A4 /VREF+
P1.5/UCA0RXD/
UCA0SOMI/TA1.1/TMS/
A5
P1.6/UCA0CLK/
TA1CLK/TDI/TCLK/A6
5
6
P1.7/UCA0STE/SMCLK/
TDO/A7
(1)
(2)
4
7
CONTROL BITS AND SIGNALS (1)
I: 0; O: 1
00
0
Disabled
UCA0TXD/UCA0SIMO
X
01
0
Disabled
TA1.CCI2A
0
TA1.2
1
10
0
Disabled
A4, VREF+
X
X
1 (x = 4)
Disabled
JTAG TCK
X
X
X
TCK
P1.5 (I/O)
I: 0; O: 1
00
0
Disabled
UCA0RXD/UCA0SOMI
X
01
0
Disabled
TA1.CCI1A
0
TA1.1
1
10
0
Disabled
A5
X
X
1 (x = 5)
Disabled
JTAG TMS
X
X
X
TMS
P1.6 (I/O)
I: 0; O: 1
00
0
Disabled
UCA0CLK
X
01
TA1CLK
0
10
0
A6
X
X
1 (x = 6)
Disabled
JTAG TDI/TCLK
X
X
X
TDI/TCLK
P1.7 (I/O)
I: 0; O: 1
00
0
Disabled
UCA0STE
X
01
0
Disabled
SMCLK
1
10
0
Disabled
A7
X
X
1 (x = 7)
Disabled
JTAG TDO
X
X
X
TDO
Disabled
Disabled
X = don't care
Setting the ADCPCTLx bit in SYSCFG2 register disables both the output driver and input Schmitt trigger to prevent leakage when
analog signals are applied.
Detailed Description
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6.11.2 Port P2 (P2.0 to P2.2) Input/Output With Schmitt Trigger
Figure 6-2 shows the port schematic. Table 6-18 summarizes the selection of pin function.
P2REN.x
P2DIR.x
00
01
10
11
2 bit
DVSS
0
DVCC
1
00
01
10
11
P2OUT.x
From Module1
DVSS
DVSS
2 bit
P2SEL.x
EN
D
To module
P2IN.x
P2IE.x
P2 Interrupt
Q
D
S
P2IFG.x
Bus
Keeper
P2.0/XOUT
P2.1/XIN
P2.2/SYNC/ACLK
Edge
Select
P2IES.x
Figure 6-2. Port P2 (P2.0 to P2.2) Input/Output With Schmitt Trigger
Table 6-18. Port P2 (P2.0 to P2.2) Pin Functions
PIN NAME (P2.x)
x
P2.0/XOUT
0
P2.1/XIN
1
P2.2/SYNC/ACLK
2
FUNCTION
P2.0 (I/O)
XOUT
P2.1 (I/O)
XIN
P2.2 (I/O)
(1)
60
CONTROL BITS AND SIGNALS (1)
P2DIR.x
P2SELx
I: 0; O: 1
00
1
01
I: 0; O: 1
00
0
01
I: 0; O: 1
00
SYNC
0
01
ACLK
1
10
X = don't care
Detailed Description
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SLAS942A – NOVEMBER 2015 – REVISED DECEMBER 2015
6.11.3 Port P2 (P2.3 to P2.7) Input/Output With Schmitt Trigger
Figure 6-3 shows the port schematic. Table 6-19 summarizes the selection of pin function.
CAP0.2, CAP1.1, CAP1.2
CAP1.3, CAP3.0
From CapTIvate
P2REN.x
P2DIR.x
From Module1
00
01
10
11
2 bit
DVSS
0
DVCC
1
00
01
10
11
P2OUT.x
From Module1
DVSS
DVSS
2 bit
P2SEL.x
EN
D
To module
P2IN.x
P2IE.x
P2 Interrupt
Q
D
S
P2IFG.x
Edge
Select
P2IES.x
Bus
Keeper
P2.3/CAP0.2
P2.4/UCA1CLK/CAP1.1
P2.5/UCA1RXD/UCA1SOMI/CAP1.2
P2.6/UCA1TXD/UCA1SIMO/CAP1.3
P2.7/CAP3.0
Figure 6-3. Port P2 (P2.3 to P2.7) Input/Output With Schmitt Trigger
Detailed Description
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Table 6-19. Port P2 (P2.3 to P2.7) Pin Functions
CONTROL BITS AND SIGNALS (1)
PIN NAME (P2.x)
P2.3/CAP0.2
P2.4/UCA1CLK/
CAP1.1
x
3
FUNCTION
P2.3 (I/O)
CAP0.2
4
P2.7/CAP3.0
(1)
62
6
7
I: 0; O: 1
00
0
X
X
1
00
0
UCA1CLK
X
01
0
X
X
1
I: 0; O: 1
00
0
UCA1RXD/UCA1SOMI
X
01
0
CAP1.2
X
X
1
P2.6 (I/O)
P2.6/UCA1TXD/
UCA1SIMO/CAP1.3
ANALOG
FUNCTION
I: 0; O: 1
P2.5 (I/O)
5
P2SELx
P2.4 (I/O)
CAP1.1
P2.5/UCA1RXD/
UCA1SOMI/CAP1.2
P2DIR.x
I: 0; O: 1
00
0
UCA1TXD/UCA1SIMO
X
01
0
CAP1.3
X
X
1
I: 0; O: 1
0
0
X
X
1
P2.7 (I/O)
CAP3.0
X = don't care
Detailed Description
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SLAS942A – NOVEMBER 2015 – REVISED DECEMBER 2015
6.11.4 Port P3 (P3.0 to P3.2) Input/Output With Schmitt Trigger
Figure 6-4 shows the port schematic. Table 6-20 summarizes the selection of pin function.
CAP0.0, CAP1.0, CAP3.2
From CapTIvate
P3REN.x
P3DIR.x
From Module1
00
01
10
11
2 bit
DVSS
0
DVCC
1
00
01
10
11
P3OUT.x
From Module1
DVSS
DVSS
2 bit
P3SEL.x
EN
D
To module
P3IN.x
Bus
Keeper
P3.0/CAP0.0
P3.1/UCA1STE/CAP1.0
P3.2/CAP3.2
Figure 6-4. Port P3 (P3.0 to P3.2) Input/Output With Schmitt Trigger
NOTE
CapTIvate shared with I/Os configuration
The CapTIvate function and GPIOs are powered by different power supplies (1.5 V and
3.3 V, respectively).
To prevent pad damage when changing the function, TI recommends checking the external
application circuit of each pad before enabling the alternate function.
Detailed Description
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Table 6-20. Port P3 (P3.0 to P3.2) Pin Functions
CONTROL BITS AND SIGNALS (1)
PIN NAME (P3.x)
P3.0/CAP0.0
P3.1/UCA1STE/
CAP1.0
x
0
1
FUNCTION
P3.0 (I/O)
CAP0.0
(1)
64
2
P3SEL.x
ANALOG
FUNCTION
I: 0; O: 1
00
0
X
X
1
P3.1 (I/O)
I: 0; O: 1
00
0
UCA1STE
X
01
0
CAP1.0
P3.2/CAP3.2
P3DIR.x
P3.2 (I/O)
CAP3.2
X
X
1
I: 0; O: 1
00
0
X
X
1
X = don't care
Detailed Description
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SLAS942A – NOVEMBER 2015 – REVISED DECEMBER 2015
6.12 Device Descriptors
Table 6-21 lists the Device IDs of the devices. Table 6-22 lists the contents of the device descriptor taglength-value (TLV) structure for the devices.
Table 6-21. Device IDs
DEVICE ID
DEVICE
1A05h
1A04h
MSP430FR2633
82h
3Ch
MSP430FR2533
82h
3Dh
MSP430FR2632
82h
3Eh
MSP430FR2532
82h
3Fh
Table 6-22. Device Descriptors
DESCRIPTION
ADDRESS
VALUE
Info length
1A00h
06h
CRC length
1A01h
06h
1A02h
per unit
1A03h
per unit
CRC value (1)
Information Block
Device ID
1A05h
See Table 6-21
1A06h
per unit
Firmware revision
1A07h
per unit
Die record tag
1A08h
08h
Lot wafer ID
Die Record
Die X position
Die Y position
Test result
1A09h
0Ah
1A0Ah
per unit
1A0Bh
per unit
1A0Ch
per unit
1A0Dh
per unit
1A0Eh
per unit
1A0Fh
per unit
1A10h
per unit
1A11h
per unit
1A12h
per unit
1A13h
per unit
ADC calibration tag
1A14h
per unit
ADC calibration length
1A15h
per unit
1A16h
per unit
1A17h
per unit
1A18h
per unit
ADC gain factor
ADC offset
ADC 1.5-V reference temperature 30°C
ADC 1.5-V reference temperature 85°C
(1)
1A04h
Hardware revision
Die record length
ADC Calibration
MSP430FR2633, MSP430FR2632,
MSP430FR2533, MSP430FR2532
1A19h
per unit
1A1Ah
per unit
1A1Bh
per unit
1A1Ch
per unit
1A1Dh
per unit
The CRC value covers the check sum from 0x1A04h to 0x1AEFh by applying the CRC-CCITT-16 polynomial of x16 + x12 + x5 + 1.
Detailed Description
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Table 6-22. Device Descriptors (continued)
MSP430FR2633, MSP430FR2632,
MSP430FR2533, MSP430FR2532
DESCRIPTION
ADDRESS
VALUE
Calibration tag
1A1Eh
12h
Calibration length
1A1Fh
04h
1A20h
per unit
1A21h
per unit
1A22h
per unit
1A23h
per unit
Reference and DCO Calibration 1.5-V reference factor
DCO tap setting for 16 MHz, temperature 30°C (2)
(2)
This value can be directly loaded into DCO bits in CSCTL0 registers to get accurate 16-MHz frequency at room temperature, especially
when the MCU exits from LPM3 and below. TI suggests using the predivider to decrease the frequency if the temperature drift might
result an overshoot beyond 16 MHz.
6.13 Memory
6.13.1 Memory Organization
Table 6-23 summarizes the memory organization of the devices.
Table 6-23. Memory Organization
ACCESS
MSP430FR2633
MSP430FR2632
MSP430FR2533
MSP430FR2532
Read/Write
(Optional Write
Protect) (1)
15KB
FFFFh–FF80h
FFFFh–C400h
8KB
FFFFh–FF80h
FFFFh–E000h
15KB
FFFFh–FF80h
FFFFh–C400h
8KB
FFFFh–FF80h
FFFFh–E000h
Read/Write
4KB
2FFFh–2000h
2KB
27FFh–2000h
2KB
27FFh–2000h
1KB
23FFh–2000h
Read/Write
(Optional Write
Protect) (2)
512B
19FFh–1800h
512B
19FFh–1800h
512B
19FFh–1800h
512B
19FFh–1800h
Bootstrap loader (BSL1)
Memory (ROM)
Read only
2KB
17FFh–1000h
2KB
17FFh–1000h
2KB
17FFh–1000h
2KB
17FFh–1000h
Bootstrap loader (BSL2)
Memory (ROM)
Read only
1KB
FFFFFh–FFC00h
1KB
FFFFFh–FFC00h
1KB
FFFFFh–FFC00h
1KB
FFFFFh–FFC00h
CapTIvate Libraries and
Driver Libraries (ROM)
Read only
12KB
6FFFh–4000h
12KB
6FFFh–4000h
12KB
6FFFh–4000h
12KB
6FFFh–4000h
Peripherals
Read/Write
4KB
0FFFh–0000h
4KB
0FFFh–0000h
4KB
0FFFh–0000h
4KB
0FFFh–0000h
Memory (FRAM)
Main: interrupt vectors and
signatures
Main: code memory
RAM
Information Memory (FRAM)
(1)
(2)
66
The Program FRAM can be write protected by setting PFWP bit in SYSCFG0 register. See the SYS chapter in MSP430FR2633 Family
User's Guide (SLAU445) for more details
The Information FRAM can be write protected by setting DFWP bit in SYSCFG0 register. See the SYS chapter in MSP430FR2633
Family User's Guide (SLAU445) for more details
Detailed Description
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SLAS942A – NOVEMBER 2015 – REVISED DECEMBER 2015
6.13.2 Peripheral File Map
Table 6-24 lists the available peripherals and the register base address for each. Table 6-25 through list
the registers and address offsets for each peripheral.
Table 6-24. Peripherals Summary
BASE ADDRESS
SIZE
Special Functions (See Table 6-25)
MODULE NAME
0100h
0010h
PMM (See Table 6-26)
0120h
0020h
SYS (See Table 6-27)
0140h
0040h
CS (See Table 6-28)
0180h
0020h
FRAM (See Table 6-29)
01A0h
0010h
CRC (See Table 6-30)
01C0h
0008h
WDT (See Table 6-31)
01CCh
0002h
Port P1, P2 (See Table 6-32)
0200h
0020h
Port P3 (See Table 6-33)
0220h
0020h
RTC (See Table 6-34)
0300h
0010h
Timer0_A3 (See Table 6-35)
0380h
0030h
Timer1_A3 (See Table 6-36)
03C0h
0030h
Timer2_A2 (See Table 6-37)
0400h
0030h
Timer3_A2 (See Table 6-38)
0440h
0030h
MPY32 (See Table 6-39)
04C0h
0030h
eUSCI_A0 (See Table 6-40)
0500h
0020h
eUSCI_A1 (See Table 6-41)
0520h
0020h
eUSCI_B0 (See Table 6-42)
0540h
0030h
Backup Memory (See Table 6-43)
0660h
0020h
ADC (See Table 6-44)
0700h
0040h
CapTIvate (See CapTivate Design Center for details )
0A00h
0200h
Table 6-25. Special Function Registers (Base Address: 0100h)
REGISTER DESCRIPTION
SFR interrupt enable
SFR interrupt flag
SFR reset pin control
ACRONYM
OFFSET
SFRIE1
00h
SFRIFG1
02h
SFRRPCR
04h
Table 6-26. PMM Registers (Base Address: 0120h)
ACRONYM
OFFSET
PMM control 0
REGISTER DESCRIPTION
PMMCTL0
00h
PMM control 1
PMMCTL1
02h
PMM control 2
PMMCTL2
04h
PMM interrupt flags
PMMIFG
0Ah
PM5 control 0
PM5CTL0
10h
Detailed Description
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Table 6-27. SYS Registers (Base Address: 0140h)
REGISTER DESCRIPTION
ACRONYM
OFFSET
SYSCTL
00h
Bootloader configuration area
SYSBSLC
02h
JTAG mailbox control
SYSJMBC
06h
JTAG mailbox input 0
SYSJMBI0
08h
JTAG mailbox input 1
SYSJMBI1
0Ah
JTAG mailbox output 0
SYSJMBO0
0Ch
JTAG mailbox output 1
SYSJMBO1
0Eh
Bus error vector generator
SYSBERRIV
18h
User NMI vector generator
SYSUNIV
1Ah
System control
System NMI vector generator
SYSSNIV
1Ch
Reset vector generator
SYSRSTIV
1Eh
System configuration 0
SYSCFG0
20h
System configuration 1
SYSCFG1
22h
System configuration 2
SYSCFG2
24h
Table 6-28. CS Registers (Base Address: 0180h)
ACRONYM
OFFSET
CS control 0
REGISTER DESCRIPTION
CSCTL0
00h
CS control 1
CSCTL1
02h
CS control 2
CSCTL2
04h
CS control 3
CSCTL3
06h
CS control 4
CSCTL4
08h
CS control 5
CSCTL5
0Ah
CS control 6
CSCTL6
0Ch
CS control 7
CSCTL7
0Eh
CS control 8
CSCTL8
10h
Table 6-29. FRAM Registers (Base Address: 01A0h)
REGISTER DESCRIPTION
ACRONYM
OFFSET
FRAM control 0
FRCTL0
00h
General control 0
GCCTL0
04h
General control 1
GCCTL1
06h
Table 6-30. CRC Registers (Base Address: 01C0h)
REGISTER DESCRIPTION
ACRONYM
OFFSET
CRC16DI
00h
CRC data input reverse byte
CRCDIRB
02h
CRC initialization and result
CRCINIRES
04h
CRC result reverse byte
CRCRESR
06h
CRC data input
Table 6-31. WDT Registers (Base Address: 01CCh)
REGISTER DESCRIPTION
Watchdog timer control
68
Detailed Description
ACRONYM
OFFSET
WDTCTL
00h
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Table 6-32. Port P1, P2 Registers (Base Address: 0200h)
REGISTER DESCRIPTION
ACRONYM
OFFSET
P1IN
00h
Port P1 output
P1OUT
02h
Port P1 direction
P1DIR
04h
Port P1 input
Port P1 pulling enable
P1REN
06h
Port P1 selection 0
P1SEL0
0Ah
Port P1 selection 1
P1SEL1
0Ch
Port P1 interrupt vector word
P1IV
0Eh
Port P1 interrupt edge select
P1IES
18h
P1IE
1Ah
P1IFG
1Ch
P2IN
01h
Port P2 output
P2OUT
03h
Port P2 direction
P2DIR
05h
Port P1 interrupt enable
Port P1 interrupt flag
Port P2 input
Port P2 pulling enable
P2REN
07h
Port P2 selection 0
P2SEL0
0Bh
Port P2 selection 1
P2SEL1
0Ch
Port P2 interrupt vector word
P2IV
1Eh
Port P2 interrupt edge select
P2IES
19h
P2IE
1Bh
P2IFG
1Dh
Port P2 interrupt enable
Port P2 interrupt flag
Table 6-33. Port P3 Registers (Base Address: 0220h)
REGISTER DESCRIPTION
Port P3 input
ACRONYM
OFFSET
P3IN
00h
Port P3 output
P3OUT
02h
Port P3 direction
P3DIR
04h
Port P3 pulling enable
P3REN
06h
Port P3 selection 0
P3SEL0
0Ah
Port P3 selection 1
P3SEL1
0
Table 6-34. RTC Registers (Base Address: 0300h)
REGISTER DESCRIPTION
RTC control
RTC interrupt vector
ACRONYM
OFFSET
RTCCTL
00h
RTCIV
04h
RTC modulo
RTCMOD
08h
RTC counter
RTCCNT
0Ch
Detailed Description
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Table 6-35. Timer0_A3 Registers (Base Address: 0380h)
REGISTER DESCRIPTION
ACRONYM
OFFSET
TA0CTL
00h
Capture/compare control 0
TA0CCTL0
02h
Capture/compare control 1
TA0CCTL1
04h
Capture/compare control 2
TA0CCTL2
06h
TA0R
10h
Capture/compare 0
TA0CCR0
12h
Capture/compare 1
TA0CCR1
14h
Capture/compare 2
TA0CCR2
16h
TA0EX0
20h
TA0IV
2Eh
TA0 control
TA0 counter
TA0 expansion 0
TA0 interrupt vector
Table 6-36. Timer1_A3 Registers (Base Address: 03C0h)
REGISTER DESCRIPTION
TA1 control
ACRONYM
OFFSET
TA1CTL
00h
Capture/compare control 0
TA1CCTL0
02h
Capture/compare control 1
TA1CCTL1
04h
Capture/compare control 2
TA1CCTL2
06h
TA1R
10h
Capture/compare 0
TA1CCR0
12h
Capture/compare 1
TA1CCR1
14h
Capture/compare 2
TA1CCR2
16h
TA1 counter
TA1 expansion 0
TA1 interrupt vector
TA1EX0
20h
TA1IV
2Eh
Table 6-37. Timer2_A2 Registers (Base Address: 0400h)
REGISTER DESCRIPTION
TA2 control
ACRONYM
OFFSET
TA2CTL
00h
Capture/compare control 0
TA2CCTL0
02h
Capture/compare control 1
TA2CCTL1
04h
TA2 counter
TA2R
10h
Capture/compare 0
TA2CCR0
12h
Capture/compare 1
TA2CCR1
14h
TA2EX0
20h
TA2IV
2Eh
TA2 expansion 0
TA2 interrupt vector
Table 6-38. Timer3_A2 Registers (Base Address: 0440h)
REGISTER DESCRIPTION
ACRONYM
OFFSET
TA3CTL
00h
Capture/compare control 0
TA3CCTL0
02h
Capture/compare control 1
TA3CCTL1
04h
TA3R
10h
Capture/compare 0
TA3CCR0
12h
Capture/compare 1
TA3CCR1
14h
TA3 control
TA3 counter
TA3 expansion 0
TA3 interrupt vector
70
Detailed Description
TA3EX0
20h
TA3IV
2Eh
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SLAS942A – NOVEMBER 2015 – REVISED DECEMBER 2015
Table 6-39. MPY32 Registers (Base Address: 04C0h)
REGISTER DESCRIPTION
16-bit operand 1 – multiply
16-bit operand 1 – signed multiply
16-bit operand 1 – multiply accumulate
16-bit operand 1 – signed multiply accumulate
16-bit operand 2
16 × 16 result low word
16 × 16 result high word
ACRONYM
OFFSET
MPY
00h
MPYS
02h
MAC
04h
MACS
06h
OP2
08h
RESLO
0Ah
RESHI
0Ch
16 × 16 sum extension
SUMEXT
0Eh
32-bit operand 1 – multiply low word
MPY32L
10h
32-bit operand 1 – multiply high word
MPY32H
12h
32-bit operand 1 – signed multiply low word
MPYS32L
14h
32-bit operand 1 – signed multiply high word
MPYS32H
16h
MAC32L
18h
32-bit operand 1 – multiply accumulate low word
32-bit operand 1 – multiply accumulate high word
MAC32H
1Ah
32-bit operand 1 – signed multiply accumulate low word
MACS32L
1Ch
32-bit operand 1 – signed multiply accumulate high word
MACS32H
1Eh
32-bit operand 2 – low word
OP2L
20h
32-bit operand 2 – high word
OP2H
22h
32 × 32 result 0 – least significant word
RES0
24h
32 × 32 result 1
RES1
26h
32 × 32 result 2
RES2
28h
32 × 32 result 3 – most significant word
RES3
2Ah
MPY32CTL0
2Ch
MPY32 control 0
Table 6-40. eUSCI_A0 Registers (Base Address: 0500h)
REGISTER DESCRIPTION
ACRONYM
OFFSET
eUSCI_A control word 0
UCA0CTLW0
00h
eUSCI_A control word 1
UCA0CTLW1
02h
eUSCI_A control rate 0
UCA0BR0
06h
UCA0BR1
07h
eUSCI_A control rate 1
eUSCI_A modulation control
UCA0MCTLW
08h
UCA0STAT
0Ah
eUSCI_A receive buffer
UCA0RXBUF
0Ch
eUSCI_A transmit buffer
UCA0TXBUF
0Eh
eUSCI_A LIN control
UCA0ABCTL
10h
eUSCI_A IrDA transmit control
lUCA0IRTCTL
12h
eUSCI_A IrDA receive control
IUCA0IRRCTL
13h
UCA0IE
1Ah
UCA0IFG
1Ch
UCA0IV
1Eh
eUSCI_A status
eUSCI_A interrupt enable
eUSCI_A interrupt flags
eUSCI_A interrupt vector word
Detailed Description
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Table 6-41. eUSCI_A1 Registers (Base Address: 0520h)
ACRONYM
OFFSET
eUSCI_A control word 0
REGISTER DESCRIPTION
UCA1CTLW0
00h
eUSCI_A control word 1
UCA1CTLW1
02h
eUSCI_A control rate 0
UCA1BR0
06h
UCA1BR1
07h
eUSCI_A control rate 1
eUSCI_A modulation control
UCA1MCTLW
08h
UCA1STAT
0Ah
eUSCI_A receive buffer
UCA1RXBUF
0Ch
eUSCI_A transmit buffer
UCA1TXBUF
0Eh
eUSCI_A LIN control
UCA1ABCTL
10h
eUSCI_A IrDA transmit control
lUCA1IRTCTL
12h
eUSCI_A IrDA receive control
IUCA1IRRCTL
13h
UCA1IE
1Ah
UCA1IFG
1Ch
UCA1IV
1Eh
eUSCI_A status
eUSCI_A interrupt enable
eUSCI_A interrupt flags
eUSCI_A interrupt vector word
Table 6-42. eUSCI_B0 Registers (Base Address: 0540h)
ACRONYM
OFFSET
eUSCI_B control word 0
REGISTER DESCRIPTION
UCB0CTLW0
00h
eUSCI_B control word 1
UCB0CTLW1
02h
eUSCI_B bit rate 0
UCB0BR0
06h
eUSCI_B bit rate 1
UCB0BR1
07h
eUSCI_B status word
UCB0STATW
08h
eUSCI_B byte counter threshold
UCB0TBCNT
0Ah
eUSCI_B receive buffer
UCB0RXBUF
0Ch
eUSCI_B transmit buffer
UCB0TXBUF
0Eh
eUSCI_B I2C own address 0
UCB0I2COA0
14h
eUSCI_B I2C own address 1
UCB0I2COA1
16h
eUSCI_B I2C own address 2
UCB0I2COA2
18h
eUSCI_B I2C own address 3
UCB0I2COA3
1Ah
UCB0ADDRX
1Ch
UCB0ADDMASK
1Eh
eUSCI_B receive address
eUSCI_B address mask
eUSCI_B I2C slave address
eUSCI_B interrupt enable
eUSCI_B interrupt flags
eUSCI_B interrupt vector word
72
Detailed Description
UCB0I2CSA
20h
UCB0IE
2Ah
UCB0IFG
2Ch
UCB0IV
2Eh
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Table 6-43. Backup Memory Registers (Base Address: 0660h)
ACRONYM
OFFSET
Backup memory 0
REGISTER DESCRIPTION
BAKMEM0
00h
Backup memory 1
BAKMEM1
02h
Backup memory 2
BAKMEM2
04h
Backup memory 3
BAKMEM3
06h
Backup memory 4
BAKMEM4
08h
Backup memory 5
BAKMEM5
0Ah
Backup memory 6
BAKMEM6
0Ch
Backup memory 7
BAKMEM7
0Eh
Backup memory 8
BAKMEM8
10h
Backup memory 9
BAKMEM9
12h
Backup memory 10
BAKMEM10
14h
Backup memory 11
BAKMEM11
16h
Backup memory 12
BAKMEM12
18h
Backup memory 13
BAKMEM13
1Ah
Backup memory 14
BAKMEM14
1Ch
Backup memory 15
BAKMEM15
1Eh
Table 6-44. ADC Registers (Base Address: 0700h)
REGISTER DESCRIPTION
ACRONYM
OFFSET
ADC control 0
ADCCTL0
00h
ADC control 1
ADCCTL1
02h
ADC control 2
ADCCTL2
04h
ADCLO
06h
ADC window comparator low threshold
ADC window comparator high threshold
ADCHI
08h
ADC memory control 0
ADCMCTL0
0Ah
ADC conversion memory
ADCMEM0
12h
ADC interrupt enable
ADC interrupt flags
ADC interrupt vector word
ADCIE
1Ah
ADCIFG
1Ch
ADCIV
1Eh
Detailed Description
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6.14 Identification
6.14.1 Revision Identification
The device revision information is included as part of the top-side marking on the device package. The
device-specific errata sheet describes these markings (see Section 8.2).
The hardware revision is also stored in the Device Descriptor structure in the Info Block section. For
details on this value, see the Hardware Revision entries in Section 6.12.
6.14.2 Device Identification
The device type can be identified from the top-side marking on the device package. The device-specific
errata sheet describes these markings (see Section 8.2).
A device identification value is also stored in the Device Descriptor structure in the Info Block section. For
details on this value, see the Device ID entries in Section 6.12.
6.14.3 JTAG Identification
Programming through the JTAG interface, including reading and identifying the JTAG ID, is described in
detail in the MSP430 Programming Via the JTAG Interface User's Guide (SLAU320).
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7 Applications, Implementation, and Layout
NOTE
Information in the following Applications section is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI's customers are responsible for
determining suitability of components for their purposes. Customers should validate and test
their design implementation to confirm system functionality.
7.1
Device Connection and Layout Fundamentals
This section discusses the recommended guidelines when designing with the MSP430 devices. These
guidelines are to make sure that the device has proper connections for powering, programming,
debugging, and optimum analog performance.
7.1.1
Power Supply Decoupling and Bulk Capacitors
TI recommends connecting a combination of a 10-µF plus a 100-nF low-ESR ceramic decoupling
capacitor to the DVCC and DVSS pins. Higher-value capacitors may be used but can impact supply rail
ramp-up time. Decoupling capacitors must be placed as close as possible to the pins that they decouple
(within a few millimeters). Additionally, TI recommends separated grounds with a single-point connection
for better noise isolation from digital-to-analog circuits on the board and to achieve high analog accuracy.
DVCC
Digital
Power Supply
Decoupling
+
10 µF
100 nF
DVSS
Figure 7-1. Power Supply Decoupling
7.1.2
External Oscillator
This device supports only a low-frequency crystal (32 kHz) on the XIN and XOUT pins. External bypass
capacitors for the crystal oscillator pins are required.
It is also possible to apply digital clock signals to the XIN input pin that meet the specifications of the
respective oscillator if the appropriate XT1BYPASS mode is selected. In this case, the associated XOUT
pin can be used for other purposes. If the XIN and XOUT pins are not used, they must be terminated
according to Section 4.6.
Figure 7-2 shows a typical connection diagram.
XIN
CL1
XOUT
CL2
Figure 7-2. Typical Crystal Connection
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See the application report MSP430 32-kHz Crystal Oscillators (SLAA322) for more information on
selecting, testing, and designing a crystal oscillator with the MSP430 devices.
7.1.3
JTAG
With the proper connections, the debugger and a hardware JTAG interface (such as the MSP-FET or
MSP-FET430UIF) can be used to program and debug code on the target board. In addition, the
connections also support the MSP-GANG production programmers, thus providing an easy way to
program prototype boards, if desired. Figure 7-3 shows the connections between the 14-pin JTAG
connector and the target device required to support in-system programming and debugging for 4-wire
JTAG communication. Figure 7-4 shows the connections for 2-wire JTAG mode (Spy-Bi-Wire).
The connections for the MSP-FET and MSP-FET430UIF interface modules and the MSP-GANG are
identical. Both can supply VCC to the target board (through pin 2). In addition, the MSP-FET and MSPFET430UIF interface modules and MSP-GANG have a VCC sense feature that, if used, requires an
alternate connection (pin 4 instead of pin 2). The VCC sense feature detects the local VCC present on the
target board (that is, a battery or other local power supply) and adjusts the output signals accordingly.
Figure 7-3 and Figure 7-4 show a jumper block that supports both scenarios of supplying VCC to the target
board. If this flexibility is not required, the desired VCC connections may be hard-wired to eliminate the
jumper block. Pins 2 and 4 must not be connected at the same time.
For additional design information regarding the JTAG interface, see the MSP430 Hardware Tools User's
Guide (SLAU278).
VCC
Important to connect
MSP430FRxxx
J1 (see Note A)
DVCC
J2 (see Note A)
R1
47 kW
JTAG
VCC TOOL
VCC TARGET
TEST
2
RST/NMI/SBWTDIO
1
4
3
6
5
8
7
10
9
12
11
14
13
TDO/TDI
TDO/TDI
TDI
TDI
TMS
TCK
TMS
TCK
GND
RST
TEST/SBWTCK
C1
1 nF
(see Note B)
A.
B.
DVSS
If a local target power supply is used, make connection J1. If power from the debug or programming adapter is used,
make connection J2.
The upper limit for C1 is 1.1 nF when using current TI tools.
Figure 7-3. Signal Connections for 4-Wire JTAG Communication
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VCC
Important to connect
MSP430FRxxx
J1 (see Note A)
DVCC
J2 (see Note A)
R1
47 kΩ
(see Note B)
JTAG
VCC TOOL
VCC TARGET
2
1
4
3
6
5
8
7
10
9
12
11
14
13
TDO/TDI
RST/NMI/SBWTDIO
TCK
GND
TEST/SBWTCK
C1
1 nF
(see Note B)
A.
B.
DVSS
Make connection J1 if a local target power supply is used, or make connection J2 if the target is powered from the
debug or programming adapter.
The device RST/NMI/SBWTDIO pin is used in 2-wire mode for bidirectional communication with the device during
JTAG access, and any capacitance that is attached to this signal may affect the ability to establish a connection with
the device. The upper limit for C1 is 1.1 nF when using current TI tools.
Figure 7-4. Signal Connections for 2-Wire JTAG Communication (Spy-Bi-Wire)
7.1.4
Reset
The reset pin can be configured as a reset function (default) or as an NMI function in the Special Function
Register (SFR), SFRRPCR.
In reset mode, the RST/NMI pin is active low, and a pulse applied to this pin that meets the reset timing
specifications generates a BOR-type device reset.
Setting SYSNMI causes the RST/NMI pin to be configured as an external NMI source. The external NMI is
edge sensitive, and its edge is selectable by SYSNMIIES. Setting the NMIIE enables the interrupt of the
external NMI. When an external NMI event occurs, the NMIIFG is set.
The RST/NMI pin can have either a pullup or pulldown that is enabled or not. SYSRSTUP selects either
pullup or pulldown, and SYSRSTRE causes the pullup (default) or pulldown to be enabled (default) or not.
If the RST/NMI pin is unused, it is required either to select and enable the internal pullup or to connect an
external 47-kΩ pullup resistor to the RST/NMI pin with a 1.1-nF pulldown capacitor. The pulldown
capacitor should not exceed 1.1 nF when using devices with Spy-Bi-Wire interface in Spy-Bi-Wire mode or
in 4-wire JTAG mode with TI tools like FET interfaces or GANG programmers.
See the MSP430FR4xx and MSP430FR2xx Family User's Guide (SLAU445) for more information on the
referenced control registers and bits.
7.1.5
Unused Pins
For details on the connection of unused pins, see Section 4.6.
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7.1.6
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General Layout Recommendations
•
•
•
•
•
7.1.7
Proper grounding and short traces for external crystal to reduce parasitic capacitance. See the
application report MSP430 32-kHz Crystal Oscillators (SLAA322) for recommended layout guidelines.
Proper bypass capacitors on DVCC and reference pins, if used.
Avoid routing any high-frequency signal close to an analog signal line. For example, keep digital
switching signals such as PWM or JTAG signals away from the oscillator circuit and ADC signals.
Refer to the Circuit Board Layout Techniques design guide (SLOA089) for a detailed discussion of
PCB layout considerations. This document is written primarily about op amps, but the guidelines are
generally applicable for all mixed-signal applications.
Proper ESD level protection should be considered to protect the device from unintended high-voltage
electrostatic discharge. See the application report MSP430 System-Level ESD Considerations
(SLAA530) for guidelines.
Do's and Don'ts
During power up, power down, and device operation, DVCC must not exceed the limits specified in
Section 5.1, Absolute Maximum Ratings. Exceeding the specified limits may cause malfunction of the
device including erroneous writes to RAM and FRAM.
7.2
Peripheral- and Interface-Specific Design Information
7.2.1
ADC Peripheral
7.2.1.1
Partial Schematic
DVSS
Using an
External
Positive
Reference
Using an
External
Negative
Reference
VREF+/VEREF+
+
10 µF
100 nF
VEREF+
10 µF
100 nF
Figure 7-5. ADC Grounding and Noise Considerations
7.2.1.2
Design Requirements
As with any high-resolution ADC, appropriate printed-circuit board layout and grounding techniques should
be followed to eliminate ground loops, unwanted parasitic effects, and noise.
Ground loops are formed when return current from the ADC flows through paths that are common with
other analog or digital circuitry. If care is not taken, this current can generate small unwanted offset
voltages that can add to or subtract from the reference or input voltages of the ADC. The general
guidelines in Section 7.1.1 combined with the connections shown in Figure 7-5 prevent this.
In addition to grounding, ripple and noise spikes on the power-supply lines that are caused by digital
switching or switching power supplies can corrupt the conversion result. TI recommends a noise-free
design using separate analog and digital ground planes with a single-point connection to achieve high
accuracy.
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Figure 7-5 shows the recommended decoupling circuit when an external voltage reference is used. The
internal reference module has a maximum drive current as described in the sections ADC Pin Enable and
1.2-V Reference Settings of the MSP430FR4xx and MSP430FR2xx Family User's Guide (SLAU445).
The reference voltage must be a stable voltage for accurate measurements. The capacitor values that are
selected in the general guidelines filter out the high- and low-frequency ripple before the reference voltage
enters the device. In this case, the 10-µF capacitor buffers the reference pin and filters any low-frequency
ripple. A bypass capacitor of 100 nF filters out any high-frequency noise.
7.2.1.3
Layout Guidelines
Components that are shown in the partial schematic (see Figure 7-5) should be placed as close as
possible to the respective device pins to avoid long traces, because they add additional parasitic
capacitance, inductance, and resistance on the signal.
Avoid routing analog input signals close to a high-frequency pin (for example, a high-frequency PWM),
because the high-frequency switching can be coupled into the analog signal.
7.2.2
CapTIvate Peripheral
This section provides a brief introduction to the CapTIvate technology with examples of PCB layout and
performance from the design kit. A more detailed description of the CapTIvate technology and the tools
needed to be successful, application development tools, hardware design guides, and software library,
can be found in the CapTIvate Technology Design Center.
7.2.2.1
Device Connection and Layout Fundamentals
7.2.2.1.1 VREG
The VREG pin requires a 1-µF capacitor to regulate the 1.5-V LDO internal to the device (Vreg). This
capacitor must be placed as close as possible to the microcontroller. Figure 7-6 shows the layout of the
CAPTIVATE-FR2633, zooming in on the capacitor connected to the VREG pin.
Figure 7-6. VREG Capacitor and Channel Series Resistors
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7.2.2.1.2 ESD Protection
Typically, the laminate overlay provides several kilovolts of breakdown isolation to protect the circuit from
ESD strikes. More ESD protection can be added with a series resistor placed on each channel used. A
value of 470 Ω is recommended and is found on the development tool.
7.2.2.1.3 Mutual- and Self-Capacitance
CapTIvate technology enables both self-mode and mutual-mode capacitance measurements.
Section 7.2.2.1.4 and Section 7.2.2.1.5 provide a brief description and examples, taken from the
CAPTIVATE-PHONE and CAPTIVATE-BSWP panels found in the design kit, for self- and mutual-mode
capacitance measurements, respectively.
7.2.2.1.4 Self-Capacitance
Self-capacitance electrodes are characterized by having only one channel from the IC that both excites
and measures the capacitance. The capacitance being measured is between the electrode and earth
ground, so any capacitance local to the PCB or outside of the PCB (a touch event) influences the
measurement.
PCB layout design guidelines to minimize local parasitic capacitances and maximize the affect of external
capacitances (a touch) can be found in the CapTIvate Technology Design Center. Figure 7-7, taken from
the CAPTIVATE-BSWP panel, shows that the area of the button should be consistent with the touch area,
in this case a 400-mil (10.16-mm) diameter circle. To minimize parasitics on the PCB, the ground pour on
the bottom layer is hatched and there is no pour directly below the electrode: 50-mil (1.27-mm) spacing
between the electrode and ground fill.
Figure 7-7. Self-Capacitance Electrodes
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7.2.2.1.5 Mutual Capacitance
Mutual capacitance is characterized by having two channels, receive (Rx) and transmit (Tx), from the IC
with the focus being the capacitance between the two. Coupling to earth ground still has an affect, but this
is secondary to the mutual capacitance between the Rx and Tx electrodes.
PCB layout design guidelines for mutual capacitance structures can also be found in the CapTIvate
Technology Design Center. Figure 7-8, taken from CAPTIVATE-PHONE, shows that the Tx electrode is a
copy of the Rx electrode expanded to surround the Rx electrode. Both the Rx and Tx electrodes are in the
shape of hollow squares: the Tx electrode is 300 × 300 mils (7.62 × 7.62 mm) and the Rx electrode is
150 × 150 mils (3.81 × 3.81 mm). Both electrodes are 50 mils (1.27 mm) wide.
Figure 7-8. Mutual-Capacitance Electrodes
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7.2.2.2
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Measurements
The following measurements are taken from the CapTIvate Technology Design Center, using the
CAPTIVATE-PHONE and CAPTIVATE-BSWP panels. Unless otherwise stated, the settings used are the
out-of-box settings, which can be found in the example projects. The intent of these measurements is to
show performance in a configuration that is readily available and reproducible.
Figure 7-9. CAPTIVATE-PHONE and CAPTIVATE-BSWP Panels
7.2.2.2.1 SNR
The CapTIvate technology Design Center provides a specific view for analyzing the signal-to-noise ratio of
each element. Figure 7-10 shows that the SNR tab can be used to establish a confidence level in the
settings that are chosen.
Figure 7-10. SNR Tab
Table 7-1 summarizes
numericKeypadSensor.
82
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Applications, Implementation, and Layout
SNR
results
from
the
CAPTIVATE-PHONE
panel
keypad,
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Table 7-1. CAPTIVATE-PHONE SNR Results
ELEMENT
SNR
(dB)
ELEMENT
SNR
(dB)
E00
31.49
E06
38.03
E01
37.20
E07
35.48
E02
36.34
E08
37.28
E03
38.50
E09
–
E04
34.76
E10
–
E05
39.62
E11
–
Table 7-2 summarizes the SNR results from the CAPTIVATE-BSWP panel keypad, keypadSensor.
Table 7-2. CAPTIVATE-BSWP SNR Results
ELEMENT
SNR
(dB)
ELEMENT
SNR
(dB)
E00
37.90
E04
39.28
E01
47.26
E05
29.67
E02
36.79
E06
36.63
E03
33.73
E07
34.07
7.2.2.2.2 Sensitivity
To show sensitivity, in terms of farads, the internal reference capacitor is used as the change in
capacitance. In the mutual-capacitance case, the 0.1-pF capacitor is used. In the self-capacitance case,
the 1-pF reference capacitor is used. For simplicity, the results for only button 1 on both the CAPTIVATEPHONE and CAPTIVATE-BSWP panels are reported in Table 7-3.
Table 7-3. Button Sensitivity
CAPTIVATE-PHONE BUTTON 1
CAPTIVATE-BSWP BUTTON 1
CONVERSION
COUNT
CONVERSION
GAIN
100
100
25
6
50
8
200
200
50
10
100
16
200
100
50
21
100
31
800
400
200
70
400
112
800
200
200
140
400
202
800
100
200
257
400
333
CONVERSION
TIME (µs)
COUNTS FOR
0.1-pF
CHANGE
CONVERSION
TIME (µs)
COUNTS FOR
1-pF CHANGE
An alternative measure in sensitivity is the ability to resolve capacitance change over a wide range of base
capacitance. Table 7-4 shows example conversion times (for a self-mode measurement of discrete
capacitors) that can be used to achieve the desired resolution for a given parasitic load capacitance.
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Table 7-4. Button Sensitivity
CAPACITANC
E Cp (pF) (1)
CONVERSION
COUNT/GAIN
CONVERSION
TIME (µs)
COUNTS FOR
0.130-pF
CHANGE
COUNTS FOR
0.260-pF
CHANGE
COUNTS FOR
0.520-pF
CHANGE
23
400/100
200
10
23
35
50
550/100
275
11
24
37
78
650/100
325
11
23
36
150
850/100
425
11
22
35
(2)
1200/200
600
11
23
37
200 (2)
1200/150
600
13
26
41
150
(1)
(2)
These measurements were taken with the CapTIvate MCU processor board with the 470-Ω series
resistors replaced with 0-Ω resistors.
0-V discharge voltage is used.
7.2.2.2.3 Power
The low-power mode LPM3 specifications in Section 5.7 are derived from the CapTIvate technology
design kit as indicated in the notes.
7.3
Typical Applications
Table 7-5 lists tools that demonstrate the use of the MSP430FR263x devices in various real-world
application scenarios. Consult these designs for additional guidance regarding schematics, layout, and
software implementation. For the most up-to-date list of available TI Designs, see the device-specific
product folders listed in Section 8.3.
Table 7-5. TI Designs
DESIGN NAME
LINK
MSP CapTIvate™ MCU Development Kit Evaluation Model
http://www.ti.com/tool/msp-capt-fr2633
Capacitive Touch Thermostat User Interface Reference Design
http://www.ti.com/tool/tidm-captivate-thermostat-ui
84
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8 Device and Documentation Support
8.1
Device Support
8.1.1
Development Support
8.1.1.1
Getting Started and Next Steps
For more information on the MSP low-power microcontrollers and the tools and libraries that are available
to help with your development, visit the Getting Started page.
8.1.1.2
Development Tools Support
8.1.1.2.1 Hardware Features
See the Code Composer Studio for MSP430 User's Guide (SLAU157) for details on the available features.
MSP430
ARCHITECTURE
4-WIRE
JTAG
2-WIRE
JTAG
BREAKPOINTS
(N)
RANGE
BREAKPOINTS
CLOCK
CONTROL
STATE
SEQUENCER
TRACE
BUFFER
LPMx.5
DEBUGGING
SUPPORT
EEM
VERSION
MSP430Xv2
Yes
Yes
3
Yes
Yes
No
No
No
S
8.1.1.2.2 Recommended Hardware Options
All MSP430 MCUs are supported by a wide variety of software and hardware development tools. Tools
are available from TI and various third parties. See them all at MSP430 Tools.
8.1.1.2.2.1 Experimenter Boards
Experimenter Boards and Evaluation kits are available for some MSP430 devices. These kits feature
additional hardware components and connectivity for full system evaluation and prototyping. See MSP430
Tools for details.
8.1.1.2.2.2 Debugging and Programming Tools
Hardware programming and debugging tools are available from TI and from its third-party suppliers. See
the full list of available tools at MSP430 Tools.
PART NUMBER
PC PORT
FEATURES
MSP-FET430UIF
USB
MSP430 USB debugging interface. Compatible with 4-wire JTAG and
2-wire Spy-Bi-Wire (SBW) JTAG modes
MSP-FET
USB
MSP MCU programmer and debugger. The MSP-FET is compatible
with Code Composer Studio v6 and later.
PROVIDER
Texas Instruments
Texas Instruments
8.1.1.2.2.3 Production Programmers
The production programmers expedite loading firmware to devices by programming several devices
simultaneously.
PART NUMBER
MSP-GANG
PC PORT
Serial and USB
FEATURES
Program up to eight devices at a time. Works with a PC or as a
stand‑alone package.
PROVIDER
Texas Instruments
8.1.1.2.3 Recommended Software Options
8.1.1.2.3.1 Integrated Development Environments
Software development tools are available from TI or from third parties. Open-source solutions are also
available.
This device is supported by Code Composer Studio™ IDE (CCS).
Device and Documentation Support
Submit Documentation Feedback
Product Folder Links: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532
Copyright © 2015, Texas Instruments Incorporated
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SLAS942A – NOVEMBER 2015 – REVISED DECEMBER 2015
www.ti.com
8.1.1.2.3.2 MSPWare
MSPWare is a collection of code examples, data sheets, and other design resources for all MSP devices
delivered in a convenient package. In addition to providing a complete collection of existing MSP design
resources, MSPWare also includes a high-level API called MSP430 Driver Library. This library makes it
easy to program MSP hardware. MSPWare is available as a component of CCS or as a stand-alone
package.
8.1.1.2.3.3 Command-Line Programmer
MSP Flasher is an open-source shell-based interface for programming MSP MCUs through a FET
programmer or eZ430 using JTAG or Spy-Bi-Wire (SBW) communication. MSP Flasher can be used to
download binary files (.txt or .hex) files directly to the MSP MCU without the need for an IDE.
8.1.2
Device Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
MSP430 MCUs and support tools. Each MSP430 MCU commercial family member has one of three
prefixes: MSP, PMS, or XMS (for example, MSP430FR2633). TI recommends two of three possible prefix
designators for its support tools: MSP and MSPX. These prefixes represent evolutionary stages of product
development from engineering prototypes (with XMS for devices and MSPX for tools) through fully
qualified production devices and tools (with MSP for devices and MSP for tools).
Device development evolutionary flow:
XMS – Experimental device that is not necessarily representative of the electrical specifications of the final
device
MSP – Fully qualified production device
Support tool development evolutionary flow:
MSPX – Development-support product that has not yet completed TI internal qualification testing.
MSP – Fully-qualified development-support product
XMS devices and MSPX development-support tools are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
MSP devices and MSP development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (XMS) have a greater failure rate than the standard production
devices. TI recommends that these devices not be used in any production system because their expected
end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the
package type (for example, RHB) and temperature range (for example, T). Figure 8-1 provides a legend
for reading the complete device name for any family member.
86
Device and Documentation Support
Copyright © 2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532
MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532
www.ti.com
SLAS942A – NOVEMBER 2015 – REVISED DECEMBER 2015
MSP 430 FR 2 633 I RHB T
Processor Family
MCU Platform
Device Type
Optional: Tape and Reel
Series
Feature Set
Packaging
Optional: Temperature Range
Processor Family
MSP = Mixed-signal processor
XMS = Experimental silicon
MCU Platform
430 = MSP430 16-bit low-power platform
Device Type
Memory Type
FR = FRAM
Series
4 = Up to 16 MHz with LCD
2 = Up to 16 MHz without LCD
Feature Set
First and Second Digits – CapTIvate Performance
63 = 4 CapTIvate blocks with full performance
53 = 4 CapTIvate blocks with downgraded performance
Optional: Temperature Range
S = 0°C to 50°C
I = –40°C to 85°C
T = –40°C to 105°C
Packaging
www.ti.com/packaging
Optional: Distribution Format
T = Small Reel
R = Large Reel
No Marking = Tube or Tray
Third Digit – FRAM (KB) / SRAM (KB)
3 = 16 / 4 (16 / 2 for 53 device)
2 = 8 / 2 ( 8 / 1 for 53 device)
Figure 8-1. Device Nomenclature
Device and Documentation Support
Submit Documentation Feedback
Product Folder Links: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532
Copyright © 2015, Texas Instruments Incorporated
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SLAS942A – NOVEMBER 2015 – REVISED DECEMBER 2015
8.2
www.ti.com
Documentation Support
The following documents describe the MSP430FR263x and MSP430FR253x MCUs. Copies of these
documents are available on the Internet at www.ti.com.
88
SLAU445
MSP430FR4xx and MSP430FR2xx Family User's Guide. Detailed description of all
modules and peripherals available in this device family.
SLAZ660
MSP430FR2633 Device Erratasheet. Describes the known exceptions to the functional
specifications for all silicon revisions of this MCU.
SLAZ661
MSP430FR2533 Device Erratasheet. Describes the known exceptions to the functional
specifications for all silicon revisions of this MCU.
SLAZ662
MSP430FR2632 Device Erratasheet. Describes the known exceptions to the functional
specifications for all silicon revisions of this MCU.
SLAZ663
MSP430FR2532 Device Erratasheet. Describes the known exceptions to the functional
specifications for all silicon revisions of this MCU.
SLAU278
MSP430 Hardware Tools User's Guide. This manual describes the hardware of the TI
MSP-FET430 Flash Emulation Tool (FET). The FET is the program development tool for the
MSP430 ultra-low-power microcontroller. Both available interface types, the parallel port
interface and the USB interface, are described.
SLAU610
MSP430FR4xx and MSP430FR2xx Bootloader (BSL) User's Guide. The bootloader (BSL)
provides a method to program memory during MSP430 MCU project development and
updates. It can be activated by a utility that sends commands using a serial protocol. The
BSL enables the user to control the activity of the MSP430 MCU and to exchange data using
a personal computer or other device.
SLAU320
MSP430 Programming Via the JTAG Interface. This document describes the functions that
are required to erase, program, and verify the memory module of the MSP430 flash-based
and FRAM-based microcontroller families using the JTAG communication port. In addition, it
describes how to program the JTAG access security fuse that is available on all MSP430
MCUs. This document describes access to the MCU using both the standard 4-wire JTAG
interface and the 2-wire JTAG interface, which is also referred to as Spy-Bi-Wire (SBW).
SLAA322
MSP430 32-kHz Crystal Oscillators. Selection of the right crystal, correct load circuit, and
proper board layout are important for a stable crystal oscillator. This application report
summarizes crystal oscillator function and explains the parameters to select the correct
crystal for MSP430 ultra-low power operation. In addition, hints and examples for correct
board layout are given. The document also contains detailed information on the possible
oscillator tests to ensure stable oscillator operation in mass production.
SLOA089
Circuit Board Layout Techniques. Op amp circuitry is analog circuitry and is very different
from digital circuitry. It must be partitioned in its own section of the board using special layout
techniques. Printed circuit board effects become most apparent in high-speed analog
circuits, but common mistakes described in this chapter can even affect the performance of
audio circuits. The purpose of this chapter is to discuss some of the more common mistakes
made by designers and how they degrade performance, and to provide simple fixes to avoid
the problems.
SLAA530
MSP430 System-Level ESD Considerations. System-Level ESD has become increasingly
demanding with silicon technology scaling towards lower voltages and the need for designing
cost-effective and ultra-low-power components. This application report addresses three
different ESD topics to help board designers and OEMs understand and design robust
system-level designs.
Device and Documentation Support
Copyright © 2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532
MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532
www.ti.com
8.3
SLAS942A – NOVEMBER 2015 – REVISED DECEMBER 2015
Related Links
Table 8-1 lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 8-1. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
MSP430FR2633
Click here
Click here
Click here
Click here
Click here
MSP430FR2533
Click here
Click here
Click here
Click here
Click here
MSP430FR2632
Click here
Click here
Click here
Click here
Click here
MSP430FR2532
Click here
Click here
Click here
Click here
Click here
8.4
Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the
respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;
see TI's Terms of Use.
TI E2E™ Community
TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At
e2e.ti.com, you can ask questions, share knowledge, explore ideas, and help solve problems with fellow
engineers.
TI Embedded Processors Wiki
Texas Instruments Embedded Processors Wiki. Established to help developers get started with embedded
processors from Texas Instruments and to foster innovation and growth of general knowledge about the
hardware and software surrounding these devices.
8.5
Trademarks
CapTIvate, MSP430, Code Composer Studio, E2E are trademarks of Texas Instruments.
8.6
Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
8.7
Export Control Notice
Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data
(as defined by the U.S., EU, and other Export Administration Regulations) including software, or any
controlled product restricted by other applicable national regulations, received from disclosing party under
nondisclosure obligations (if any), or any direct product of such technology, to any destination to which
such export or re-export is restricted or prohibited by U.S. or other applicable laws, without obtaining prior
authorization from U.S. Department of Commerce and other competent Government authorities to the
extent required by those laws.
8.8
Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
Device and Documentation Support
Submit Documentation Feedback
Product Folder Links: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532
Copyright © 2015, Texas Instruments Incorporated
89
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SLAS942A – NOVEMBER 2015 – REVISED DECEMBER 2015
www.ti.com
9 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the
most current data available for the designated devices. This data is subject to change without notice and
revision of this document. For browser-based versions of this data sheet, see the left-hand navigation.
90
Mechanical, Packaging, and Orderable Information
Copyright © 2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532
PACKAGE OPTION ADDENDUM
www.ti.com
20-Dec-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
MSP430FR2532IRGER
ACTIVE
VQFN
RGE
24
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
FR2532
MSP430FR2532IRGET
ACTIVE
VQFN
RGE
24
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
FR2532
MSP430FR2533IDA
ACTIVE
TSSOP
DA
32
46
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
FR2533
MSP430FR2533IDAR
ACTIVE
TSSOP
DA
32
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
FR2533
MSP430FR2533IRHBR
ACTIVE
VQFN
RHB
32
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
FR2533
MSP430FR2533IRHBT
ACTIVE
VQFN
RHB
32
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
FR2533
MSP430FR2632IRGER
ACTIVE
VQFN
RGE
24
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
FR2632
MSP430FR2632IRGET
ACTIVE
VQFN
RGE
24
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
FR2632
MSP430FR2633IDA
ACTIVE
TSSOP
DA
32
46
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
FR2633
MSP430FR2633IDAR
ACTIVE
TSSOP
DA
32
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
FR2633
MSP430FR2633IRHBR
ACTIVE
VQFN
RHB
32
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
FR2633
MSP430FR2633IRHBT
ACTIVE
VQFN
RHB
32
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
FR2633
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
20-Dec-2015
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Jan-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
MSP430FR2532IRGER
VQFN
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
RGE
24
3000
330.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
MSP430FR2533IDAR
TSSOP
DA
32
2000
330.0
24.4
8.6
11.5
1.6
12.0
24.0
Q1
MSP430FR2533IRHBR
VQFN
RHB
32
3000
330.0
12.4
5.3
5.3
1.1
8.0
12.0
Q2
MSP430FR2632IRGER
VQFN
RGE
24
3000
330.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
MSP430FR2633IDAR
TSSOP
DA
32
2000
330.0
24.4
8.6
11.5
1.6
12.0
24.0
Q1
MSP430FR2633IRHBR
VQFN
RHB
32
3000
330.0
12.4
5.3
5.3
1.1
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Jan-2016
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
MSP430FR2532IRGER
VQFN
RGE
24
3000
367.0
367.0
35.0
MSP430FR2533IDAR
TSSOP
DA
32
2000
367.0
367.0
45.0
MSP430FR2533IRHBR
VQFN
RHB
32
3000
367.0
367.0
35.0
MSP430FR2632IRGER
VQFN
RGE
24
3000
367.0
367.0
35.0
MSP430FR2633IDAR
TSSOP
DA
32
2000
367.0
367.0
45.0
MSP430FR2633IRHBR
VQFN
RHB
32
3000
367.0
367.0
35.0
Pack Materials-Page 2
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