EL5210, EL5410 ® Data Sheet July 5, 2007 30MHz Rail-to-Rail Input-Output Op Amps Features The EL5210 and EL5410 are low power, high voltage rail-torail input-output amplifiers. The EL5210 contains two amplifiers in one package and the EL5410 contains four amplifiers. Operating on supplies ranging from 5V to 15V, while consuming only 2.5mA per amplifier, the EL5410 and EL5210 have a bandwidth of 30MHz (-3dB). They also provide common mode input ability beyond the supply rails, as well as rail-to-rail output capability. This enables these amplifiers to offer maximum dynamic range at any supply voltage. • 30MHz -3dB bandwidth The EL5410 and EL5210 also feature fast slewing and settling times, as well as a high output drive capability of 30mA (sink and source). These features make these amplifiers ideal for high speed filtering and signal conditioning application. Other applications include battery power, portable devices, and anywhere low power consumption is important. The EL5410 is available in a space-saving 14 Ld TSSOP package, as well as the industry-standard 14 Ld SOIC. The EL5210 is available in the 8 Ld MSOP and 8 Ld SOIC packages. Both feature a standard operational amplifier pin out. These amplifiers operate over a temperature range of -40°C to +85°C. FN7185.3 • Supply voltage = 4.5V to 16.5V • Low supply current (per amplifier) = 2.5mA • High slew rate = 33V/µs • Unity-gain stable • Beyond the rails input capability • Rail-to-rail output swing • Available in both standard and space-saving fine pitch packages • Pb-free plus anneal available (RoHS compliant) Applications • Driver for A-to-D Converters • Data Acquisition • Video Processing • Audio Processing • Active Filters • Test Equipment • Battery Powered Applications • Portable Equipment Pinouts EL5410 (14 LD TSSOP, SOIC) TOP VIEW VOUTA 1 14 VOUTD VINA- 2 VINA+ 3 13 VIND- - + + EL5210 (8 LD MSOP, SOIC) TOP VIEW VOUTA 1 VINA- 2 8 VS+ - 7 VOUTB + 12 VIND+ VINA+ 3 - 6 VINB- + VS+ 4 11 VS- VINB+ 5 VINB- 6 VOUTB 7 1 VS- 4 5 VINB+ 10 VINC+ + + - - 9 VINC8 VOUTC CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2003-2005, 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners. EL5210, EL5410 Ordering Information PART NUMBER PART MARKING PACKAGE PKG. DWG. # EL5210CS 5210CS 8 Ld SOIC MDP0027 EL5210CS-T7* 5210CS 8 Ld SOIC MDP0027 EL5210CS-T13* 5210CS 8 Ld SOIC MDP0027 EL5210CSZ (Note) 5210CSZ 8 Ld SOIC (Pb-free) MDP0027 EL5210CSZ-T7* (Note) 5210CSZ 8 Ld SOIC (Pb-free) MDP0027 EL5210CSZ-T13* (Note) 5210CSZ 8 Ld SOIC (Pb-free) MDP0027 EL5210CY J 8 Ld MSOP MDP0043 EL5210CY-T7* J 8 Ld MSOP MDP0043 EL5210CY-T13* J 8 Ld MSOP MDP0043 EL5210CYZ (Note) BATAA 8 Ld MSOP (Pb-free) MDP0043 EL5210CYZ-T7* (Note) BATAA 8 Ld MSOP (Pb-free) MDP0043 EL5210CYZ-T13* (Note) BATAA 8 Ld MSOP (Pb-free) MDP0043 EL5410CS 5410CS 14 Ld SOIC MDP0027 EL5410CS-T7* 5410CS 14 Ld SOIC MDP0027 EL5410CS-T13* 5410CS 14 Ld SOIC MDP0027 EL5410CSZ (Note) 5410CSZ 14 Ld SOIC (Pb-free) MDP0027 EL5410CSZ-T7* (Note) 5410CSZ 14 Ld SOIC (Pb-free) MDP0027 EL5410CSZ-T13* (Note) 5410CSZ 14 Ld SOIC (Pb-free) MDP0027 EL5410CR 5410CR 14 Ld TSSOP MDP0044 EL5410CR-T7* 5410CR 14 Ld TSSOP MDP0044 EL5410CR-T13* 5410CR 14 Ld TSSOP MDP0044 EL5410CRZ (Note) 5410CRZ 14 Ld TSSOP (Pb-free) M14.173 EL5410CRZ-T7* (Note) 5410CRZ 14 Ld TSSOP (Pb-free) M14.173 EL5410CRZ-T13* (Note) 5410CRZ 14 Ld TSSOP (Pb-free) M14.173 *“-T7” or “-T13” suffix is for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2 FN7185.3 July 5, 2007 EL5210, EL5410 Absolute Maximum Ratings (TA = +25°C) Thermal Information Supply Voltage between VS+ and VS- . . . . . . . . . . . . . . . . . . . .+18V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . VS- - 0.5V, VS + 0.5V Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 30mA Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Operating Temperature . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. Electrical Specifications PARAMETER VS+ = +5V, VS- = -5V, RL = 1kΩ and CL = 12pF to 0V, TA = +25°C unless otherwise specified. DESCRIPTION CONDITION MIN (Note 4) TYP MAX (Note 4) UNIT 3 15 mV INPUT CHARACTERISTICS VOS Input Offset Voltage TCVOS Average Offset Voltage Drift (Note 1) IB Input Bias Current RIN Input Impedance 1 GW CIN Input Capacitance 2 pF CMIR Common-Mode Input Range CMRR Common-Mode Rejection Ratio for VIN from -5.5V to 5.5V 50 70 dB AVOL Open-Loop Gain -4.5V ≤ VOUT ≤ 4.5V 65 80 dB VCM = 0V 7 VCM = 0V 2 -5.5 µV/°C 60 +5.5 nA V OUTPUT CHARACTERISTICS VOL Output Swing Low IL = -5mA VOH Output Swing High IL = 5mA ISC IOUT -4.9 4.8 -4.8 V 4.9 V Short Circuit Current ±120 mA Output Current ±30 mA 80 dB POWER SUPPLY PERFORMANCE PSRR Power Supply Rejection Ratio VS is moved from ±2.25V to ±7.75V IS Supply Current (Per Amplifier) No Load 2.5 60 3.75 mA DYNAMIC PERFORMANCE SR Slew Rate (Note 2) -4.0V ≤ VOUT ≤ 4.0V, 20% to 80% 33 V/µs tS Settling to +0.1% (AV = +1) (AV = +1), VO = 2V Step 140 ns BW -3dB Bandwidth 30 MHz GBWP Gain-Bandwidth Product 20 MHz PM Phase Margin 50 ° CS Channel Separation f = 5MHz 110 dB dG Differential Gain (Note 3) RF = RG = 1kΩ and VOUT = 1.4V 0.12 % dP Differential Phase (Note 3) RF = RG = 1kΩ and VOUT = 1.4V 0.17 ° 3 FN7185.3 July 5, 2007 EL5210, EL5410 Electrical Specifications PARAMETER VS+ = 5V, VS- = 0V, RL = 1kΩ and CL = 12pF to 2.5V, TA = +25°C unless otherwise specified. DESCRIPTION CONDITION MIN (Note 4) TYP MAX (Note 4) UNIT 3 15 mV INPUT CHARACTERISTICS VOS Input Offset Voltage TCVOS Average Offset Voltage Drift (Note 1) IB Input Bias Current RIN Input Impedance 1 GW CIN Input Capacitance 2 pF CMIR Common-Mode Input Range CMRR Common-Mode Rejection Ratio for VIN from -0.5V to 5.5V 45 66 dB AVOL Open-Loop Gain 0.5V ≤ VOUT ≤ 4.5V 65 80 dB VCM = 2.5V 7 VCM = 2.5V 2 -0.5 µV/°C 60 +5.5 nA V OUTPUT CHARACTERISTICS VOL Output Swing Low IL = -5mA VOH Output Swing High IL = 5mA ISC IOUT 100 4.8 200 mV 4.9 V Short Circuit Current ±120 mA Output Current ±30 mA 80 dB POWER SUPPLY PERFORMANCE PSRR Power Supply Rejection Ratio VS is moved from 4.5V to 15.5V IS Supply Current (Per Amplifier) No Load 2.5 60 3.75 mA DYNAMIC PERFORMANCE SR Slew Rate (Note 2) 1V ≤ VOUT ≤ 4V, 20% to 80% 33 V/µs tS Settling to +0.1% (AV = +1) (AV = +1), VO = 2V Step 140 ns BW -3dB Bandwidth 30 MHz GBWP Gain-Bandwidth Product 20 MHz PM Phase Margin 50 ° CS Channel Separation f = 5MHz 110 dB dG Differential Gain (Note 3) RF = RG = 1kΩ and VOUT = 1.4V 0.30 % dP Differential Phase (Note 3) RF = RG = 1kΩ and VOUT = 1.4V 0.66 ° 4 FN7185.3 July 5, 2007 EL5210, EL5410 Electrical Specifications PARAMETER VS+ = 15V, VS- = 0V, RL = 1kΩ and CL = 12pF to 7.5V, TA = +25°C unless otherwise specified. DESCRIPTION CONDITION MIN (Note 4) TYP MAX (Note 4) UNIT 3 15 mV INPUT CHARACTERISTICS VOS Input Offset Voltage TCVOS Average Offset Voltage Drift (Note 1) IB Input Bias Current RIN Input Impedance 1 GW CIN Input Capacitance 2 pF CMIR Common-Mode Input Range CMRR Common-Mode Rejection Ratio for VIN from -0.5V to 15.5V 53 72 dB AVOL Open-Loop Gain 0.5V ≤ VOUT ≤ 14.5V 65 80 dB VCM = 7.5V 7 VCM = 7.5V 2 -0.5 µV/°C 60 +15.5 nA V OUTPUT CHARACTERISTICS VOL Output Swing Low IL = -7.5mA VOH Output Swing High IL = 7.5mA ISC IOUT 170 14.65 350 mV 14.83 V Short Circuit Current ±120 mA Output Current ±30 mA 80 dB POWER SUPPLY PERFORMANCE PSRR Power Supply Rejection Ratio VS is moved from 4.5V to 15.5V IS Supply Current (Per Amplifier) No Load 2.5 60 3.75 mA DYNAMIC PERFORMANCE SR Slew Rate (Note 2) 1V ≤ VOUT ≤ 14V, 20% to 80% 33 V/µs tS Settling to +0.1% (AV = +1) (AV = +1), VO = 2V Step 140 ns BW -3dB Bandwidth 30 MHz GBWP Gain-Bandwidth Product 20 MHz PM Phase Margin 50 ° CS Channel Separation f = 5MHz 110 dB dG Differential Gain (Note 3) RF = RG = 1kΩ and VOUT = 1.4V 0.10 % dP Differential Phase (Note 3) RF = RG = 1kΩ and VOUT = 1.4V 0.11 ° NOTES: 1. Measured over operating temperature range 2. Slew rate is measured on rising and falling edges 3. NTSC signal generator used 4. Parts are 100% tested at +25°C. Over temperature limits established by characterization and are not production tested. 5 FN7185.3 July 5, 2007 EL5210, EL5410 Typical Performance Curves EL5410 Input Offset Voltage Drift EL5410 Input Offset Voltage Distribution 25 15 21 19 17 13 11 Input Offset Voltage Drift, TCVOS (µV/°C) Input Bias Current vs Temperature Input Offset Voltage vs Temperature 0.008 4 0.004 Input Bias Current (µA) 5 3 2 1 VS=±5V 0 -0.004 -0.008 0 -50 -10 30 70 110 -0.012 -50 150 -10 Temperature (°C) 70 110 150 110 150 Output Low Voltage vs Temperature -4.85 4.96 -4.87 Output Low Voltage (V) 4.95 VS=±5V IOUT=5mA 4.94 4.93 VS=±5V IOUT=5mA -4.89 -4.91 -4.93 4.92 4.91 -50 30 Temperature (°C) Output High Voltage vs Temperature Output High Voltage (V) 9 1 12 8 10 6 4 2 -0 -2 -4 0 -6 0 -8 5 -10 100 7 10 5 Quantity (Amplifiers) 200 -12 Quantity (Amplifiers) 300 Input Offset Voltage (mV) Input Offset Voltage (mV) Typical Production Distortion 20 3 VS=±5V TA=25°C 400 VS=±5V Typical Production Distortion 15 500 -10 30 70 Temperature (°C) 6 110 150 -4.95 -50 -10 30 70 Temperature (°C) FN7185.3 July 5, 2007 EL5210, EL5410 Typical Performance Curves (Continued) Open-Loop Gain vs Temperature Slew Rate vs Temperature 33.85 90 Slew Rate (V/µS) Open-Loop Gain (dB) 33.80 VS=±5V RL=1kΩ 85 80 VS=±5V 33.75 33.70 33.65 75 33.60 70 -50 -10 30 70 110 33.55 -40 150 0 2.9 TA=25°C 160 VS=±5V 2.65 2.5 Supply Current (mA) Supply Current (mA) 120 2.7 2.7 2.3 2.1 1.9 2.6 2.55 2.5 2.45 1.7 2.4 -50 1.5 4 8 12 16 20 -10 Supply Voltage (V) 30 70 110 150 8 10 Temperature (°C) Differential Gain and Phase Harmonic Distortion vs VOP-P -30 0.25 VS=±5V AV=2 RL=1kΩ 0.15 VS=±5V AV=1 RL=1k FIN = 1MHz -40 0.05 -0.05 0 100 200 0.20 0.10 Distortion (dB) Diff Gain (%) 80 EL5410 Supply Current per Amplifier vs Temperature EL5410 Supply Current per Amplifier vs Supply Voltage Diff Phase (°) 40 Temperature (°C) Temperature (°C) HD3 -50 HD2 -60 -70 0 -0.10 -80 0 100 IRE 7 200 0 2 4 6 VOP-P (V) FN7185.3 July 5, 2007 EL5210, EL5410 Typical Performance Curves (Continued) Open Loop Gain and Phase vs Frequency Frequency Response for Various RL 140 250 5 150 3 Phase 20 -50 Gain VS=±5V TA=25°C RL=1kΩ to GND CL=12pF to GND -20 -150 Magnitude (Normalized) (dB) 50 60 10kΩ Phase (°) Gain (dB) 100 -250 -60 10 100 10k 1k 100k 1M 10M 1kΩ 1 560Ω 0 -1 AV=1 VS=±5V CL=12pF -3 150Ω -5 100M 1M 100k Closed Loop Output Impedance vs Frequency Frequency Response for Various CL 20 200 AV=1 VS=±5V TA=25°C 1000pF 10 160 47pF 0 Output Impedance (Ω) Magnitude (Normalized) (dB) 100pF 10pF -10 RL=1kΩ AV=1 VS=±5V -20 -30 100k 120 80 40 1M 10M 0 10k 100M 100k Maximum Output Swing vs Frequency 8 70 6 60 0 10k CMRR (dB) 80 2 10M 30M CMRR vs Frequency 10 4 1M Frequency (Hz) Frequency (Hz) Maximum Output Swing (VP-P) 100M 10M Frequency (Hz) Frequency (Hz) VS=±5V TA=25°C AV=1 RL=1kΩ CL=12pF Distortion <1% 50 VS=±5V TA=25°C 40 30 100k 1M Frequency (Hz) 8 10M 10 100 1k 10k 100k 1M 10M 30M Frequency (Hz) FN7185.3 July 5, 2007 EL5210, EL5410 Typical Performance Curves (Continued) Input Voltage Noise Spectral Density vs Frequency PSRR vs Frequency 80 1000 PSRR+ PSRR (dB) Voltage Noise (nV/√Hz) PSRR- 60 40 VS=±5V TA=25°C 20 100 10 1 0 100 1k 10k 100k 1M 100 10M 1k 0.010 -60 0.008 -80 0.006 -100 XTalk (dB) THD+ N (%) 10M 100M Channel Separation vs Frequency Response 0.004 VS=±5V RL=1kΩ AV=1 VIN=0.5VRMS Dual measured Channel A to B Quad measured Channel A to D or B to C Other combinations yield improved rejection -120 VS=±5V RL=1kΩ AV=1 VIN=110mVRMS -140 0 -160 1k 10k 1k 100k 10k Small-Signal Overshoot vs Load Capacitance 1M 10M 30M Settling Time vs Step Size 5 100 VS=±5V AV=1 RL=1kΩ VIN=±50mV TA=25°C 4 3 2 Step Size (V) 80 100k Frequency (Hz) Frequency (Hz) Overshoot (%) 1M Frequency (Hz) Total Harmonic Distortion + Noise vs Frequency 0.002 100k 10k Frequency (Hz) 60 40 VS=±5V AV=1 RL=1k CL=12pF TA=25°C 0.1% 1 0 -1 -2 0.1% -3 20 -4 0 10 100 Load Capacitance (pF) 9 1000 -5 70 90 110 130 150 170 190 210 230 Settling Time (ns) FN7185.3 July 5, 2007 EL5210, EL5410 Typical Performance Curves (Continued) Large Signal Transient Response 1V Small Signal Transient Response 200ns 50mV 100ns VS=±5V TA=25°C AV=1 RL=1kΩ CL=12pF VS=±5V TA=25°C AV=1 RL=1kΩ CL=12pF Pin Descriptions EL5210 EL5410 Name 1 1 VOUTA Function Equivalent Circuit Amplifier A Output VS+ VS- GND Circuit 1 2 2 VINA- Amplifier A Inverting Input VS+ VSCircuit 2 3 3 VINA+ 8 4 VS+ 5 5 VINB+ Amplifier B Non-Inverting Input (Reference Circuit 2) 6 6 VINB- Amplifier B Inverting Input (Reference Circuit 2) 7 7 VOUTB Amplifier B Output (Reference Circuit 1) 8 VOUTC Amplifier C Output (Reference Circuit 1) 9 VINC- Amplifier C Inverting Input (Reference Circuit 2) 10 VINC+ Amplifier C Non-Inverting Input (Reference Circuit 2) 11 VS- 12 VIND+ Amplifier D Non-Inverting Input (Reference Circuit 2) 13 VIND- Amplifier D Inverting Input (Reference Circuit 2) 14 VOUTD Amplifier D Output (Reference Circuit 1) 4 10 Amplifier A Non-Inverting Input (Reference Circuit 2) Positive Power Supply Negative Power Supply FN7185.3 July 5, 2007 EL5210, EL5410 Applications Information continuous current never exceeds ±30mA. This limit is set by the design of the internal metal interconnects. Product Description The EL5210 and EL5410 voltage feedback amplifiers are fabricated using a high voltage CMOS process. They exhibit Rail-to-Rail input and output capability, are unity gain stable and have low power consumption (2.5mA per amplifier). These features make the EL5210 and EL5410 ideal for a wide range of general-purpose applications. Connected in voltage follower mode and driving a load of 1kΩ and 12pF, the EL5210 and EL5410 have a -3dB bandwidth of 30MHz while maintaining a 33V/µS slew rate. The EL5210 is a dual amplifier while the EL5410 is a quad amplifier. Output Phase Reversal The EL5210 and EL5410 are immune to phase reversal as long as the input voltage is limited from VS- -0.5V to VS+ +0.5V. Figure 2 shows a photo of the output of the device with the input voltage driven beyond the supply rails. Although the device's output will not change phase, the input's overvoltage should be avoided. If an input voltage exceeds supply voltage by more than 0.6V, electrostatic protection diodes placed in the input stage of the device begin to conduct and overvoltage damage could occur. Operating Voltage, Input, and Output 1V 10µs The EL5210 and EL5410 are specified with a single nominal supply voltage from 5V to 15V or a split supply with its total range from 5V to 15V. Correct operation is guaranteed for a supply range of 4.5V to 16.5V. Most EL5210 and EL5410 specifications are stable over both the full supply range and operating temperatures of -40°C to +85°C. Parameter variations with operating voltage and/or temperature are shown in the typical performance curves. The input common-mode voltage range of the EL5210 and EL5410 extends 500mV beyond the supply rails. The output swings of the EL5210 and EL5410 typically extend to within 100mV of positive and negative supply rails with load currents of 5mA. Decreasing load currents will extend the output voltage range even closer to the supply rails. Figure 1 shows the input and output waveforms for the device in the unity-gain configuration. Operation is from ±5V supply with a 1kΩ load connected to GND. The input is a 10VP-P sinusoid. The output voltage is approximately 9.8VP-P. 10µs 5V FIGURE 2. OPERATION WITH BEYOND-THE-RAILS INPUT Power Dissipation With the high-output drive capability of the EL5210 and EL5410 amplifiers, it is possible to exceed the 125°C 'absolute-maximum junction temperature' under certain load current conditions. Therefore, it is important to calculate the maximum junction temperature for the application to determine if load conditions need to be modified for the amplifier to remain in the safe operating area. The maximum power dissipation allowed in a package is determined according to: Output VS=±5V TA=25°C AV=1 VIN=10VP-P 1V T JMAX – T AMAX P DMAX = --------------------------------------------Θ JA Input 5V VS=±2.5V TA=25°C AV=1 VIN=6VP-P Where: TJMAX = Maximum Junction Temperature TAMAX= Maximum Ambient Temperature FIGURE 1. OPERATION WITH RAIL-TO-RAIL INPUT AND OUTPUT Short Circuit Current Limit The EL5210 and EL5410 will limit the short circuit current to ±120mA if the output is directly shorted to the positive or the negative supply. If an output is shorted indefinitely, the power dissipation could easily increase such that the device may be damaged. Maximum reliability is maintained if the output 11 ΘJA = Thermal Resistance of the Package PDMAX = Maximum Power Dissipation in the Package. The maximum power dissipation actually produced by an IC is the total quiescent supply current times the total power supply voltage, plus the power in the IC due to the loads, or: P DMAX = Σi [ V S × I SMAX + ( V S + – V OUT i ) × I LOAD i ] FN7185.3 July 5, 2007 EL5210, EL5410 when sourcing, and Packages Mounted on a JEDEC JESD51-3 Low Effective Thermal Conductivity Test Board P DMAX = Σi [ V S × I SMAX + ( V OUT i – V S - ) × I LOAD i ] 1200 MAX TJ=125°C 1000 Power Dissipation (mW) when sinking. Where: i = 1 to 2 for Dual and 1 to 4 for Quad VS = Total Supply Voltage ISMAX = Maximum Supply Current Per Amplifier 800 606mW 600 625mW SO8 θJA=160°C/W 200 MSOP8 θJA=206°C/W 0 ILOADi = Load current 0 If we set the two PDMAX equations equal to each other, we can solve for RLOADi to avoid device overheat. Figure 3 and Figure 4 provide a convenient way to see if the device will overheat. The maximum safe power dissipation can be found graphically, based on the package type and the ambient temperature. By using the previous equation, it is a simple matter to see if PDMAX exceeds the device's power derating curves. To ensure proper operation, it is important to observe the recommended derating curves shown in Figure 3 and Figure 4. Packages Mounted on a JEDEC JESD51-7 High Effective Thermal Conductivity Test Board 1.136W Power Dissipation (mW) MAX TJ=125°C 1.0W 1000 909mW 833mW 800 600 SO14 θJA=88°C/W SO8 θJA=110°C/W 400 TSSOP14 θJA=100°C/W MSOP8 θJA=115°C/W 200 0 0 25 TSSOP14 θJA=165°C/W 485mW 400 VOUTi = Maximum Output Voltage of the Application 1200 SO14 θJA=120°C/W 833mW 75 85 50 100 125 150 Ambient Temperature (°C) FIGURE 3. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE 12 25 50 75 85 100 125 150 Ambient Temperature (°C) FIGURE 4. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE Unused Amplifiers It is recommended that any unused amplifiers in a dual and a quad package be configured as a unity gain follower. The inverting input should be directly connected to the output and the non-inverting input tied to the ground plane. Driving Capacitive Loads The EL5210 and EL5410 can drive a wide range of capacitive loads. As load capacitance increases, however, the -3dB bandwidth of the device will decrease and the peaking increase. The amplifiers drive 10pF loads in parallel with 1kΩ with just 1.2dB of peaking, and 100pF with 6.5dB of peaking. If less peaking is desired in these applications, a small series resistor (usually between 5Ω and 50Ω) can be placed in series with the output. However, this will obviously reduce the gain slightly. Another method of reducing peaking is to add a "snubber" circuit at the output. A snubber is a shunt load consisting of a resistor in series with a capacitor. Values of 150Ω and 10nF are typical. The advantage of a snubber is that it does not draw any DC load current or reduce the gain. Power Supply Bypassing and Printed Circuit Board Layout The EL5210 and EL5410 can provide gain at high frequency. As with any high-frequency device, good printed circuit board layout is necessary for optimum performance. Ground plane construction is highly recommended, lead lengths should be as short as possible and the power supply pins must be well bypassed to reduce the risk of oscillation. For normal single supply operation, where the VS- pin is connected to ground, a 0.1µF ceramic capacitor should be placed from VS+ to pin to VS- pin. A 4.7µF tantalum capacitor should then be connected in parallel, placed in the region of the amplifier. One 4.7µF capacitor may be used for multiple devices. This same capacitor combination should be placed at each supply pin to ground if split supplies are to be used. FN7185.3 July 5, 2007 EL5210, EL5410 Small Outline Package Family (SO) A D h X 45° (N/2)+1 N A PIN #1 I.D. MARK E1 E c SEE DETAIL “X” 1 (N/2) B L1 0.010 M C A B e H C A2 GAUGE PLANE SEATING PLANE A1 0.004 C 0.010 M C A B L b 0.010 4° ±4° DETAIL X MDP0027 SMALL OUTLINE PACKAGE FAMILY (SO) INCHES SYMBOL SO-14 SO16 (0.300”) (SOL-16) SO20 (SOL-20) SO24 (SOL-24) SO28 (SOL-28) TOLERANCE NOTES A 0.068 0.068 0.068 0.104 0.104 0.104 0.104 MAX - A1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 ±0.003 - A2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 ±0.002 - b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 ±0.003 - c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 ±0.001 - D 0.193 0.341 0.390 0.406 0.504 0.606 0.704 ±0.004 1, 3 E 0.236 0.236 0.236 0.406 0.406 0.406 0.406 ±0.008 - E1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 ±0.004 2, 3 e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 Basic - L 0.025 0.025 0.025 0.030 0.030 0.030 0.030 ±0.009 - L1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 Basic - h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 Reference - 16 20 24 28 Reference - N SO-8 SO16 (0.150”) 8 14 16 Rev. M 2/07 NOTES: 1. Plastic or metal protrusions of 0.006” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994 13 FN7185.3 July 5, 2007 EL5210, EL5410 Mini SO Package Family (MSOP) 0.25 M C A B D MINI SO PACKAGE FAMILY (N/2)+1 N E MDP0043 A E1 MILLIMETERS PIN #1 I.D. 1 B (N/2) e H C SEATING PLANE 0.10 C N LEADS SYMBOL MSOP8 MSOP10 TOLERANCE NOTES A 1.10 1.10 Max. - A1 0.10 0.10 ±0.05 - A2 0.86 0.86 ±0.09 - b 0.33 0.23 +0.07/-0.08 - c 0.18 0.18 ±0.05 - D 3.00 3.00 ±0.10 1, 3 E 4.90 4.90 ±0.15 - E1 3.00 3.00 ±0.10 2, 3 e 0.65 0.50 Basic - L 0.55 0.55 ±0.15 - L1 0.95 0.95 Basic - N 8 10 Reference - 0.08 M C A B b Rev. D 2/07 NOTES: 1. Plastic or metal protrusions of 0.15mm maximum per side are not included. L1 2. Plastic interlead protrusions of 0.25mm maximum per side are not included. A 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. c SEE DETAIL "X" A2 GAUGE PLANE L A1 0.25 3° ±3° DETAIL X 14 FN7185.3 July 5, 2007 EL5210, EL5410 Thin Shrink Small Outline Package Family (TSSOP) MDP0044 0.25 M C A B D THIN SHRINK SMALL OUTLINE PACKAGE FAMILY A (N/2)+1 N MILLIMETERS SYMBOL 14 LD 16 LD 20 LD 24 LD 28 LD TOLERANCE PIN #1 I.D. E E1 1 (N/2) B 0.20 C B A 2X N/2 LEAD TIPS TOP VIEW 0.05 e C SEATING PLANE H A 1.20 1.20 1.20 1.20 1.20 Max A1 0.10 0.10 0.10 0.10 0.10 ±0.05 A2 0.90 0.90 0.90 0.90 0.90 ±0.05 b 0.25 0.25 0.25 0.25 0.25 +0.05/-0.06 c 0.15 0.15 0.15 0.15 0.15 +0.05/-0.06 D 5.00 5.00 6.50 7.80 9.70 ±0.10 E 6.40 6.40 6.40 6.40 6.40 Basic E1 4.40 4.40 4.40 4.40 4.40 ±0.10 e 0.65 0.65 0.65 0.65 0.65 Basic L 0.60 0.60 0.60 0.60 0.60 ±0.15 L1 1.00 1.00 1.00 1.00 1.00 Reference Rev. F 2/07 0.10 M C A B b 0.10 C N LEADS SIDE VIEW NOTES: 1. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15mm per side. 2. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm per side. SEE DETAIL “X” 3. Dimensions “D” and “E1” are measured at dAtum Plane H. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. c END VIEW L1 A A2 GAUGE PLANE 0.25 L A1 0° - 8° DETAIL X 15 FN7185.3 July 5, 2007 EL5210, EL5410 Thin Shrink Small Outline Plastic Packages (TSSOP) M14.173 N INDEX AREA E 0.25(0.010) M E1 2 SYMBOL 3 0.05(0.002) -A- INCHES GAUGE PLANE -B1 14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE B M 0.25 0.010 SEATING PLANE L A D -C- α e A1 b A2 c 0.10(0.004) 0.10(0.004) M C A M B S MIN 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AC, Issue E. MILLIMETERS MIN MAX NOTES A - 0.047 - 1.20 - A1 0.002 0.006 0.05 0.15 - A2 0.031 0.041 0.80 1.05 - b 0.0075 0.0118 0.19 0.30 9 c 0.0035 0.0079 0.09 0.20 - D 0.195 0.199 4.95 5.05 3 E1 0.169 0.177 4.30 4.50 4 e 0.026 BSC 0.65 BSC - E 0.246 0.256 6.25 6.50 - L 0.0177 0.0295 0.45 0.75 6 8o 0o N NOTES: MAX α 14 0o 14 7 8o Rev. 2 4/06 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees) All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 16 FN7185.3 July 5, 2007