AD AD9389KSTZ-80 800 mhz high performance hdmi/dvi transmitter Datasheet

800 MHz High Performance
HDMI™/DVI Transmitter
AD9389
HDMI/DVI transmitter compatible with HDMI 1.1 and
HDCP 1.1
Single 1.8 V power supply
Video/audio inputs are 3.3 V tolerant
Supports HDCP 1.1 with encrypted internal HDCP key
storage
80-lead LQFP
Digital video
80 MHz operation supports all video formats from 480i to
1080i and 720p
Programmable 2-way color space converter
Supports RGB, YCbCr, DDR, ITU656 formats
Auto input video format detection
Digital audio
Supports standard S/PDIF for stereo or compressed audio
up to 192 kHz
8-channel LPCM I2S audio up to 192 kHz
Special features for easy system design
On-chip MPU to perform HDCP operations
On-chip I2C® master to handle EDID reading
5 V tolerant I2C and MPD I/Os, no extra device needed
No audio master clock needed for S/PDIF support
FUNCTIONAL BLOCK DIAGRAM
HTPG
SCL SDA
REGISTER
CONFIGURATION
LOGIC
I2C
SLAVE
I2C
MASTER
HDCP
CONTROLLER
HDCP
CIPHER
HSYNC
Tx0[1:0]
VIDEO
DATA
CAPTURE
DE
D[23:0]
S/PDIF
MCLK
I2S[3:0]
DDCSCL
SWING_ADJ
CLK
VSYNC
DDSDA
Tx1[1:0]
COLOR
SPACE
CONVERSION
4:2:2
TO
4:4:4
CONVERSION
HDM
ITX
CORE
Tx2[1:0]
TxC[1:0]
XOR
MASK
AUDIO
DATA
CAPTURE
AD9389
05724-001
FEATURES
Figure 1.
APPLICATIONS
DVD players and recorders
Digital set-top boxes
AV receivers
Digital cameras and camcorders
GENERAL DESCRIPTION
The AD9389 is an 80 MHz high-definition multimedia interface (HDMI 1.1) transmitter. It supports HDTV formats up to
1080i and 720p, and graphic resolutions up to XGA (1024 × 768
@ 75 Hz). With the inclusion of HDCP, the AD9389 allows the
secure transmission of protected content as specified by the
HDCP 1.1 protocol.
The AD9389 supports both S/PDIF and 8-channel I2S audio.
Its high fidelity 8-channel I2S can transmit either stereo or
7.1 surround audio at 192 kHz. The S/PDIF can carry stereo
LPCM (linear pulse code modulation) audio or compressed
audio including Dolby® Digital, DTS®, and THX®.
The AD9389 helps to reduce system design complexity and cost
by incorporating such features as HDCP master, I2C master for
EDID reading, a single 1.8 V power supply, and 5 V tolerance
on I2C and hot plug detect pins.
Fabricated in an advanced CMOS process, the AD9389 is provided in a space-saving, 80-lead, surface-mount, Pb-free plastic
LQFP and is specified over the 0°C to 70°C temperature range.
EVALUATION KITS AND OTHER RESOURCES
Evaluation kits, reference design schematics, software quick
start guide, and codes are available from the Analog Devices
local sales and marketing personnel.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
AD9389
TABLE OF CONTENTS
Features .............................................................................................. 1
I2S Audio...................................................................................... 16
Applications....................................................................................... 1
S/PDIF Audio.............................................................................. 16
Functional Block Diagram .............................................................. 1
CTS Generation.......................................................................... 16
General Description ......................................................................... 1
N Parameter ................................................................................ 17
Evaluation Kits and Other Resources ............................................ 1
CTS Parameter............................................................................ 17
Revision History ............................................................................... 2
Packet Configuration ................................................................. 18
Electrical Specifications ................................................................... 3
Pixel Repetition .......................................................................... 18
Absolute Maximum Ratings............................................................ 5
HDCP Handling......................................................................... 19
Explanation of Test Levels ........................................................... 5
EDID Reading............................................................................. 19
ESD Caution.................................................................................. 5
Interrupts..................................................................................... 19
Pin Configuration and Function Descriptions............................. 6
Power Management ................................................................... 19
I2C Addresses ................................................................................ 8
2-Wire Serial Register Map ........................................................... 20
List of Reference Documents...................................................... 8
2-Wire Serial Control Register Detail Chip Identification ....... 33
Format Standards ......................................................................... 8
Source Product Description (SPD) Infoframe ....................... 37
Design Guide..................................................................................... 9
2-Wire Serial Control Port ............................................................ 40
General Description..................................................................... 9
Data Transfer via Serial Interface............................................. 40
Video Data Capture...................................................................... 9
Serial Interface Read/Write Examples ..................................... 41
Input Formats................................................................................ 9
PCB Layout Recommendations.................................................... 42
4:2:2 to 4:4:4 Data Conversion.................................................. 14
Power Supply Bypassing ............................................................ 42
Horizontal Sync, Vertical Sync, and DE Generation ............. 14
Digital Inputs .............................................................................. 42
DE Generation ............................................................................ 14
Color Space Converter (CSC) Common Settings...................... 43
Hsync and Vsync Generation ................................................... 14
Outline Dimensions ....................................................................... 45
Color Space Conversion Matrix (CSC) ................................... 15
Ordering Guide .......................................................................... 45
Audio Data Capture ....................................................................... 16
REVISION HISTORY
1/06—Revision 0: Initial Version
Rev. 0 | Page 2 of 48
AD9389
ELECTRICAL SPECIFICATIONS
Table 1.
Parameter
DIGITAL INPUTS
Input Voltage, High (VIH)
Input Voltage, Low (VIL)
Input Current, High (VIH)
Input Current, Low (VIL)
Input Capacitance
DIGITAL OUTPUTS
Output Voltage, High (VOH)
Output Voltage, Low (VOL)
THERMAL CHARACTERISTICS
θJC Junction-to-Case
Thermal Resistance
θJA Junction-to-Ambient
Thermal Resistance
Ambient Temperature
DC SPECIFICATIONS
Input Leakage Current, IIL
Input Clamp Voltage (−16 mA)
Input Clamp Voltage (+16 mA)
Differential High Level Output Voltage
Differential Output Short-Circuit Current
POWER SUPPLY
VDD (All) Supply Voltage
VDD Supply Voltage Noise
Complete Power-Down Current
(Everything Except I2C)
Quiet Power Down Current
(Monitor Detect On)
Transmitter Supply Current
(27 MHz Typical Random Pattern)
Transmitter Supply Current
(80 MHz Typical Random Pattern)
Transmitter Total Power
(80 MHz Single Pixel Stripe Pattern; Worst
Case Operating Conditions)
AC SPECIFICATIONS
CLK Frequency
CLK Duty Cycle
Worst Case CLK Input Jitter
Setup Time to CLK Falling Edge
Hold Time to CLK Falling Edge
TMDS Differential Swing
VSYNC and HSYNC Delay from DE Falling Edge
VSYNC and HSYNC Delay to DE Rising Edge
DE High Time
DE Low Time
Differential Output Swing Low-to-High
Transition Time
Differential Swing Output High-to-Low
Transition Time
Temp
Test Level 1
Min
Full
Full
Full
Full
25°C
VI
VI
V
V
V
1.4
Full
Full
VI
VI
AVDD − 0.1
Typ
25°C
25°C
25°C
V
V
Unit
0.7
−1.0
+1.0
V
V
mA
mA
pF
3
V
Full
Max
0
25
0.4
V
V
25
°C/W
30
70
°C/W
°C
+10
μA
V
VI
V
V
V
V
−10
Full
Full
25°C
IV
V
IV
1.71
25°C
VI
7
mA
25°C
VI
165
mA
25°C
IV
185
Full
VI
25°C
25°C
Full
25°C
25°C
25°C
IV
VII
VI
VI
VI
VII
VI
VI
VI
VI
VII
75
25°C
VII
75
Rev. 0 | Page 3 of 48
−0.8
+0.8
AVCC
1.8
6
13.5
40
TBD
TBD
800
1000
1
1
10
V
μA
1.89
50
13
V
mV p-p
mA
205
mA
430
mW
80
60
1.0
TBD
TBD
1200
490
MHz
%
ns
ns
ns
mV
UI
UI
UI
UI
ps
490
ps
8191
138
AD9389
Parameter
AUDIO AC TIMING
Sample Rate (I2S and S/PDIF)
I2S Cycle Time
I2S Setup Time
I2S Hold Time
Audio Pipeline Delay
1
Temp
Test Level 1
Min
Full
25°C
25°C
25°C
25°C
IV
IV
IV
IV
IV
32
See Table 3.
Rev. 0 | Page 4 of 48
Typ
15
0
75
Max
Unit
192
1
kHz
UI
ns
ns
μs
AD9389
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Digital Inputs
Digital Output Current
Operating Temperature Range
Storage Temperature Range
Maximum Junction Temperature
Maximum Case Temperature
Rating
5 V to 0.0 V
20 mA
−40°C to +85°C
−65°C to +150°C
150°C
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
EXPLANATION OF TEST LEVELS
Table 3.
Level
Test
I
100% production tested.
II
100% production tested at 25°C and sample tested at
specified temperatures.
Sample tested only.
III
IV
V
VI
VII
Parameter is guaranteed by design and characterization
testing.
Parameter is a typical value only.
100% production tested at 25°C; guaranteed by design
and characterization testing.
Limits defined by HDMI specification.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 5 of 48
AD9389
DVDD
DVDD
DVDD
DVDD
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
GND
GND
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
60
GND
59
GND
DE 3
58
D15
HSYNC 4
57
D16
VSYNC 5
56
D17
CLK 6
55
D18
S/PDIF 7
54
D19
53
D20
52
D21
I2S1 10
51
D22
I2S2 11
50
D23
I2S3 12
49
NC
SCLK 13
48
NC
LRCLK 14
47
SDA
GND 15
46
SCL
PVDD 16
45
DDSDA
GND 17
44
DDCSCL
GND 18
43
GND
PVDD 19
42
GND
PVDD 20
41
AVDD
DVDD 1
PIN 1
D0 2
AD9389
MCLK 8
TOP VIEW
(Not to Scale)
I2S0 9
05724-002
INT
GND
Tx2+
Tx2–
AVDD
Tx1+
Tx1–
PD/A0
GND
Tx0+
Tx0–
AVDD
TxC+
TxC–
GND
HPD
AVDD
EXT_SW
GND
PVDD
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Figure 2. Pin Configuration
Table 4. Complete Pinout List
Pin Type
INPUTS
Pin No.
50 to 58,
65 to 78, 2
6
3
4
5
23
25
7
8
12 to 9
13
14
33
Mnemonic
Description
Value
D[23:0]
Video Data Input
1.8 V CMOS
CLK
DE
HSYNC
VSYNC
EXT_SW
HPD
S/PDIF
MCLK
I2S[3:0]
SCLK
LRCLK
PD/A0
Video Clock Input
Data Enable Bit for Digital Video
Horizontal SYNC Input
Vertical SYNC Input
Differential Output Swing Adjustment
Hot Plug Detect Signal
S/PDIF (Sony/Philips Digital Interface) Audio Input Pin
Audio Reference Clock, from 128 × fS to 512 × fS
I2S Audio Data Inputs
I2S Audio Clock
Left/Right Channel Selection
Power-Down Control
1.8 V CMOS
1.8 V CMOS
1.8 V CMOS
1.8 V CMOS
1.8 V CMOS
1.8 V CMOS
1.8 V CMOS
1.8 V CMOS
1.8 V CMOS
1.8 V CMOS
1.8 V CMOS
1.8 V CMOS
TxC+
TxC−
Tx2+
Tx2−
Tx1+
Tx1−
Differential Clock Output
Differential Clock Output Complement
Differential Output Channel 2
Differential Output Channel 2 Complement
Differential Output Channel 1
Differential Output Channel 1 Complement
TMDS
OUTPUTS
28, 27
38, 37
35, 34
Rev. 0 | Page 6 of 48
TMDS
TMDS
AD9389
Pin Type
Pin No.
31, 30
Mnemonic
Tx0+
Tx0−
INT
Description
Differential Output Channel 0
Differential Output Channel 0 Complement
Interrupt
Value
TMDS
24, 29, 36, 41
1, 61, 62, 63, 64
16, 19, 20, 21
15, 17, 18, 22,
26, 32, 39, 42,
43, 59, 60, 79,
80
AVDD
DVDD
PVDD
GND
Output Power Supply
Digital and I/O Power Supply
PLL Power Supply
Ground
1.8 V
1.8 V
1.8 V
0V
47
46
45
44
48, 49
SDA
SCL
DDSDA
DDCSCL
NC
Serial Port Data I/O
Serial Port Data Clock (100 kHz Maximum)
Serial Port Data I/O to Receiver
Serial Port Data Clock to Receiver
No Connect.
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
40
1.8 V CMOS
POWER SUPPLY
CONTROL
NO CONNECT
Table 5. Pin Function Descriptions
Pin Mnemonic
OUTPUTS
TxC+
TxC−
Tx2+
Tx2−
Tx1+
Tx1−
Tx0+
Tx0−
INT
SERIAL PORT (2-WIRE)
SDA
SCL
DDSDA
DDCSCL
INPUTS
D[23:0]
CLK
DE
HSYNC
VSYNC
EXT_SW
HPD
S/PDIF
MCLK
I2S[3:0]
I2S CLK
LRCLK
PD/A0
Description
Differential Clock Output at Pixel Clock Rate; Transition Minimized Differential Signaling (TMDS).
Differential Clock Output Complement.
Differential Output of the Red Data at 10× the Pixel Clock Rate; TMDS.
Differential Red Output Complement.
Differential Output of the Green Data at 10× the Pixel Clock Rate; TMDS.
Differential Green Output Complement.
Differential Output of the Blue Data at 10× the Pixel Clock Rate; TMDS.
Differential Blue Output Complement.
Interrupt.
Serial Port Data I/O.
Serial Port Data Clock.
Serial Port Data I/O Master to Receiver.
Serial Port Data Clock Master to Receiver.
For a full, functional description of the 2-wire serial register, refer to the 2-Wire Serial Control Port section.
Digital Input in RGB or YCbCr Format.
Video Clock Input.
Data Enable for Video Data.
Horizontal Sync Input.
Vertical Sync Input. This is the input for vertical sync.
Place an 887 Ω resistor (1% tolerance) between this pin and ground.
Hot Plug Detect. This indicates to the interface whether the receiver is connected.
S/PDIF Audio Input. This is the audio input from a Sony/Philips Digital Interface.
Audio Reference Clock. Can be set from 128 × fS to 512 × fS.
I2S Audio Inputs. These represent the eight channels of audio (two per input) available through I2S.
I2S Audio Clock.
Left/Right Channel Selection.
Power Down.
Rev. 0 | Page 7 of 48
AD9389
Pin Mnemonic
Description
POWER SUPPLY
DVDD
AVDD
PVDD
GND
Main Power Supply. These pins supply power to the main elements of the circuit. They should be filtered and as
quiet as possible.
Output Power Supply.
Clock Generator Power Supply. The most sensitive portion of the AD9389 is the clock generation circuitry. These
pins provide power to the clock PLL (phase-locked loop) and help the user design for optimal performance. The
designer should provide quiet, noise-free power to these pins.
Ground. The ground return for all circuitry on-chip. It is recommended that the AD9389 be assembled on a single
solid ground plane, with careful attention given to ground current paths.
I2C ADDRESSES
The SDA/SCL programming address can be 0x72 or 0x7A based on whether the PD/A0 pin is pulled high (10 kΩ resistor = 0x7A) or
pulled low (10 kΩ resistor = 0x72).
The EDID EEPROM on the receiver is expected to have an address of 0xA0.
LIST OF REFERENCE DOCUMENTS
Table 6.
Document
EIA/CEA-861B
HDMI v1.1
HDCPv1.1
ITU-R BT.656-3
Description
Describes audio and video infoframes as well as the E-EDID structure for HDMI.
Defining document for HDMI Version 1.1. Can be located at www.hdmi.org.
Defining document for HDCP Version 1.1. Can be located at www.digital-cp.com.
Defining document for BT656.
FORMAT STANDARDS
In this document, data is represented in a variety of ways.
Table 7.
Data Type
0xNN
0bNN
NN
Bit
Format
Hexadecimal (base-16) numbers are represented using the C language notation, preceded by 0x.
Binary (base-2) numbers are represented using the C language notation, preceded by 0b.
Decimal (base-10) numbers are represented using no additional prefixes or suffixes.
Bits are numbered in little-endian format, that is, the least significant bit (LSB) of a byte or word is referred to as Bit 0.
Rev. 0 | Page 8 of 48
AD9389
DESIGN GUIDE
Table 8. Input Formats Supported
GENERAL DESCRIPTION
The AD9389 HDMI transmitter provides a high bandwidth digital
content protected (HDCP) digital link between a wide range of
digital input formats—both audio and video (see Table 8) and
output formats (see Table 9). Video and audio data are captured
and prepared for transmission while two separate I2C buses (one of
which is a master) are used to program and provide content
protection for the data to be transmitted.
VIDEO DATA CAPTURE
The AD9389 can accept video data from as few as eight pins
(YCbCr DDR) representing 8-bit data or as many as 24 pins
representing 12-bit data. The AD9389 is capable of detecting
all of the 34 video formats defined in the EIA/CEA-861B
specification. If video ID (VID) 32, 33, or 34 is present, the user
needs to set Register 0x15[0] to 0b1, as these modes have VREF
frequencies of 30 Hz or less. The user can read the detected
video format at 0x3E[7:2]. Formats outside the EIA/CEA-861B
specification can be read in 0x3F[7:5]. Detailed line count
differences for 240p and 288p modes can be read from
0x3F[4:3]. In order to distinguish between an aspect ratio of 4:3
and one of 16:9, 0x17[1] should be set accordingly.
No. of Bits
12
12
24
24
16
20
24
8
10
12
8
10
12
Input Format
RGB (DDR)
YCbCr 4:4:4 (DDR)
RGB 4:4:4
YCbCr 4:4:4
YCbCr 4:2:2 (ITU.601)
YCbCr 4:2:2 (ITU.601)
YCbCr 4:2:2 (ITU.601)
YCbCr (DDR)
YCbCr (DDR)
YCbCr (DDR)
YCbCr 4:2:2 (ITU.656)
YCbCr 4:2:2 (ITU.656)
YCbCr 4:2:2 (ITU.656)
Table 9. Output Formats Supported
No. of Bits
24
24
16
20
24
Output Format
RGB 4:4:4
YCbCr 4:4:4
YCbCr 4:2:2
YCbCr 4:2:2
YCbCr 4:2:2
INPUT FORMATS
tSETUP
INPUT CLOCKRISING EDGE
tHOLD
INPUT DATA:
D(23:0), DE, SYNCS
tHOLD
tHOLD
05724-013
tSETUP
Figure 3. Timing for Data Input
Rev. 0 | Page 9 of 48
AD9389
Normal 4:4:4 Input Format (RGB or YCbCr) Input ID = 0
An input format of RGB 4:4:4 or YCbCr 4:4:4 can be selected by setting the input ID (0x15[3:1]) to 0b000. The input color space (CS)
must be selected by setting 0x16[0] to 0b0 for RGB or 0b1 for YCbCr. There is no need to set the input style (0x16[3:2]).
Table 10.
Input Format
RGB 4:4:4
YCbCr 4:4:4
23
22
21
20 19
R[7:0]
Cr[7:0]
18
17
16
15
Data[23:0]
14 13 12
G[7:0]
Y[7:0]
11
10
9
8
7
6
5
4 3 2
B[7:0]
Cb[7:0]
1
0
YCbCr 4:2:2 Formats (24 bits, 20 bits, or 16 bits) with Separate Sync, Input ID = 1
An input with YCbCr 4:2:2 with separate syncs can be selected by setting the Input ID (0x15[3:1]) to 0b001. The input CS (0x16[0]) must
be set to 0b1 for proper operation. The data bit width (24 bits, 20 bits, or 16 bits) must be set with 0x16[5:4]. The three input pin
assignment styles are shown in Table 11. The input style can be set in 0x16[3:2].
Table 11.
Input Format
23
22
YCbCr 4:2:2 Sep.
Sync (24 bit)
YCbCr 4:2:2 Sep.
Sync (20 bit)
YCbCr 4:2:2 Sep.
Sync (20 bit)
21
20
19
18
17
16
15 14
Style 1
Data[23:0]
13 12 11
Cb[11:4]
Cr[11:4]
Cb[9:2]
Cr[9:2]
Cb[7:0]
Cr[7:0]
10
Y[11:4]
Y[11:4]
Y[9:2]
Y[9:2]
Y[7:0]
Y[7:0]
Style 2
24-bit
20-bit
16-bit
24-bit
20-bit
16-bit
Cb[11:0]
Cr[11:0]
Cb[9:0]
Cr[9:0]
Cb[7:0]
Cr[7:0]
Y[11:0]
Y[11:0]
Y[9:0]
Y[9:0]
Y[7:0]
Y[7:0]
Y[11:0]
Y[11:0]
Y[9:0]
Y[9:0]
Y[7:0]
Y[7:0]
Style 3
Cb[11:0]
Cr[11:0]
Cb[9:0]
Cr[9:0]
Cb[7:0]
Cr[7:0]
Rev. 0 | Page 10 of 48
9
8
7
6
5
Cb[3:0]
Cr[3:0]
Cb[1:0]
Cr[1:0]
4
3
2
1
Y[3:0]
Y[3:0]
Y[1:0]
Y[1:0]
0
AD9389
YCbCr 4:2:2 Formats (24 bits, 20 bits, or 16 bits) with Embedded Syncs, Input ID = 2
An input with YCbCr 4:2:2 with embedded syncs can be selected by setting the input ID (0x15[3:1]) to 0b010. HSYNC and VSYNC are
embedded as Start of Active Video (SAV) and End of Active Video (EAV). The input CS (0x16[0]) must be set to 0b1 for proper
operation. The data bit width (24 = 12 bits, 20 = 10 bits, or 16 = 8 bits) must be set with 0x16[5:4]. The three input pin assignment styles
are shown in Table 12. The input style can be set in 0x16[3:2]. The only difference between Input ID 1 and Input ID 2 is that the syncs on
ID 2 are embedded in the data much like ITU 656 running at 1× clock and double width.
Table 12.
Input Format
23
YCbCr 4:2:2 Sep.
Sync (24 bit)
YCbCr 4:2:2 Sep.
Sync (20 bit)
YCbCr 4:2:2 Sep.
Sync (16 bit)
Cb[11:4]
Cr[11:4]
Cb[9:2]
Cr[9:2]
Cb[7:0]
Cr[7:0]
24-bit
Cb[11:0]
Cr[11:0]
Cb[9:0]
Cr[9:0]
Cb[7:0]
Cr[7:0]
20-bit
16-bit
24-bit
20-bit
16-bit
22
21
20
19
18
17
16
Y[11:0]
Y[11:0]
Y[9:0]
Y[9:0]
Y[7:0]
Y[7:0]
Data[23:0]
15 14 13 12 11 10
Style 1
Y[11:4]
Y[11:4]
Y[9:2]
Y[9:2]
Y[7:0]
Y[7:0]
Style 2
Y[11:0]
Y[11:0]
Y[9:0]
Y[9:0]
Y[7:0]
Y[7:0]
Style 3
Cb[11:0]
Cr[11:0]
Cb[9:0]
Cr[9:0]
Cb[7:0]
Cr[7:0]
9
8
7
6
5
4
Cb[3:0]
Cr[3:0]
Cb[1:0]
Cr[1:0]
3
2
1
0
Y[3:0]
Y[3:0]
Y[1:0]
Y[1:0]
YCbCr 4:2:2 Formats (Double Data Rate) Formats (12 bits, 10 bits, or 8 bits) with Separate Syncs, Input ID = 3
An input with YCbCr 4:2:2 DDR data and separate syncs can be selected by setting the input ID (0x15[3:1]) to 0b011. The Input CS (0x16
[0]) must be set to 0b1. The data bit width (12 bits, 10 bits, or 8 bits) must be set with 0x16[5:4]. The two input pin assignment styles are
shown in Table 13. The input style can be set in 0x16[3:2].
Table 13.
Input Format
12-bit
10-bit
8-bit
12-bit
10-bit
8-bit
23
22
21
20
19
18
17
16
Data[23:0]
14 13 12 11 10 9 8 7 6 5 4
Style 1
Cb/Y/Cr/Y[11:4]
Cb/Y/Cr/Y[9:2]
Cb/Y/Cr/Y[7:0]
Style 2
Cb/Y/Cr/Y[11:0]
Cb/Y/Cr/Y[9:0]
Cb/Y/Cr/Y[7:0]
15
Rev. 0 | Page 11 of 48
3
[3:0]
[1:0]
2
1
0
AD9389
YCbCr 4:2:2 DDR (Double Data Rate) Formats (12 bits, 10 bits, or 8 bits) with Embedded Syncs, Input ID = 4
An input with YCbCr 4:2:2 DDR data and embedded syncs (ITU 656) can be selected by setting the input ID (0x15[3:1]) to 0b100. The
Input CS (0x16[0]) must be set to 0b1. The data bit width (12 bits, 10 bits, or 8 bits) must be set with 0x16[5:4]. The two input pin
assignment styles are shown in Table 14. The input style can be set in 0x16[3:2]. The order of data input is the order in the table (for
example, 12 bit data is accepted as: Cb0, Y0, Cr0, Y1, Cb2, Y2, Cr2, Y3).
Table 14.
Input Format
23
22
21
20
19
18
17
Data[23:0]
15 14 13 12
Style 1
Cb/Y/Cr/Y[11:4]
Cb/Y/Cr/Y[9:2]
Cb/Y/Cr/Y[7:0]
Style 2
16
12-bit
10-bit
8-bit
12-bit
10-bit
8-bit
11
10
9
8
7
6
5
4
3
2
1
0
[3:0]
[1:0]
Cb/Y/Cr/Y[11:0]
Cb/Y/Cr/Y[9:0]
Cb/Y/Cr/Y[7:0]
Normal 4:4:4 Input Format (RGB or YCbCr) Clocked at Double Data Rate (DDR), Input ID = 5
An input with YCbCr 4:4:4 DDR data and separate syncs can be selected by setting the input ID (0x15[3:1]) to 0b011. The input CS
(0x16[0]) must be set to 0b1. The data bit width (12 bits, 10 bits, or 8 bits) must be set with 0x16[5:4]. The three input pin assignment
styles are shown in Table 15. The input style can be set in 0x16[3:2].
Table 15.
Input Format
23
22
21
20
19
18
17
16
15 14
Style 1
Data[23:0]
13 12
11
10
G[3:0]
RGB 4:4:4 (DDR)
(1 st edge,
2 nd edge)
YCbCr 4:4:4 (DDR)
(1 st edge,
2 nd edge)
9
8
7
6
4
3
2
B[7:0]
R[7:0]
Y[3:0]
5
G[7:4]
Cb[7:0]
Cr[7:0]
Y[7:4]
R[7:0]
G[7:4]
Style 2
RGB 4:4:4 (DDR)
(1 st edge,
2 nd edge)
YCbCr 4:4:4 (DDR)
(1 st edge,
2 nd edge)
G[3:0]
B[7:0]
Cr[7:0]
Y[3:0]
Y[7:4]
Cb[7:0]
Style 3
Y[7:0]
YCbCr 4:4:4 (DDR)
(1 st edge,
2 nd edge)
Cb[3:0]
Rev. 0 | Page 12 of 48
Cb[7:4]
Cr[7:0]
1
0
AD9389
YCbCr 4:2:2 Formats (24 bits, 20 bits, or 16 bits) DDR with Separate Sync, Input ID = 6
An input format of YCbCr 4:2:2 DDR can be selected by setting the input ID (0x15[3:1]) to 0b110. The three different input pin
assignment styles are shown in Table 16. The input style can be set in 0x16[3:2]. The input CS (0x16[0]) must be set to 0b1. The data bit
width (12 bits, 10 bits, or 8 bits) must be set to with 0x16[5:4].
The 1st or the 2nd edge can be the rising or falling edge. The data input edge is defined in 0x16[1]. 0b0 = rising edge; 0b1 = falling edge.
Pixel 0 is the first pixel of the 4:2:2 word and should be where DE starts.
Table 16.
Input Format
YCbCr 4:2:2 Sep.
Syncs (DDR)
12-bit
23
22
21
1st Pixel
20
19
18
17
Data[23:0]
16 15 14 13 12
Style 1
1st Edge
2nd
Edge
11
10
Y[7:4]
Cb[11:4]
Y[7:4]
Cr[11:4]
Y[5:4]
Cb[9:4]
Y[5:4]
Cr[9:4]
Cb[3:0]
Cb[7:4]
Cr[3:0]
Cr[7:4]
2nd Pixel
YCbCr 4:2:2 Sep.
Syncs (DDR)
10-bit
YCbCr 4:2:2 Sep.
Syncs (DDR)
8-bit
Style 2
12-bit
Y[11:0]
Cb[11:0]
Y[11:0]
Cr[11:0]
Y[9:0]
Cb[9:0]
Y[9:0]
Cr[9:0]
Y[7:0]
Cb[7:0]
Y[7:0]
Cr[7:0]
10-bit
8-bit
Style 3
12-bit
Cb[11:0]
Y[11:0]
Cr[11:0]
Y[11:0]
Cb[9:0]
Y[9:0]
Cr[9:0]
Y[9:0]
Cb[7:0]
Y[7:0]
Cr[7:0]
Y[7:0]
10-bit
8-bit
Rev. 0 | Page 13 of 48
9
8
7
6
5
Cb[3:0]
Cr[3:0]
Cb[3:0]
Cr[3:0]
Y[3:0]
Y[7:4]
Y[3:0]
Y[7:4]
4
3
2
Y[3:0]
Y[11:8]
Y[3:0]
Y[11:8]
Y[3:0]
Y[9:6]
Y[3:0]
Y[9:6]
1
0
AD9389
4:2:2 TO 4:4:4 DATA CONVERSION
DE GENERATION
The AD9389 has the ability to convert YCbCr video from 4:4:4
to 4:2:2 and 4:2:2 to 4:4:4. To convert from 4:4:4 to 4:2:2, the
video data goes through a filter first to remove any artificial
downsampling noise. To convert from 4:2:2 to 4:4:4, the
AD9389 utilizes either the zero-order upconversion (pixel
repetition) or first-order upconversion (linear interpolation).
The upconversion and downconversions are used when the
video output timing format does not match the video input
timing format. The video output format is set by Register
0x16[7:6]. The video input format is set by the video ID
(0x15[3:1]) and video color space (0x16[0]). The default mode
for upconversion is pixel repetition. To use linear interpolation,
set Register 0x17[2] to 1.
The AD9389 offers a choice of DE from an external pin, or an
internally generated DE. To activate the internal DE generation,
set Register 0x17[0] to 1. Registers 0x35 to 0x3A are used to
define the DE. 0x35 and 0x36[7:6] define the number of pixels
from the HS leading edge to the DE leading edge. 0x36[5:0] are
the number of HSYNCs between the leading edge of VS and
DE. 0x37[7:5] defines the difference of HS counts during VS
blanking for interlace video. 0x37[4:0] and 0x38[7:1] indicate
the width of the DE. 0x39 and 0x3A[7:4] are the number of
lines of active video (see Figure 4).
HSYNC AND VSYNC GENERATION
For video with embedded HSYNC and VSYNC, such as EAV
and SAV, found in ITU 656 format, it is necessary to reconstruct
HSYNC and VSYNC. This is done with registers 0x30 to 0x34.
0x30 and 0x31[7:6] specify the number of pixels between the
HSYNC leading edge and the trailing edge of DE. Register
0x31[5:0] and Register 0x32[7:4] are the duration of the
HSYNC in pixel clocks. 0x32[3:0] and 0x33[7:2] are the number
of HS pulses between the trailing edge of the last DE and the
leading edge of the VSYNC pulse. Register 0x33[1:0] and
0x34[7:0] are the duration of VSYNC in units of HSYNCs.
HSYNC and VSYNC polarity can be specified by setting
0x17[6] (for VSYNC) and 0x17[5] (for HSYNC).
HORIZONTAL SYNC, VERTICAL SYNC, AND DE
GENERATION
When transmitting video data across the TMDS interface, it
is necessary to have an HSYNC, VSYNC, and data enable (DE)
defined for the image. ITU-656 based sources have start of
active video (SAV) and end of active video (EAV) signals built
in, but the HSYNC and VSYNC must be generated (the DE is
implied by the SAV and EAV signals). Other sources (with
separate syncs) have HSYNC, VSYNC, and DE supplied at the
same time as the pixel data.
VS DELAY
R0x36[5:0]
ACTIVE
VIDEO
WIDTH
R0x37[4:0], R0x38[7:1]
HEIGHT
R0x39, R0x3A[7:4]
05724-003
HS DELAY
R0x35, R0x36[7:6]
Figure 4. Active Video
SAV
EAV
b
a
a: HSYNC PLACEMENT
R0x30, R0x31[7:6]
05724-005
HSYNC
b: HSYNC DURATION
R0x31[5:0], R0x32[7:4]
Figure 5. HSYNC Reconstruction
Rev. 0 | Page 14 of 48
AD9389
EAV
SAV
VSYNC
a
b
05724-006
a: VSYNC PLACEMENT
R0x32[3:0], R0x33[7:2]
b: VSYNC DURATION
R0x33[1:0], R0x34
Figure 6. VSYNC Reconstruction
CSC_Mode[1:0]
a4[12:0]
a1[12:0]
RIN[11:0]
×
×
1
4096
+
+
a2[12:0]
BIN[11:0]
×
×
1
4096
×
1
4096
×4
2
×2
1
+
ROUT[11:0]
0
GIN[11:0]
×
05724-008
a3[12:0]
Figure 7. Single CSC Channel
COLOR SPACE CONVERSION MATRIX (CSC)
The color space conversion matrix in the AD9389 consists of three
identical processing channels. In each channel, three input values
are multiplied by three separate coefficients. Also included are an
offset value for each row of the matrix and a scaling multiple for all
values. Each value is 13-bit, twos complement resolution to ensure
the signal integrity is maintained. The CSC is designed to run at
speeds up to 80 MHz supporting resolutions up to 1080i at 60 Hz
and UXGA at 60 Hz. With any-to-any color space support, RGB,
YUV, YCbCr, and other formats are supported by the CSC.
The main inputs, RIN, GIN, and BIN come from the 8-bit to 12-bit
inputs from each channel. These inputs are based on the input
format detailed in Table 10 to Table 16. The mapping of these
inputs to the CSC inputs is shown in Table 17.
Table 17. CSC Port Mapping
Input Channel
R/Cr
Gr/Y
B/Cb
CSC Input Channel
RIN
GIN
BIN
One of the three channels is represented in Figure 7. In each
processing channel, the three inputs are multiplied by three
separate coefficients marked a1, a2, and a3. These coefficients
are divided by 4096 to obtain nominal values ranging from
−0.9998 to +0.9998. The variable labeled a4 is used as an offset
control. The CSC_Mode setting is the same for all three
processing channels. This multiplies all coefficients and offsets
by a factor of 2CSC_Mode.
The functional diagram for a single channel of the CSC, as per
Figure 7, is repeated for the remaining G and B channels. The coefficients for these channels are b1, b2, b3, b4, c1, c2, c3, and c4.
Register settings for several common conversions are listed in
the Color Space Converter (CSC) Common Settings section.
For a detailed functional description and more programming
examples, refer to AN-795, The AD9880 Color Space Converter
User's Guide.
B
Rev. 0 | Page 15 of 48
AD9389
AUDIO DATA CAPTURE
The AD9389 is capable of receiving audio data in either I2S or
S/PDIF format for packetization and transmission over the
HDMI interface.
I2S AUDIO
The AD9389 can accommodate from two to eight channels of I2S
audio at up to a 192 kHz sampling rate. Selection of I2S audio mode
(vs. S/PDIF) is set with 0x0A[4] = 0. The detected sampling
frequency (from 32 kHz to 192 kHz) can be read in 0x04[7:4]. The
output sampling frequency (from 32 kHz to 192 kHz) can be
selected with 0x15[7:4]. The number of channels and the specific
channels can be selected in 0x0C[5:2] and 0x50[7:5]. If all eight
channels (I2S0 to I2S3) are required, setting all bits or 0x0C[5:2] to 1
selects eight channels. If I2S0 only is needed, setting 0x0C[2] to 1
selects this. The placement of these packets with respect to their
output can be specified in Register 0x0E to Register 0x11. Default
settings place all channels in their respective position (I2S0 left
channel in Channel 0 left position, I2S3 right channel in Channel 3
right position), but this mapping is completely programmable.
The AD9389 supports standard I2S, left-justified I2S, and rightjustified I2S formats via 0x0C[1:0] and sample word lengths
between 16 bits and 24 bits (0x14[3:0]).
S/PDIF AUDIO
The AD9389 is capable of accepting two channel LPCM and
encoded audio up to a 192 kHz sampling rate via the S/PDIF.
S/PDIF audio input is selected by setting 0x0A[4] = 1. The
AD9389 is capable of accepting S/PDIF with or without an
MCLK input. When no MCLK is present, the AD9389 makes
the determination of the CTS value (N/CTS determines the
MCLK frequency).
CTS GENERATION
Audio data being carried across the HDMI link, which is driven
by a TMDS (video) clock only, does not retain the original
audio sample clock.
The task of recreating this clock at the sink is called audio clock
regeneration. There are a variety of clock regeneration methods
that can be implemented in an HDMI sink, each with a
different set of performance characteristics. The HDMI
specification does not attempt to define exactly how these
mechanisms operate. It does, however, present a possible
configuration and it does define the data items that the HDMI
source supplies to the HDMI sink in order to allow the HDMI
sink to adequately regenerate the audio clock. It also defines
how that data is generated. In many video source devices, the
audio and video clocks are generated from a common clock
(coherent clocks). In this situation, there exists a rational
(integer divided by integer) relationship between these two
clocks. The HDMI clock regeneration architecture can take
advantage of this rational relationship and can also work in an
environment where there is no such relationship between these
two clocks, that is, where the two clocks are truly asynchronous
or where their relationship is unknown.
Figure 8 shows the system architecture model used by HDMI
for audio clock regeneration. The source determines the
fractional relationship between the video clock and an audio
reference clock (128 × audio sample rate) and passes the
numerator and denominator for that fraction to the sink across
the HDMI link. The sink can then recreate the audio clock from
the TMDS clock by using a clock divider and a clock multiplier.
The exact relationship between the two clocks is
128 × fS = fTMDS_clock × N/CTS
The source determines the value of the numerator N as stated in
Section 7.2.1 of the HDMI specification. Typically, this value N
is used in a clock divider to generate an intermediate clock that
is slower than the 128 × fS clock by the factor N. The source
typically determines the value of the denominator cycle time
stamp (CTS) by counting the number of TMDS clocks in each
of the 128 × fS/N clocks.
SOURCE DEVICE
CYCLE
TIME
COUNTER
CTS1
TMDS
VIDEO CLOCK
CLOCK
N
REGISTER
N
DIVIDE
BY
CTS
MULTIPLY
BY
N
128 × fS
N1
1N AND
CTS VALUES ARE TRANSMITTED USING THE “AUDIO CLOCK REGENERATION”
PACKET. VIDEO CLOCK IS TRANSMITTED ON TMDS CLOCK CHANNEL.
Figure 8. Audio Clock Regeneration
Rev. 0 | Page 16 of 48
05724-007
DIVIDE
BY
N
128 × fS
SINK DEVICE
AD9389
N PARAMETER
N shall be an integer number that meets the following
restriction: 128 × fS/1500 Hz ≤ N ≤ 128 × fS/300 Hz with a
recommended optimal value of 128 × fS/1000 Hz equals N.
For coherent audio and video clock sources, use Table 18 to
Table 20 to determine the value of N. For noncoherent sources
or sources where coherency is not known, use the equations
previously described.
CTS PARAMETER
CTS is an integer number that satisfies the following:
(Average CTS Value) = (fTMDS_clock × N)/(128 × fS)
Recommended N and Expected CTS Values
The recommended value of N for several standard pixel clocks
is given in Table 18 to Table 20. It is recommended that sources
with noncoherent clocks use the values listed for the pixel clock
type labeled Other.
Table 18. Recommended N and Expected CTS Values for
32 kHz Audio
Pixel Clock (MHz)
25.1/1.001
25.2
27
27 × 1.001
54
54 × 1.001
74.25/1.001
N
4576
4096
4096
4096
4096
4096
11648
74.25
148.5/1.001
148.5
Other
4096
11648
4096
4096
1
32 kHz
CTS
28125
25200
27000
27027
54000
54054
210937 to
210938 1
74250
421875
148500
Measured
This value alternates because of the restriction on N.
Table 19. Recommended N and Expected CTS Values for 44.1 kHz Audio and Multiples
Pixel Clock (MHz)
25.1/1.001
25.2
27
27 × 1.001
54
54 × 1.001
74.25/1.001
74.25
148.5/1.001
148.5
Other
N
7007
6272
6272
6272
6272
6272
17836
6272
8918
6272
6272
44.1 kHz
CTS
31250
28000
3000
30030
60000
60060
234375
82500
234975
165000
Measured
N
14014
12544
12544
12544
12544
12544
35672
12544
17836
12544
15244
88.2 kHz
CTS
31250
28000
30000
30030
60000
60060
234375
82500
234375
16500
Measured
N
28028
25088
25088
25088
25088
25088
71344
25088
35672
25088
25088
176.4 kHz
CTS
31250
28000
30000
30030
60000
60060
234375
82500
123375
162000
Measured
N
27456
24576
24576
24576
24576
24576
46592
24576
23296
24576
24576
176.4 kHz
CTS
28125
25200
27027
27027
54000
74250
140625
74250
140625
148500
Measured
Table 20. Recommended N and Expected CTS Values for 48 kHz Audio and Multiples
Pixel Clock (MHz)
25.1/1.001
25.2
27
27 × 1.001
54
54 × 1.001
74.25/1.001
74.25
148.5/1.001
148.5
Other
N
6864
6144
6144
6144
6144
6144
11648
6144
5824
6144
6144
44.1 kHz
CTS
28125
25200
27000
27027
54000
54054
140625
74250
140625
148500
Measured
N
13728
12288
12288
12288
12288
12288
23296
12288
11648
12288
12288
Rev. 0 | Page 17 of 48
88.2 kHz
CTS
28125
25200
27027
27027
54000
54054
140625
74250
140625
148500
Measured
AD9389
The AD9389 has two modes for CTS generation: manual mode
and auto mode. In manual mode, the user can program the CTS
number directly into the chip (0x07 to 0x09) and select this
external mode by setting 0x0A[7] to 1. In auto mode, the chip
computes the CTS based on the actual audio and video rates.
This can be selected by setting 0x0A[7] to 0, and the results can
be read from 0x04 to 0x06. Manual mode is good for coherent
audio and video, where the audio and video clock are generated
from the same crystal; thus CTS should be a fixed number. The
auto mode is appropriate for incoherent audio-video, where
there is no simple integer ratio between the audio and video
clock. A filter is available (0x0A[6:5]) to stabilize the chip
generated CTS. The 20-bit N value can be programmed into the
AD9389 in Register 0x01 to Register 0x03.
PIXEL REPETITION
PACKET CONFIGURATION
For max mode (0x3B[6:5] = 01), based on the input video
format, the AD9389 selects the maximum repetition factor. The
advantage of the max mode is that it is independent of the audio
sampling rate.
The AD9389 supports all the packets listed in the HDMI 1.1
specification. Each packet can be separately enabled and disabled. Based on the audio and video input, the packets are
added to the HDMI link at the earliest time, so that a minimum
delay is incurred. Notice the ISRC1 packet has one bit to enable
the ISRC2 packet. For the general control packet, remember to
clear or reset the bits to avoid system lock-up.
Due to HDMI specification and bandwidth requirements,
sometimes it is necessary to set clock multiplication by 2× and
4× in order to maintain the minimum TMDS clock frequency.
The AD9389 offers three choices for the user to implement this
function: auto mode, manual mode, and max mode (0x3B[6:5]).
For the auto mode (0x3B[6:5] = 00), based on the input video
format (either programmed by user, or chip detection) and
audio sampling rate, the AD9389 automatically sets the pixel
repetition factor (0x3D[7:6]).
For manual mode (0x3B[6:5] = 1×), the user programs the pixel
repetition factor in 0x3B[4:3].
Table 21. Pixel Repetition—Valid Pixel Repeat Values for Each Format
Video Code
1
2, 3
4
5
6, 7
8, 9
10, 11
12, 13
14, 15
16
17, 18
19
20
21, 22
23, 24
25, 26
27, 28
29, 30
31
32
33
34
1
Video Description
640 × 480p @ 60 Hz
720 × 480p @ 59.94/60 Hz
1280 × 720p @ 59.94/60 Hz
1920 × 1080i @ 59.94/60 Hz
720/1440 × 480i @ 59.94/60 Hz
720/1440 × 240p @ 59.94/60 Hz
2880 × 480i @ 59.94/60 Hz
2880 × 240p @ 59.94/60 Hz
1440 × 480p @ 59.94/60 Hz
1920 × 1080p @ 59.94/60 Hz
720 × 576p @ 50 Hz
1280 × 720p @ 50 Hz
1920 × 1080i @ 50 Hz
720/1440 × 576i @ 50 Hz
720/1440 × 288p @ 50 Hz
2880 × 576i @ 50 Hz
2880 × 288 @ 50 Hz
1440 × 576p @ 50 Hz
1920 × 1080p @ 50 Hz
1920 × 1080p @ 23.97/24 Hz
1920 × 1080p @ 25 Hz
1920 × 1080p @ 29.9/30 Hz
EIA/CEA-861B Pixel Repeat Values
No repetition
No repetition
No repetition
No repetition
Pixel sent 2 times
Pixel sent 2 times
Pixel sent 0 to 10 times
Pixel sent 1 to 10 times
No repetition
No repetition
No repetition
No repetition
No repetition
Pixel sent 2 times
Pixel sent 2 times
Pixel sent 1 to 10 times
Pixel sent 1 to 10 times
No repetition
No repetition
No repetition
No repetition
No repetition
HDMI Pixel Repeat Values
No repetition
No repetition
No repetition
No repetition
Pixel sent 2 times
Pixel sent 2 times
Pixel sent 1 to 10 times
Pixel sent 1 to 10 times
Pixel sent 1 to 2 times 1
No repetition
No repetition
No repetition
No repetition
Pixel sent 2 times
Pixel sent 2 times
Pixel sent 1 to 10 times
Pixel sent 1 to 10 times
Pixel sent 1 to 2 times1
No repetition
No repetition
No repetition
No repetition
Denotes change from EIA/CEA-861B valid values. Pixel repetition is required to support some audio formats at 720 × 480p and 720 × 576p video format timings.
Rev. 0 | Page 18 of 48
AD9389
HDCP HANDLING
INTERRUPTS
The AD9389 has a built-in microcontroller to handle HDCP
transmitter states, including handling downstream HDCP
repeaters. To activate HDCP from a system level, the main
controller needs to set 0xAF[7] to 1 to inform AD9389 that the
video stream should be encrypted. The AD9389 takes control
from there, and implements all remaining tasks defined by the
HDCP 1.1 specification.
The AD9389 has interrupts to help with the system design: hot
plug detection, receiver sense, VS detection, audio FIFO
overflow, ITU 656 error, EDID ready, HDCP error, and BKSV
ready. Interrupts can be cleared by writing 1 into the interrupt
register (0x96, 0x97). There are read-only registers (0xC5,
0xC6) to show the state of these signals. Masks (0x94, 0x95) are
available to let the user selectively activate each interrupt. To
enable a specific interrupt register, write 1 to the corresponding
mask bit.
The system controller should monitor the status of HDCP by
reading Register 0xB8[6] (indicating the HDCP link has been
established). There are also some error flags (0xC5[7] and
0xC8[7:4]) to help debug the system.
The AD9389 also supports AV functions to suspend HDCP
temporarily. To set AV mute, clear 0x45[7] and set 0x45[6]
to 1. To clear AV mute, clear 0x45[6] and set 0x45[7] to 1. (Note
that it is invalid to set the two mute bits at the same time.)
For more information, refer to application note AN-810, EDID
and HDCP Controller User Guide for the AD9889.
EDID READING
The AD9389 has an I2C master (DDC Pin 44 and Pin 45) to
read the EDID based on system need. It buffers segment 0 once
HPD is detected. The system can request other segments by
programming Register 0xC4. An interrupt bit (0x96[2])
indicates the completion of EDID rebuffering.
To read the EDID data from the AD9389, use the AD9389
programming bus (Pin 46 and Pin 47) with I2C Address 0x7E.
This is the default address but can be changed by writing the
desired address into Register 0x43.
POWER MANAGEMENT
The AD9389 power-down pin polarity depends on the
AD9389’s I2C address selection. To use 0x72, the PD pin is high
active. To use 0x7A, the PD pin is low active. The power-down
pin polarity can be verified by reading Register 0x42[7].
The AD9389 can be powered down or reset either by Pin 33 or
by Register 0x41[6]. During power-down mode, all the circuits
are inactive except the I2C slave and some circuits related to
mode and activity detection. During power-down mode, the
chip status can still be read through the I2C slave. To enter
normal power-down mode, either drive Pin 33 to 1, or set
0x41[6] to 1. To further reduce power consumption, disable the
receiver sense detection by setting Register 0xA4[2] to 1.
For HDCP security reasons, the I2C power-down bit is also
reset by the power-down pin. Anytime after power down, the
user needs to drive the PD pin back to 0, and set 0x41[6] to
0 to activate the chip.
For more information, refer to Application Note AN-810, EDID
and HDCP Controller User Guide for the AD9889.
Rev. 0 | Page 19 of 48
AD9389
2-WIRE SERIAL REGISTER MAP
The AD9389 is initialized and controlled by a set of registers that determine the operating modes. An external controller is employed to
write and read the control registers through the two-line serial interface port.
Table 22. Control Register Map
Hex
Address
0x00
0x01
Read/Write or
Read Only
Read
Read/Write
Bits
[7:0]
[3:0]
Default
Value
00000000
****0000
Register Name
Chip Revision
N[19:16]
0x02
0x03
0x04
Read/Write
Read/Write
Read
[7:0]
[7:0]
[7:4]
00000000
00000000
0000****
N[15:8]
N[7:0]
S/PDIF_SF
[3:0]
****0000
CTS_Int[19:16]
0x05
0x06
0x07
Read
Read
Read/Write
[7:0]
[7:0]
[3:0]
00000000
00000000
****0000
CTS_Int[15:8]
CTS_Int[7:0]
CTS_Ext[19:16]
0x08
0x09
0x0A
Read/Write
Read/Write
Read/Write
[7:0]
[7:0]
[7]
00000000
00000000
0*******
CTS_Ext[15:8]
CTS_Ext[7:0]
CTS_Sel
[6:5]
*10*****
Avg_Mode
[4]
***0****
Audio_Sel
[3]
****0***
MCLK_SP
[2]
*****0**
MCLK_I2S
[1:0]
******01
MCLK_Ratio
Rev. 0 | Page 20 of 48
Description
Revision of the chip, start from 0.
20-bit N used with cycle time stamp (CTS) (see Table
18 to Table 20 for appropriate settings) to regenerate
the audio clock in the receiver. For remaining bits, see
0x02 and 0x03. Used only with I2S audio, not S/PDIF.
The middle byte of N.
The lower byte of N.
S/PDIF sampling frequency for S/PDIF audio decoded
from hardware. This information is used both by the
audio Rx and the pixel repetition.
0011 = 32 kHz.
0000 = 44.1 kHz.
0010 = 48 kHz.
1000 = 88.2 kHz.
1010 = 96 kHz.
1100 = 176.4 kHz.
1110 = 192 kHz.
Default = 0x0.
CTS measured (internal). This 20-bit value is used in
the receiver with the N value to regenerate an audio
clock. For remaining bits, see 0x05 and 0x06.
Middle byte of measured CTS.
Low byte of measured CTS.
CTS (external). This 20-bit value is used in the receiver
with the N value to regenerate an audio clock. For
remaining bits, see 0x08 and 0x09.
Middle byte of external CTS.
Low byte of external CTS.
CTS source select.
0 = internal CTS.
1 = external CTS.
Default = 0.
CTS filter mode.
00 = no filter.
01 = divide by 4.
10 = divide by 8.
11 = divide by16.
Default = 10.
Audio type select.
0 = I2S.
1 = S/PDIF.
Default = 0.
MCLK for S/PDIF.
1 = MCLK active.
0 = MCLK inactive.
Default = 0.
MCLK for I2S.
1 = I2S MCLK active.
0 = I2S MCLK inactive.
Default = 0.
MCLK ratio.
AD9389
Hex
Address
Read/Write or
Read Only
Bits
Default
Value
Register Name
0x0B
Read/Write
[6]
*0******
MCLK_Pol
[5]
**0*****
Flat_Line
[4:0]
[5:2]
****0111
**1111**
Test bits
[1:0]
******00
I2S Format
0x0C
Read/Write
I2S enable
0x0D
Read/Write
[4:0]
***11000
I2S_bit_width
0x0E
Read/Write
[5:3]
**000***
SUBPKT0_L_src
[2:0]
[5:3]
[2:0]
[5:3]
[2:0]
[5:3]
[2:0]
[5]
*****001
**010***
*****011
**100***
*****101
**110***
*****111
**0*****
SUBPKT0_R_src
SUBPKT1_L_src
SUBPKT1_R_src
SUBPKT2_L_src
SUBPKT2_R_src
SUBPKT3_L_src
SUBPKT3_R_src
CR_bit
[4:2]
***000**
a_info
[1:0]
******00
Clk_Acc
[7:0]
00000000
Category Code
0x0F
Read/Write
0x10
Read/Write
0x11
Read/Write
0x12
Read/Write
0x13
Read/Write
Rev. 0 | Page 21 of 48
Description
00 = × 128 fS.
01 = × 256 fS.
10 = × 384 fS.
11 = × 512 fS.
Default = 01.
MCLK polarity.
0 = rising edge.
1 = falling edge.
Default = 0.
Flat line.
1 = flat line audio (audio sample not valid).
0 = normal.
Default = 0.
Must be set to 0x7 for proper operation.
I2S enable for the four I2S pins (active).
0001 = I2S0.
0010 = I2S1.
0100 = I2S2.
1000 = I2S3.
Default = 1111 for all.
I2S format.
00 = standard I2S mode.
01 = right-justified I2S mode.
10 = left-justified I2S mode.
11 = raw IEC60958 mode.
Default = 0.
I2S bit width. For right justified audio only. Default is
24. Not valid for widths greater than 24.
Registers 0x0E to 0x11 should be set based on the
speaker mapping information obtained from EDID.
Source of sub packet 0, left channel. Default = 000.
Source of sub packet 0, right channel. Default = 001.
Source of sub packet 1, left channel. Default = 010.
Source of sub packet 1, right channel. Default = 011.
Source of sub packet 2, left channel. Default = 100.
Source of sub packet 2, right channel. Default = 101.
Source of sub packet 3, left channel. Default = 110.
Source of sub packet 3, right channel. Default = 111.
Copyright bit.
0 = copyright.
1 = not copyright protected.
Additional information for channel status bits.
000 = 2 audio channels without pre-emphasis.
100 = 2 audio channels with 50/15 μs pre-emphasis.
010 = reserved.
110 = reserved.
Default = 000.
Clock accuracy.
00 = Level II, normal accuracy ±1000 × 10−6.
01 = Level III, variable pitch shifted clock.
10 = Level I, high accuracy ±50 × 10−6.
11 = reserved.
Default = 00.
Category code for audio infoframe; see IEC 60958.
AD9389
Hex
Address
0x14
Read/Write or
Read Only
Read/Write
0x15
Read/Write
0x16
Read/Write
Bits
[7:4]
[3:0]
Default
Value
0000****
****0000
Register Name
Source Number
Word Length
[7:4]
0000****
I2S_SF
[3:1]
****000*
VFE_input_id
[0]
*******0
low_frq_video
[7:6]
00******
VFE_out_fmt
[5:4]
**00****
VFE_422_width
[3:2]
****00**
VFE_input_style
Rev. 0 | Page 22 of 48
Description
Source number.
Audio word length.
0000 = not specified.
0100 = 16 bits.
0011 = 17 bits.
0010 = 18 bits.
0001 = 19 bits.
0101 = 20 bits.
1000 = not specified.
1100 = 20 bits.
1011 = 21 bits.
1010 = 22 bits.
1001 = 23 bits.
1101 = 24 bits.
Default = 0x0.
Sampling frequency for I2S audio. This information is
used both by the audio Rx and the pixel repetition.
0011 = 32 kHz.
0000 = 44.1 kHz.
0010 = 48 kHz.
1000 = 88.2 kHz.
1010 = 96 kHz.
1100 = 176.4 kHz.
1110 = 192 kHz.
Default = 0x0.
Input video format.
000 = RGB and YCbCr 4:4:4 (Y on Green).
001 = YCbCr 4:2:2; 16-bit, 20-bit, and 24-bit.
010 = Same as 001 with HS and VS embedded as SAV
and EAV.
011 = ITU656 with separated syncs.
100 = ITU656 with embedded syncs.
101 = DDR RGB 4:4:4 or YCbCr 4:4:4.
110 = DDR YCbCr 4:2:2.
111 = undefined.
Default = 000.
Video refresh rate.
0 = VREF > 30 Hz.
1 = VREF ≤ 30 Hz refresh rate video.
Default = 0.
Video output format. This should be written along
with 0x45[5:4].
00 = RGB 4:4:4.
01 = YCbCr 4:4:4.
1x = YCbCr 4:2:2.
Default = 00.
4:2:2 input, could be either 8-bit, 10-bit, or 12-bit.
x0 = 12 bits.
01 = 10 bits.
11 = 8 bits.
Default = 00.
Styles refer to the input pin assignments. See Table 23
to Table 28.
x0 = Style 1.
01 = Style 2.
11 = Style 3.
AD9389
Hex
Address
0x17
Read/Write or
Read Only
Read/Write
Bits
[1]
Default
Value
******0*
Register Name
VFE_input_edge
[0]
*******0
VFE_input_cs
[7]
0*******
itu_error_correct_en
[6]
*0******
itu_vsync_pol
[5]
**0*****
itu_hsync_pol
[4:3]
***00***
csc_mode
[2]
*****0**
gen_444_en
[1]
******0*
ASP_ratio
[0]
*******0
deGen_en
0x18
0x19
Read/Write
Read/Write
[4:0]
[7:0]
***00110
01100010
CSC_A1_MSB
CSC_A1_LSB
0x1A
0x1B
Read/Write
Read/Write
[4:0]
[7:0]
***00100
10101000
CSC_A2_MSB
CSC_A2_LSB
0x1C
0x1D
Read/Write
Read/Write
[4:0]
[7:0]
***00000
00000000
CSC_A3_MSB
CSC_A3_LSB
0x1E
Read/Write
[4:0]
***11100
CSC_A4_MSB
Description
Video data input edge. Defines the first clock edge of
video word clocked.
0 = rising edge.
1 = falling edge.
Default = 0 (in reference to DDR).
Video input color space.
0 = RGB.
1 = YCbCr.
Default = 0.
ITU656 error correction. This must be enabled if using
ITU656 format.
0 = disable.
1 = enable.
Default = 0.
VS polarity from regenerated ITU 656 input.
0 = high polarity.
1 = low polarity.
Default = 0.
HS polarity from regenerated ITU 656 input.
0 = high polarity.
1 = low polarity.
Default = 0.
Sets the fixed point position of the CSC coefficients,
including the a4, b4, and c4 offsets.
00 = ±1.0, (from −4096 to +4095).
01 = ±2.0, (from −8192 to +8190.)
1× = ±4.0, (from −16,384 to +16,380).
Default = 000.
4:2:2 to 4:4:4 upconversion mode.
1 = uses interpolation.
0 = no interpolation.
Default = 0.
Aspect ratio of input video.
0 = 4:3.
1 = 16:9.
Default = 0.
Enable DE generator. The DE generator should be
enabled when a DE input is not provided.
1 = enable DE generator.
Default = 0 (see Register 0x30 to Register 0x3A).
MSB of 0x19.
Color space converter (CSC) coefficient for equation:
ROUT = (a1 × RIN) + (a2 × GIN) + (a3 × BIN) + a4
GOUT = (b1 × RIN) + (b2 × GIN) + (b3 × BIN) + b4
BOUT = (c1 × RIN) + (c2 × GIN) + (c3 × BIN) + c4
MSB of 0x1B.
CSC coefficient for equation:
ROUT = (a1 × RIN) + (a2 × GIN) + (a3 × BIN) + a4
GOUT = (b1 × RIN) + (b2 × GIN) + (b3 × BIN) + b4
BOUT = (c1 × RIN) + (c2 × GIN) + (c3 × BIN) + c4
MSB of 0x1D.
CSC coefficient for equation:
ROUT = (a1 × RIN) + (a2 × GIN) + (a3 × BIN) + a4
GOUT = (b1 × RIN) + (b2 × GIN) + (b3 × BIN) + b4
BOUT = (c1 × RIN) + (c2 × GIN) + (c3 × BIN) + c4
MSB of 0x1F.
B
B
B
Rev. 0 | Page 23 of 48
AD9389
Hex
Address
0x1F
Read/Write or
Read Only
Read/Write
Bits
[7:0]
Default
Value
10000100
Register Name
CSC_A4_LSB
0x20
0x21
Read/Write
Read/Write
[4:0]
[7:0]
***11100
10111111
CSC_B1_MSB
CSC_B1_LSB
0x22
0x23
Read/Write
Read/Write
[4:0]
[7:0]
***00100
10101000
CSC_B2_MSB
CSC_B2_LSB
0x24
0x25
Read/Write
Read/Write
[4:0]
[7:0]
***11110
01110000
CSC_B3_MSB
CSC_B3_LSB
0x26
0x27
Read/Write
Read/Write
[4:0]
[7:0]
***00010
00011110
CSC_B4_MSB
CSC_B4_LSB
0x28
0x29
Read/Write
Read/Write
[4:0]
[7:0]
***00000
00000000
CDC_C1_MSB
CSC_C1_LSB
0x2A
0x2B
Read/Write
Read/Write
[4:0]
[7:0]
***00100
10101000
CSC_C2_MSB
CSC_C2_LSB
0x2C
0x2D
Read/Write
Read/Write
[4:0]
[7:0]
***01000
00010010
CSC_C3_MSB
CSC_C3_LSB
0x2E
0x2F
Read/Write
Read/Write
[4:0]
[7:0]
***11011
10101100
CSC_C4_MSB
CSC_C4_LSB
0x30
Read/Write
[7:0]
00000000
VFE_hs_pla_MSB
0x31
Read/Write
0x32
Read/Write
[7:6]
[5:0]
[7:4]
[3:0]
00******
**000000
0000****
****0000
VFE_hs_pla_LSB
VFE_hs_dur_MSB
VFE_hs_dur_LSB
VFE_vs_pla_MSB
0x33
Read/Write
0x34
0x35
Read/Write
Read/Write
[7:2]
[1:0]
[7:0]
[7:0]
000000**
******00
00000000
00000000
VFE_vs_pla_LSB
VFE_vs_dur_MSB
VFE_vs_dur_LSB
VFE_hsDelayIn_MSB
Description
CSC coefficient for equation:
ROUT = (a1 × RIN) + (a2 × GIN) + (a3 × BIN) + a4
GOUT = (b1 × RIN) + (b2 × GIN) + (b3 × BIN) + b4
BOUT = (c1 × RIN) + (c2 × GIN) + (c3 × BIN) + c4
MSB of 0x21.
CSC coefficient for equation:
ROUT = (a1 × RIN) + (a2 × GIN) + (a3 × BIN) + a4
GOUT = (b1 × RIN) + (b2 × GIN) + (b3 × BIN) + b4
BOUT = (c1 × RIN) + (c2 × GIN) + (c3 × BIN) + c4
MSB of 0x23.
CSC coefficient for equation:
ROUT = (a1 × RIN) + (a2 × GIN) + (a3 × BIN) + a4
GOUT = (b1 × RIN) + (b2 × GIN) + (b3 × BIN) + b4
BOUT = (c1 × RIN) + (c2 × GIN) + (c3 × BIN) + c4
MSB of 0x25.
CSC coefficient for equation:
ROUT = (a1 × RIN) + (a2 × GIN) + (a3 × BIN) + a4
GOUT = (b1 × RIN) + (b2 × GIN) + (b3 × BIN) + b4
BOUT = (c1 × RIN) + (c2 × GIN) + (c3 × BIN) + c4
MSB of 0x27.
CSC coefficient for equation:
ROUT = (a1 × RIN) + (a2 × GIN) + (a3 × BIN) + a4
GOUT = (b1 × RIN) + (b2 × GIN) + (b3 × BIN) + b4
BOUT = (c1 × RIN) + (c2 × GIN) + (c3 × BIN) + c4
MSB of 0x29.
CSC coefficient for equation:
ROUT = (a1 × RIN) + (a2 × GIN) + (a3 × BIN) + a4
GOUT = (b1 × RIN) + (b2 × GIN) + (b3 × BIN) + b4
BOUT = (c1 × RIN) + (c2 × GIN) + (c3 × BIN) + c4
MSB of 0x2B.
CSC coefficient for equation:
ROUT = (a1 × RIN) + (a2 × GIN) + (a3 × BIN) + a4
GOUT = (b1 × RIN) + (b2 × GIN) + (b3 × BIN) + b4
BOUT = (c1 × RIN) + (c2 × GIN) + (c3 × BIN) + c4
MSB of 0x2D.
CSC coefficient for equation:
ROUT = (a1 × RIN) + (a2 × GIN) + (a3 × BIN) + a4
GOUT = (b1 × RIN) + (b2 × GIN) + (b3 × BIN) + b4
BOUT = (c1 × RIN) + (c2 × GIN) + (c3 × BIN) + c4
MSB of 0x2F.
CSC coefficient for equation:
ROUT = (a1 × RIN) + (a2 × GIN) + (a3 × BIN) + a4
GOUT = (b1 × RIN) + (b2 × GIN) + (b3 × BIN) + b4
BOUT = (c1 × RIN) + (c2 × GIN) + (c3 × BIN) + c4
Most significant 8 bits for HSYNC placement for ITU
656 HSYNC regeneration.
HSYNC placement lower 2 bits (see 0x30).
Most significant 6 bits for HSYNC duration.
HSYNC duration lower 4 bits (see 0x31).
Most significant 4 bits for VSYNC placement for ITU
656 VSYNC regeneration.
VSYNC placement lower 6 bits (see 0x32).
Most significant 2 bits for VSYNC duration.
VSYNC duration lower 8 bits (see 0x33).
Most significant 8 bits for HSYNC delay in for ITU 656
HSYNC regeneration.
B
B
B
B
B
B
B
B
B
Rev. 0 | Page 24 of 48
AD9389
Hex
Address
0x36
Read/Write or
Read Only
Read/Write
0x37
0x38
0x39
0x3A
0x3B
Read/Write
Bits
[7:6]
[5:0]
[7:5]
Default
Value
00******
**000000
000*****
Register Name
VFE_hsDelayIn_LSB
VFE_vsDelayIn
Interlace Offset
Read/Write
Read/Write
Read/Write
Read/Write
[4:0]
[7:1]
[7:0]
[7:4]
[7]
***00000
0000000*
00000000
0000****
1*******
VFE_width_MSB
VFE_width
VFE_height_MSB
VFE_height
ext_audioSF_sel
[6:5]
*00*****
pr_mode
[4:3]
***00***
ext_PLL_pr
[2:1]
*****00*
ext_target_pr
[0]
*******0
csc_en
0x3C
Read/Write
[5:0]
**000000
ext_VID_to_Rx
0x3D
Read
0x3E
0x3F
Read
Read
[7:6]
[5:0]
[7:2]
[7:5]
00******
**000000
000000**
000*****
pr_to_Rx
VID_to_Rx
VFE_fmt_VID
VFE_aux_vid
[4:3]
***00***
VFE_prog_mode
Rev. 0 | Page 25 of 48
Description
HSYNC delay in lower 2 bits (see 0x35).
VSYNC delay in for DE generation.
Sets the difference (in HSYNCs) in field length
between Field 0 and Field 1.
Most significant 5 bits for frame width.
Lower 7 bits for frame width (see 0x37).
Most significant 8 bits for frame height.
Lower 4 bits for frame height (see 0x39).
Audio sampling frequency select.
Valid when using S/PDIF input.
0 = fS extracted from SPDIF.
1 = fS set via 0x15[7:4].
Default = 1 (only used during pixel repetition mode).
Pixel repetition mode selection. Set to b00 unless
nonstandard video is supported.
00 = auto mode.
01 = max mode.
1x = manual mode (see 0x3B Bits [4:3]).
Default = 00.
External value for PLL pixel repetition.
00 = ×1.
01 = ×2.
10 = ×4.
11 = ×4.
Default = 00.
User programmed pixel repetition number to send to
Rx. Default = 00.
CSC enable.
0 = no CSC.
1 = enable CSC.
Default = 0.
User programmed VID to send to Rx. See Table 24 for
full VID formats. Default = 0x00.
The actual pixel repetition sent to Rx.
The actual VID sent to HDMI Rx (see Table 24).
VID detected by video FE (see Table 24).
This register is for video input formats that are not
inside the 861B table.
000 = 480i not active.
001 = 240p not active.
010 = 576i not active.
011 = 288p not active.
100 = 480i active.
101 = 240p active.
110 = 576i active.
111 = 288p active.
Default = 000.
Information about 240p and 288p.
240p − 01 = 262 lines.
240p − 10 = 263 lines.
288p − 01 = 312 lines.
288p − 10 = 313 lines.
288p − 11 = 314 lines.
Default = 00.
AD9389
Hex
Address
0x40
0x41
0x42
Read/Write or
Read Only
Read/Write
Read/Write
Read
0x43
0x44
Read/Write
Read/Write
0x45
Read/Write
Bits
[7]
[6]
Default
Value
0*******
*0******
Register Name
GC_pkt_en
SPD_pkt_en
[5]
[4]
[3]
[6]
**0*****
***0****
****0***
*1******
MPEG_pkt_en
ACP_pkt_en
ISRC_pkt_en
system_PD
[5]
[4]
**0*****
***1****
Test bit
INTR_pol
[3]
[7]
****0***
1*******
initiate_scan
PD_pol
[6]
*0******
HPD_state
[5]
**0*****
MSEN_state
[7:0]
[7]
[6]
[5]
[4]
[3]
[7]
[6]
[5:4]
01111110
0*******
*1******
**1*****
***1****
****1***
0*******
*0******
**00****
EDID_ID
spdif_en
N_CTS_pkt_en
audio_sample_pkt_en
aviIF_pkt_en
audioIF_pkt_en
clear_avmute
set_avmute
Y1Y0
[3]
****0***
Active Format
Information Status
[2:1]
*****00*
Bar Information
Rev. 0 | Page 26 of 48
Description
1 = enable general control packet. Default = 0.
1 = enable source product descriptor packet.
Default = 0.
1 = enable MPEG packet. Default = 0.
1 = enable ACP packet. Default = 0.
1 = enable ISRC packet. Default = 0.
0 = all circuits powered up.
1 = power down the whole chip, except I2C, HPD
interrupt and MSEN interrupt.
Default = 1.
Must be set to 0.
Interrupt polarity.
0 = low active interrupt.
1 = high active interrupt.
Default = 1.
1 = initiate scan. Default = 1.
Polarity for power-down pin.
0 = low active.
1 = high active.
State of the hot plug detection.
0 = hot plug detect inactive.
1 = hot plug active.
State of the monitor connection.
0 = HDMI clock termination not detected.
1 = HDMI clock termination detected.
The I2C address for EDID memory. Default = 0x7E.
1 = enable S/PDIF receiver. Default = 0.
1 = enable N_CTS packet. Default = 1.
1 = enable audio sample packet. Default = 1.
1 = enable avi info frame. Default = 1.
1 = enable audio info frame. Default = 1.
1 = clear av mute. Default = 0.
1 = set av mute. Default = 0.
Output format, should be written when 0x16[7:6] is
written.
00 = RGB.
01 = YCbCr 4:2:2.
10 = YCbCr 4:4:4.
11 = reserved.
Default = 00.
Active format information present.
0 = no data.
1 = active format information valid.
Default = 0.
B[1:0].
00 = no bar information.
01 = horizontal bar information valid.
10 = vertical bar information valid.
11 = horizontal and vertical bar information valid.
Default = 00.
AD9389
Hex
Address
Read/Write or
Read Only
Bits
Default
Value
Register Name
Description
0x46
Read/Write
[7:6]
00******
Scan Information
[5:4]
**00****
Colorimetry
[3:2]
****00**
Picture Aspect Ratio
[1:0]
******00
Nonuniform Picture
Scaling
S[1:0].
00 = no information.
01 = overscanned (television).
10 = underscanned (computer).
11 = undefined.
Default = 00.
C[1:0].
00 = no data.
01 = SMPTE 170M, ITU601.
10 = ITU709.
11 = undefined.
Default = 00.
M[1:0].
00 = no data.
01 = 4:3.
10 = 16:9.
11 = undefined.
Default = 00.
SC[1:0].
00 = No known nonuniform scaling.
01 = picture has been scaled horizontally.
10 = picture has been scaled vertically.
11 = picture has been scaled horizontally and vertically.
Default = 00.
R[3:0].
1000 = same as picture aspect ratio.
1001 = 4:3 (center).
1010 = 16:9 (center).
1011 = 14:9 (center).
Default = 0x0.
This represents the line number at the end of the top
horizontal bar. If 0, there is no horizontal bar.
0x47
Read/Write
[7:4]
0000****
Active Format Aspect
Ratio
0x48
0x49
0x4A
0x4B
Read/Write
Read/Write
Read/Write
Read/Write
[7:0]
[7:0]
[7:0]
[7:0]
00000000
00000000
00000000
00000000
Active Line Start LSB
Active Line Start MSB
Active Line End LSB
Active Line End MSB
0x4C
0x4D
0x4E
0x4F
Read/Write
Read/Write
Read/Write
Read/Write
[7:0]
[7:0]
[7:0]
[7:0]
00000000
00000000
00000000
00000000
Active Pixel Start LSB
Active Pixel Start MSB
Active Pixel End LSB
Active Pixel End MSB
0x50
Read/Write
[7:5]
000*****
audio_IF_CC
[4]
***0****
audio_IF_DM_INH
[3:0]
****0000
Level Shift
Rev. 0 | Page 27 of 48
This represents the line number at the beginning of a
lower horizontal bar. If greater than the number of active
video lines, there is no lower horizontal bar.
This represents the last pixel in a vertical pillar bar at the
left side of the picture. If 0, there is no left bar.
This represents the first horizontal pixel in a vertical pillar
bar at the right side of the picture. If greater than the
maximum number of horizontal pixels, there is no
vertical bar.
Channel count.
000 = refer to stream header.
001 = 2 channels.
010 = 3 channels.
…
111 = 8 channels.
Default = 000.
Down-mix inhibit.
0 = Permitted or no information about this.
1 = Prohibited.
Default = 0.
LSV[3:0]. Level Shift Values with attenuation information.
0000 = 0 dB attenuation.
0001 = 1 dB attenuation.
…
1111 = 15 dB attenuation.
Default = 0x0.
AD9389
Hex
Address
0x51
Read/Write or
Read Only
Read/Write
Bits
[7:0]
Default
Value
00000000
0x52
Read/Write
[7:0]
00000000
0x53
0x54
0x55
0x56
0x57
0x58
0x59
0x5A
0x5B
0x5C
0x5D
0x5E
0x5F
0x60
0x61
0x62
0x63
0x64
0x65
0x66
0x67
0x68
0x69
0x6A
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
Source Product
Description Infoframe
Byte 1. (SPD_B1)
SPD_B2
SPD_B3
SPD_B4
SPD_B5
SPD_B6
SPD_B7
SPD_B8
SPD_B9
SPD_B10
SPD_B11
SPD_B12
SPD_B13
SPD_B14
SPD_B15
SPD_B16
SPD_B17
SPD_B18
SPD_B19
SPD_B20
SPD_B21
SPD_B22
SPD_B23
SPD_B24
SPD_B25
0x6B
0x6C
0x6D
0x6E
Read/Write
Read/Write
Read/Write
Read/Write
[7:0]
[7:0]
[7:0]
[7:0]
00000000
00000000
00000000
00000000
MPEG_B0
MPEG_B1
MPEG_B2
MPEG_B3
0x6F
Read/Write
[7]
0*******
MPEG_FR
0x70
Read/Write
[6:5]
*00*****
MPEG_MF
Register Name
Speaker Mapping
Rev. 0 | Page 28 of 48
Description
CA[7:0]. Speaker mapping or placement for up to
8 channels (see Table 24).
Default = 0x00.
Vendor name character 1 (VN1).
VN2.
VN3.
VN4.
VN5.
VN6.
VN7.
VN8.
Product description character 1 (PD1).
PD2.
PD3.
PD4.
PD5.
PD6.
PD7.
PD8.
PD9.
PD10.
PD11.
PD12.
PD13.
PD14.
PD15.
PD16.
Source device information code.
Code defines source, such as DVD or STB.
Default = 0x00.
MB[0]. Lower byte of MPEG bit rate: Hz. This is the
lower 8 bits of 32 bits (4 bytes) that specify the MPEG
bit rate in Hz.
MB[1].
MB[2].
MB[3] (upper byte).
FR indicates new picture or repeat.
0 = new field or picture.
1 = repeated field.
Default = 0.
MPEG frame indicator.
MF[1:0] identifies whether frame is an I, B, or P
picture.
00 = unknown.
01 = I picture.
10 = B picture.
11 = P picture.
Default = 00.
AD9389
Hex
Address
0x71
Read/Write or
Read Only
Read/Write
Bits
[7:0]
Default
Value
00000000
0x72
Read/Write
[7:0]
00000000
ACP_byte1
0x73
Read/Write
[7]
0*******
ISRC1 Continued
[6]
*0******
ISRC1_valid
[5:3]
**000***
ISRC1 Status
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
ISRC1_PB0
ISRC1_PB1
ISRC1_PB2
ISRC1_ PB3
ISRC1_ PB4
ISRC1_ PB5
ISRC1_ PB6
ISRC1_ PB7
ISRC1_ PB8
ISRC1_ PB9
ISRC1_ PB10
ISRC1_ PB11
ISRC1_ PB12
ISRC1_ PB13
ISRC1_ PB14
ISRC1_ PB15
ISRC2_ PB0
ISRC2_ PB1
ISRC2_ PB2
ISRC2_ PB3
ISRC2_ PB4
ISRC2_ PB5
ISRC2_ PB6
ISRC2_ PB7
ISRC2_ PB8
ISRC2_ PB9
ISRC2_ PB10
ISRC2_ PB11
0x74
0x75
0x76
0x77
0x78
0x79
0x7A
0x7B
0x7C
0x7D
0x7E
0x7F
0x80
0x81
0x82
0x83
0x84
0x85
0x86
0x87
0x88
0x89
0x8A
0x8B
0x8C
0x8D
0x8E
0x8F
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Register Name
Audio Content
Protection Packet (ACP)
Type
Rev. 0 | Page 29 of 48
Description
ACP type.
0 = generic audio.
1 = IEC 60958-identified audio.
2 = DVD audio.
3 = reserved for SACD.
Default = 0x00.
Audio content protection.
[7:6] audio_copy_permission.
[5:3] audio_copy_number.
[2:1] quality.
[0] transaction.
International standard recording code continued
(ISRC1). Indicates an ISRC2 packet is being
transmitted.
1 = the 2nd ISRC packet is needed.
Default = 0.
0 = ISRC1 status bits and PBs not valid.
1 = ISRC1 status bits and PBs valid.
Default = 0.
These bits indicate beginning, middle, and end of a
track.
001 = start.
010 = middle.
100 = end.
Default = 000.
ISRC1 Packet Byte 0.
ISRC1 Packet Byte 1.
ISRC1 Packet Byte 2.
ISRC1 Packet Byte 3.
ISRC1 Packet Byte 4.
ISRC1 Packet Byte 5.
ISRC1 Packet Byte 6.
ISRC1 Packet Byte 7.
ISRC1 Packet Byte 8.
ISRC1 Packet Byte 9.
ISRC1 Packet Byte 10.
ISRC1 Packet Byte 11.
ISRC1 Packet Byte 12.
ISRC1 Packet Byte 13.
ISRC1 Packet Byte 14.
ISRC1 Packet Byte 15.
ISRC2 Packet Byte 0.
ISRC2 Packet Byte 1.
ISRC2 Packet Byte 2.
ISRC2 Packet Byte 3.
ISRC2 Packet Byte 4.
ISRC2 Packet Byte 5.
ISRC2 Packet Byte 6.
ISRC2 Packet Byte 7.
ISRC2 Packet Byte 8.
ISRC2 Packet Byte 9.
ISRC2 Packet Byte 10.
ISRC2 Packet Byte 11.
AD9389
Hex
Address
0x90
0x91
0x92
0x93
0x94
0x95
Read/Write or
Read Only
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
0x96
Read/Write
0x97
Read/Write
0x98
Read/Write
Bits
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:6]
Default
Value
00000000
00000000
00000000
00000000
11000000
00******
Register Name
ISRC2_ PB12
ISRC2_ PB13
ISRC2_ PB14
ISRC2_ PB15
mask1
mask2
[7]
[6]
[5]
[4]
[3]
[2]
[7]
[6]
0*******
*0******
**0*****
***0****
****0***
*****0**
0*******
*0******
HPD_INT
MSEN_INT
VS_INT
AUD_FIFO_FULL_INT
ITU656_ERR_INT
EDID_RDY_INT
HDCP_ERR_INT
BKSV_flag
[2]
[7]
*****0**
0******
Test bit
Test bits
[3:0]
****0010
0x9C
Read/Write
[7:0]
0x9D
Read/Write
[3:0]
0xA2
Read/Write
0xA3
0xAF
0xB0
0xB1
0xB2
0xB3
0xB4
0xB5
0xB6
Description
ISRC2 Packet Byte 12.
ISRC2 Packet Byte 13.
ISRC2 Packet Byte 14.
ISRC2 Packet Byte 15.
Mask for Interrupt Group1 (0x96).
Mask for Interrupt Group 2 (0x97[7:6].
[7] for HDCP error.
[6] for BKSV flag.
Interrupt for hot plug detect (HPD).
Interrupt for monitor connection (MSEN).
Interrupt for active VS edge.
Interrupt for audio FIFO overflow.
Interrupt for ITU656 error.
Interrupt for EDID Ready.
Interrupt bit from HDCP master.
Set to 1 to instruct the MPU to read the BKSV or the
EDID MEM for revocation list checking.
Must be written to 1 for proper operation.
Must be written to 0 for proper operation.
Must be written to 0x2 for proper operation.
Test bits
Must be written to 0x3A for proper operation.
Test bit
Must be written to 1 for proper operation.
[7:0]
Test bits
Must be written to 0x87 for proper operation.
Read/Write
[7:0]
Test bits
Must be written to 0x87 for proper operation.
Read/Write
[7]
0*******
HDCP_desired
[5]
[4]
**0*****
***1****
frame_enc
[3]
[1]
****0***
******0*
ext_HDMI_MODE
[0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
*******0
00000000
00000000
00000000
00000000
00000000
00000000
00000000
An_0
An_1
An_2
An_3
An_4
An_5
An_6
HDCP encryption.
0 = input A/V content not to be encrypted.
1 = the input A/V content should be encrypted.
Default = 0.
Must be written to 0 for proper operation.
Frame encryption.
0 = the current frame should not be encrypted.
1 = the current frame should be encrypted.
Default = 1.
Must be written to 0 for proper operation.
HDMI mode.
0 = DVI.
1 = HDMI.
Default = 0.
Must be written to 0 for proper operation.
Byte 0 of An.
Byte 1 of An.
Byte 2 of An.
Byte 3 of An.
Byte 4 of An.
Byte 5 of An.
Byte 6 of An.
Read
Read
Read
Read
Read
Read
Read
****0***
Rev. 0 | Page 30 of 48
AD9389
Hex
Address
0xB7
0xBA
0xBE
Read/Write or
Read Only
Read
Read/Write
Read
Bits
[7:0]
[6]
Default
Value
00000000
*0******
Register Name
An_7
ENC_on
[5]
**0*****
int_HDMI_MODE
[4]
[7:5]
***0****
000*****
keys_read_error
clk_delay
[4]
***0****
Description
Byte 7 of An.
1 = the A/V content is being encrypted.
0 = not encrypted.
Default = 0.
Digital mode.
1 = HDMI mode.
0 = DVI mode.
1 = HDCP key reading error.
Edge select for input video clock.
011 = positive edge capture.
111 = negative edge capture.
Default = 000.
Must be written to 1 for proper operation.
[3]
****0***
Must be written to 0 for proper operation.
[7]
[6]
0*** ****
*0** ****
BCAPS
Repeater
[5]
**0* ****
KSV ready
[4]
[3:2]
[1]
***0 ****
**** 00**
**** **0*
Test bit
Test bit
HDCP support
[0]
**** ***0
Fast HDCP
0xBF
0xC0
0xC1
0xC2
0xC3
0xC4
Read
Read
Read
Read
Read
Read/Write
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
00000000
00000000
00000000
00000000
00000000
00000000
BKSV1
BKSV2
BKSV3
BKSV4
BKSV5
EDID Segment
0xC5
Read
0xC6
Read
0xC7
Read/Write
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
[4]
[3]
[2]
[1]
[0]
[7]
[6:0]
0*******
*0******
**0*****
***0****
****0***
*****0**
******0*
*******0
***0****
****0***
*****0**
******0*
*******0
0*******
*0000000
Error Flag
AN Stop
HDCP Enabled
EDID Ready Flag
I2C Interrupt
RI Flag
BKSV Update Flag
PJ Flag
HDMI Mode
HDCP Requested
Rx Sense
EEPROM Read OK
TMDS Output Enabled
BKSV Flag
BKSV Count
Rev. 0 | Page 31 of 48
HDMI reserved.
HDCP repeater.
0 = HDCP receiver is not repeater capable.
1 = HDCP receiver is repeater capable.
KSV FIFO ready.
1 = HDCP receiver has compiled list of attached KSVs.
Must be written to 0 for proper operation.
Reserved.
HDCP 1.1 features support.
0 = HDCP receiver does not support version 1.1
features.
1 = HDCP receiver supports 1.1 features such as
enhanced encryption status signaling (EESS).
Fast authentication.
0 = HDCP Receiver not capable of fast authentication.
1 = HDCP Receiver capable of receiving unencrypted
video during the session re-authentication.
BKSV read from Rx by the HDCP controller 40 bits
(5 bytes).
Sets the E-DDC segment used by the EDID fetch
routine.
Error flag.
AN stop.
HDCP enabled.
EDID ready.
I2C.
RI.
BKSV update.
PJ.
HDMI.
HDCP requested.
Rx sense.
EEPROM read.
TMDS output enabled.
BKSV flag.
BKSV count
AD9389
Hex
Address
0xC8
Read/Write or
Read Only
Read
0xC9
Read/Write
Bits
[7:4]
[3:0]
[3:0]
Default
Value
0000****
****0000
****0011
Register Name
HDCP Controller Error
HDCP Controller State
EDID Tries
Rev. 0 | Page 32 of 48
Description
HDCP controller error, see Table 28.
HDCP controller state.
Number of times that the EDID is read if unsuccessful.
Default = 0x3.
AD9389
2-WIRE SERIAL CONTROL REGISTER DETAIL CHIP IDENTIFICATION
0x00—Bits[7:0] Chip Revision
0x0A—Bit[3] MCLK_SP
An 8-bit register that represents the silicon revision.
If MCLK is available for S/PDIF, it is used for bit recovery;
otherwise, internal circuitry is used.
0x01—Bits[3:0] N[19:16]
These are the most significant four bits of a 20-bit word used
along with the 20-bit CTS term in the receiver to regenerate the
audio clock.
0x02—Bits[7:0] N[15-8]
0x03—Bits[7:0] [(7-0]
0x04—Bits[3:0] CTS_Int[19:16]
1 = MCLK active
0 = MCLK inactive
Default = 0
0x0A—Bit[2] MCLK_I2S
1 = I2S MCLK active
0 = I2S MCLK inactive
Default = 0
These are the most significant four bits of a 20-bit word used
along with the 20-bit N term in the receiver to regenerate the
audio clock. This is the measured or internal CTS. The internal
or external CTS can be selected via 0x0A Bit 7.
0x05—Bits[7:0] CTS_Int[15:8]
0x06—Bits[7:0] CTS_In[7:0]
0x07—Bits[3:0] CT_Ext[19:16])
If MCLK is available for I2S, it is used for bit recovery;
otherwise, internal circuitry is used.
0x0A—Bits[1:0] MCLK_Ratio
00 = ×128 fS
01 = ×256 fS
10 = ×384 fS
11 = ×512 fS
Default = 01
These are the most significant four bits of a 20-bit word used
along with the 20-bit N term in the receiver to regenerate the
audio clock. This is the external CTS. The internal or external
CTS can be selected via 0x0A Bit 7.
0x0B—Bit[6] MCLK_ Pol
0x08—Bits[7:0] CTS_Ext[15:8]
0x09—Bits[7:0] CTS_Ext[7:0]
0x0A—Bits[7] CTS_Sel
0x0B—Bit[5] Flat_Line
When internal CTS is selected, the CTS is calculated by the
AD9389.
0 = internal CTS
1 = external CTS
0x0A—Bits[6:5] Avg_Mode
00 = no filter
01 = divide by 4
10 = divide by 8
11 = divide by 16
Default = 10
0x0A—Bit[4] Audio_Sel
0 = I2S
1 = S/PDIF
Default = 0
0 = rising edge
1 = falling edge
Default = 0
1 = flat line audio (audio sample not valid)
0 = normal
Default = 0
0x0C—Bits[5:2] I2S enable
0001 = I2S0
0010 = I2S1
0100 = I2S2
1000 = I2S3
Default = 1111 for all
0x0C—Bits[1:0] I2S Format
00 = standard I2S mode
01 = right-justified I2S mode
10 = left-justified I2S mode
11 = raw IEC60958 mode
Default = 00
0x0D—Bits[4:0] I2S bit width
For right-justified audio only. Default is 11000 (24). Not valid
for widths greater than 24.
0x0E—Bits[5:3] SUBPKT0_L_src
Source of audio subpacket 0 (left channel) data. Default
is 000.
Rev. 0 | Page 33 of 48
AD9389
Table 23. Source of Subpacket Audio
0x1B—Bits[7:0] CSC_A2_LSB
Field Code
000
001
010
011
100
101
110
111
See Register 0x1A.
Channel (0 to 3) and Left/Right
Channel 0 Left
Channel 0 Right
Channel 1 Left
Channel 1 Right
Channel 2 Left
Channel 2 Right
Channel 3 Left
Channel 3 Right
0x1C—Bits[4:0] CSC_A3_MSB
The default value for the 13-bit a3 is 0x0000.
0x1D—Bits[7:0] CSC_A3_LSB
0x1E—Bits[4:0] CSC_A4_MSB
The default value for the 13-bit a4 is 0x1C84.
0x0E—Bits[2:0] SUBPKT0_R_src
0x1F—Bits[7:0] CSC_A4_LSB
0x20—Bits[4:0] CSC_B1_MSB
Default is 001 (see Table 27).
The default value for the 13-bit b1 is 0x1CBF.
0x0F—Bits[5:3] SUBPKT1_L_src
Default is 010 (see Table 27).
0x21—Bits[7:0] CSC_B1_LSB
0x22—Bits[4:0] CSC_B2_MSB
0x0F—Bits[2:0] SUBPKT1_R_src
The default value for the 13-bit b2 is 0x04A8.
Default is 011 (see Table 27).
0x10—Bits[5:3] SUBPKT2_L_src
0x23—Bits[7:0] CSC_B2_LSB
0x24—Bits[4:0] CSC_B3_MSB
Default is 100 (see Table 27).
The default value for the 13-bit b3 is 0x1E70.
0x10—Bits[2:0] SUBPKT2_R_src
0x25—Bits[7:0] CSC_B3_LSB
0x26—Bits[4:0] CSC_B4_MSB
Default is 101 (see Table 27).
The default value for the 13-bit b4 is 0x021E.
0x11—Bits[5:3] SUBPKT3_L_src
0x27—Bits[7:0] CSC_B4_LSB
0x28—Bits[4:0] CSC_C1_MSB
Default is 110 (see Table 27).
0x11—Bits[2:0] SUBPKT3_R_src
The default value for the 13-bit c1 is 0x0000.
Default is 111 (see Table 27).
0x18—Bits[4:0] CSC_A1_MSB
These five bits form the 5 MSBs of the Color Space Conversion
coefficient a1. Combined with the 8 LSBs of the following
register, they form a 13-bit, twos complement coefficient that is
user programmable. The equation takes the form of
ROUT = (a1 × RIN) + (a2 × GIN) + (a3 × BIN) + a4
GOUT = (b1 × RIN) + (b2 × GIN) + (b3 × BIN) + b4
BOUT = (c1 × RIN) + (c2 × GIN) + (c3 × BIN) + c4
0x29—Bits[7:0] CSC_C1_LSB
0x2A—Bits[4:0] CSC_C2_MSB
The default value for the 13-bit c2 is 0x04A8.
0x2B—Bits[7:0] CSC_C2_LSB
0x2C—Bits[4:0] CSC_C3_MSB
The default value for the 13-bit c3 is 0x0812.
0x2D—Bits[7:0] CSC_C3_LSB
0x2E—Bits[4:0] CSC_C4_MSB
The default value for the 13-bit, a1 coefficient is 0x0662.
The default value for the 13-bit c4 is 0x1BAC.
0x19—Bits[7:0] CSC_A1_LSB
0x2F—Bits[7:0] CSC_C4_LSB
See Register 0x18.
0x1A—Bits[4:0] CSC_A2_MSB
These five bits form the 5 MSBs of the Color Space Conversion
coefficient a2. This combined with the 8 LSBs of the following
register form a 13-bit, twos complement coefficient that is user
programmable. The equation takes the form of
ROUT = (a1 × RIN) + (a2 × GIN) + (a3 × BIN) + a4
GOUT = (b1 × RIN) + (b2 × GIN) + (b3 × BIN) + b4
BOUT = (c1 × RIN) + (c2 × GIN) + (c3 × BIN) + c4
The default value for the 13-bit a2 coefficient is 0x04A8.
Rev. 0 | Page 34 of 48
AD9389
0x3C—Bits[5:0] ext_VID_to_Rx
0x4A—Bits[7:0] Active Line End LSB
Table 24.
Combined with the MSB in Register 0x4B, the bits indicate the
last line of active video. All lines past this comprise a lower
horizontal bar. This is used in letter-box modes. If the 2-byte
value is greater than the number of lines in the display, there is
no lower horizontal bar.
0x4B—Bits[7:0] Active Line End MSB
See Register 0x4A.
0x4C—Bits[7:0] Active Pixel Start LSB
Combined with the MSB in Register 0x4D, these bits indicate
the first pixel in the display that is active video. All pixels before
this comprise a left vertical bar. If the 2-byte value is 0x00, there
is no left bar.
0x4D—Bits[7:0] Active Pixel Start MSB
See Register 0x4C.
0x4E—Bits[7:0] Active Pixel End LSB
Combined with the MSB in Register 0x4F, these bits indicate
the last active video pixel in the display. All pixels past this
comprise a right vertical bar. If the 2-byte value is greater than
the number of pixels in the display, there is no vertical bar.
0x4F—Bits[7:0] Active Pixel End MSB
See Register 0x4E.
LINE1, PIXEL 1
4:3 DISPLAY
ACTIVE LINE END
R0x4A, R0x4B
05724-009
TOP HORIZONTAL BAR
ACTIVE LINE START
R0x48, R0x49
BOTTOM HORIZONTAL BAR
Figure 9. Horizontal Bars
VREF can range from 59.826 Hz to 60.115 Hz.
VREF can range from 49.761 Hz to 50.080 Hz.
0x3D—Bits[7:6] pr_to_Rx
0x43—Bits[7:0] EDID Read Address
ACTIVE PIXEL START
R0x4C, R0x4D
This is a programmable I2C address from which the EDID
information (1 to 256 segment) can be read. Default is 0x7E.
ACTIVE PIXEL END
R0x4E, R0x4F
LINE1, PIXEL 1
4:3 DISPLAY
0x48—Bits[7:0] Active Line Start LSB
Combined with the MSB in Register 0x49, these bits indicate
the beginning line of active video. All lines before this comprise
a top horizontal bar. This is used in letter-box modes. If the
2-byte value is 0x00, there is no horizontal bar.
0x49—Bits[7:0] Active Line Start MSB
See Register 0x48.
Figure 10. Vertical Bars
Rev. 0 | Page 35 of 48
05724-010
2
Vertical Refresh
~60 Hz1
~60 Hz
~60 Hz
~60 Hz
~60 Hz
~60 Hz
~60 Hz
~60 Hz
~60 Hz
~60 Hz
~60 Hz
~60 Hz
~60 Hz
~60 Hz
~60 Hz
~60 Hz
~50 Hz2
~50 Hz
~50 Hz
~50 Hz
~50 Hz
~50 Hz
~50 Hz
~50 Hz
~50 Hz
~50 Hz
~50 Hz
~50 Hz
~50 Hz
~50 Hz
~50 Hz
24 Hz to 30 Hz
24 Hz to 30 Hz
24 Hz to 30 Hz
LEFT VERTICAL BAR
1
Format
480p
480p
480p
720p
1080i
480i
480i
240p
240p
480i
480i
240p
240p
480p
480p
1080p
576p
576p
720p
1080i
576i
576i
288p
288p
576i
576i
288p
288p
576p
576p
1080p
1080p
1080p
1080p
RIGHT VERTICAL BAR
VID
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
AD9389
0x50—Bits[7:5] audio_IF_cc
0x50—Bits[4] audi_IF_DM_INH
0x50—Bits[3:0] Level Shift
000 = refer to stream header
001 = 2 channels
010 = 3 channels
…
111 = 8 channels
LSV[3:0] – Level Shift Values with attenuation information.
0000 = 0 dB attenuation
0001 = 1 dB attenuation
…
1111 = 15 dB attenuation
Default = 0x0
0x51—Bits[7:0] Speaker Mapping
These bits define the suggested placement of speakers.
Table 25.
Bit 4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Bit 3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
CA
Bit 2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Bit 1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Bit 0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Bit 8
RRC
RRC
RRC
RRC
FRC
FRC
FRC
FRC
FRC
FRC
FRC
FRC
FRC
FRC
FRC
FRC
Bit 7
Bit 6
RC
RC
RC
RC
RLC
RLC
RLC
RLC
FLC
FLC
FLC
FLC
FLC
FLC
FLC
FLC
FLC
FLC
FLC
FLC
RR
RR
RR
RR
RR
RR
RR
RR
RR
RR
RR
RR
RR
RR
RR
RR
Rev. 0 | Page 36 of 48
Channel Number
Bit 5
Bit 4
FC
FC
RC
RC
RC
FC
RC
FC
RL
RL
RL
FC
RL
FC
RL
RL
RL
FC
RL
FC
RL
RL
RL
FC
RL
FC
FC
FC
RC
RC
RC
FC
RC
FC
RL
RL
RL
FC
RL
FC
Bit 3
LFE
LFE
LFE
LFE
LFE
LFE
LFE
LFE
LFE
LFE
LFE
LFE
LFE
LFE
LFE
LFE
Bit 2
FR
FR
FR
FR
FR
FR
FR
FR
FR
FR
FR
FR
FR
FR
FR
FR
FR
FR
FR
FR
FR
FR
FR
FR
FR
FR
FR
FR
FR
FR
FR
FR
Bit 1
FL
FL
FL
FL
FL
FL
FL
FL
FL
FL
FL
FL
FL
FL
FL
FL
FL
FL
FL
FL
FL
FL
FL
FL
FL
FL
FL
FL
FL
FL
FL
FL
AD9389
SOURCE PRODUCT DESCRIPTION (SPD) INFOFRAME
0x52—Bits[7:0] SPD_B1
0x6B—Bits[7:0] MPEG_B0
This is the first character in eight that is the name of the
company that appears on the product. The data characters are
7-bit ASCII code.
This is the lower 8 bits of 32 bits that specify the MPEG bit rate
in Hz.
0x53—Bits[7:0] SPD_B 2 (VN2)
0x54—Bits[7:0] SPD_B 3(VN3)
0x55—Bits[7:0] SPD_B 4(VN4)
0x56—Bits[7:0] SPD_B 5(VN5)
0x57—Bits[7:0] SPD_B 6(VN6)
0x58—Bits[7:0] SPD_B 7(VN7)
0x59—Bits[7:0] SPD_B 8(VN8)
0x5A—Bits[7:0] SBD_B9
This bit indicates that a continuation of the 16 ISRC1 packet
bytes (an ISRC2 packet) is being transmitted.
0x73—Bit[6] ISRC1 Valid
This bit indicates whether ISRC1 packet bytes are valid.
Table 27.
Product Description Character 1 (PD1)
This is the first character of 16 that contains the model number
and a short description of the product. The data characters are
7-bit ASCII code.
0x5B—Bits[7:0] SBD_B10(PD2)
0x5C—Bits[7:0] SBD_B11(PD3)
0x5D—Bits[7:0] SBD_B12(PD4)
0x5E—Bits[7:0] SBD_B13(PD5)
0x5F—Bits[7:0] SBD_B14(PD6)
0x60—Bits[7:0] SBD_B15(PD7)
0x61—Bits[7:0] SBD_B16(PD8)
0x62—Bits[7:0] SBD_B17(PD9)
0x63—Bits[7:0] SBD_B18(PD10)
0x64—Bits[7:0] SBD_B19(PD11)
0x65—Bits[7:0] SBD_B20(PD12)
0x66—Bits[7:0] SBD_B21(PD13)
0x67—Bits[7:0] SBD_B22(PD14)
0x68—Bits[7:0] SBD_B23(PD15)
0x69—Bits[7:0] SBD_B24(PD16)
0x6A—Bits[7:0] Source Device Information Code
These bytes classify the source device.
Table 26.
SDI Code
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A to 0xFF
Source
Unknown
Digital STB
DVD
D-VHS
HDD Video
DVC
DSC
Video CD
Game
PC general
Reserved
0x6C—Bits[7:0] MPEG_B1
0x6D—Bits[7:0] MPEG_B2
0x6E—Bits[7:0] MPEG_B3
0x73—Bits[7] ISRC1 Continued
ISRC1
0
1
Valid
ISRC1 Status bits and PBs not valid
ISRC1 Status bits and PBs valid
0x73—Bits[5:3] ISRC1 Status
These bits define where the samples are in the ISRC track: at
least two transmissions of 001 occur at the beginning of the
track; continuous transmission of 010 occurs in the middle of
the track, followed by at least two transmissions of 100 near the
end of the track.
0x74—Bits[7:0] ISRC1_PB0
0x75—Bits[7:0] ISRC1_PB1
0x76—Bits[7:0] ISRC1_PB2
0x77—Bits[7:0] ISRC1_PB3
0x78—Bits[7:0] ISRC1_PB4
0x79—Bits[7:0] ISRC1_PB5
0x7A—Bits[7:0] ISRC1_PB6
0x7B—Bits[7:0] ISRC1_PB7
0x7C—Bits[7:0] ISRC1_PB8
0x7D—Bits[7:0] ISRC1_PB9
0x7E—Bits[7:0] ISRC1_PB10
0x7F—Bits[7:0] ISRC1_PB11
0x80—Bits[7:0] ISRC1_PB12
0x81—Bits[7:0] ISRC1_PB13
0x82—Bits[7:0] ISRC1_PB14
0x83—Bits[7:0] ISRC1_PB15
Rev. 0 | Page 37 of 48
AD9389
0x84—Bits[7:0] ISRC2_PB0
This is transmitted only when the ISRC continue bit (Register
0x73 Bit 7) is set to 1.
0x85—Bits[7:0] ISRC2_PB1
0x86—Bits[7:0] ISRC2_PB2
0x87—Bits[7:0] ISRC2_PB3
0x88—Bits[7:0] ISRC2_PB4
0x89—Bits[7:0] ISRC2_PB5
0x8A—Bits[7:0] ISRC2_PB6
0x8B—Bits[7:0] ISRC2_PB7
0x8C—Bits[7:0] ISRC2_PB8
0x8D—Bits[7:0] ISRC2_PB9
0x8E—Bits[7:0] ISRC2_PB10
0x8F—Bits[7:0] ISRC2_PB11
0x90—Bits[7:0] ISRC2_PB12
0x91—Bits[7:0] ISRC2_PB13
0x92—Bits[7:0] ISRC2_PB14
0x93—Bits[7:0] ISRC2_PB15
0x94—Bits[7:0] mask1
0x95—Bits[7:6] mask2
0x96—Bit[7] HPD_INT
0x96—Bit[6] MSEN_INT
0x96—Bit[5] VS_INT
0x96—Bit[4]AUD_FIFO_FULL_INT
0x96—Bit[3] ITU656_ERR_INT
0x96—Bit[2] EDID_RDY_INT
0x97—Bit[7] HDCP_ERR_INT
0x97—Bit[6] BKSV_flag
0x97—Bit[2]
0x98—Bit[7]
0x98—Bits[3:0]
0x9C—Bits[7:0]
0x9D—Bits[3:0]
0xA2—Bits[7:0]
0xA3—Bits[7:0]
0xAF—Bit[7] HDCP_desired
0xAF—Bit[4] frame_enc
0xAF—Bit[1] ext_HDMI_MODE
0xB0—Bits[7:0] An_0
0xB1—Bits[7:0] An_1
0xB2—Bits[7:0] An_2
0xB3—Bits[7:0] An_3
0xB4—Bits[7:0] An_4
0xB5—Bits[7:0] An_5
0xB6—Bits[7:0] An_6
0xB7—Bits[7:0] An_7
0xB7—Bit[6] ENC_on
0xB7—Bit[5] int_HDMI_MODE
0xB7—Bit[4] keys_read_error
0xBA—Bits[7:5] clk_delay
0xBA—Bit[4] clk_delay
0xBE—Bit[7] BCAPS
0xBE—Bit[6]
0xBE—Bit[5]
0xBE—Bit[4]
0xBE—Bits[3:2]
0xBE—Bit[1]
0xBE—Bit[0]
0xBF—Bits[7:0] Bksv1
0xC0—Bits[7:0] Bksv Byte2
0xC1—Bits[7:0] Bksv3
0xC2—Bits[7:0] Bksv4
0xC3—Bits[7:0] Bksv5
0xC4—Bits[7:0] EDID Segment
These bits support up to 256 EDID segments that can be
addressed. The requested segment address is written here before
initiation of the read.
0xC5—Bit[7] ErrorFlag
0xC5—Bit[6] AN Stop
0xC5—Bit[5] HDCP Enabled
0xC5—Bit[4] EDID Ready
0xC5—Bit[3] I2C
0xC5—Bit[2] RI
0xC5—Bit[1] BKSV Update
0xC5—Bit[0] PJ
0xC6—Bit[4] HDMI Mode
0xC6—Bit[3] HDCP Requested
0xC6—Bit[2] Rx Sense
0xC6—Bit[1] EEPROM Read
0xC7—Bit[7] BKSV Flag
0xC7—Bits[6:0] BKSV Count
Rev. 0 | Page 38 of 48
AD9389
0xC8—Bits[7:4] HDCP Controller Error
0xC8—Bits[3:0] HDCP Controller State
When an error occurs in the HDCP flow, it is reported here
after setting the error flag (0xC5[7]).
This information is used in troubleshooting the HDCP
controller.
Table 28.
0xC9—Bits[3:0] EDID Read Tries
Error Code
0000
0001
0010
0011
0100
0101
0110
0111
1000
Error Condition
No error
Bad receiver BKSV
Ri mismatch
Pj mismatch
I2C error (usually a no acknowledge)
Timed out waiting for downstream repeater
Maximum cascade of repeaters exceeded
SHA-1 hash check of BKSV list failed
Too many devices connected to repeater tree
These bits define the number of times the EDID attempts to be
read if unsuccessful.
Rev. 0 | Page 39 of 48
AD9389
2-WIRE SERIAL CONTROL PORT
A 2-wire serial interface is provided. Up to two AD9389 devices
can be connected to the 2-wire serial interface, with each device
having a unique address.
DATA TRANSFER VIA SERIAL INTERFACE
The 2-wire serial interface comprises a clock (SCL) and a
bidirectional data (SDA) pin. The analog flat panel interface
acts as a slave for receiving and transmitting data over the serial
interface. When the serial interface is not active, the logic levels
on SCL and SDA are pulled high by external pull-up resistors.
If the AD9389 does not acknowledge the master device during
a write sequence, the SDA remains high so the master can
generate a stop signal. If the master device does not acknowledge the AD9389 during a read sequence, the AD9389 interprets this as the end of data. The SDA remains high so the
master can generate a stop signal.
Data received or transmitted on the SDA line must be stable for
the duration of the positive going SCL pulse. Data on SDA must
change only when SCL is low. If SDA changes state while SCL is
high, the serial interface interprets that action as a start or stop
sequence.
There are five components to serial bus operation:
• Start signal
• Slave address byte
• Base register address byte
• Data byte to read or write
• Stop signal
The first 8 bits of data transferred after a start signal comprise a
7-bit slave address (the first 7 bits) and a single R/W bit (the
eighth bit). The R/W bit indicates the direction of data transfer,
read from (1) or write to (0) the slave device. If the transmitted
slave address matches the address of the device, the AD9389
acknowledges by bringing SDA low on the ninth SCL pulse. If
the addresses do not match, the AD9389 does not acknowledge.
Table 29. Serial Port Addresses
Bit 6
A5
1
1
Bit 5
A4
1
1
Bit 4
A3
1
1
Bit 3
A2
0
0
Writing data to specific control registers of the AD9389 requires that the 8-bit address of the control register of interest
be written to after the slave address has been established. This
control register address is the base address for subsequent write
operations. The base address auto-increments by one for each
byte of data written after the data byte intended for the base
address.
Data is read from the control registers of the AD9389 in a
similar manner. Reading requires two data transfer operations:
When the serial interface is inactive (SCL and SDA are high),
communications are initiated by sending a start signal. The start
signal is a high-to-low transition on SDA while SCL is high.
This signal alerts all slave devices that a data transfer sequence
is coming.
Bit 2
A1
0
0
Bit 1
A0
0
1
•
The base address must be written with the R/W bit of the
slave address byte low to set up a sequential read operation.
•
Reading (the R/W bit of the slave address byte high) begins
at the previously established base address. The address of
the read register auto-increments after each byte is
transferred.
To terminate a read/write sequence to the AD9389, a stop signal
must be sent. A stop signal comprises a low-to-high transition
of SDA while SCL is high.
A repeated start signal occurs when the master device driving the
serial interface generates a start signal without first generating a
stop signal to terminate the current communication. This is used to
change the mode of communication (read/write) between the slave
and master without releasing the serial interface lines.
SDA
tBUFF
tSTAH
tDSU
tDHO
tSTASU
tSTOSU
tDAL
SCL
05724-011
Bit 7
A6 (MSB)
0
0
For each byte of data read from or written to, the MSB is the
first bit of the sequence.
tDAH
Figure 11. Serial Port Read/Write Timing
Rev. 0 | Page 40 of 48
AD9389
SERIAL INTERFACE READ/WRITE EXAMPLES
Write to one control register:
Read from four consecutive control registers:
•
•
Start signal
Slave address byte (R/W bit = low)
•
•
Start signal
Slave address byte (R/W bit = low)
•
•
•
•
•
•
Base address byte
Data byte to base address
Stop signal
Write to four consecutive control registers
Start signal
Slave address byte (R/W bit = low)
•
•
•
Base address byte
Start signal
Slave address byte (R/W bit = high)
•
•
•
•
•
•
Base address byte
Data byte to base address
Data byte to (base address + 1)
Data byte to (base address + 2)
Data byte to (base address + 3)
Stop signal
•
•
•
•
•
Data byte from base address
Data byte from (base address + 1)
Data byte from (base address + 2)
Data byte from (base address + 3)
Stop signal
Read from one control register:
Start signal
Slave address byte (R/W bit = low)
•
•
•
Base address byte
Start signal
Slave address byte (R/W bit = high)
•
•
Data byte from base address
Stop signal
SDA
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
ACK
05724-012
•
•
SCL
Figure 12. Serial Interface—Typical Byte Transfer
Rev. 0 | Page 41 of 48
AD9389
PCB LAYOUT RECOMMENDATIONS
POWER SUPPLY BYPASSING
It is also recommended to use a single ground plane for the
entire board. Experience has shown repeatedly that the noise
performance is the same or better with a single ground plane.
Using multiple ground planes can be detrimental because each
separate ground plane is smaller, and long ground loops can
result.
It is recommended to bypass each power supply pin with a
0.1 μF capacitor. The exception is when two or more supply
pins are adjacent to each other. For these groupings of
powers/grounds, it is necessary to have only one bypass
capacitor. The fundamental idea is to have a bypass capacitor
within about 0.5 cm of each power pin. Also, avoid placing the
capacitor on the opposite side of the PC board from the
AD9389, as that interposes resistive vias in the path.
In some cases, using separate ground planes is unavoidable,
therefore, it is recommended to place a single ground plane
under the AD9389. The location of the split should be at the
receiver of the digital outputs. For this case, it is even more
important to place components wisely because the current
loops are much longer (current takes the path of least
resistance).
The AD9389 is a high precision, high speed analog device. As
such, to get the maximum performance out of the part, it is
important to have a well laid out board. The following is a guide
for designing a board using the AD9389.
The bypass capacitors should be physically located between the
power plane and the power pin. Current should flow from the
power plane to the capacitor to the power pin. Do not make the
power connection between the capacitor and the power pin.
Placing a via underneath the capacitor pads, down to the power
plane, is generally the best approach.
It is particularly important to maintain low noise and good
stability of PVDD (the clock generator supply). Abrupt changes
in PVDD can result in similarly abrupt changes in sampling clock
phase and frequency. This can be avoided by careful attention to
regulation, filtering, and bypassing. It is highly desirable to
provide separate regulated supplies for each of the analog
circuitry groups (VDD and PVDD).
DIGITAL INPUTS
The digital inputs on the AD9389 are designed to work with
1.8 V signals, but are tolerant of 3.3 V signals. Therefore, no
extra components need to be added if using 3.3 V logic.
Any noise that gets onto the HSYNC, VSYNC, or clock input
traces can add jitter to the system. Therefore, minimize the
trace lengths and do not run any digital or other high frequency
traces near them. All TMDS lines must maintain a 50 Ω
impedance trace and it is recommended that the trace lengths
be as short as possible. To request a sample layout, send email to
[email protected].
Some graphic controllers use substantially different levels of
power when active (during active picture time) and when idle
(during horizontal and vertical sync periods). This can result in
a measurable change in the voltage supplied to the analog
supply regulator, which can in turn produce changes in the
regulated analog supply voltage. This can be mitigated by
regulating the analog supply, or at least PVDD, from a different,
cleaner power source (for example, from a 12 V supply).
Rev. 0 | Page 42 of 48
AD9389
COLOR SPACE CONVERTER (CSC) COMMON SETTINGS
Table 30. HDTV YCbCr (0 to 255) to RGB (0 to 255) (Default Setting for AD9389)
Register
Address
Value
Register
Address
Value
Register
Address
Value
0x18
0x0C
0x20
0x1C
0x28
0x00
Red/Cr Coeff 1
0x19
0x52
Green/Y Coeff 1
0x21
0x54
Blue/Cb Coeff 1
0x29
0x00
0x1A
0x08
0x22
0x08
0x2A
0x08
Red/Cr Coeff 2
0x1B
0x00
Green/Y Coeff 2
0x23
0x00
Blue/Cb Coeff 2
0x2B
0x00
0x1C
0x00
0x24
0x3E
0x2C
0x0E
Red/Cr Coeff 3
0x1D
0x00
Green/Y Coeff 3
0x25
0x89
Blue/Cb Coeff 3
0x2D
0x87
0x1E
0x19
0x26
0x02
0x2E
0x18
Red/Cr Offset
0x1F
0xD7
Green/Y Offset
0x27
0x91
Blue/Cb Offset
0x2F
0xBD
Table 31. HDTV YCbCr (16 to 235) to RGB (0 to 255)
Register
Address
Value
Register
Address
Value
Register
Address
Value
0x18
0x47
0x20
0x1D
0x28
0x00
Red/Cr Coeff 1
0x19
0x2C
Green/Y Coeff 1
0x21
0xDD
Blue/Cb Coeff 1
0x29
0x00
0x1A
0x04
0x22
0x04
0x2A
0x04
Red/Cr Coeff 2
0x1B
0xA8
Green/Y Coeff 2
0x23
0xA8
Blue/Cb Coeff 2
0x2B
0xA8
0x1C
0x00
0x24
0x1F
0x2C
0x08
Red/Cr Coeff 3
0x1D
0x00
Green/Y Coeff 3
0x25
0x26
Blue/Cb Coeff 3
0x2D
0x 75
0x1E
0x1C
0x26
0x01
0x2E
0x1B
Red/Cr Offset
0x1F
0x1F
Green/Y Offset
0x27
0x34
Blue/Cb Offset
0x2F
0x7B
Table 32. SDTV YCbCr (0 to 255) to RGB (0 to 255)
Register
Address
Value
Register
Address
Value
Register
Address
Value
0x18
0x2A
0x20
0x1A
0x28
0x00
Red/Cr Coeff 1
0x19
0xF8
Green/Y Coeff 1
0x21
0x6A
Blue/Cb Coeff. 1
0x29
0x00
0x1A
0x08
0x22
0x08
0x2A
0x08
Red/Cr Coeff 2
0x1B
0x00
Green/Y Coeff 2
0x23
0x00
Blue/Cb Coeff 2
0x2B
0x00
0x1C
0x00
0x24
0x1D
0x2C
0x0D
Red/Cr Coeff 3
0x1D
0x00
Green/Y Coeff 3
0x25
0x50
Blue/Cb Coeff 3
0x2D
0xDB
0x1E
0x1A
0x26
0x04
0x2E
0x19
Red/Cr Offset
0x1F
0x84
Green/Y Offset
0x27
0x23
Blue/Cb Offset
0x2F
0x12
Table 33. SDTV YCbCr (16 to 235) to RGB (0 to 255)
Register
Address
Value
Register
Address
Value
Register
Address
Value
0x18
0x46
0x20
0x1C
0x28
0x00
Red/Cr Coeff 1
0x19
0x63
Green/Y Coeff 1
0x21
0xC0
Blue/Cb Coeff 1
0x29
0x00
0x1A
0x04
0x22
0x04
0x2A
0x04
Red/Cr Coeff 2
0x1B
0xA8
Green/Y Coeff 2
0x23
0xA8
Blue/Cb Coeff 2
0x2B
0xA8
Rev. 0 | Page 43 of 48
0x1C
0x00
0x24
0x1E
0x2C
0x08
Red/Cr Coeff 3
0x1D
0x00
Green/Y Coeff 3
0x25
0x6F
Blue/Cb Coeff 3
0x2D
0x11
0x1E
0x1C
0x26
0x02
0x2E
0x1B
Red/Cr Offset
0x1F
0x84
Green/Y Offset
0x27
0x1E
Blue/Cb Offset
0x2F
0xAD
AD9389
Table 34. RGB (0 to 255) to HDTV YCbCr (0 to 255)
Register
Address
Value
Register
Address
Value
Register
Address
Value
0x18
0x08
0x20
0x03
0x28
0x1E
Red/Cr Coeff 1
0x19
0x2D
Green/Y Coeff 1
0x21
0x68
Blue/Cb Coeff 1
0x29
0x21
0x1A
0x18
0x22
0x0B
0x2A
0x19
Red/Cr Coeff 2
0x1B
0x93
Green/Y Coeff 2
0x23
0x71
Blue/Cb Coeff 2
0x2B
0xB2
0x1C
0x1F
0x24
0x01
0x2C
0x08
Red/Cr Coeff 3
0x1D
0x3F
Green/Y Coeff 3
0x25
0x27
Blue/Cb Coeff 3
0x2D
0x2D
0x1E
0x08
0x26
0x00
0x2E
0x08
Red/Cr Offset
0x1F
0x00
Green/Y Offset
0x27
0x00
Blue/Cb Offset
0x2F
0x00
Table 35. RGB (0 to 255) to HDTV YCbCr (16 to 235)
Register
Address
Value
Register
Address
Value
Register
Address
Value
0x18
0x07
0x20
0x02
0x28
0x1E
Red/Cr Coeff 1
0x19
0x06
Green/Y Coeff 1
0x21
0xED
Blue/Cb Coeff 1
0x29
0x64
0x1A
0x19
0x22
0x09
0x2A
0x1A
Red/Cr Coeff 2
0x1B
0xA0
Green/Y Coeff 2
0x23
0xD3
Blue/Cb Coeff 2
0x2B
0x96
0x1C
0x1F
0x24
0x00
0x2C
0x07
Red/Cr Coeff 3
0x1D
0x5B
Green/Y Coeff 3
0x25
0xFD
Blue/Cb Coeff 3
0x2D
0x06
0x1E
0x08
0x26
0x01
0x2E
0x08
Red/Cr Offset
0x1F
0x00
Green/Y Offset
0x27
0x00
Blue/Cb Offset
0x2F
0x00
Table 36. RGB (0 to 255) to SDTV YCbCr (0 to 255)
Register
Address
Value
Register
Address
Value
Register
Address
Value
0x18
0x08
0x20
0x04
0x28
0x1D
Red/Cr Coeff 1
0x19
0x2D
Green/Y Coeff 1
0x21
0xC9
Blue/Cb Coeff 1
0x29
0x3F
0x1A
0x19
0x22
0x09
0x2A
0x1A
Red/Cr Coeff 2
0x1B
0x27
Green/Y Coeff 2
0x23
0x64
Blue/Cb Coeff 2
0x2B
0x93
0x1C
0x1E
0x24
0x01
0x2C
0x08
Red/Cr Coeff 3
0x1D
0xAC
Green/Y Coeff 3
0x25
0xD3
Blue/Cb Coeff 3
0x2D
0x2D
0x1E
0x08
0x26
0x00
0x2E
0x08
Red/Cr Offset
0x1F
0x00
Green/Y Offset
0x27
0x00
Blue/Cb Offset
0x2F
0x00
Table 37. RGB (0 to 255) to SDTV YCbCr (16 to 235)
Register
Address
Value
Register
Address
Value
Register
Address
Value
0x18
0x07
0x20
0x04
0x28
0x1D
Red/Cr Coeff 1
0x19
0x06
Green/Y Coeff 1
0x21
0x1C
Blue/Cb Coeff 1
0x29
0xA3
0x1A
0x1A
0x22
0x08
0x2A
0x1B
Red/Cr Coeff 2
0x1B
0x1E
Green/Y Coeff 2
0x23
0x11
Blue/Cb Coeff 2
0x2B
0x57
Rev. 0 | Page 44 of 48
0x1C
0x1E
0x24
0x01
0x2C
0x07
Red/Cr Coeff 3
0x1D
0xDC
Green/Y Coeff 3
0x25
0x91
Blue/Cb Coeff 3
0x2D
0x06
0x1E
0x08
0x26
0x01
0x2E
0x08
Red/Cr Offset
0x1F
0x00
Green/Y Offset
0x27
0x00
Blue/Cb Offset
0x2F
0x00
AD9389
OUTLINE DIMENSIONS
0.75
0.60
0.45
16.20
16.00 SQ
15.80
1.60
MAX
61
80
60
1
PIN 1
14.20
14.00 SQ
13.80
TOP VIEW
(PINS DOWN)
1.45
1.40
1.35
0.15
0.05
0.20
0.09
7°
3.5°
0°
0.10 MAX
COPLANARITY
SEATING
PLANE
VIEW A
20
41
40
21
VIEW A
0.65
BSC
LEAD PITCH
ROTATED 90° CCW
0.38
0.32
0.22
COMPLIANT TO JEDEC STANDARDS MS-026-BEC
Figure 13. 80-Lead Low Profile Quad Flat Package [LQFP]
(ST-80-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD9389KSTZ-80 1
AD9389/PCB
1
Temperature Range
0°C to 70°C
Package Description
80-Lead Low Profile Quad Flat Package (LQFP)
Evaluation Board
Z = Pb-free part.
Rev. 0 | Page 45 of 48
Package Option
ST-80-2
AD9389
Notes
Rev. 0 | Page 46 of 48
AD9389
NOTES
Rev. 0 | Page 47 of 48
AD9389
NOTES
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent
Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05724-0-1/06(0)
Rev. 0 | Page 48 of 48