MN101EFA8/A7/A3/A2/G0 Series 8-bit Single-chip Microcontroller PubNo. 216A8-015E 1.1 Overview 1.1.1 Overview The MN101E series of 8-bit single-chip microcomputers (the memory expansion version of MN101C series) incorporate multiple types of peripheral functions. This chip series is well suited for automotive power window, camera, TV, CD, printer, telephone, home appliance, PPC, fax machine, music instrument and other applications. This LSI brings to embedded microcomputer applications flexible, optimized hardware configurations and a simple efficient instruction set. MN101EFA7G/A8G/A2G/A3G/G0G have an internal 128 KB of ROM and 6 KB of RAM. MN101EFA7D/A8D/A2D/A3D/G0D have an internal 64 KB of ROM and 4 KB of RAM. Peripheral functions include 5 external interrupts (3 external interrupts in MN101EFAG0G(D)), including NMI, 10 timer counters, 4 types of serial interfaces, A/D converter, watchdog timer and buzzer output. The system configuration is suitable for system control microcontroller. With 3 oscillation systems (internal frequency: 16 MHz, high-speed crystal/ceramic frequency: max. 10 MHz, low-speed crystal/ceramic frequency: 32.768 kHz) contained on the chip, the system clock can be switched to high-speed frequency input (NORMAL mode) or PLL input (PLL mode), or low-speed frequency input (SLOW mode). The system clock is generated by dividing the oscillation clock or PLL clock. The best operation clock for the system can be selected by switching its frequency ratio by programming. High speed mode has NORMAL mode which is based on the clock dividing fpll, (fpll is generated by original oscillation and PLL), by 2 (fpll/2), and the double speed mode which is based on the clock not dividing fpll. A machine cycle (minimum instruction execution time) in NORMAL mode is 200 ns when the original oscillation fosc is 10 MHz (PLL is not used). A machine cycle in the double speed mode, in which the CPU operates on the same clock as the external clock, is 100 ns when fosc is 10 MHz. A machine cycle in the PLL mode is 50 ns (maximum). Publication date: November 2014 1 MN101EFA8/A7/A3/A2/G0 Series 8-bit Single-chip Microcontroller PubNo. 216A8-015E 1.1.2 Product Summary This manual describes the following model. Table:1.1.1 Product Summary Model ROM Size RAM Size MN101EFA8G 128 KB 6 KB MN101EFA8D 64 KB 4 KB MN101EFA3G 128 KB 6 KB MN101EFA3D 64 KB 4 KB MN101EFA7G 128 KB 6 KB MN101EFA7D 64 KB 4 KB MN101EFA2G 128 KB 6 KB MN101EFA2D 64 KB 4 KB MN101EFG0G 128 KB 6 KB MN101EFG0D 64 KB 4 KB Publication date: November 2014 Classification Capacitive Touch Detection Circuit Flash EEPROM version Package 80 Pin TQFP 80 Pin LQFP Flash EEPROM version - Flash EEPROM version 64 Pin TQFP 64 Pin LQFP Flash EEPROM version - Flash EEPROM version - 56 Pin TQFP 2 MN101EFA8/A7/A3/A2/G0 Series 8-bit Single-chip Microcontroller PubNo. 216A8-015E 1.2 Hardware Functions Feature - Memory Capacity: ROM 128 KB / 64 KB RAM 6 KB / 4 KB - Package: MN101EFA8/A3 Series 80-Pin TQFP (12 mm 12 mm / 0.50 mm pitch, halogen free) 80-Pin LQFP (14 mm 14 mm / 0.65 mm pitch, halogen free) MN101EFA7/A2 Series 64-Pin TQFP (10 mm 10 mm / 0.50 mm pitch, halogen free) 64-Pin LQFP (14 mm 14 mm / 0.80 mm pitch) MN101EFG0 Series 56-Pin TQFP (10 mm 10 mm / 0.65 mm pitch, halogen free) Panasonic "halogen free" semiconductor products refer to the products made of molding resin and interposer which conform to the following standards. - Bromine : 900 ppm (Maximum Concentration Value) - Chlorine : 900 ppm (Maximum Concentration Value) - Bromine + Chlorine : 1500 ppm (Maximum Concentration Value) The above-mentioned standards are based on the numerical value described in IEC61249-2-21. Antimony and its compounds are not added intentionally. - Machine Cycle: High-speed mode 0.05 s / 20 MHz (4.0 V to 5.5 V) Low-speed mode 62.5 s / 32 kHz (4.0 V to 5.5 V) - Oscillation circuit: 3 channel oscillation circuit Internal oscillation (frc): 16 MHz Crystal/ceramic (fosc): Maximum 10 MHz Crystal/ceramic (fx): Maximum 32.768 kHz -Clock Multiplication circuit (PLL Circuit) PLL circuit output clock (fpll): fosc multiplied by 2, 3, 4, 5, 6, 8, 10, 1/2 frc multiplication by 4, 5 enable -Clock Gear for System Clock System Clock (fs): fpll divided by 1, 2, 4, 16, 32, 64, 128 -Clock Gear for control clock of peripheral function Control clock of peripheral function (fpll-div): stop or fpll divided by 1, 2, 4, 8, 16 Publication date: November 2014 3 MN101EFA8/A7/A3/A2/G0 Series 8-bit Single-chip Microcontroller PubNo. 216A8-015E - Memory Bank: Expands data memory space by the bank system (by 64 KB, 16 banks) Source address bank / Destination address bank - Operation Mode: NORMAL mode (High-speed mode) SLOW mode (Low-speed mode) HALT mode STOP mode (The operation clock can be switched in each mode.) - Operating Voltage: 4.0 V to 5.5 V - Operation ambient temperature: -40 C to +85 C - Interrupt: MN101EFA8 Series: 36 interrupts MN101EFA3 Series: 28 interrupts MN101EFA7 Series: 32 interrupts MN101EFA2 Series: 28 interrupts MN101EFG0 Series: 26 interrupts <Non-maskable interrupt> - Non-maskable interrupt and Watchdog timer overflow interrupt <Timer interrupts> - Timer 0 interrupt - Timer 1 interrupt - Timer 2 interrupt - Timer 3 interrupt - Timer 6 interrupt - Time base timer interrupt - Timer 7 interrupt - Timer 7 compare register 2 match interrupt - Timer 8 interrupt - Timer 8 compare register 2 match interrupt - Timer 9 overflow interrupt - Timer 9 underflow interrupt - Timer 9 compare register 2 match interrupt <Serial Interface interrupts> - Serial interface 0 interrupt - Serial interface 0 UART reception interrupt - Serial interface 1 interrupt - Serial interface 1 UART reception interrupt - Serial interface 2 interrupt - Serial interface 2 UART reception interrupt - Serial interface 4 interrupt - Serial interface 4 stop condition interrupt Publication date: November 2014 4 MN101EFA8/A7/A3/A2/G0 Series 8-bit Single-chip Microcontroller PubNo. 216A8-015E <A/D interrupt> - A/D conversion interrupt <External interrupts> - IRQ0: Edge selectable, noise filter connection available - IRQ1: Edge selectable, noise filter connection available - IRQ2: Edge selectable, noise filter connection available, both edges interrupt - IRQ3: Edge selectable, noise filter connection available, both edges interrupt - IRQ4: Edge selectable, noise filter connection available, both edges interrupt, Key scan interrupt <Touch Detect interrupts> - Touch 0 detect interrupt - Touch 0 detect error interrupt - Touch 0 round interrupt - Touch 0 data transmission interrupt (MN101EFA3/A2/G0 Series don't have this function) - Touch 1 detect interrupt - Touch 1 detect error interrupt - Touch 1 round interrupt - Touch 1 data transmission interrupt (MN101EFA7/A3/A2/G0 Series don't have this function) - Timer Counter: 10 timers - 8-bit timer for general use 4 sets - 16-bit timer for general use 2 sets - Motor control 16-bit timer 1 set - 8-bit free-run timer 1 set - Time base timer 1 set - Baud rate timer 1 set Timer 0 (8-bit timer for general use) - Square wave output (Timer pulse output) - Added pulse (2-bit) type PWM output can be output to large current pin TM0IOA - Event count - Simple pulse measurement - Clock source fpll-div, fpll-div/4, fpll-div/16, fpll-div/32, fpll-div/64, fpll-div/128, fs/2, fs/4, fs/8, fx, External clock, Timer A output Timer 1 (8-bit timer for general use) - Square wave output (Timer pulse output) can be output to large current pin TM1IOA - Event count - 16-bit cascade connected (with Timer 0) - Clock source fpll-div, fpll-div/4, fpll-div/16, fpll-div/32, fpll-div/64, fpll-div/128, fs/2, fs/4, fs/8, fx, External clock, Timer A output Publication date: November 2014 5 MN101EFA8/A7/A3/A2/G0 Series 8-bit Single-chip Microcontroller PubNo. 216A8-015E Timer 2 (8-bit timer for general use) - Square wave output (Timer pulse output) - Added pulse (2-bit) type PWM output can be output to large current pin TM2IOA - Event count - Simple pulse measurement - 24-bit cascade connected (with Timer 0 and Timer 1) - Clock source fpll-div, fpll-div/4, fpll-div/16, fpll-div/32, fpll-div/64, fpll-div/128, fs/2, fs/4, fs/8, fx, External clock, Timer A output Timer 3 (8-bit timer for general use) - Square wave output (Timer pulse output) can be output to large current pin TM3IOA - Event count - 16-bit cascade connected (with Timer 2) - 32-bit cascade connected (with Timer 0 and Timer 1 and Timer 2) - Clock source fpll-div, fpll-div/4, fpll-div/16, fpll-div/32, fpll-div/128, fs/2, fs/4, fs/8, fx, External clock, Timer A output Timer 6 (8-bit free-run timer, Time base timer) 8-bit free-run timer - Clock source fpll-div, fpll-div/212, fpll-div/213, fs, fx, fx/22, fx/23, fx/212, fx/213 Time base timer - Interrupt generation cycle fpll-div/27, fpll-div/28, fpll-div/29, fpll-div/210, fpll-div/213, fpll-div/215, fx/27, fx/28, fx/29, fx/210, fx/213, fx/215 Timer 7 (16-bit timer for general use) - Square wave output (Timer pulse output) - High precision PWM output (Cycle/Duty continuous changeable) can be output to large current pin TM7IOA - Event count - Input capture function (Both edges can be operated) - Clock source fpll-div, fpll-div/2, fpll-div/4, fpll-div/16, fs, fs/2, fs/4, fs/16, Timer A divided by 1, 2, 4, 16, External clock divided by 1, 2, 4, 16 Timer 8 (16-bit timer for general use) - Square wave output (Timer pulse output) - High precision PWM output (Cycle/Duty continuous changeable) can be output to large current pin TM8IOA - Event count - Input capture function (Both edges can be operated) - Clock source fpll-div, fpll-div/2, fpll-div/4, fpll-div/16, fs, fs/2, fs/4, fs/16, Timer A divided by 1, 2, 4, 16, External clock divided by 1, 2, 4, 16 Publication date: November 2014 6 MN101EFA8/A7/A3/A2/G0 Series 8-bit Single-chip Microcontroller PubNo. 216A8-015E Timer 9 (Motor control 16-bit timer) - Square wave output (Timer pulse output) can be output to large current pin TM9IOA - Event count - Complementary 3-phase PWM output can be output to large current pin TM9OD0 to TM9OD5 (Triangle wave and saw tooth wave are supported, dead time insertion available) - Clock source fpll-div, fpll-div/2, fpll-div/4, fpll-div/16, fs, fs/2, fs/4, fs/16, Timer A divided by 1, 2, 4, 16, External clock divided by 1, 2, 4, 16 Timer A (Baud rate timer) - Clock output for peripheral functions - Clock source fpll-div, fpll-div/2, fpll-div/4, fpll-div/8, fpll-div/16, fpll-div/32, fs/2, fs/4 - Watchdog timer Time-out cycle can be selected from fs/216, fs/218, fs/220 On detection of 2 errors, forcibly hard reset inside LSI. Operation start timing is selectable. (At reset release or write to register) - Buzzer Output/ Reverse Buzzer Output Output frequency can be selected from fpll-div/29, fpll-div/210, fpll-div/211, fpll-div/212, fpll-div/213, fpll-div/214, fx/23, fx/24 - A/D Converter: 10-bit 16 channels (MN101EFA8/A3 Series) 10-bit 12 channels (MN101EFA7/A2/G0 Series) - Serial Interface: 4 channels Serial 0: UART (full duplex)/ Clock synchronous Clock synchronous serial interface - Transfer clock source fpll-div/2, fpll-div/4, fpll-div/16, fpll-div/64, fs/2, fs/4, Timer 0 to 3 or Timer A divided by 1, 2, 4, 8, 16, External clock - MSB/LSB can be selected as the first bit to be transferred, arbitrary sizes of 2 to 8 bits are selectable. - Sequence transmission, reception or both are available Full duplex UART - Baud rate timer, selected from Timer 0 to 3 or Timer A - Parity check, overrun error/ framing error detection - Transfer size 7 to 8 bits can be selected Serial 1: UART (full duplex)/ Clock synchronous Clock synchronous serial interface - Transfer clock source fpll-div/2, fpll-div/4, fpll-div/16, fpll-div/64, fs/2, fs/4, Timer 0 to 3 or Timer A divided by 1, 2, 4, 8, 16, External clock - MSB/LSB can be selected as the first bit to be transferred, arbitrary sizes of 2 to 8 bits are selectable. - Sequence transmission, reception or both are available. Full duplex UART - Baud rate timer, selected from Timer 0 to 3 or Timer A - Parity check, overrun error/ framing error detection - Transfer size 7 to 8 bits can be selected Publication date: November 2014 7 MN101EFA8/A7/A3/A2/G0 Series 8-bit Single-chip Microcontroller PubNo. 216A8-015E Serial 2: UART (full duplex)/ Clock synchronous Clock synchronous serial interface - Transfer clock source fpll-div/2, fpll-div/4, fpll-div/16, fpll-div/64, fs/2, fs/4, Timer 0 to 3 or Timer A divided by 1, 2, 4, 8, 16, External clock - MSB/LSB can be selected as the first bit to be transferred, arbitrary sizes of 2 to 8 bits are selectable. - Sequence transmission, reception or both are available. Full duplex UART - Baud rate timer, selected from Timer 0 to 3 or Timer A - Parity check, overrun error/ framing error detection - Transfer size 7 to 8 bits can be selected Serial 4: Multi master IIC/ Clock synchronous Clock synchronous serial interface - Transfer clock source fpll-div/2, fpll-div/4, fpll-div/16, fpll-div/32, fs/2, fs/4, Timer 0 to 3 or Timer A divided by 1, 2, 4, 8, 16, External clock - MSB/LSB can be selected as the first bit to be transferred, arbitrary sizes of 2 to 8 bits are selectable. - Sequence transmission, reception or both are available. Multi master IIC - 7-bit slave address is settable. - General call communication mode is supported. - Automatic Reset: Power detection level: 4.3 V (at rising), 4.2 V (at falling) - LED Driver: 8 pins (Port A) - Touch Sensor Timer: 2 unit/ 12 channels (MN101EFA8 Series only) 1 unit/ 8 channels (MN101EFA7 Series only) - Ports (MN101EFA8/A3 Series) I/O ports Serial Interface pins Timer I/O Buzzer output pins A/D input pins External Interrupt pins LED (large current) driver Touch sensor input pins Touch sensor resistor connect pins High-speed oscillation Low-speed oscillation Special pins Operation mode input pins Reset input pin Analog reference voltage input pin Power pins Publication date: November 2014 70 pins 21 pins 19 pins 4 pins 16 pins 5 pins 8 pins 12 pins (MN101EFA3 Series does not have this function) 4 pins (MN101EFA3 Series does not have this function) 2 pins 2 pins 9 pins 3 pins 1 pin 1 pin 4 pins 8 MN101EFA8/A7/A3/A2/G0 Series 8-bit Single-chip Microcontroller PubNo. 216A8-015E - Ports (MN101EFA7/A2 Series) I/O ports Serial Interface pins Timer I/O Buzzer output A/D input pins External Interrupt pins LED (large current) driver Touch sensor input pins Touch sensor resistor connect pins High-speed oscillation Low-speed oscillation Special pins Operation mode input pins Reset input pin Analog reference voltage input pin Power pins - Ports (MN101EFG0 Series) I/O ports Serial Interface pins Timer I/O Buzzer output A/D input pins External Interrupt pins LED (large current) driver High-speed oscillation Low-speed oscillation Special pins Operation mode input pins Reset input pin Analog reference voltage input pin Power pins Publication date: November 2014 55 pins 15 pins 19 pins 4 pins 12 pins 5 pins 8 pins 8 pins (MN101EFA2 Series does not have this function) 2 pins (MN101EFA2 Series does not have this function) 2 pins 2 pins 8 pins 3 pins 1 pin 1 pin 3 pins 48 pins 12 pins 15 pins 4 pins 12 pins 3 pins 8 pins 2 pins 2 pins 8 pins 3 pins 1 pin 1 pin 3 pins 9 MN101EFA8/A7/A3/A2/G0 Series 8-bit Single-chip Microcontroller PubNo. 216A8-015E 1.3 Pin Description Pin configuration 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 PB0/AN8/TSIN0 PB1/AN9/TS0IN1 PB2/AN10/TS0IN2 PB3/AN11/TS0IN3 P94/AN12/TS0IN4 P93/AN13/TS0IN5 P92/AN14/TS0IN6 P33/AN15/TS0IN7/SBO4B/SDA4B P34/TS0RC/SBT4B/SCL4B P35/TS0OP/SBI4B P43/TS1OP/SBO0B/TXD0B P44/TS1RC/SBI0B/RXD0B P45/TS1IN0/SBT0B P46/TS1IN1 P47/TS1IN2 P57/TS1IN3/BUZZERA P56/NBUZZERA P55 P54 P53 1.3.1 1 2 3 4 5 6 7 8 9 ATRST NRST/P27 XI/P90 XO/P91 VSS OSC1/P25 OSC2/P26 VDD5 MMOD VDD18 DMOD 10 11 12 13 14 15 16 17 18 19 20 MN101EFA8 Series (80pinTQFP/LQFPTop View) 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 P52/SBT1A P51/SBI1A/RXD1A P50/SBO1A/TXD1A P62/TM1IOB P63/TM3IOB P64 P65/SBO2/TXD2 P66/SBI2/RXD2 P67/SBT2 P70/KEY0/SBI4A P71/KEY1/SBO4A/SDA4A P72/KEY2/SBT4A/SCL4A P73/KEY3 P74/KEY4 P75/KEY5/SBO1B/TXD1B P76/KEY6/SBI1B/RXD1B P77/KEY7/SBT1B P80/TM9OD0 P81/TM9OD1 P82/TM9OD2 N.C. VSS OCD_DATA/P00 OCD_CLK/TM9IOB/P01 RXD0A/SBI0A/TM7IOB/P02 TXD0A/SBO0A/TM8IOB/P03 SBT0A/TM2IOB/TM0IOB/P04 P05 P06 P07 IRQ0/P20 IRQ1/P21 IRQ2/P22 IRQ3/P23 IRQ4/P24 BUZZERB/P87 NBUZZERB/P86 TM9OD5/P85 TM9OD4/P84 TM9OD3/P83 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 TM0IOA/LED0/AN0/PA0 TM1IOA/LED1/AN1/PA1 TM2IOA/LED2/AN2/PA2 TM3IOA/LED3/AN3/PA3 LED4/AN4/PA4 TM7IOA/LED5/AN5/PA5 TM8IOA/LED6/AN6/PA6 TM9IOA/LED7/AN7/PA7 VREF+ Figure:1.3.1 Pin Configuration (MN101EFA8 Series 80-pin TQFP/LQFP) Publication date: November 2014 10 MN101EFA8/A7/A3/A2/G0 Series 8-bit Single-chip Microcontroller LED4/AN4/PA4 1 TM7IOA/LED5/AN5/PA5 2 TM8IOA/LED6/AN6/PA6 3 TM9IOA/LED7/AN7/PA7 4 VREF+ 5 ATRST 6 NRST/P27 7 XI/P90 9 VSS 10 OSC1/P25 11 P52/TS0IN6/SBT1A P50/TS0RC/SBO1A/TXD1A P62/TS0OP/TM1IOB P63/TM3IOB P64 52 51 50 49 P55/AN11/TS0IN3 57 P51/TS0IN7/SBI1A/RXD1A P56/AN10/TS0IN2/NBUZZER 58 53 P57/AN9/TS0IN1/BUZZER 59 54 P94/AN8/TS0IN0 60 55 PA0/AN0/LED0/TM0IOA 61 P54/TS0IN4 PA1/AN1/LED1/TM1IOA 62 P53/TS0IN5 PA2/AN2/LED2/TM2IOA 63 MN101EFA7 Series (64pin TQFP/LQFP Top View) 8 XO/P91 56 PA3/AN3/LED3/TM3IOA 64 PubNo. 216A8-015E 48 P65/SBO2/TXD2 47 P66/SBI2/RXD2 46 P67/SBT2 45 P70/KEY0/SBI4A 44 P71/KEY1/SBO4A/SDAA4 43 P72/KEY2/SBT4A/SCL4A 42 P73/KEY3 41 P74/KEY4 40 P75/KEY5/SBO1B/TXD1B 39 P76/KEY6/SBI1B/RXD1B 38 P77/KEY7/SBT1B 37 P80/TM9OD0 31 32 TM9OD5/P85 28 IRQ3/P23 NBUZZERB/P86 27 IRQ2/P22 30 26 IRQ1/P21 29 25 IRQ0/P20 IRQ4/P24 24 P06 BUZZERB/P87 23 P84/TM9OD4 P05 33 22 P83/TM9OD3 SBT0A/TM2IOB/TM0IOB/P04 16 DMOD 21 P82/TM9OD2 34 TXD0A/SBO0A/TM8IOB/P03 15 VDD18 20 P81/TM9OD1 35 RXD0A/SBI0A/TM7IOB/P02 36 19 14 OCD_CLK/TM9IOB/P01 MMOD 18 13 17 VDD5 N.C. 12 OCD_DATA/P00 OSC2/P26 Figure:1.3.2 Pin Configuration (MN101EFA7 Series 64-pin TQFP/LQFP) Publication date: November 2014 11 MN101EFA8/A7/A3/A2/G0 Series 8-bit Single-chip Microcontroller 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 PB0/AN8 PB1/AN9 PB2/AN10 PB3/AN11 P94/AN12 P93/AN13 P92/AN14 P33/AN15/SBO4B/SDA4B P34/SBT4B/SCL4B P35/SBI4B P43/SBO0B/TXD0B P44/SBI0B/RXD0B P45/SBT0B P46 P47 P57/BUZZERA P56/NBUZZERA P55 P54 P53 PubNo. 216A8-015E TM0IOA/LED0/AN0/PA0 TM1IOA/LED1/AN1/PA1 TM2IOA/LED2/AN2/PA2 TM3IOA/LED3/AN3/PA3 LED4/AN4/PA4 TM7IOA/LED5/AN5/PA5 TM8IOA/LED6/AN6/PA6 TM9IOA/LED7/AN7/PA7 VREF+ MN101EFA3 Series (80pin TQFP/LQFP Top View) 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 P52/SBT1A P51/SBI1A/RXD1A P50/SBO1A/TXD1A P62/TM1IOB P63/TM3IOB P64 P65/SBO2/TXD2 P66/SBI2/RXD2 P67/SBT2 P70/KEY0/SBI4A P71/KEY1/SBO4A/SDA4A P72/KEY2/SBT4A/SCL4A P73/KEY3 P74/KEY4 P75/KEY5/SBO1B/TXD1B P76/KEY6/SBI1B/RXD1B P77/KEY7/SBT1B P80/TM9OD0 P81/TM9OD1 P82/TM9OD2 P07 IRQ0/P20 IRQ1/P21 IRQ2/P22 IRQ3/P23 IRQ4/P24 BUZZERB/P87 NBUZZERB/P86 TM9OD5/P85 TM9OD4/P84 TM9OD3/P83 N.C. VSS OCD_DATA/P00 OCD_CLK/TM9IOB/P01 RXD0A/SBI0A/TM7IOB/P02 TXD0A/SBO0A/TM8IOB/P03 SBT0A/TM2IOB/TM0IOB/P04 P05 P06 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 ATRST NRST/P27 XI/P90 XO/P91 VSS OSC1/P25 OSC2/P26 VDD5 MMOD VDD18 DMOD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Figure:1.3.3 Pin Configuration (MN101EFA3 Series 80-pin TQFP/LQFP) Publication date: November 2014 12 MN101EFA8/A7/A3/A2/G0 Series 8-bit Single-chip Microcontroller LED4/AN4/PA4 1 TM7IOA/LED5/AN5/PA5 2 TM8IOA/LED6/AN6/PA6 3 TM9IOA/LED7/AN7/PA7 4 VREF+ 5 ATRST 7 XI/P90 8 XO/P91 9 VSS 10 OSC1/P25 11 VDD5 MMOD 48 P65/SBO2/TXD2 47 P66/SBI2/RXD2 46 P67/SBT2 45 P70/KEY0/SBI4A 44 P71/KEY1/SBO4A/SDA4A 43 P72/KEY2/SBT4A/SCL4A 42 P73/KEY3 41 P74/KEY4 40 P75/KEY5/SBO1B/TXD1B 39 P76/KEY6/SBI1B/RXD1B 38 P77/KEY7/SBT1B 37 P80/TM9OD0 36 P81/TM9OD1 P82/TM9OD2 P52/SBT1A P51/SBI1A/RXD1A P50/SBO1A/TXD1A P62/TM1IOB P63/TM3IOB P64 53 52 51 50 49 P55/AN11 54 P56/AN10/NBUZZER 57 P54 P57/AN9/BUZZER 58 P53 P94/AN8 59 55 PA0/AN0/LED0/TM0IOA 60 56 PA1/AN1/LED1/TM1IOA 61 PA2/AN2/LED2/TM2IOA 62 6 NRST/P27 OSC2/P26 63 64 PA3/AN3/LED3/TM3IOA PubNo. 216A8-015E MN101EFA2 Series (64pin TQFP/LQFP Top View) 12 13 14 20 21 22 23 24 25 26 27 28 29 30 31 32 RXD0A/SBI0A/TM7IOB/P02 TXD0A/SBO0A/TM8IOB/P03 SBT0A/TM2IOB/TM0IOB/P04 P05 P06 IRQ0/P20 IRQ1/P21 IRQ2/P22 IRQ3/P23 IRQ4/P24 BUZZERB/P87 NBUZZERB/P86 TM9OD5/P85 P84/TM9OD4 19 P83/TM9OD3 33 OCD_CLK/TM9IOB/P01 34 18 16 17 DMOD N.C. 15 OCD_DATA/P00 VDD18 35 Figure:1.3.4 Pin Configuration (MN101EFA2 Series 64-pin TQFP/LQFP) Publication date: November 2014 13 MN101EFA8/A7/A3/A2/G0 Series 8-bit Single-chip Microcontroller PA3/AN3/LED3/TM3IOA PA2/AN2/LED2/TM2IOA PA1/AN1/LED1/TM1IOA PA0/AN0/LED0/TM0IOA P94/AN8 P57/AN9/BUZZER P56/AN10/NBUZZER P55/AN11 P54 P50 P62/TM1IOB P63/TM3IOB P64 P65/SBO2/TXD2 56 55 54 53 52 51 50 49 48 47 46 45 44 43 PubNo. 216A8-015E LED4/AN4/PA4 1 42 P66/SBI2/RXD2 TM7IOA/LED5/AN5/PA5 2 41 P67/SBT2 TM8IOA/LED6/AN6/PA6 3 40 P70/KEY0/SBI4A TM9IOA/LED7/AN7/PA7 4 39 P71/KEY1/SBO4A/SDA4A VREF+ 5 38 P72/KEY2/SBT4A/SCL4A ATRST 6 37 P73/KEY3 NRST/P27 7 36 P74/KEY4 XI/P90 8 35 P75/KEY5/SBO1B/TXD1B XO/P91 9 34 P76/KEY6/SBI1B/RXD1B VSS 10 33 P77/KEY7/SBT1B OSC1/P25 11 32 P80/TM9OD0 OSC2/P26 12 31 13 P81/TM9OD1 VDD5 14 30 MMOD P82/TM9OD2 29 P83/TM9OD3 25 26 27 28 NBUZZERB/P86 TM9OD5/P85 TM9OD4/P84 IRQ1/P21 24 23 IRQ2/P22 22 IRQ0/P20 BUZZERB/P87 21 SBT0A/TM2IOB/TM0IOB/P04 OCD_CLK/TM9IOB/P01 20 18 19 17 RXD0A/SBI0A/TM7IOB/P02 16 DMOD OCD_DATA/P00 TXD0A/SBO0A/TM8IOB/P03 15 VDD18 MN101EFG0 Series (56pinTQFP Top View) Figure:1.3.5 Pin Configuration (MN101EFG0 Series 56-pin TQFP Publication date: November 2014 14 MN101EFA8/A7/A3/A2/G0 Series 8-bit Single-chip Microcontroller PubNo. 216A8-015E 1.3.2 Pin Specification : With function -: Without function Table remarks Pins I/O Direction Control P00 in/out P0DIR0 P01 P02 P03 P04 in/out in/out in/out in/out P0DIR1 P0DIR2 P0DIR3 P0DIR4 Pin Control P0PLU0 Special Functions Functions Description OCD_DATA On-boad programmer data pin TM9IOB Timer 9 input/output OCD_CLK On-boad programmer clock supply pin TM7IOB Timer 7 input/output P0PLU1 P0PLU2 P0PLU3 P0PLU4 SBI0A Serial 0 data input RXD0A UART 0 data input TM8IOB Timer 8 input/output SBO0A Serial 0 data input/output TXD0A UART 0 data input/output TM0IOB Timer 0 input/output TM2IOB Timer 2 input/output SBT0A Serial 0 clock input/output MN101EFA8 MN101EFA3 MN101EFA7 MN101EFA2 MN101EFG0 Series Series Series Series Series P05 in/out P0DIR5 P0PLU5 - - - P06 in/out P0DIR6 P0PLU6 - - - P07 in/out P0DIR7 P0PLU7 - - - - - P20 in/out P2DIR0 P2PLU0 IRQ0 External Interrupt 0 P21 in/out P2DIR1 P2PLU1 IRQ1 External Interrupt 1 P22 in/out P2DIR2 P2PLU2 IRQ2 External Interrupt 2 P23 in/out P2DIR3 P2PLU3 IRQ3 External Interrupt3 - P24 in/out P2DIR4 P2PLU4 IRQ4 External Interrupt4 - P25 in/out P2DIR5 P2PLU5 OSC1 Seramic/crystal high-speed clock input P26 in/out P2DIR6 P2PLU6 OSC2 Seramic/crystal high-speed clock output P27 in/out - - NRST Reset SB04B Serial 4 data input/output - - - - - - - - - - - - - - - P33 P34 P35 P43 P44 in/out in/out in/out in/out in/out P3DIR3 P3DIR4 P3DIR5 P4DIR3 P4DIR4 SDA4B Multi-master IIC 4 data input/output AN15 Analog 15 input P3PLUD3 P3PLUD4 TS0IN7 Touch sensor 0 input 7 SBT4B Serial 4 clock input/output SCL4B Multi-master IIC 4 clock input/output TS0RC Touch sensor 0 RC connect SBI4B Serial 4 data input TS0OP Touch sensor 0 output P3PLUD5 P4PLU3 P4PLU4 Publication date: November 2014 SBO0B Serial 0 data input/output TXD0B UART 0 data input/output TS1OP Touch sensor 1 output SBI0B Serial 0 data input RXD0B UART 0 data input TS1RC Touch sensor 1 RC connect - - - - 15 MN101EFA8/A7/A3/A2/G0 Series 8-bit Single-chip Microcontroller PubNo. 216A8-015E : With function -: Without function Table remarks Pins P45 P46 P47 P50 P51 P52 P53 P54 P55 P56 I/O Direction Control Pin Control in/out P4DIR5 P4PLU5 in/out in/out in/out in/out in/out in/out in/out in/out in/out P4DIR6 P4DIR7 P5DIR0 P5DIR1 P5DIR2 P5DIR3 P5DIR4 P5DIR5 P5DIR6 Special Functions SBT0B Serial 0 clock input/output TS1IN0 Touch sensor 1 input 0 - - TS1IN1 Touch sensor 1 input 1 P4PLU6 - - TS1IN2 Touch sensor 1 input 2 SBO1A Serial 1 data input/output TXD1A UART 1 data input/output TS0RC Touch sensor 0 RC connect SBI1A Serial 1 data input RXD1A UART 1 data input TS0IN7 P4PLU7 P5PLU0 *1 P5PLUD0 *2 P5PLU1 *1 P5PLUD1 *2 P5PLU2 *1 P5PLUD2 *2 P5PLU3 *1 P5PLUD3 *2 P5PLU4 *1 P5PLUD4 *2 P5PLU5 *1 P5PLUD5 *2 P5PLU6 *1 P5PLUD6 *2 P62 in/out in/out P5DIR7 P6DIR2 P5PLU7 *1 P5PLUD7 *2 - SBT1A Serial 1 clock input/output TS0IN6 Touch sensor 0 input 6 - - - - TS0IN5 Touch sensor 0 input 5 - - - - TS0IN4 Touch sensor 0 input 4 - - Touch sensor 0 input 3 NBUZZERA Buzzer reverse output AN10 Analog 10 input - - - - - - TS0IN3 - - Touch sensor 0 input 7 Analog 11 input - - - - - - AN11 - - TS0IN2 P57 Functions Description MN101EFA8 MN101EFA3 MN101EFA7 MN101EFA2 MN101EFG0 Series Series Series Series Series - - - Buzzer output Analog 9 input - TS1IN3 Touch sensor 1 input 3 TS0IN1 Touch sensor 0 input 1 - TM1IOB Timer 1 input/output TS0OP Touch sensor 0 output - - -- - - - - - - - - - - - P6PLU2 - Touch sensor 0 input 2 AN9 -- - BUZZERA - - - P63 in/out P6DIR3 P6PLU3 TM3IOB Timer 3 input/output P64 in/out P6DIR4 P6PLU4 - - SBO2 Serial 2 data input/output P65 in/out P6DIR5 P6PLU5 TXD2 UART 2 data input/output P66 P67 P70 in/out in/out in/out P6DIR6 P6DIR7 P7DIR0 SBI2 Serial 2 data input RXD2 UART 2 data input SBT2 Serial 2 clock input/output KEY0 Key interrupt 0 SBI4A Serial 4 data input P6PLU6 P6PLU7 P7PLU0 *1 MN101EFA8/A3 Series *2 MN101EFA7/A2/G0 Series Publication date: November 2014 16 MN101EFA8/A7/A3/A2/G0 Series 8-bit Single-chip Microcontroller PubNo. 216A8-015E Table remarks Pins I/O Direction Control P71 in/out P7DIR1 P72 in/out P7DIR2 Pin Control P7PLU1 P7PLU2 Special Functions Functions Description KEY1 Key interrupt 1 SBO4A Serial 4 data input/output SDA4A Multi-master IIC 4 data input/output KEY2 Key interrupt 2 SBT4A Serial 4 clock input/output SCL4A Multi-master IIC 4 clock input/output : With function -: Without function MN101EFA8 MN101EFA3 MN101EFA7 MN101EFA2 MN101EFG0 Series Series Series Series Series P73 in/out P7DIR3 P7PLU3 KEY3 Key interrupt 3 P74 in/out P7DIR4 P7PLU4 KEY4 Key interrupt 4 KEY5 Key interrupt 5 P75 in/out P7DIR5 P7PLU5 SBO1B Serial 1 data input/output P76 P77 in/out in/out P7DIR6 P7DIR7 P7PLU6 TXD1B UART 1 data input/output KEY6 Key interrupt 6 SBI1B Serial 1 data input RXD1B UART 1 data input KEY7 Key interrupt 7 SBT1B Serial 1 clock input/output P7PLU7 P80 in/out P8DIR0 P8PLU0 TM9OD0 Timer 9 output 0 P81 in/out P8DIR1 P8PLU1 TM9OD1 Timer 9 output 1 P82 in/out P8DIR2 P8PLU2 TM9OD2 Timer 9 output 2 P83 in/out P8DIR3 P8PLU3 TM9OD3 Timer 9 output 3 P84 in/out P8DIR4 P8PLU4 TM9OD4 Timer 9 output 4 P85 in/out P8DIR5 P8PLU5 TM9OD5 Timer 9 output 5 P86 in/out P8DIR6 P8PLU6 NBUZZERB Buzzer reverse output P87 in/out P8DIR7 P8PLU7 BUZZERB Buzzer output P90 in/out P9DIR0 P9PLUD0 XI Seramic/crystal low-speed clock input P91 in/out P9DIR1 P9PLUD1 XO Seramic/crystal low-speed clock output P92 in/out P9DIR2 P9PLUD2 - - - - - - - - - - - P93 P94 in/out in/out P9DIR3 P9DIR4 AN14 Analog 14 input TS0IN6 Touch sensor 0 input 6 AN13 Analog 13 input TS0IN5 Touch sensor 0 input 5 P9PLUD3 AN12 Analog 12 input TS0IN4 Touch sensor 0 input 4 - - P9PLUD4 AN8 Analog 8 input TS0IN0 Touch sensor 0 input 0 - PA0 in/out PADIR0 PAPLU0 Publication date: November 2014 AN0 Analog 0 input LED0 LED driving pin 0 TM0IOA Timer 0 input/output 17 MN101EFA8/A7/A3/A2/G0 Series 8-bit Single-chip Microcontroller PubNo. 216A8-015E : With function -: Without function Table remarks Pins I/O Direction Control PA1 in/out PADIR1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 in/out in/out in/out in/out in/out in/out in/out in/out in/out in/out PADIR2 PADIR3 PADIR4 PADIR5 PADIR6 PADIR7 PBDIR0 PBDIR1 PBDIR2 PBDIR3 Pin Control PAPLU1 PAPLU2 PAPLU3 Special Functions Functions Description AN1 Analog 1 input LED1 LED driving pin 1 TM1IOA Timer 1 input/output AN2 Analog 2 input LED2 LED driving pin 2 TM2IOA Timer 2 input/output AN3 Analog 3 input LED3 LED driving pin 3 TM3IOA Timer 3 input/output AN4 Analog 4 input LED4 LED driving pin 4 AN5 Analog 5 input LED5 LED driving pin 5 TM7IOA Timer 7 input/output PAPLU4 PAPLU5 PAPLU6 PAPLU7 AN6 Analog 6 input LED6 LED driving pin 6 TM8IOA Timer 8 input/output AN7 Analog 7 input LED7 LED driving pin 7 TM9IOA Timer 9 input/output AN8 Analog 8 input TS0IN0 Touch sensor 0 input 0 AN9 Analog 9 input TS0IN1 Touch sensor 0 input 1 AN10 Analog 10 input TS0IN2 Touch sensor 0 input 2 AN11 Analog 11 input TS0IN3 Touch sensor 0 input 3 PBPLUD0 PBPLUD1 PBPLUD2 PBPLUD3 Publication date: November 2014 MN101EFA8 MN101EFA3 MN101EFA7 MN101EFA2 MN101EFG0 Series Series Series Series Series - - - - - - - - - - - - - - - - 18 MN101EFA8/A7/A3/A2/G0 Series 8-bit Single-chip Microcontroller PubNo. 216A8-015E 1.3.3 Pin Functions Table remarks Pins MN101EF A8/A3 Series MN101EF A7/A2 Series MN101EF G0 Series I/O VDD5 17 13 13 - VSS 14, 22 10 10 - VDD18 19 15 15 - OSC1 15 11 11 Input OSC2 16 12 12 Output Function -: Without function Description Power connect pins Apply 4.0 V to 5.5 V to VDD5 and 0 V connect 0.1 F + 1 F or larger bypass capacitor for internal power stabilization. Internal power output pin This pin is output 1.8 V from internal power circuit. Don’t use the power supply to external device. For internal power circuit output stability, connect at least 0.1 F + 1 F one bypass capacitor between VDD18 and VSS. High speed operation clock input pin High speed operation clock output pin Connect these oscillation pins to ceramic or crystal ocsillators for high-frequency clock operation. If the clock is an external input, connect it to OSC1 and leave OSC2 open. The chip will not operate with an external clock when using STOP mode. NRST 11 7 7 I/O Reset pin [Active low] This pin resets the chip when power is turned on, is allocated as P27 and contains an internal pull-up resistor (Typ. 50 k). Setting this pin low initialize the internal state of the device. Thereafter, setting the input to high releases the reset. The hardware waits for the system clock to stabilize, then processes the reset interrupt. If a capacitor is to be inserted between NRST and VSS, it is recommended that a discharge diode be placed between NRST and VDD5. ATRST 10 6 6 input Auto reset setting pin Input "High" to enable auto reset function and "Low” to disable this function I/O I/O port 0 8-bit CMOS tri-state I/O port. Each bit can be set individually as either an input or output by P0DIR register. A pull-up resistor for each bit can be selected individually by P0PLU register. At reset, the input mode is selected and pull-up resistor is disabled (high impedance). I/O I/O port 2 7-bit CMOS tri-state I/O port. Each bit can be set individually as either an input or output by P2DIR register. A pull-up resistor for each bit can be selected individually by P2PLU register. At reset, the input mode is selected and pull-up resistor is disabled (high impedance) input port 2 P27 has an N-channel open-drain configuration. I/O port 3 3-bit CMOS tri-state I/O port. Each bit can be set individually as either an input or output by P3DIR register. A pull-up /pull-down resistor for each bit can be selected individually by P3PLUD register. A pull-up/down resistor connection for each port can be selected individually in SELUD register. A pull-up/pull down can not be mixed. At reset, the input mode is selected and pull-up resistor is disabled (high impedance). I/O port 4 5-bit CMOS tri-state I/O port. Each bit can be set individually as either an input or output by P4DIR register. A pull-up resistor for each bit can be selected individually by P4PLU register. At reset, the input mode is selected and pull-up resistor is disabled (high impedance). P00 23 18 17 P01 24 19 18 P02 25 20 19 P03 26 21 20 P04 27 22 21 P05 28 23 - P06 29 24 - P07 30 - - P20 31 25 22 P21 32 26 23 P22 33 27 24 P23 34 28 - P24 35 29 - P25 15 11 11 P26 16 12 12 P27 11 7 7 P33 73 - - P34 72 - - input I/O P35 71 - - P43 70 - - P44 69 - - P45 68 - - P46 67 - - P47 66 - - Publication date: November 2014 I/O 19 MN101EFA8/A7/A3/A2/G0 Series 8-bit Single-chip Microcontroller PubNo. 216A8-015E Table remarks Pins MN101EF A8/A3 Series MN101EF A7/A2 Series MN101EF G0 Series P50 58 52 47 P51 59 53 - P52 60 54 - P53 61 55 - P54 62 56 48 P55 63 57 49 P56 64 58 50 P57 65 59 51 P62 57 51 46 P63 56 50 45 P64 55 49 44 P65 54 48 43 P66 53 47 42 P67 52 46 41 P70 51 45 40 P71 50 44 39 P72 49 43 38 P73 48 42 37 I/O 47 41 36 P75 46 40 35 P76 45 39 34 P77 44 38 33 P80 43 37 32 P81 42 36 31 P82 41 35 30 P83 40 34 29 P84 39 33 28 P85 38 32 27 P86 37 31 26 P87 36 30 25 P90 12 8 8 P91 13 9 9 P92 74 - - P93 75 - - P94 76 60 52 PA0 1 61 53 PA1 2 62 54 PA2 3 63 55 PA3 4 64 56 PA4 5 1 1 PA5 6 2 2 PA6 7 3 3 PA7 8 4 4 I/O port 5 I/O I/O port 6 6-bit CMOS tri-state I/O port. Each bit can be set individually as either an input or output by P6DIR register. A pull-up resistor for each bit can be selected individually by P6PLU register. At reset, the input mode is selected and pull-up resistor is disabled (high impedance). I/O I/O port 7 8-bit CMOS tri-state I/O port. Each bit can be set individually as either an input or output by P7DIR register. A pull-up resistor for each bit can be selected individually by P7PLU register. At reset, the input mode is selected and pull-up resistor is disabled (high impedance). I/O I/O port 8 8-bit CMOS tri-state I/O port. Each bit can be set individually as either an input or output by P8DIR register. A pull-up resistor for each bit can be selected individually by P8PLU register. At reset, the input mode is selected and pull-up resistor is disabled (high impedance). I/O port 9 5-bit CMOS tri-state I/O port. Each bit can be set individually as either an input or output by P9DIR register. A pull-up /pull-down resistor for each bit can be selected individually by P9PLUD register. A pull-up/down resistor connection for each port can be selected individually in SELUD register. A pull-up/pull down can not be mixed. At reset, the input mode is selected and pull-up resistor is disabled (high impedance). I/O port A 8-bit CMOS tri-state I/O port. Each bit can be set individually as either an input or output by PADIR register. A pull-up resistor for each bit can be selected individually by PAPLU register. At reset, the input mode is selected and pull-up resistor is disabled (high impedance). I/O I/O Publication date: November 2014 Description 8-bit CMOS tri-state I/O port. Each bit can be set individually as either an input or output by P5DIR register. A pull-up /pull-down resistor for each bit can be selected individually by P5PLUD register. A pull-up/down resistor connection for each port can be selected individually in SELUD register. A pull-up/pull down can not be mixed. At reset, the input mode is selected and pull-up resistor is disabled (high impedance). Pull-down function is not equipped in MN101EFA8/A3 Series. I/O P74 Function -: Without function 20 MN101EFA8/A7/A3/A2/G0 Series 8-bit Single-chip Microcontroller PubNo. 216A8-015E Table remarks Pins MN101EF A8/A3 Series MN101EF A7/A2 Series MN101EF G0 Series PB0 80 - - PB1 79 - - PB2 78 - - PB3 77 - - SBO0A 26 21 20 SBO0B 70 - - SBO1A 58 52 - SBO1B 46 40 35 I/O I/O SBO2 54 48 43 SBO4A 50 44 39 SBO4B 72 - - SBI0A 25 20 19 SBI0B 69 - - SBI1A 59 53 - SBI1B 45 39 34 SBI2 53 47 42 SBI4A 51 45 40 SBI4B 71 - - SBT0A 27 22 21 SBT0B 68 - - SBT1A 60 54 - SBT1B 44 38 33 SBT2 52 46 41 SBT4A 49 43 38 SBT4B 72 - - TXD0A 26 21 20 TXD0B 70 - - TXD1A 58 52 - TXD1B 46 40 35 TXD2 54 48 43 RXD0A 25 20 19 RXD0B 69 - - RXD1A 59 53 - RXD1B 45 39 34 RXD2 53 47 42 SDA4A 50 44 39 SDA4B 72 - - SCL4A 49 43 38 SCL4B 72 - - Output Input I/O Output Input I/O I/O Publication date: November 2014 Function -: Without function Description I/O port B 4-bit CMOS tri-state I/O port. Each bit can be set individually as either an input or output by PBDIR register. A pull-up /pull-down resistor for each bit can be selected individually by PBPLUD register. A pull-up/down resistor connection for each port can be selected individually in SELUD register. A pull-up/pull down can not be mixed. At reset, the input mode is selected and pull-up resistor is disabled (high impedance). Serial interface transmission data output pins Transmission data output pins for serial interface 0,1,2,4. The output configuration, either COMS push-pull or Nch open-drain can be selected in P0ODC, P3ODC, P4ODC, P5ODC, P6ODC and P7ODC registers. Pull-up resistor can be selected in P0PLU, P3PLUD, P4PLU, P5PLU(D), P6PLU, and P7PLU registers. Select output mode in P0DIR, P3DIR, P4DIR, P5DIR, P6DIR, and P7DIR registers and set serial data output mode in serial mode register 1 (SC0MD1, SC1MD1, SC2MD1, SC4MD1). These can be used as normal I/O pins when serial interface is not used. Serial interface reception data input pins Reception data input pins for serial interface 0,1,2,4. Pull-up resistor can be selected in P0PLU, P3PLUD, P4PLU, P5PLU(D), P6PLU and P7PLU registers. Select the output mode in P0DIR, P3DIR, P4DIR, P5DIR, P6DIR and P7DIR registers and select serial data input mode in serial mode register 1 (SC0MD1, SC1MD1, SC2MD1, SC4MD1). These can be used as normal I/O pins when serial interface is not used. Serial interface Clock I/O pins Clock I/O pins for serial interface 0,1,2,4. The output configuration, either COMS push-pull or Nch open-drain can be selected in P0ODC, P3ODC, P4ODC, P5ODC, P6ODC and P7ODC registers. Pull-up resistor can be selected in P0PLU, P3PLUD, P4PLU, P5PLU(D), P6PLU and P7PLU registers. Select clock I/O in P0DIR, P3DIR, P4DIR, P5DIR, P6DIR and P7DIR registers and serial mode register 1 (SC0MD1, SC1MD1, SC2MD1, SC4MD1) with the communication mode. These can be used as normal I/O pins when serial interface is not used. UART transmission data output pins In serial interface 0,1,2 in UART mode, this pin is configured as the transmission data output pin. The output configuration, either COMS push-pull or Nch open-drain can be selected in P0ODC, P4ODC, P5ODC, P6ODC and P7ODC registers. Pull-up resistor can be selected by P0PLU, P4PLU, P5PLU(D), P6PLU and P7PLU registers. Select the output mode in P0DIR, P4DIR, P5DIR, P6DIR and P7DIR registers and select serial data output mode in serial mode register 1 (SC0MD1, SC1MD1, SC2MD1). These can be used as normal I/O pins when serial interface is not used. UART reception data output pins In serial interface 0,1,2 in UART mode, this pin is configured as the reception data input pin. Pull-up resistor can be selected in P0PLU, P4PLU, P5PLU(D), P6PLU and P7PLU registers. Select the input mode in P0DIR, P4DIR, P5DIR, P6DIR and P7DIR registers and select serial input in serial mode register 1 (SC0MD1, SC1MD1, SC2MD1). These can be used as normal I/O pins when serial interface is not used. IIC data I/O pins In serial interface 4 in IIC mode, this pin is configured as the data I/ O pin. For the output configuration, select Nch open-drain in P3ODC and P7ODC register and set pull-up resistor in P3PLUD and P7PLU register. Select the output mode in P0DIR register and select serial data I/O mode by serial mode register 1 (SC4MD1). These can be used as normal I/O pin when serial interface is not used. IIC clock I/O pins In serial interface 4 in IIC mode, this pin is configured as the clock I/O pin. For the output configuration, select Nch open-drain in P0ODC and P7ODC register and set pull-up resistor by P0PLU and P7PLU register. Select the output mode at P0DIR register and select serial clock I/O mode in serial mode register 1 (SC4MD1). These can be used as normal I/O pin when serial interface is not used 21 MN101EFA8/A7/A3/A2/G0 Series 8-bit Single-chip Microcontroller PubNo. 216A8-015E Table remarks MN101EF A8/A3 Series MN101EF A7/A2 Series MN101EF G0 Series TM0IOA 1 61 53 TM0IOB 27 22 21 TM1IOA 2 62 54 TM1IOB 57 51 46 TM2IOA 3 63 55 TM2IOB 27 22 21 TM3IOA 4 64 56 TM3IOB 56 50 45 Pins I/O I/O BUZZERA 65 59 51 BUZZERB 36 30 25 NBUZZERA 64 58 50 NBUZZERB 37 31 26 Output TM7IOA 6 2 2 TM7IOB 25 20 19 TM8IOA 7 3 3 TM8IOB 26 21 20 I/O TM9IOA 8 4 4 TM9IOB 24 19 18 TM9OD0 43 37 32 TM9OD1 42 36 31 TM9OD2 41 35 30 Output TM9OD3 40 34 29 TM9OD4 39 33 28 TM9OD5 38 32 27 VREF+ 9 5 5 AN0 1 61 53 AN1 2 62 54 AN2 3 63 55 AN3 4 64 56 AN4 5 1 1 AN5 6 2 2 AN6 7 3 3 AN7 8 4 4 AN8 80 60 52 - AN9 79 59 51 78 58 50 AN11 77 57 49 AN12 76 - - AN13 75 - - AN14 74 - - AN15 73 - - Publication date: November 2014 Description Timer I/O pins Event counter clock input pin, timer output and PWM signal output pin for 8-bit timer 0 to 3. To use this pin as event clock input, configure it as input by P0DIR, P6DIR and PADIR register. In the input mode, pull-up resistor can be selected in P0PLU, P6PLU, and PAPLU registers. For timer output, PWM signal output, select the special function pin in P0OMD1, P0OMD2, P6OMD and PAOMD registers, and set to the output mode in P0DIR, P6DIR and PADIR registers. These can be used as normal I/O pins when Timer I/O pin is not used. Buzzer output pins Piezoelectric buzzer driving pin. Buzzer output is available to Port 5, 8. The driving frequency can be set in DLYCTR register. In order to select Buzzer output, select the special function pin in P5OMD, P8OMD register, and set P5DIR, P8DIR register to the output mode. At the same time, select Buzzer output in oscillation stabilization wait control register (DLYCTR). These can be used as normal I/O pins when Buzzer output is not used. Timer I/O pins Event counter clock input pin, timer output and PWM signal output pin for 16-bit timer7,8 and 9. To use this pin as event clock input, configure it as input with P0DIR and PADIR registers. In the input mode, pull-up resistor can be selected by P0PLU and PAPLU registers. For timer output, PWM signal output, select the special function pin in P0OMD1 and PAOMD registers, and set to the output mode in P0DIR and PADIR registers. These can be used as normal I/O pins when not used as timer I/O pins. Timer PWM output PWM signal output pin for 16-bit timer 9. Select the special function pin in P8OMD register, and set to the output mode in P8DIR register. These can be used as normal I/O pins when not used as timer I/O pins. A/D reference voltage input pin Reference power supply pin for A/D converter. Normally, the values of VREF+ = VDD5 is used. [MN101EFA8/A3 Series] Analog input pins for 16-channel, 10-bit A/D converter. Select the analog input by P3IMD, P9IMD, PAIMD, PBIMD register. When not used for analog input, these pins can be used as normal input pins. input AN10 Function -: Without function Analog input pins [MN101EFA7/A2/G0 Series] Analog input pins for 12-channel, 10-bit A/D converter. Select the analog input by P5IMD, P9IMD, PAIMD register. When not used for analog input, these pins can be used as normal input pins. 22 MN101EFA8/A7/A3/A2/G0 Series 8-bit Single-chip Microcontroller PubNo. 216A8-015E Table remarks Pins MN101EF A8/A3 Series MN101EF A7/A2 Series MN101EF G0 Series IRQ0 31 25 22 IRQ1 32 26 23 IRQ2 33 27 24 IRQ3 34 28 - IRQ4 35 29 - KEY0 51 45 40 KEY1 50 44 39 KEY2 49 43 38 KEY3 48 42 37 KEY4 47 41 36 KEY5 46 40 35 KEY6 45 39 34 KEY7 44 38 33 LED0 1 61 53 LED1 2 62 54 LED2 3 63 55 LED3 4 64 56 LED4 5 1 1 LED5 6 2 2 LED6 7 3 3 I/O Function -: Without function Description Input External interrupt External interrupt input pins. Select the external interrupt input enable by IRQCNT register. The valid edge for IRQ0 to 4 can be selected with IRQnICR register. IRQ2 to 4 can be set at both edges at pin voltage level. When not used for interrupts, these can be used as normal input pins. Input Key interrupt input pins Input pins for KEY interrupt based on OR condition result of pin inputs. These can be set to key input pins by 1-bit with KEY interrupt control register (KEYT3_1IMD, KEY3_2_IMD). When not used for KEY input, these pins can be used as normal I/O pins. LED drive pins Large current output pins. Select the large current output by LEDCNT registers. When not used for LED output, these pins can be used as normal I/O pins. Output LED7 8 4 4 DMOD 20 16 15 Input Mode switch input pins Set always to VDD5 level. MMOD 18 14 14 Input ROM area switch input pins at start Set always to VSS level. TS0IN0 80 60 - TS0IN1 79 59 - TS0IN2 78 58 - TS0IN3 77 57 - TS0IN4 76 56 - TS0IN5 75 55 Input Touch sensor input pins These pins are not equipped in MN101EFA3 Series, MN101EFA2 Series and MN101EFG0 Series. Input pins for Touch Sensor Timer of 12 channels (8 channels of MN101EFA7 Series). Set "Used" to corresponding channel by TS0TCHSEL, TS1TCHSEL register. This setup is available regardless of the setting of port control registers. These can be used as normal I/O pins when Touch Sensor Timer is not used. Touch sensor resistor connect pins. These pins are not equipped in MN101EFA3 Series, MN101EFA2 Series and MN101EFG0 Series. These are used in the following cases. 1. External resistor connection for Touch Sensor Timer Set both TS0MD, TS1MD and RS0MD, RS1MD of TS0TMD, TS1TMD register to "1”. 2. The capacitor/resistor connection for Touch Sensor using A/D converter Set TS0ADCNT, TS1ADCNT register. This setup is available regardless of the setting of port control registers. These can be used as normal I/O pins when Touch Sensor Timer is not used. TS0IN6 74 54 - TS0IN7 73 53 - TS1IN0 68 - - TS1IN1 67 - - TS1IN2 66 - - TS1IN3 65 - - TS0RC 72 52 - TS1RC 69 - - TS0OP 71 51 - TS1OP 70 - - Input Output Publication date: November 2014 23 MN101EFA8/A7/A3/A2/G0 Series 8-bit Single-chip Microcontroller PubNo. 216A8-015E For the MMOD setup in rewriting the flash memory, refer to [Chapter 16 16.5 User Mode Microcontroller Rewriting], [Chapter 16 16.6 BOOT Mode Microcontroller Rewriting], [Chapter 16 16.7 Appendix]. .. .. Publication date: November 2014 24 MN101EFA8/A7/A3/A2/G0 Series 8-bit Single-chip Microcontroller PubNo. 216A8-015E 1.4 Block Diagram XI, P90 XO, P91 ROM 128 KB RAM 6 KB Port 6 8-bit Timer 0 Serial Interface 0 8-bit Timer 1 Serial Interface 1 8-bit Timer 2 Serial Interface 2 8-bit Timer 3 Serial Interface 4 8-bit Timer A Watchdog Timer Time Base Timer A Buzzer 16-bit Timer 7 Motor Control Timer 9 Auto Reset PA0, AN0, LED0, TM0IOA PA1, AN1, LED1, TM1IOA PA2, AN2, LED2, TM2IOA PA3, AN3, LED3, TM3IOA PA4, AN4, LED4 PA5, AN5, LED5, TM7IOA PA6, AN6, LED6, TM8IOA PA7, AN7, LED7, TM9IOA PB0, AN8, TS0IN0 PB1, AN9, TS0IN1 PB2, AN10, TS0IN2 PB3, AN11, TS0IN3 ATRST NRST, P27 Touch Sensor Timer SBI4B, P35, TS0OP SCL4B, SBT4B, P34, TS0RC AN8, PB0, TS0IN0 AN9, PB1, TS0IN1 AN10, PB2, TS0IN2 AN11, PB3, TS0IN3 AN12, P94, TS0IN4 AN13, P93, TS0IN5 AN14, P92, TS0IN6 SDA4B, SBO4B, AN15, P33, TS0IN7 TXD0B, SBO0B, P43, TS1OP RXD0B, SBI0B, P44, TS1RC SBT0B, P45, TS1IN0 P46, TS1IN1 P47, TSIN12 BUZZERA, TSIN13 VREF+ TM0IOA, LED0, PA0, AN0 TM1IOA, LED1, PA1, AN1 TM2IOA, LED2, PA2, AN2 TM3IOA, LED3, PA3, AN3 LED4, PA4, AN4 TM7IOA, LED5, PA5, AN5 TM8IOA, LED6, PA6, AN6 TM9IOA, LED7, PA7, AN7 TS0IN0, PB0, AN8 TS0IN1, PB1, AN9 TS0IN2, PB2, AN10 TS0IN3, PB3, AN11 TS0IN4, P94, AN12 TSIN05, P93, AN13 TSIN06, P92, AN14 SDA4B, SBO4B, TSIN07, P33, AN15 P90, XI P91, XO P92, AN14, TS0IN6 P93, AN13, TS0IN5 P94, AN14, TS0IN4 External Interrupt 16-bit Timer 8 A/D Converter P80, TM9OD0 P81, TM9OD1 P82, TM9OD2 P83, TM9OD3 P84, TM9OD4 P85, TM9OD5 P86, NBUZZERB P87, BUZZERB Port B PLL CPU AM13E Port A Internal High-speed Oscillator Circuit P70, KEY0, SBI4A P71, KEY1, SBO4A, SDA4A P72, KEY2, SBT4A, SCL4A P73, KEY3 P74, KEY4 P75, KEY5, SBO1B, TXD1B P76, KEY6, SBI1B, RXD1B P77, KEY7, SBT1B Port 9 Port 5 TM1IOB, P62 TM3IOB, P63 P64 TXD2, SBO2, P65 RXD2, SBI2, P66 SBT2, P67 Crystal/Ceramic Low-speed Oscillator Circuit Port 8 TXD1A, SBO1A, P50 RXD1A, SBI1A, P51 SBT1A, P52 P53 P54 P55 NBUZZERA, P56 BUZZERA, TS1IN3, P57 Crystal/Ceramic High-speed Oscillator Circuit Port 7 Port 4 TXD0B, SBO0B, TS1OP, P43 RXD0B, SBI0B, TS1RC, P44 SBT0B, TS1IN0, P45 TS1IN1, P46 TS1IN2, P47 Port 3 SDA4B, SBO4B, TSIN07, AN15, P33 SCL4B, SBT4B, TS0RC, P34 SBI4B, TS0OP, P35 Port 2 IRQ0, P20 IRQ1, P21 IRQ2, P22 IRQ3, P23 IRQ4, P24 OSC1, P25 OSC2, P26 NRST, P27 Port 0 OCD_DATA, P00 OCD_CLK, TM9IOB, P01 RXD0A, SBI0A, TM7IOB, P02 TXD0A, SBO0A, TM8IOB, P03 SBT0A, TM2IOB, TM0IOB, P04 P05 P06 P07 VDD18 VDD5 VSS MMOD DMOD Block Diagram OSC1, P25 OSC2, P26 1.4.1 Figure:1.4.1 Block Diagram * Varies depending on models. Refer to [Chapter 1.1.2 Product Summary] and [Chapter 1.3.3 Pin Functions]. Publication date: November 2014 25 MN101EFA8/A7/A3/A2/G0 Series 8-bit Single-chip Microcontroller PubNo. 216A8-015E 1.5 Electrical Characteristics This LSI manual describes standard specifications. When using this LSI, consult our sales offices for the product specifications. Structure CMOS integrated circuit Application General-purpose Function CMOS 8-bit single chip microcomputer Publication date: November 2014 26 MN101EFA8/A7/A3/A2/G0 Series 8-bit Single-chip Microcontroller PubNo. 216A8-015E 1.5.1 Absolute Maximum Ratings VSS = 0 V A. Absolute Maximum Ratings *2 *3 *4 Parameter Symbol Rating A1 Power supply voltage VDD5 -0.3 to +7.0 A2 Power supply voltage VDD18 -0.3 to +2.5 A3 Input pin voltage VI -0.3 to VDD5 +0.3 (upper limit: 7.0 V) A4 Output pin voltage VO -0.3 to VDD5 +0.3 (upper limit: 7.0 V) A5 I/O pin voltage VIO1 -0.3 to VDD5 +0.3 (upper limit: 7.0 V) LED output IOL1 (peak) 30 Other than LED output IOL2 (peak) 20 A8 All pins IOH (peak) -10 A9 LED output IOL1 (avg) 20 Other than LED output IOL2 (avg) 15 All pins IOH (avg) -5 PD 400 A16 Operating ambient temperature Topr -40 to +85 A17 Storage temperature TSTG -55 to +125 A6 A7 A10 Peak output current Average output current *1 A11 Unit V mA A12 A13 Power dissipation A14 mW A15 C *1 Applied to any 100 ms period. *2 Connect at least one bypass capacitor of 0.1 F + 1.0 F or larger between VDD5 pin and GND for the internal power voltage stabilization. *3 Connect appropriate capacitor about 0.1 F + 1.0 F between VDD18 pin and VSS pin, near the microcontroller according to the Figure:1.5.1 shown below for the internal power supply stabilization. VDD18 VSS 0.1 µF 1.0 µF LSI Figure:1.5.1 Capacitor Connection between VDD18 and VSS Pins *4 The absolute maximum ratings are the limit values beyond which the LSI may be damaged. Publication date: November 2014 27 MN101EFA8/A7/A3/A2/G0 Series 8-bit Single-chip Microcontroller PubNo. 216A8-015E 1.5.2 Operating Conditions B. Operating Conditions VSS = 0 V Ta = -40 C to +85 C Rating Parameter Symbol Conditions Unit MIN TYP MAX Power supply voltage *5 B1 Power supply voltage VDD1 B2 RAM retention power supply voltage VDD2 4.0 5.5 During STOP mode 2.2 5.5 tc1 VDD5 = 4.0 V to 5.5 V (When ROMHND of HANDSHAKE register is “1”.) 0.05 tc2 VDD5 = 4.0 V to 5.5 V (When ROMHND of HANDSHAKE register is “0”.) 0.10 tc3 VDD5 = 4.0 V to 5.5 V V Operating speed *6 B3 B4 Instruction execution time fs B5 s 61 *5 fs: Machine clock frequency *6 tc1 to 2 : when the machine clock is selected from external high-speed oscillation, internal high-speed oscillation, or both the oscillations multiplied by PLL. tc7: when the machine clock is selected from external low-speed oscillation. External Oscillator 1 Figure:1.5.2 B6 Frequency fhosc1 VDD5 is within the specified operating power supply voltage range. (Refer to the ratings of B1 to B2 for the operating supply voltage range) B7 Internal feedback resistor Rf10 VDD5 = 5.0 V 2.0 10 MHz 980 k 32.768 kHz 6.2 M External Oscillator 2 Figure:1.5.2 B8 Frequency B9 Internal feedback resistor Publication date: November 2014 fsosc1 VDD5 = 4.0 V to 5.5 V Rf20 VDD5 = 5.0 V 28 MN101EFA8/A7/A3/A2/G0 Series 8-bit Single-chip Microcontroller PubNo. 216A8-015E P25/OSC1 Rf10 fhosc1 P26/OSC2 LSI C12 C11 Feedback resistor is embedded. Figure:1.5.2 External Oscillator 1 P90/XI Rf20 fsosc1 P91/XO LSI C22 C21 Feedback resistor is embedded. Figure:1.5.3 External Oscillator 2 Connect external capacitors suited for the used oscillator. The reference value denotes external capacity value based on our matching result. When crystal oscillator or ceramic oscillator is used, the oscillation frequency is changed depending on the value of capacitor. For external capacity value, please consult the oscillator manufacturer and perform matching tests enough for determining appropriate values. .. .. Publication date: November 2014 29 MN101EFA8/A7/A3/A2/G0 Series 8-bit Single-chip Microcontroller PubNo. 216A8-015E VDD5 = 4.0 V to 5.5 V VSS = 0 V Ta = -40 C to +85 C Rating Parameter Symbol Conditions Unit MIN TYP MAX External clock input 1 OSC1 (OSC2 is unconnected) B10 Clock frequency B11 High-level pulse width *7 2 fhosc2 twh1 10.0 45 Figure:1.5.4 B12 Low-level pulse width *7 twl1 45 B13 Rising time twr1 0 5.0 B14 Falling time twf1 0 5.0 *7 MHz ns Figure:1.5.4 The clock duty ratio should be 45 % to 55 % External clock input 2 XI (XO is unconnected) B15 Clock frequency B16 High-level pulse width *7 fsosc2 twh2 B17 Low-level pulse width *7 twl2 B18 Rising time twr2 B19 Falling time Publication date: November 2014 twf2 32.768 kHz 4.5 s 4.5 s Figure:1.5.5 0 20 ns 0 20 ns Figure:1.5.5 30 MN101EFA8/A7/A3/A2/G0 Series 8-bit Single-chip Microcontroller PubNo. 216A8-015E 0.8VDD5 0.2VDD5 twr1 twf1 twh1 twl1 twc1 Figure:1.5.4 OSC1 Timing Chart 0.8VDD5 0.2VDD5 twr2 twf2 twh2 twl2 twc2 Figure:1.5.5 XI Timing Chart Publication date: November 2014 31 MN101EFA8/A7/A3/A2/G0 Series 8-bit Single-chip Microcontroller PubNo. 216A8-015E 1.5.3 DC Characteristics C. DC Characteristics VSS = 0 V Ta = -40 C to +85 C Rating Parameter Symbol Conditions Unit MIN TYP MAX Power supply current *8 C1 IDD1 VDD5=5 V fosc=10 MHz [Double-speed mode: fs=fosc] (PLL is not used) *9 5 14 C2 IDD2 VDD5=5 V fosc=10 MHz [Multiplied by 2, Divided by 2: fs=fosc] (PLL is used) *9 6 18 C3 IDD3 VDD5=5 V fosc=10 MHz [Multiplied by 2: fs=20 MHz] (PLL is used) *9 9 20 C4 IDD4 VDD5=5 V frc=16 MHz [Double-speed mode: fs=16 MHz] (PLL is not used) *9 6 15 Power supply current during operation mA C5 Power supply current during operation IDD5 VDD5=5 V fx=32.768 kHz [fs=fx/2] 200 400 A C6 Power supply current during STOP mode IDD6 VDD5=5 V 145 245 A *8 Measured without loading (pull-up and pull-down resistors are not connected.) To measure the power supply current during operation IDD1 to IDD4; 1. Set all I/O pins to input mode, 2. Set the CPU mode to “NORMAL mode”, 3. Fix pin MMOD to VSS level and input pins to VDD5 level 4. Input the rectangular wave of 10 MHz with amplitude of VDD5 and VSS, from pin OSC1. To measure the power supply current during SLOW mode IDD5; 1. Set all I/O pins to input mode 2. Set the CPU mode to "SLOW mode" 3. Fix the MMOD to VSS level and input pins to VDD5 level To measure the power supply current during STOP mode IDD6; 1. Set the CPU mode to “STOP mode”, 2. Fix pin MMOD to VSS level and input pin to VDD5 level 3. Open pin OSC1. *9 When ROMHND of HANDSHAKE register is set to “1” Publication date: November 2014 32 MN101EFA8/A7/A3/A2/G0 Series 8-bit Single-chip Microcontroller PubNo. 216A8-015E VDD5 = 4.0 V to 5.5 V VSS = 0 V Ta = -40 C to +85 C Rating Parameter Symbol Conditions Unit MIN TYP MAX Input pin 1 ATRST, MMOD C7 Input high voltage VIH1 0.8VDD5 VDD5 C8 Input low voltage VIL1 0 0.2VDD5 C9 Input leakage current ILK1 VIN = 0 V to VDD5 ±2 V A Input pin 2 P27/NRST C10 Input high voltage VIH2 0.8VDD5 VDD5 C11 Input low voltage VIL2 0 0.15VDD5 C12 Pull-up resistor RRH2 Publication date: November 2014 VDD5=5 V, VIN= VSS 10 50 100 V k 33 MN101EFA8/A7/A3/A2/G0 Series 8-bit Single-chip Microcontroller PubNo. 216A8-015E VDD5 = 4.0 V to 5.5 V VSS = 0 V Ta = -40 C to +85 C Rating Parameter Symbol Conditions Unit MIN TYP MAX Input pin 3 P00 to P07, P20 to P26, P43 to P47, P50 to P57, P62 to P67, P70 to P77, P80 to P87 (MN101EFA8/A3 Series) P00 to P06, P20 to P26, P62 to P67, P70 to P77, P80 to P87 (MN101EFA7/A2 Series) P00 to P04, P20 to P22, P25, P26, P62 to P67, P70 to P77, P80 to P87 (MN101EFG0 Series) C13 Input high voltage VIH3 0.8VDD5 VDD5 C14 Input low voltage VIL3 0 0.2VDD5 C15 Input leakage current ILK3 VIN=0 V to VDD5 C16 Pull-up resistor RRH3 VDD5=5.0 V, VIN=VSS Pull-up resistor ON 10 C17 Output high voltage VOH3 VDD5=5.0 V, IOH=-0.5 mA 4.5 C18 Output low voltage VOL3 VDD5=5.0 V, IOL=1.0 mA 50 V ±2 A 100 k V 0.5 Input pin 4 PA0 to PA7 C19 Input high voltage VIH4 0.8VDD5 VDD5 C20 Input low voltage VIL4 0 0.2VDD5 C21 Input leakage current ILK4 VIN=0 V to VDD5 ±2 A 100 k C22 Pull-up resistor RRH4 VDD5=5.0 V, VIN=VSS Pull-up resistor ON 10 C23 Output high voltage VOH4 VDD5=5.0 V, IOH=-0.5 mA 4.5 C24 Output low voltage 1 VOL41 VDD5=5.0 V, IOL=1.0 mA LED output OFF 0.5 C25 Output low voltage 2 VOL42 VDD5=5.0 V, IOL=15.0 mA LED output ON 1.0 50 V V Input pin 5 P33 to P35, P90 to P94, PB0 to PB3 (MN101EFA8/A3 Series) P50 to P57, P90, P91, P94 (MN101EFA7/A2 Series) P50 , P54 to P57, P90, P91, P94 (MN101EFG0 Series) C26 Input high voltage VIH5 0.8VDD5 VDD5 C27 Input low voltage VIL5 0 0.2VDD5 C28 Input leakage current ILK5 VIN=0 V to VDD5 ±2 RRH5 VDD5=5.0 V, VIN=VSS Pull-up resistor ON 10 C30 Pull-down resistor RRL5 VDD5=5.0 V, VIN=VDD5 Pull-down resistor ON 10 C31 Output high voltage VOH5 VDD5=5.0 V, IOH=-0.5 mA 4.5 C32 Output low voltage VOL5 VDD5=5.0 V, IOL=1.0 mA C29 Pull-up resistor Publication date: November 2014 50 V A 100 k 50 100 V 0.5 34 MN101EFA8/A7/A3/A2/G0 Series 8-bit Single-chip Microcontroller PubNo. 216A8-015E VDD5 = 4.0 V to 5.5 V VSS = 0 V Ta = -40 C to +85 C Rating Parameter Symbol Conditions Unit MIN TYP MAX Input pin 6 DMOD C33 Input high voltage VIH6 0.8VDD5 VDD5 C34 Input low voltage VIL6 0 0.2VDD5 C35 Pull-up resistor RRH6 Publication date: November 2014 VDD5=5.0 V, VIN=VSS Pull-up resistor ON 10 50 100 V k 35 MN101EFA8/A7/A3/A2/G0 Series 8-bit Single-chip Microcontroller PubNo. 216A8-015E 1.5.4 A/D Converter Characteristics D. A/D Converter Characteristics *11 VDD5 = 5.0 V VSS = 0 V Ta = -40 C to +85 C Rating Parameter Symbol Conditions Unit MIN TYP MAX D1 Resolution 10 D2 Non-linearity error 1 D3 Differential non-linearity error 1 D4 Zero transition voltage D5 Full-scale transition voltage VDD5=5.0 V, VSS=0 V VREF+=5.0 V TAD=800 ns D6 A/D conversion time TAD=800 ns 12.93 D7 Sampling time TAD=800 ns 1.6 D8 Reference voltage Note) 4.0 VDD5 D9 Analog input voltage VSS VREF+ D10 Analog input leakage current Channel OFF VADIN=VSS to VDD5 ±2 D11 Reference voltage pin input leakage current Ladder resistance OFF VSS VREF+ VDD5 ±5 D12 Ladder resistance *11 TAD is A/D conversion clock cycle. The specification values of D2 to D5 are guaranteed on the condition of VDD5=VREF+=5 V, VSS=0 V. VDD5=5.0 V, VSS=0 V VREF+=5.0 V TAD=800 ns VREF+ RLADD VDD5=5.0 V Bits ±3 ±3 10 4970 LSB 30 mV 4990 s V A 15 40 80 k Even if A/D function is not used, the voltage of VREF+ pin must be set between VDD5 and 4.0 V. .. .. Publication date: November 2014 36 MN101EFA8/A7/A3/A2/G0 Series 8-bit Single-chip Microcontroller PubNo. 216A8-015E 1.5.5 Auto Reset Characteristics E. Auto Reset Characteristics VDD5 = VRST to 5.5 V VSS = 0 V Ta = -40 C to +85 C Rating Parameter Symbol Conditions Unit MIN TYP MAX Power supply voltage E1 Operating supply voltage VDD7 Auto reset is used VRST 5.5 V Power supply voltage E2 Power detection level VRST1 At rising 4.10 4.30 4.50 E3 Power detection level VRST2 At falling 4.00 4.20 4.40 E4 Supply voltage change rate t/V 1.5.6 2 V ms/V Internal High-speed Oscillation Circuit F. Internal High-speed Oscillation Circuit VDD5 = 4.0 V to 5.5 V VSS = 0 V Rating Parameter Symbol Conditions Unit MIN F1 Internal high-speed oscillation circuit frequency F2 Temperature dependence F3 of oscillation frequency Publication date: November 2014 frc Ta = -40 C to +85 C frc3 Ta = 25 C frc4 Ta = -40 C to +85 C TYP MAX 16 -5.0 MHz 5.0 % 37 MN101EFA8/A7/A3/A2/G0 Series 8-bit Single-chip Microcontroller PubNo. 216A8-015E 1.5.7 Flash EEPROM Program Conditions G. Flash EEPROM Program Conditions VDD5 = 4.0 V to 5.5 V VSS = 0 V Ta = -40 C to +85 C Rating Parameter Symbol Conditions Unit MIN TYP MAX G1 Supply voltage VDDEW 4.0 Programming/Erasing G2 times of 32KB, 20KB Sector *2 EMAX1 1000 Times 10000 Times 5.5 V G3 Programming/Erasing times of 4KB Sector *2 EMAX2 G4 Data retention period of 32KB, 20KB Sector *1 THOLD1 Ta= 85C, P/E times 1000 20 Years Data retention period of 4KB Sector *1 THOLD2 Ta= 85C, P/E times 1000 *2 20 Years G5 THOLD3 Ta= 65C, P/E times 10000 *2 20 Years *1 Contain the period when power supply voltage is not supplied. *2 Programming/Erasing times(P/E Times) is counted by the number of time a sector is erased. It is controlled on sector basis. For example, if writing 1 byte of data in any sector for hundred of times and then erasing the sector, a single rewriting is counted. Also, the number of times of rewriting in another sector, in which erasing is not performed, is not counted. Overwriting data is disabled. To rewrite data, write the data after erasing sectors. Publication date: November 2014 38 MN101EFA8/A7/A3/A2/G0 Series 8-bit Single-chip Microcontroller PubNo. 216A8-015E 1.6 Package Dimension Package code: TQFP080-P-1212FUnit: mm Figure:1.6.1 80-pin TQFP Package Dimension This package dimension is subject to change. Before using this product, please obtain product specifications from our sales offices. .. Publication date: November 2014 39 MN101EFA8/A7/A3/A2/G0 Series 8-bit Single-chip Microcontroller PubNo. 216A8-015E Package code: LQFP080-P-1414EUnit: mm Figure:1.6.2 80-pin LQFP Package Dimension This package dimension is subject to change. Before using this product, please obtain product specifications from our sales offices. .. Publication date: November 2014 40 MN101EFA8/A7/A3/A2/G0 Series 8-bit Single-chip Microcontroller PubNo. 216A8-015E Package code: TQFP064-P-1010DUnit: mm Figure:1.6.3 64-pin TQFP Package Dimension This package dimension is subject to change. Before using this product, please obtain product specifications from our sales offices. .. Publication date: November 2014 41 MN101EFA8/A7/A3/A2/G0 Series 8-bit Single-chip Microcontroller PubNo. 216A8-015E Package code: LQFP064-P-1414Unit: mm Figure:1.6.4 64-pin LQFP Package Dimension This package dimension is subject to change. Before using this product, please obtain product specifications from our sales offices. .. Publication date: November 2014 42 MN101EFA8/A7/A3/A2/G0 Series 8-bit Single-chip Microcontroller PubNo. 216A8-015E Package code: TQFP056-P-1414Unit: mm Figure:1.6.5 56-pin TQFP Package Dimension This package dimension is subject to change. Before using this product, please obtain product specifications from our sales offices. .. Publication date: November 2014 43 Request for your special attention and precautions in using the technical information and semiconductors described in this book (1) If any of the products or technical information described in this book is to be exported or provided to non-residents, the laws and regulations of the exporting country, especially, those with regard to security export control, must be observed. (2) The technical information described in this book is intended only to show the main characteristics and application circuit examples of the products. No license is granted in and to any intellectual property right or other right owned by Panasonic Corporation or any other company. Therefore, no responsibility is assumed by our company as to the infringement upon any such right owned by any other company which may arise as a result of the use of technical information described in this book. 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