ON MC74VHCT04A Hex inverter Datasheet

ON Semiconductort
Hex Inverter
MC74VHCT04A
The MC74VHCT04A is an advanced high speed CMOS inverter
fabricated with silicon gate CMOS technology. It achieves high speed
operation similar to equivalent Bipolar Schottky TTL while
maintaining CMOS low power dissipation.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7V, allowing the interface of 5V systems
to 3V systems.
The VHCT inputs are compatible with TTL levels. This device can
be used as a level converter for interfacing 3.3V to 5.0V, because it has
full 5V CMOS level output swings.
The VHCT04A input structures provide protection when voltages
between 0V and 5.5V are applied, regardless of the supply voltage.
The output structures also provide protection when VCC = 0V. These
input and output structures help prevent device destruction caused by
supply voltage − input/output voltage mismatch, battery backup, hot
insertion, etc.
• High Speed: tPD = 4.7ns (Typ) at VCC = 5V
• Low Power Dissipation: ICC = 2μA (Max) at TA = 25°C
• TTL−Compatible Inputs: VIL = 0.8V; VIH = 2.0V
• Power Down Protection Provided on Inputs and Outputs
• Balanced Propagation Delays
• Designed for 4.5V to 5.5V Operating Range
• Low Noise: VOLP = 1.0V (Max)
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300mA
• ESD Performance: HBM > 2000V; Machine Model > 200V
• Chip Complexity: 48 FETs or 12 Equivalent Gates
w
D SUFFIX
14−LEAD SOIC PACKAGE
CASE 751A−03
DT SUFFIX
14−LEAD TSSOP PACKAGE
CASE 948G−01
M SUFFIX
14−LEAD SOIC EIAJ PACKAGE
CASE 965−01
ORDERING INFORMATION
MC74VHCTXXAD
MC74VHCTXXADT
MC74VHCTXXAM
FUNCTION TABLE
These devices are available in Pb−free package(s). Specifications herein
apply to both standard and Pb−free devices. Please see our website at
www.onsemi.com for specific Pb−free orderable part numbers, or
contact your local ON Semiconductor sales office or representative.
A1
A2
A3
A4
A5
A6
1
2
3
4
5
6
9
8
11
10
13
12
March, 2006 − Rev. 3
Inputs
Outputs
A
Y
L
H
H
L
Y1
Y2
VCC
A6
Y6
A5
Y5
A4
Y4
14
13
12
11
10
9
8
Y3
Y=A
Y4
Y5
Y6
Figure 1. Logic Diagram
© Semiconductor Components Industries, LLC, 2006
SOIC
TSSOP
SOIC EIAJ
1
2
3
4
5
6
7
A1
Y1
A2
Y2
A3
Y3
GND
Figure 2. Pinout: 14−Lead Packages (Top View)
1
Publication Order Number:
MC74VHCT04A/D
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MAXIMUM RATINGS*
Symbol
Value
Unit
VCC
DC Supply Voltage
Parameter
– 0.5 to + 7.0
V
Vin
DC Input Voltage
– 0.5 to + 7.0
V
Vout
DC Output Voltage
– 0.5 to + 7.0
– 0.5 to VCC + 0.5
V
VCC = 0
High or Low State
IIK
Input Diode Current
− 20
mA
IOK
Output Diode Current (VOUT < GND; VOUT > VCC)
± 20
mA
Iout
DC Output Current, per Pin
± 25
mA
ICC
DC Supply Current, VCC and GND Pins
± 50
mA
PD
Power Dissipation in Still Air,
500
450
mW
Tstg
Storage Temperature
– 65 to + 150
_C
SOIC Packages†
TSSOP Package†
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND v (Vin or Vout) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V CC ).
Unused outputs must be left open.
* Absolute maximum continuous ratings are those values beyond which damage to the device
may occur. Exposure to these conditions or conditions beyond those indicated may
adversely affect device reliability. Functional operation under absolute−maximum−rated
conditions is not implied.
†Derating — SOIC Packages: – 7 mW/_C from 65_ to 125_C
TSSOP Package: − 6.1 mW/_C from 65_ to 125_C
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RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
VCC
DC Supply Voltage
Vin
DC Input Voltage
Vout
DC Output Voltage
VCC = 0
High or Low State
TA
Operating Temperature
tr, tf
Input Rise and Fall Time
VCC =5.0V ±0.5V
Min
Max
Unit
4.5
5.5
V
0
5.5
V
0
0
5.5
VCC
V
− 40
+ 85
_C
0
20
ns/V
DC ELECTRICAL CHARACTERISTICS
TA = 25°C
Min
Symbol
Parameter
VIH
Minimum High−Level
Input Voltage
4.5 to
5.5
VIL
Maximum Low−Level
Input Voltage
4.5 to
5.5
VOH
Minimum High−Level
Output Voltage
Vin = VIH or VIL
IOH = − 50μA
4.5
4.4
IOH = − 8mA
4.5
3.94
Maximum Low−Level
Output Voltage
Vin = VIH or VIL
IOL = 50μA
4.5
IOL = 8mA
VOL
Test Conditions
VCC
V
Typ
TA = − 40 to 85°C
Max
2.0
Min
Max
2.0
0.8
4.5
Unit
V
0.8
4.4
V
V
3.80
0.0
0.1
0.1
4.5
0.36
0.44
V
Iin
Maximum Input
Leakage Current
Vin = 5.5 V or GND
0 to 5.5
± 0.1
± 1.0
μA
ICC
Maximum Quiescent
Supply Current
Vin = VCC or GND
5.5
2.0
20.0
μA
ICCT
Quiescent Supply
Current
Per Input: VIN = 3.4V
Other Input: VCC or GND
5.5
1.35
1.50
mA
IOPD
Output Leakage
Current
VOUT = 5.5V
0
0.5
5.0
μA
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2
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AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns)
TA = 25°C
Symbol
Parameter
tPLH,
tPHL
Maximum Propagation
Delay, A to Y
Cin
Test Conditions
VCC = 5.0 ± 0.5V
CL = 15pF
CL = 50pF
Maximum Input Capacitance
Min
TA = − 40 to 85°C
Typ
Max
Min
Max
Unit
4.7
5.5
6.7
7.7
1.0
1.0
7.5
8.5
ns
4
10
10
pF
Typical @ 25°C, VCC = 5.0V
11
CPD
Power Dissipation Capacitance (Note 1)
pF
1. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC/6 (per buffer). CPD is used to determine the
no−load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.
NOISE CHARACTERISTICS (Input tr = tf = 3.0ns, CL = 50pF, VCC = 5.0V)
TA = 25°C
Symbol
Typ
Characteristic
Max
Unit
VOLP
Quiet Output Maximum Dynamic VOL
0.8
1.0
V
VOLV
Quiet Output Minimum Dynamic VOL
−0.8
−1.0
V
VIHD
Minimum High Level Dynamic Input Voltage
2.0
V
VILD
Maximum Low Level Dynamic Input Voltage
0.8
V
TEST POINT
A
3V
OUTPUT
1.5V
DEVICE
UNDER
TEST
GND
tPLH
Y
tPHL
1.5V
CL*
VOH
VOL
*Includes all probe and jig capacitance
Figure 3. Switching Waveforms
Figure 4. Test Circuit
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3
OUTLINE DIMENSIONS
D SUFFIX
SOIC−14
CASE 751A−03
ISSUE F
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
−A−
14
8
−B−
1
0.25 (0.010)
G
0.25 (0.010)
M
T B
B
M
F
J
M
K
D 14 PL
M
R X 45 _
C
−T−
SEATING
PLANE
P 7 PL
7
S
A
S
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4
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
8.55
8.75
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.337
0.344
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0_
7_
0.228
0.244
0.010
0.019
OUTLINE DIMENSIONS
DT SUFFIX
TSSOP
CASE 948G−01
ISSUE O
14X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
V
S
S
S
N
2X
14
L/2
0.25 (0.010)
8
M
B
−U−
L
PIN 1
IDENT.
N
F
7
1
0.15 (0.006) T U
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE −W−.
S
DETAIL E
K
A
−V−
K1
J J1
ÇÇÇ
ÉÉ
ÇÇÇ
ÉÉ
SECTION N−N
−W−
C
0.10 (0.004)
−T− SEATING
PLANE
D
G
H
DETAIL E
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5
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50
−−−
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.50
0.60
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.193
0.200
0.169
0.177
−−−
0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.020
0.024
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0_
8_
OUTLINE DIMENSIONS
M SUFFIX
SO−14
CASE 965−01
ISSUE O
14
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
LE
8
Q1
E HE
L
7
1
M_
DETAIL P
Z
D
VIEW P
A
e
A1
b
0.13 (0.005)
c
M
0.10 (0.004)
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6
DIM
A
A1
b
c
D
E
e
HE
0.50
LE
M
Q1
Z
MILLIMETERS
MIN
MAX
−−−
2.05
0.05
0.20
0.35
0.50
0.18
0.27
9.90
10.50
5.10
5.45
1.27 BSC
7.40
8.20
0.50
0.85
1.10
1.50
10 _
0_
0.70
0.90
−−−
1.42
INCHES
MIN
MAX
−−−
0.081
0.002
0.008
0.014
0.020
0.007
0.011
0.390
0.413
0.201
0.215
0.050 BSC
0.291
0.323
0.020
0.033
0.043
0.059
10 _
0_
0.028
0.035
−−−
0.056
Notes
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7
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are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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MC74VHCT04A/D
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