Rohm BU9728AKV For 128-140 segment type lcd lcd segment driver Datasheet

TECHNICAL NOTE
LCD Segment Driver series
For 128～140 Segment type LCD
LCD Segment Driver
BU9728AKV, BU9795AKV/FV/GUW
● Outline
This is LCD segment driver for 126 to 140 segment type display. There is a lineup which is suitable for
multi function display and is integrated display RAM and power supply circuit for LCD driving with 4
common output type: BU9728AKV and BU9795AKV/FV/GUW.
○
○
128Segment (SEG32×COM4) Driver BU9728AKV
140Segment (SEG35×COM4) Driver BU9795AKV/FV/GUW
BU9728AKV
・・・・・・・P.1
・・・・・・・P.10
128Segment (SEG32×COM4) Driver
● Feature (BU9728AKV)
______________
__________
1) 4wire serial interface (SCK, SD, C / D, CS)
2) Integrated RAM for display data (DDRAM) : 32 × 4bit (Max 128 Segment)
3) LCD driving port: 4 Common output, 32 Segment output
4) Display duty: 1/4 duty
5) Integrated Oscillator circuit (external resister type)
6) Integrated Power supply circuit for LCD driving (1/3 bias)
7) Low voltage / low power consumption design: +2.5～5.5V
● Uses (BU9728AKV)
DVC, Car audio, Telephone
● Absolute Maximum Ratings
Parameter
(Ta=25degree, VSS=0V)
Symbol
Limits
(BU9728AKV)
Unit
Remarks
Power Supply Voltage1
VDD
-0.3 ～
+7.0
V
Power supply
Power Supply Voltage2
VLCD
-0.3
+7.0
V
LCD drive voltage
Allowable loss
Pd
Operational temperature range
Topr
Storage temperature range
Input voltage range
Output voltage range
～
400
mW
-40 ～
+85
degree
Tstg
-55
+125
degree
VIN
-0.3 to VDD+0.3
V
VOUT
-0.3 to VDD+0.3
V
～
When use more than Ta=25C, subtract
4mW per degree.
*This product is not designed against radioactive ray.
● Recommend operating conditions (Ta=25degree, VSS=0V) (BU9728AKV)
Parameter
Symbol
MIN
TYP
MAX
Unit
Remarks
Power Supply Voltage1
VDD
2.5
5.5
V
Power Supply Voltage2
VLCD
0
VDD
V
VDD≧V1≧V2≧V3≧VSS
Oscillator frequency
fOSC
36
KHz
Rf=470kΩ
This document is not delivery specifications.
Jul. 2008
● Electrical Characteristics (BU9728AKV)
DC Characteristics (VDD=2.5～5.5V, VSS=0V, Ta=25degree, unless otherwise specified)
Limit
Symbo
Uni
Condition
Parameter
Min.
Typ.
Max.
t
l
“H” level input voltage
VIH1
0.8×VDD
-
VDD
V
VO=0.9×VDD
or 0.1×VDD
Terminal
SC1, SD, SCK,
______________
__________
_______________________
C / D, C S, R E S E T
“L” level input voltage
VIL1
0
-
0.2×VDD
V
VO=0.1×VDD
or 0.9×VDD
LCD Driver on resistance
RON
-
-
30
kΩ
|△VON|=0.1V
SEG0～31, COM0～3
“L” level Input current1
IIL1
-
-
100
μA
VIN=0
_______________________
“L” level Input current2
IIL2
-
-
2
μA
VIN=0
“H” level Input current
IIH
-2
-
-
μA
VIN=VDD
Input capacitance
CI
-
5
-
pF
0.05
1
μA *2 Display OFF
40
80
μA *3 Display ON
Power consumption
100
250
μA *4 MPU Access
*1: LCD Driver on resistance is not included internal power supply impedance
*2: V3=0V, All input terminal are connected to VDD or VSS.
*3: V3=0V, Rf=470kΩ, except of OSC1 terminals are connected to VDD or VSS.
*4: V3=0V, Rf=470kΩ, fSCK=200kHz
IDD
RESET
OSC1, SD, SCK,
______________
OSC1, SD, SCK,
______________
__________
_______________________
C / D, C S, R E S E T
______________
__________
SD, SCK, C / D , C S
VDD
AC Characteristics (VDD=2.5～5.5V, VSS=0V, Ta=25degree, unless otherwise specified)
Limit
Symbo
Unit
Condition
Parameter
l
Min. Typ. Max.
SCK rise time
tTLH
100
ns
SCK fall time
tTHL
100
ns
SCK cycle time
tCYC
800
ns
Wait time for command
tWAIT
800
ns
SCK pulse width ”H”
tWH1
300
ns
SCK pulse width ”L”
tWL1
300
ns
SD setup time
tSU1
100
ns
SD hold time
tH1
100
ns
tWH2
300
ns
CS pulse width ”H”
CS pulse width ”L”
tWL2 6400
ns
CS setup time
tSU2
100
ns
CS hold time
tH2
100
ns
C/D setup time
tSU3
100
ns
C/D hold time
tH3
100
ns
Based on SCK
8th clock rising
__________
C/D – CS time *5
tCCH
100
ns
Based on C S rising
C/D – SCK time *5
tSCH
100
ns
Based o SCK 8th clock falling
*5: Should satisfy either one condition
2/23
__________
C / D, C S
tWH2
tWL2
CS
tTH2
tSU2
tCYC
tWH1
SCK
tCYC
tWAIT
tWL1
tTLH
tSU1
SCK
tTHL
tH1
SD
SD
D7
D6
D0
D7
tCCH
tSCH
tSU3
tTH3
C/D
Fig. BU9728AKV-1 Interface timing
● Reference data
Fig. BU9728AKV-2 Command cycle
(BU9728AKV)
IDD －VDD
FRAME FREQ. － Rf
1k
(VLCD=VC=VDD,Rf=470kΩ)
80
70
500
400
Operating Current ：I DD (uA)
Frame Frequency ： FR(Hz)
700
300
200
VDD=5V
100
70
VDD=3V
50
40
30
20
10
100k
60
50
40
Accessing
30
Display
20
10
200k
300k
400k 500k
700k
0
1.0
1M
2.0
3.0
4.0
5.0
6.0
7.0
Supply Voltage：VDD(V)
Oscillation Registance：Rf( Ω)
Fig. BU9728AKV-3 Frame frequency vs. Resister value
Fig. BU9728AKV-4 Power consumption vs. Power supply
3/23
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
35
34
33
32
31
30
29
28
27
26
25
40
SEG24
41
SEG25
42
SEG26
43
SEG27
44
SEG28
45
SEG29
46
SEG30
47
SEG31
2
3
4
5
6
7
8
9
10
11
12
COM0
COM3
1
C/D
48
CS
COM2
SEG23
SD
COM1
39
SCK
OSC1
Command
Decoder
Common
Counter
COM0
SEG22
OSC2
Timing
Generator
LCD
Common
Driver
4bits
38
VDD
Command/Data
Register
SEG21
VSS
SEG31
37
V3
CS
SEG20
V2
Display Data RAM
(DD RAM)
SEG1
V1
Serial
Interface
LCD
Segment
Driver
32bits
OSC2
SEG0
Address
Counter
OSC1
C/D
36
VSS
SD
SCK
SEG15
RESET
VDD
V1
V2
V3
SEG16
LCD Driver
Bias Circuit
(BU9728AKV)
SEG17
●Pin Arrangement
SEG18
(BU9728AKV)
SEG19
● Block Diagram
24
SEG7
23
SEG6
22
SEG5
21
SEG4
20
SEG3
19
SEG2
18
SEG1
17
SEG0
16
RESET
15
COM3
14
COM2
13
COM1
Fig. BU9728AKV-6 Pin
Fig. BU9728AKV-5 Block diagram
arrangement
● Terminal description (BU9728AKV)
Terminal
No.
Type
OSC1
1
I
OSC2
2
O
V1～V3
3～5
VSS
6
VSS terminal
VDD
7
VDD terminal
SCK
8
I
Serial clock input
SD
9
I
Serial data input
CS
10
I
Chip select input “L”: active
______________
C/D
11
I
Command data judgment input
“L”: display data, “H”: command
COM0～3
12～15
O
LCD COMMON output
RESET
16
I
Reset input terminal.
It will be initialized with "L" level input.
Reset address counter, Set display off status.
17～48
O
LCD SEGMENT output
_________
SEG0～
31
Function
Int clock use mode, connect resister between OSC1 and OSC2.
Ext clock use mode, input clock from OSC1, OSC2 keep OPEN.
Power supply for LCD driving.
Keep VDD≧V1≧V2≧V3≧VSS condition.
4/23
● Block Description (BU9728AKV)
◯ ADDRESS COUNTER
An address counter shows the address of DDRAM. Address data are transferred to the address
counter automatically when an address set is written in the command/data register.
After data are written in DDRAM, +1 or +2 is done automatically with an address counter. The
choice of +1 or +2 is done automatically by the next condition.
DDRAM 8bit writing (in the 8 clock of SCK, C/D= "L")
→ +2
DDRAM 4bit rewriting (in the 8 clock of SCK, C/D= "H") → +1
And, when it is counted to 1FH, an address becomes 00H with an address counter by the next count
up.
◯ DISPLAY DATA RAM (DDRAM)
A display data RAM (DDRAM) is used to store display data. That capacity is 32 address × 4 bits.
DDRAM and the relations of the display position are as the following.
BIT
1F
1E
・・・・・・・
1D
07
06
05
04
03
02
01
00
DDRAM address
D0
COM0
D1
COM1
D2
COM2
D3
COM3
◯ TIMING GENERATER
It will be started to oscillate by connecting Rf between OSC1, OSC2, and generated display timing
signal. Also it will be able to do by external clock input.
OSC1
OSC1
EXTERNAL CLOCK INPUT
OSC2
OPEN
Rf
OSC2
(It is possible that Oscillating Frequency
is changed with Rf. )
Fig. BU9728AKV-7 Rf Oscillator Circuit
Fig. BU9728AKV-8
External Clock Input
◯ LCD DRIVE POWER SUPPLY
LCD drive power supply occurs by BU9728AKV. LCD voltage is given by VDD- V3, and it causes
V1=2・VLCD/3, V2=VLCD/3. When input LCD power supply by using external breeder register
etc.
Please keep below condition.
VDD≧V1≧V2≧V3≧VSS
VDD
VDD
V1
V1
V2
V2
V3
V3
VSS
VSS
Fig. BU9728AKV-9 Internal Power supply use
5/23
Fig. BU9728AKV-10 External Power supply use
● DETAIL OF COMMANDS (BU9728AKV)
There is the following thing in the command (The 8×n clock of SCK is C/D= "H".) of BU9728AKV.
◯ ADDRESS SET
MSB
LSB
0
0
0
A
A
A
A
A
Address data shown as AAAAA by the binary system is set on the address counter.
Address does +2 every time indication data input (for 8bit) completes input.
◯ DISPLAY ON
MSB
LSB
0
0
1
*
*
*
*
*
*:Don't Care
There are no relations with the contents of the display data RAM (DDRAM).
And all display is turned on. In this case, the contents of DDRAM don't change.
◯ DISPLAY OFF
MSB
LSB
0
1
0
*
*
*
*
*
*:Don't Care
There are no relations with the contents of the display data RAM (DDRAM).
In this case, the contents of DDRAM don't change.
◯ DISPLAY START
MSB
0
LSB
1
1
*
*
*
*
*
*:Don't Care
It will be started to oscillate and to display in accordance with the contents of DDRAM.
◯ REWRITING OF THE DISPLAY DATA RAM (DDRAM)
MSB
1
LSB
0
0
*
D
D
D
D
*:Don't Care
The binary four bits data DDDD are written in DDRAM.
A writing address is address ordered by the address set command.
Then, after this command is carried out, an address does + 1 automatically.
◯ RESET
MSB
1
LSB
1
0
*
*
*
*
*
*:Don't Care
Please execute this command first after Power on. It will be initialized as follow conditions;
・ Display OFF
・
Address counter reset
6/23
● Recommendation circuit example
(BU9728AKV)
It can use as a resistance for the
contrast adjustment when variable
resistance is given to the V3-VSS
space. The resistance of the outside
and resistance with built-in
BU9728AKV become the right
figures in this case.
The value of RC is to decide the
value which met a system referring
to the circuit of the right figure.
VDD
1MΩ
V1
1MΩ
V2
1MΩ
The value (1MΩ) of the
built-in resistance value
inside the figure is
reference value. Value
varies according to
terms of manufacture
and so on.
V3
5.0V
RC
VSS
GND
Fig. BU9728AKV-11 When a contrast adjustment mechanism is used.
● INPUT OUTPUT CIRCUIT (BU9728AKV)
Name
SD
SCK
I/O
Circuit
I
______________
C/D
VDD
__________
Name
I/O
SEG0
～
SEG31
O
Circuit
VLCD
CS
COM0
～
COM3
IN
OUT
GND
VLCD
GND
GND
Name
I/O
Circuit
OSC1
OSC2
VDD
OSC1
VDD
GND
OSC2
GND
Name
_______________________
RESET
I/O
Circuit
I
VDD
VDD
IN
GND
Fig. BU9728AKV-14 INPUT OUTPUT circuit
7/23
● Cautions on use
(1) Absolute Maximum Ratings
An excess in the absolute maximum ratings, such as supply voltage, temperature range of operating conditions, etc., can break down devices,
thus making impossible to identify breaking mode such as a short circuit or an open circuit. If any special mode exceeding the absolute maximum ratings
is assumed, consideration should be given to take physical safety measures including the use of fuses, etc.
(2) Operating conditions
These conditions represent a range within which characteristics can be provided approximately as expected. The electrical characteristics are guaranteed
under the conditions of each parameter.
(3) Reverse connection of power supply connector
The reverse connection of power supply connector can break down ICs. Take protective measures against the breakdown due to the reverse connection,
such as mounting an external diode between the power supply and the IC’s power supply terminal.
(4) Power supply line
Design PCB pattern to provide low impedance for the wiring between the power supply and the GND lines. In this regard, or the digital block power
supply and the analog block power supply, even though these power supplies has the same level of potential, separate the power supply pattern for
the digital block from that for the analog block, thus suppressing the diffraction of digital noises to the analog block power supply resulting from
impedance common to the wiring patterns. For the GND line, give consideration to design the patterns in a similar manner.
Furthermore, for all power supply terminals to ICs, mount a capacitor between the power supply and the GND terminal. At the same time, in order to use
an electrolytic capacitor, thoroughly check to be sure the characteristics of the capacitor to be used present no problem including the occurrence of
capacity dropout at a low temperature, thus determining the constant.
(5) GND voltage
Make setting of the potential of the GND terminal so that it will be maintained at the minimum in any operating state. Furthermore, check to be sure
no terminals are at a potential lower than the GND voltage including an actual electric transient.
(6) Short circuit between terminals and erroneous mounting
In order to mount ICs on a set PCB, pay thorough attention to the direction and offset of the ICs. Erroneous mounting can break down the ICs. Furthermore,
if a short circuit occurs due to foreign matters entering between terminals or between the terminal and the power supply or the GND terminal,
the ICs can break down.
(7) Operation in strong electromagnetic field
Be noted that using ICs in the strong electromagnetic field can malfunction them.
(8) Inspection with set PCB
On the inspection with the set PCB, if a capacitor is connected to a low-impedance IC terminal, the IC can suffer stress. Therefore, be sure to discharge
from the set PCB by each process. Furthermore, in order to mount or dismount the set PCB to/from the jig for the inspection process, be sure to turn OFF
the power supply and then mount the set PCB to the jig. After the completion of the inspection, be sure to turn OFF the power supply and then dismount
it from the jig. In addition, for protection against static electricity, establish a ground for the assembly process and pay thorough attention to the
transportation and the storage of the set PCB.
(9) Input terminals
In terms of the construction of IC, parasitic elements are inevitably formed in relation to potential. The operation of the parasitic element can
cause interference with circuit operation, thus resulting in a malfunction and then breakdown of the input terminal. Therefore, pay thorough attention
not to handle the input terminals, such as to apply to the input terminals a voltage lower than the GND respectively, so that any parasitic element will
operate. Furthermore, do not apply a voltage to the input terminals when no power supply voltage is applied to the IC. In addition, even if the power
supply voltage is applied, apply to the input terminals a voltage lower than the power supply voltage or within the guaranteed value of
electrical characteristics.
(10) Ground wiring pattern
If small-signal GND and large-current GND are provided, It will be recommended to separate the large-current GND pattern from the small-signal
GND pattern and establish a single ground at the reference point of the set PCB so that resistance to the wiring pattern and voltage fluctuations due to
a large current will cause no fluctuations in voltages of the small-signal GND. Pay attention not to cause fluctuations in the GND wiring pattern of
external parts as well.
(11) External capacitor
In order to use a ceramic capacitor as the external capacitor, determine the constant with consideration given to a degradation in the nominal capacitance
due to DC bias and changes in the capacitance due to temperature, etc.
(12) No Connecting input terminals
In terms of extremely high impedance of CMOS gate, to open the input terminals causes unstable state. And unstable state brings the inside
gate voltage of p-channel or n-channel transistor into active. As a result, battery current may increase. And unstable state can also causes
unexpected operation of IC. So unless otherwise specified, input terminals not being used should be connected to the power supply or GND line.
(13) Rush current
When power is first supplied to the CMOS IC, it is possible that the internal logic may be unstable and rush current may flow
instantaneously. Therefore, give special condition to power coupling capacitance, power wiring, width of GND wiring, and routing of connections.
8/23
● Order form name selection
B
U
9
7
ROHM form name
2
8
Part No.
A
K
V
－
E
2
Packaging and forming specification
Package type
KV=VQFP
E2 =Reel-shaped emboss taping
VQFP48C
< Packing information >
<Dimension>
9.0±0.2
7.0±0.1
24
48
13
1
12
0.1±0.05
1.6Max.
1.4±0.05
0.75
1.0±0.2
37
0.5±0.15
25
0.75
7.0±0.1
9.0±0.2
36
Tape
Embossed carrier tape
Quantity
1500pcs
Direction
of feed
E2
(The direction is the 1pin of product is at the upper left when you hold
reel on the left hand and you pull out the tape on the right hand)
+0.05
0.145−0.03
4° +6°
−4°
0.08 S
0.5±0.1
+0.05
0.22−0.04
0.08 M
1Pin
Reel
(Unit:mm)
9/23
Direction of feed
*When you order , please order in times the amount of package quantity.
BU9795AKV/FV/GUW
MAX140Segment (SEG35×COM4) Driver
● Feature (BU9795AKV/AFV/AGUW)
1) 3wire serial interface (CSB, SD, SCL)
2) Integrated RAM for display data (DDRAM) : 35 × 4bit (Max 140 Segment)
3) LCD driving port: 4 Common output,
Segment: 35output (BU9795AKV), 31output (BU9795AGUW), 27output (BU9795AFV)
4) Display duty: 1/4 duty
5) Integrated Buffer AMP for LCD driving power supply
6) 1/2bias, 1/3bias selectable
7) No external components
8) Low power/ Ultra low power consumption design: +2.5～5.5V
● Uses (BU9795AKV/AFV/AGUW)
Telephone, FAX, Portable equipment (POS, ECR, PDA etc.),
DSC, DVC, Car audio, Home electrical appliance, Meter equipment etc.
● Line-up
Parameter
Segment output
Common output
Package
BU9795AKV
35
4
VQFP48C
BU9795AFV
27
4
SSOP-B40
● Absolute Maximum Ratings (Ta=25degree, VSS=0V)
Symbol
Parameter
Limits
-0.5 ～ +7.0
Power supply voltage1
VDD
-0.5 ～ VDD
Power supply voltage2
VLCD
0.6
Allowable loss
Pd
0.7
0.27
Input voltage range
VIN
Operational
temperature range
Topr
-0.5 ～
VDD+0.5
-40
(BU9795AKV/AFV/AGUW)
Unit
Remark
V
Power supply
V
LCD drive voltage
When use more than Ta=25C, subtract
W
6mW per degree.(BU9795AKV)
When use more than Ta=25C, subtract
W
7mW per degree (BU9795AFV)
When use more than Ta=25C, subtract
W
2.7mW per degree (BU9795AGUW)
V
+85
degree
-55 ～ +125
Tstg
*This product is not designed against radioactive ray.
degree
～
Storage temperature range
● Recommend operating conditions
(Ta=25degree,VSS=0V)
Symbol Min. Typ.
Parameter
Power Supply voltage1
VDD
2.5
Power Supply voltage2
VLCD
0
* Please use VDD-VLCD≧2.4V condition.
BU9795AGUW
31
4
VBGA48W040
Max.
5.5
VDD-2.4
10/23
(BU9795AKV/AFV/AGUW)
Unit
V
V
Remark
Power supply
LCD drive voltage
● Electrical Characteristics(BU9795AKV/AFV/AGUW)
DC Characteristics (VDD=2.5～5.5V, VSS=0V, Ta=-40～85degree, unless otherwise specified)
Symb
Limit
Unit
Condition
Parameter
MIN
TYP
MAX
ol
VIH
0.7VDD
VDD
V
“H” level input voltage
VIL
VSS
0.3VDD
V
“L” level input voltage
IIH
1
uA
“H” level input current
IIL
-1
uA
“L” level input current
RON
3.5
kΩ
Iload=±10uA
LCD Driver on SEG
COM
RON
3.5
kΩ
resistance
VDD -2.4
VLCD
0
V
VDD-VLCD≧2.5V
VLCD supply voltage
Display off, Oscillator off
Ist
5
uA
Standby current
Power consumption 1
IDD1
-
12.5
30
uA
VDD=3.3[V], Ta=25,
Power save mode1, FR=70Hz
1/3 bias, Frame inverse
Power consumption 2
IDD2
-
20
40
uA
VDD=3.3[V], Ta=25,
Normal mode, FR=80Hz
1/3 bias, Line inverse
● Oscillation Characteristics (BU9795AKV/AFV/AGUW)
(VDD=2.5～5.5V,VSS=0V, Ta=-40～85degree)
Limit
Symb
Parameter
Frame frequency
Frame frequency1
ol
MIN
TYP
MAX
fCLK
fCLK1
56
70
80
80
104
90
Unit
Hz
Hz
Condition
FR = 80Hz setting
VDD=3.5V, 25degree
● MPU interface Characteristics (BU9795AKV/AFV/AGUW)
(VDD=2.5V～5.5V,VSS=0V, Ta=-40～85degree)
Limit
Symb
Parameter
Input rise time
Input fall time
SCL cycle time
“H” SCL pulse width
“L” SCL pulse width
SD setup time
SD hold time
CSB setup time
CSB hold time
“H” CSB pulse width
ol
MIN
TYP
MAX
tr
tf
tSCY
tSHW
tSLW
tSDS
tSDH
tCSS
tCSH
tCHW
400
100
100
20
50
50
50
50
-
80
80
-
Unit
Condition
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCHW
CSB
tCSS
tf
tSCYC
tr
tCSH
tSLW
SCL
tSHW
tSDS
tSDH
SD
Fig.BU9795AKV/FV/GUW-1 3wire Serial timing waveform
11/23
* BU9795AKV
● Block Diagram
● Pin Arrangement
COM1
＋
－
LCD
BIAS
SELECTOR
common
counter
＋
－
blink timing
generator
DDRAM
VLCD
INHb
Command
Data Decoder
Command
register
OSCIN
SEG24
25
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
Segment
driver
SEG31
common
driver
SEG32
LCD voltage generator
SEG33
VDD
SEG34
SEG0……SEG34
36
COM0
COM0……COM3
37
24
SEG23
COM2
SEG22
COM3
SEG21
VLCD
SEG20
VDD
SEG19
VSS
SEG18
OSCIO
SEG17
CSB
SEG16
SCL
SEG15
SD
SEG14
TEST
INHb
serial inter face
SEG13
SEG12
13
48
CSB
SD
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG0
TEST
SEG2
1
IF FILTER
VSS
SEG11
12
Power On Reset
SEG1
OSCILLATOR
SCL
Fig. BU9795AKV /AFV /AGUW-2A
BU9795AKV Block diagram
Fig. BU9795AKV /AFV /AGUW-3A
BU9795AKV Pin arrangement
● Terminal description
Terminal
No.
I/O
INHb
48
I
TEST
47
I
OSCIO
43
I
SD
46
I
serial data input
SCL
45
I
serial data transfer clock
CSB
44
I
Chip select
VSS
42
GND
VDD
41
Power supply
VLCD
40
Power supply for LCD driving
Terminal
Function
Input terminal for turn off display
H: turn on display
L: turn off display
Test input (ROHM use only)
Must be connect to VSS
External clock input
Ex clock and Int clock can be changed by command.
Must be connect to VSS when use internal oscillation circuit.
:
“L” active
SEG0-34
1-35
O
SEGMENT output for LCD driving
COM0-3
36-39
O
COMMON output for LCD driving
12/23
* BU9795AFV
● Block Diagram
●
COM0……COM3
Pin Arrangement
SEG4……SEG30
VDD
SEG28
SEG29
COM0
SEG30
COM2
COM1
VLCD
COM3
VDD
VSS
CSB
OSCIO
SD
SCL
INHb
TEST
SEG5
SEG4
Segment
driver
SEG7
common
driver
SEG6
LCD voltage generator
40
21
1
20
＋
LCD
BIAS
SELECTOR
－
common
counter
＋
－
blink timing
generator
DDRAM
VLCD
OSCILLATOR
Power On Reset
serial inter face
IF FILTER
VSS
TEST
CSB
SD
SCL
Fig. BU9795AKV /AFV /AGUW-2B
BU9795AFV Block diagram
Fig. BU9795AKV /AFV /AGUW-3B
BU9795AFV Pin arrangement
● Terminal description
Terminal
No.
I/O
INHb
36
I
TEST
35
I
OSCIO
31
I
SD
34
I
serial data input
SCL
33
I
serial data transfer clock
CSB
32
I
Chip select
VSS
30
GND
VDD
29
Power supply
VLCD
28
Terminal
SEG4-30
COM0-3
1-23,
37-40
24-27
Function
Input terminal for turn off display
H: turn on display
L: turn off display
Test input (ROHM use only)
Must be connect to VSS
External clock input
Ex clock and Int clock can be changed by command.
Must be connect to VSS when use internal oscillation circuit.
:
“L” active
I
Power supply for LCD driving
O
SEGMENT output for LCD driving
O
COMMON output for LCD driving
13/23
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
Command
Data Decoder
Command
register
OSCIN
SEG8
INHb
* BU9795AGUW
● Block Diagram
●
COM0……COM3
Pin Arrangement
SEG2……SEG32
1
2
3
4
5
6
7
G
(NC)
SEG13
SEG15
SEG18
SEG20
SEG22
(NC)
F
SEG11
SEG12
SEG16
SEG17
SEG21
SEG23
SEG24
E
SEG9
SEG10
SEG14
SEG19
SEG25
SEG27
SEG26
D
SEG7
SEG6
SEG8
SEG5
SEG30
SEG28
SEG29
C
SEG4
SEG3
SEG2
CSB
COM3
SEG32
SEG31
INHb
SD
VSS
VDD
COM1
COM0
TEST2
SCL
OSCIO
VLCD
COM2
(NC)
VDD
LCD voltage generator
common
driver
Segment
driver
＋
LCD
BIAS
SELECTOR
－
common
counter
＋
－
blink timing
generator
DDRAM
VLCD
INHb
Command
Data Decoder
Command
register
OSCIN
OSCILLATOR
B
Power On Reset
serial inter face
A
(NC)
IF FILTER
VSS
TEST
CSB
SD
SCL
Fig. BU9795AKV /AFV /AGUW-2C
BU9795AGUW Block diagram
Fig. BU9795AKV /AFV /AGUW-3C
BU9795AGUW Pin arrangement
● Terminal description
Terminal
I/O
Function
Input terminal for turn off display
H: turn on display
L: turn off display
Test input (ROHM use only)
Must be connect to VSS
External clock input
Ex clock and Int clock can be changed by command.
Must be connect to VSS when use internal oscillation circuit.
INHb
I
TEST
I
OSCIO
I
SD
I
serial data input
SCL
I
serial data transfer clock
CSB
I
Chip select
:
VSS
GND
VDD
Power supply
“L” active
VLCD
I
Power supply for LCD driving
SEG2-32
O
SEGMENT output for LCD driving
COM0-3
O
COMMON output for LCD driving
(Caution) About terminal number, please refer to above pin arrangement
14/23
● Command Description (BU9795AKV/AFV/AGUW)
D7 (MSB) is bit for command or data judgment.
Refer to Command and data transfer method.
C: 0: Next byte is RAM write data.
1: Next byte is command.
○ Mode Set (MODE SET)
MSB
LSB
D7
D6
D5
D4
D3
D2
D1
D0
C
1
0
*
P3
P2
*
*
(*:Don’t care)
Set display ON and OFF
Setting
Display OFF
Display ON
(DISPOFF)
(DISPON)
P3
Reset initialize condition
0
○
1
Set bias level
P2
Reset initialize condition
1/3 Bias
0
○
1/2 Bias
1
Setting
○ Address set (ADSET)
MSB
LSB
D7
D6
D5
D4
D3
D2
D1
D0
C
0
0
P4
P3
P2
P1
P0
Address data is specified in P[4:0] and P2 (ICSET command) as follows.
MSB
LSB
Internal register
Address [5]
Address [4]
・・・
Address [0]
Bit of each command
ICSET [P2]
ADSET [P4]
・・・
ADSET [P0]
15/23
○ Display control (DISCTL)
MSB
LSB
D7
D6
D5
D4
D3
D2
D1
D0
C
0
1
P4
P3
P2
P1
P0
Set Frame frequency
Setting
80Hz
71Hz
P4
0
0
P3
0
1
64Hz
1
0
53Hz
1
1
Reset initialize condition
○
Set LCD drive waveform
Setting
P2
Reset initialize condition
Line inversion
0
○
Frame inversion
1
Set Power save mode
Setting
Power save mode 1
P1
0
P0
0
Power save mode 2
0
1
Normal mode
1
0
High power mode
1
1
Reset initialize condition
○
＊ VDD-VLCD>=3.0V is required for High power mode.
○ Set IC Operation (ICSET)
MSB
D7
C
D6
1
D5
1
D4
0
D3
1
D2
P2
D1
P1
LSB
D0
P0
P2: MSB data of DDRAM address. Please refer to “ADSET” command.
Setting
Address MSB‘0’
Address MSB‘1’
P2
0
1
Reset initialize condition
○
Set Software Reset condition
Setting
No operation
Software Reset
P1
0
1
Switch between internal clock and external clock.
Setting
P0
Reset initialize condition
Internal clock
0
○
External clock input
1
16/23
○ Blink control (BLKCTL)
MSB
D7
C
D6
1
D5
1
D4
1
D3
0
D2
*
D1
P1
LSB
D0
P0
Set blink condition
Setting
OFF
0.5 Hz
1 Hz
2 Hz
P1
0
0
1
1
P0
0
1
0
1
Reset initialize condition
○
○ All pixel control (APCTL)
MSB
D7
C
D6
1
D5
1
D4
1
D3
1
D2
1
D1
P1
LSB
D0
P0
All display set ON. OFF
Setting
Normal
All pixel ON
P1
0
1
Reset initialize condition
○
Setting
Normal
All pixel OFF
P0
0
1
Reset initialize condition
○
.
17/23
● Function description
(BU9795AKV/AFV/AGUW)
○ Command and data transfer method
○ 3-SPI (3wire Serial interface)
This device is controlled by 3-wire signal (CSB, SCL, and SD).
First, Interface counter is initialized with CSB=“H",
and CSB=”L” makes SD and SCL input enable.
The protocol of 3-SPI transfer is as follows.
Each command starts with Command or Data judgment bit (D/C) as MSB data,
and continuously in order of D6 to D0 are followed after CSB =”L”.
(Internal data is latched at the rising edge of SCL, it converted to 8bits parallel data
at the falling edge of 8th CLK.)
Command/Data
Command
CSB
SCL
SD
D/C D6
D5
D4
D3
D2
D1
D0
D/C
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D/C = “H” : Command D/C = “L” : Data
Fig. BU9795AKV /AFV /AGUW-10 3-SPI Command/Data transfer format
○Write display data and transfer method
* BU9795AKV
This LSI have Display Data RAM (DDRAM) of 35×4=140bit.
The relationship between data input and display data, DDRAM data and address are as follows.
Command
0000000
a
b
c d
e
f
g
h
i
j k
l m
n
o p
…
Display Data
8 bit data will be stored in DDRAM. The address to be written is the address
specified by Address set command, and the address is automatically incremented in
every 4bit data.
Data can be continuously written in DDRAM by transmitting Data continuously.
(When RAM data is written successively after writing RAM data to 22h (SEG34),
the address is returned to 00h (SEG0) by the auto-increment function.
DDRAM address
BIT
06h
1Fh
20h
21h
22h
01h
02h
03h
04h
05h
0
a
e
i
m
q
u
COM0
1
b
f
j
n
r
v
COM1
2
c
g
k
o
s
x
COM2
3
d
h
l
p
t
y
COM3
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
07h
1Eh
00h
SEG7
・・・・・・・・
・・・・・・・・
SEG30
SEG31
SEG32
SEG33
SEG34
As data transfer to DDRAM happens every 4bit data, it will be cancelled if it changes
CSB=”L”→”H” before 4bits data transfer.
18/23
*
BU9795AFV
As SEG0, SEG1, SEG2, SEG3, SEG31, SEG32, SEG33, SEG34 are not output, these
address will be dummy address.
Dummy data
BIT
Dummy data
DDRAM address
06h
1Fh
20h
21h
22h
01h
02h
03h
04h
05h
0
a
e
i
m
q
u
COM0
1
b
f
j
n
r
v
COM1
2
c
g
k
o
s
x
COM2
3
d
h
l
p
t
y
COM3
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
07h
1Eh
00h
SEG7
・・・・・・・・
・・・・・・・・
SEG30
SEG31
SEG32
SEG33
SEG34
As data transfer to DDRAM happens every 4bit data, it will be cancelled if it changes
CSB=”L”→”H” before 4bits data transfer.
* BU9795AGUW
As SEG0, SEG1, SEG33, SEG34 are not output, these address will be dummy address.
Dummy data
BIT
Dummy data
DDRAM address
06h
1Fh
20h
21h
22h
01h
02h
03h
04h
05h
0
a
e
i
m
q
u
COM0
1
b
f
j
n
r
v
COM1
2
c
g
k
o
s
x
COM2
3
d
h
l
p
t
y
COM3
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
07h
1Eh
00h
SEG7
・・・・・・・・
・・・・・・・・
SEG30
SEG31
SEG32
SEG33
SEG34
As data transfer to DDRAM happens every 4bit data, it will be cancelled if it changes
CSB=”L”→”H” before 4bits data transfer.
○ Reset (initial) condition
Initial condition after execute Software Reset is as follows.
・ Display is OFF.
・ DDRAM address is initialized (DDRAM Data is not initialized).
・ Refer to Command Description about initialize value of register.
19/23
● Cautions of Power-On condition (BU9795AKV /AFV /AGUW)
This LSI has “P.O.R” (Power-On Reset) circuit and Software Reset function.
Please keep the following recommended Power-On conditions in order to power up
properly.
1.
Please set power up conditions to meet the recommended tR, tF, tOFF, and Vbot spec below
in order to ensure P.O.R operation.
tF
VDD
Recommendation condition of tR,tF,tOFF,Vbot
tR
tOFF
Power
tR
tF
tOFF
Vbot
Less than 1ms
Less than 1ms
More than
Less than 0.1V
150ms
Vbot
ON/OFF
Fig. BU9795AKV /AFV /AGUW-18 Power on-off waveform
2.
If it is difficult to meet above conditions, execute the following sequence after Power-On.
Because it doesn’t accept the command in power off, it is necessary to care that correspondence
by software reset doesn’t become alternative to POR function completely.
(1) CSB=”L”→”H” condition
VDD
CSB
Fig. BU9795AKV-19 CSB Timing
(2)
● IO Circuit
After CSB”H”→“L”, execute Software Reset (ICSET command).
(BU9795AKV /AFV /AGUW)
VDD
VDD
VLCD
TEST
VSS
VSS
VDD
VDD
CSB, SD, SCL
OSCIN
VSS
VSS
VDD
VDD
INHb
VSS
VSS
Fig. BU9795AKV /AFV /AGUW-20 IO circuit
20/23
● Cautions on use
(1)
Absolute Maximum Ratings
An excess in the absolute maximum ratings, such as supply voltage, temperature range of operating conditions, etc., can break down devices,
thus making impossible to identify breaking mode such as a short circuit or an open circuit. If any special mode exceeding the absolute maximum ratings
is assumed, consideration should be given to take physical safety measures including the use of fuses, etc.
(2)
Operating conditions
These conditions represent a range within which characteristics can be provided approximately as expected. The electrical characteristics are guaranteed
under the conditions of each parameter.
(3)
Reverse connection of power supply connector
The reverse connection of power supply connector can break down ICs. Take protective measures against the breakdown due to the reverse connection,
such as mounting an external diode between the power supply and the IC’s power supply terminal.
(4)
Power supply line
Design PCB pattern to provide low impedance for the wiring between the power supply and the GND lines. In this regard, or the digital block power
supply and the analog block power supply, even though these power supplies has the same level of potential, separate the power supply pattern for
the digital block from that for the analog block, thus suppressing the diffraction of digital noises to the analog block power supply resulting from
impedance common to the wiring patterns. For the GND line, give consideration to design the patterns in a similar manner.
Furthermore, for all power supply terminals to ICs, mount a capacitor between the power supply and the GND terminal. At the same time, in order to use
an electrolytic capacitor, thoroughly check to be sure the characteristics of the capacitor to be used present no problem including the occurrence of
capacity dropout at a low temperature, thus determining the constant.
(5)
GND voltage
Make setting of the potential of the GND terminal so that it will be maintained at the minimum in any operating state. Furthermore, check to be sure
no terminals are at a potential lower than the GND voltage including an actual electric transient.
(6)
Short circuit between terminals and erroneous mounting
In order to mount ICs on a set PCB, pay thorough attention to the direction and offset of the ICs. Erroneous mounting can break down the ICs. Furthermore,
if a short circuit occurs due to foreign matters entering between terminals or between the terminal and the power supply or the GND terminal,
the ICs can break down.
(7)
Operation in strong electromagnetic field
Be noted that using ICs in the strong electromagnetic field can malfunction them.
(8)
Inspection with set PCB
On the inspection with the set PCB, if a capacitor is connected to a low-impedance IC terminal, the IC can suffer stress. Therefore, be sure to discharge
from the set PCB by each process. Furthermore, in order to mount or dismount the set PCB to/from the jig for the inspection process, be sure to turn OFF
the power supply and then mount the set PCB to the jig. After the completion of the inspection, be sure to turn OFF the power supply and then dismount
it from the jig. In addition, for protection against static electricity, establish a ground for the assembly process and pay thorough attention to the
transportation and the storage of the set PCB.
(9)
Input terminals
In terms of the construction of IC, parasitic elements are inevitably formed in relation to potential. The operation of the parasitic element can
cause interference with circuit operation, thus resulting in a malfunction and then breakdown of the input terminal. Therefore, pay thorough attention
not to handle the input terminals, such as to apply to the input terminals a voltage lower than the GND respectively, so that any parasitic element will
operate. Furthermore, do not apply a voltage to the input terminals when no power supply voltage is applied to the IC. In addition, even if the power
supply voltage is applied, apply to the input terminals a voltage lower than the power supply voltage or within the guaranteed value of
electrical characteristics.
(10)
Ground wiring pattern
If small-signal GND and large-current GND are provided, It will be recommended to separate the large-current GND pattern from the small-signal
GND pattern and establish a single ground at the reference point of the set PCB so that resistance to the wiring pattern and voltage fluctuations due to
a large current will cause no fluctuations in voltages of the small-signal GND. Pay attention not to cause fluctuations in the GND wiring pattern of
external parts as well.
(11)
External capacitor
In order to use a ceramic capacitor as the external capacitor, determine the constant with consideration given to a degradation in the nominal capacitance
due to DC bias and changes in the capacitance due to temperature, etc.
(12)
No Connecting input terminals
In terms of extremely high impedance of CMOS gate, to open the input terminals causes unstable state. And unstable state brings the inside
gate voltage of p-channel or n-channel transistor into active. As a result, battery current may increase. And unstable state can also causes
unexpected operation of IC. So unless otherwise specified, input terminals not being used should be connected to the power supply or GND line.
(13)
Rush current
When power is first supplied to the CMOS IC, it is possible that the internal logic may be unstable and rush current may flow
instantaneously. Therefore, give special condition to power coupling capacitance, power wiring, width of GND wiring, and routing of connections.
21/23
● Order form name selection
B
U
9
7
ROHM form name
9
5
Part No.
A
K
V
E
－
2
Packaging and forming specification
Package type
KV=VQFP
FV= SSOP-B
GUW=VBGA
E2 =Reel-shaped emboss taping
VQFP48C
< Packing information >
<Dimension>
9.0±0.2
7.0±0.1
48
13
1
0.75
24
12
Quantity
1500pcs
Direction
of feed
E2
(The direction is the 1pin of product is at the upper left when you hold
reel on the left hand and you pull out the tape on the right hand)
4° +6°
−4°
0.08 S
0.1±0.05
1.6Max.
Embossed carrier tape
+0.05
0.145−0.03
0.75
1.4±0.05
1.0±0.2
0.5±0.15
25
37
7.0±0.1
9.0±0.2
36
Tape
0.5±0.1
+0.05
0.22−0.04
0.08 M
Direction of feed
1Pin
Reel
(Unit:mm)
*When you order , please order in times the amount of package quantity.
SSOP-B40
<Dimension>
<Tape and Reel information>
Embossed carrier tape
Tape
13.6 ± 0.2
21
1
20
0.3Min.
0.15 ± 0.1
1234
1234
1234
Direction of feed
1pin
Reel
(Unit:mm)
1234
0.08 M
1234
0.22 ± 0.1
1234
0.1
0.65
(The direction is the 1pin of product is at the upper left when you hold
reel on the left hand and you pull out the tape on the right hand)
1234
0.1
2000pcs
E2
1234
1.8 ± 0.1
7.8 ± 0.3
5.4 ± 0.2
40
Quantity
Direction
of feed
※When you order , please order in times the amount of package quantity.
VBGA048W040
<Dimension>
<Tape and Reel information>
0.10
0.9MAX
4.0 ± 0.1
1PIN MARK
4.0±0.1
Tape
Embossed carrier tape (with dry pack)
Quantity
2500pcs
Direction
of feed
E2
(The direction is the 1pin of product is at the upper left when you hold
reel on the left hand and you pull out the tape on the right hand.)
S
P=0.5×6
0.5
A
G
F
E
D
C
B
A
B
0.05 M S AB
1234
1234
1234
0.5
P=0.5 × 6
0.5±0.1
48-φ0.295±0.05
0.5 ± 0.1
0.08 S
Reel
1 2 3 4 5 6 7
(Unit:mm)
1Pin
1234
1234
1234
Direction of feed
※When you order , please order in times the amount of package quantity.
22/23
23/23
Catalog No.08T313A '08.7 ROHM ©
Appendix
Notes
No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM
CO.,LTD.
The content specified herein is subject to change for improvement without notice.
The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you
wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM
upon request.
Examples of application circuits, circuit constants and any other information contained herein illustrate the
standard usage and operations of the Products. The peripheral conditions must be taken into account
when designing circuits for mass production.
Great care was taken in ensuring the accuracy of the information specified in this document. However, should
you incur any damage arising from any inaccuracy or misprint of such information, ROHM shall bear no responsibility for such damage.
The technical information specified herein is intended only to show the typical functions of and examples
of application circuits for the Products. ROHM does not grant you, explicitly or implicitly, any license to
use or exercise intellectual property or other rights held by ROHM and other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the use of such technical information.
The Products specified in this document are intended to be used with general-use electronic equipment
or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices).
The Products are not designed to be radiation tolerant.
While ROHM always makes efforts to enhance the quality and reliability of its Products, a Product may fail or
malfunction for a variety of reasons.
Please be sure to implement in your equipment using the Products safety measures to guard against the
possibility of physical injury, fire or any other damage caused in the event of the failure of any Product, such as
derating, redundancy, fire control and fail-safe designs. ROHM shall bear no responsibility whatsoever for your
use of any Product outside of the prescribed scope or not in accordance with the instruction manual.
The Products are not designed or manufactured to be used with any equipment, device or system
which requires an extremely high level of reliability the failure or malfunction of which may result in a direct
threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment,
aerospace machinery, nuclear-reactor controller, fuel-controller or other safety device). ROHM shall bear
no responsibility in any way for use of any of the Products for the above special purposes. If a Product is intended to be used for any such special purpose, please contact a ROHM sales representative before purchasing.
If you intend to export or ship overseas any Product or technology specified herein that may be controlled under
the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law.
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Copyright © 2009 ROHM CO.,LTD.
THE AMERICAS / EUROPE / ASIA / JAPAN
Contact us : webmaster @ rohm.co. jp
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TEL : +81-75-311-2121
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Appendix-Rev4.0