CG6257AM PRELIMINARY 4Mb (256K x 16) Pseudo Static RAM Features when deselected (CE HIGH or both BHE and BLE are HIGH). The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected (CE HIGH ), outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH), or during a write operation (CE LOW and WE LOW). The addresses must not be toggled once the read is started on the device. • Wide voltage range: 2.70V–3.30V • Access Time: 70ns • Ultra-low active power — Typical active current: 2.0mA @ f = 1 MHz • • • • — Typical active current: 13mA @ f = fmax Ultra low standby power Automatic power-down when deselected CMOS for optimum speed/power Offered in a 48 Ball BGA Package Writing to the device is accomplished by taking Chip Enables (CE LOW ) and Write Enable (WE) input LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A17). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A17). Functional Description[1] The CG6257AM is a high-performance CMOS Pseudo static RAM organized as 256K words by 16 bits that supports an asynchronous memory interface. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life® (MoBL) in portable applications such as cellular telephones. The device can be put into standby mode reducing power consumption by more than 99% The device can also be put into standby mode Reading from the device is accomplished by taking Chip Enables (CE LOW) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the back of this datasheet for a complete description of read and write modes Logic Block Diagram 256K × 16 RAM Array SENSE AMPS A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ROW DECODER DATA IN DRIVERS I/O0 – I/O7 I/O8 – I/O15 COLUMN DECODER A11 A12 A13 A14 A15 A16 A17 BHE WE CE OE BLE Power- Down Circuit BHE BLE CE Note: 1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com. Weida Semiconductor, Inc. 38-XXXXX Revised August 2003 PRELIMINARY CG6257AM Pin Configuration[2, 3, 4] FBGA Top View 1 2 3 4 5 6 BLE OE A0 A1 A2 NC A I/O8 BHE A3 A4 CE I/O0 B I/O9 I/O10 A5 A6 I/O1 I/O2 C VSS I/O11 A17 A7 I/O3 Vcc D VCC I/O12 GND A16 I/O4 Vss E I/O14 I/O13 A14 A15 I/O5 I/O6 F I/O15 NC/ A19 A12 A13 WE I/O7 G NC/ A18 A8 A9 A10 A11 NC/ A20 H Note: 2. DNU pins have to be left floating. 3. Ball H1, G2 and ball H6 for the FBGA package can be used to upgrade to a 8M, 16M and a 32M density respectively. 4. NC “no connect” - not connected internally to the die. 38-XXXXX Page - 2 - of 12 PRELIMINARY CG6257AM Maximum Ratings DC Voltage Applied to Outputs in High Z State[5, 6, 7] ........................................–0.4V to 3.3V (Above which the useful life may be impaired. For user guidelines, not tested.) DC Input Voltage[5, 6, 7].....................................–0.4V to 3.3V Output Current into Outputs (LOW)............................. 20 mA Storage Temperature ................................–65°C to + 150°C Static Discharge Voltage .......................................... >2001V (per MIL-STD-883, Method 3015) Ambient Temperature with Power Applied............................................ –55°C to + 125°C Latch-Up Current .....................................................>200 mA Supply Voltage to Ground Potential................. –0.4V to 4.6V Operating Range[9] Device Range Ambient Temperature VCC CG6257AM Industrial –25°C to +85°C 2.70V to 3.30V Product Portfolio Power Dissipation Product Speed (ns) VCC Range (V) Operating ICC(mA) f = 1MHz CG6257AM Min. Typ.[8] Max. 2.70 3.0 3.30 70 f = fmax Standby ISB2(µA) Typ.[8] Max. Typ.[8] Max. Typ.[8] Max. 2 4 13 17 55 80 Notes: 5. VIL(MIN) = -0.5V for pulse durations less than 20ns. 6. VIH(Max) = Vcc + 0.5V for pulse durations less than 20ns. 7. Overshoot and undershoot specifications are characterized and are not 100% tested. 8. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25°C. 9. Vcc must be at minimal operational levels before inputs are turned ON. 38-XXXXX Page - 3 - of 12 PRELIMINARY CG6257AM Electrical Characteristics Over the Operating Range CG6257AM-70 Parameter Description Test Conditions Typ.[8] Min. VCC Supplay Voltage 2.7 VOH Output HIGH Voltage IOH = –1.0 mA VCC = 2.70V VOL Output LOW Voltage IOL = 2.0mA VCC = 2.70V VIH Input HIGH Voltage VCC= 2.7V to 3.3V VIL Input LOW Voltage VCC= 2.7V to 3.3V(F = 0) IIX Input Leakage Current IOZ ICC Max. Unit 3.3 V 2.4 V 0.4 V 0.8*Vcc VCC +0.3V V -0.3 0.4 V GND < VI < VCC –1 +1 µA Output Leakage Current GND < VO < VCC, Output Disabled –1 +1 µA VCC Operating Supply Current f = fMAX = 1/tRC 13 17 mA 2.0 4 mA 350 µA 80 µA VCC = VCCmax IOUT = 0 mA CMOS levels f = 1 MHz ISB1 Automatic CE Power-Down Current — CMOS Inputs Vcc = 3.3V CE > VCC−0.2V VIN>VCC–0.2V, VIN<0.2V) f = fMAX (Address and Data Only), f = 0 (OE, WE, BHE and BLE), VCC=3.30V ISB2 Automatic CE Power-Down Current — CMOS Inputs Vcc = 3.3V CE > VCC – 0.2V VIN > VCC – 0.2V or VIN < 0.2V, f = 0, VCC = 3.30V 55 Capacitance[10] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions Max. Unit 6 pF 8 pF TA = 25°C, f = 1 MHz, VCC = VCC(typ) Thermal Resistance[10] Description Thermal Resistance (Junction to Ambient) Test Conditions Still Air, soldered on a 3 × 4.5 inch, two-layer printed circuit board Thermal Resistance (Junction to Case) Symbol BGA Unit ΘJA 55 °C/W ΘJC 16 °C/W Note: 10. Tested initially and after any design or process changes that may affect these parameters. 38-XXXXX Page - 4 - of 12 PRELIMINARY CG6257AM AC Test Loads and Waveforms R1 VCC OUTPUT 50 pF INCLUDING JIG AND SCOPE 38-XXXXX VCC R2 10% GND Rise Time = 1 V/ns ALL INPUT PULSES 90% 90% 10% Fall Time = 1 V/ns Equivalentto: THÉVENINEQUIVALENT RTH OUTPUT V Parameters 3.0V VCC Unit R1 1179 Ω R2 1941 Ω RTH 733 Ω VTH 1.87 V Page - 5 - of 12 PRELIMINARY CG6257AM Switching Characteristics Over the Operating Range[11] 70 ns Parameter Description Min. Max. Unit READ CYCLE tRC Read Cycle Time 70 tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE LOW to Data Valid 70 ns tDOE OE LOW to Data Valid 35 ns OE LOW to LOW Z tHZOE OE HIGH to High Z[12, 14] tLZCE CE LOW to Low Z 70 [12, 14] tLZOE [12, 14] tDBE BLE / BHE LOW to Data Valid tLZBE BLE / BHE LOW to Low Z[12, 14] BLE / BHE HIGH to HIGH ns 5 Z[12, 14] Address Skew ns ns 25 ns 70 ns 5 Z[12, 14] ns ns 25 CE HIGH to High tSK 10 5 tHZCE tHZBE ns ns 25 ns 0 ns [13] WRITE CYCLE tWC Write Cycle Time 70 ns tSCE CE LOW to Write End 60 ns tAW Address Set-Up to Write End 60 ns tHA Address Hold from Write End 0 ns tSA Address Set-Up to Write Start 0 ns tPWE WE Pulse Width 45 ns tBW BLE / BHE LOW to Write End 60 ns tSD Data Set-Up to Write End 45 ns tHD Data Hold from Write End 0 ns tHZWE tLZWE WE LOW to High-Z[12, 14] WE HIGH to Low-Z[12, 14] 25 5 ns ns Notes: 11. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1ns/V, timing reference levels of VCC(typ)/2, input pulse levels of 0V to VCC(typ.), and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” section.. 12. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedence state. 13. The internal Write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write 14. High-Z and Low-Z parameters are characterized and are not 100% tested. . 38-XXXXX Page - 6 - of 12 PRELIMINARY CG6257AM Switching Waveforms Read Cycle 1 (Address Transition Controlled)[15, 16] tRC ADDRESS tSK DATA OUT tOHA tAA DATA VALID PREVIOUS DATA VALID Read Cycle 2 (OE Controlled) [15, 16] ADDRESS CE tRC tSK tPD tHZCE tACE BHE/BLE tLZBE tDBE tHZBE OE tHZOE tDOE DATA OUT VCC SUPPLY CURRENT tLZOE HIGH IMPEDANCE tPU HIGH IMPEDANCE DATA VALID tLZCE 50% 50% ICC ISB Note: 15. WE is HIGH for Read Cycle. 16. Addresses should not be toggled after the start of a read cycle 38-XXXXX Page - 7 - of 12 PRELIMINARY CG6257AM Switching Waveforms (continued) Write Cycle 1 (WE Controlled) [13, 14, 17, 18, 19] t WC ADDRESS tSCE CE tAW tSA tHA tPWE WE tBW BHE/BLE OE tSD DATAI/O tHD VALID DATA DON’T CARE tHZOE [13, 14, 17, 18, 19] Write Cycle 2 (CE Controlled) t WC ADDRESS tSCE CE tSA tAW tHA tPWE WE tBW BHE/BLE OE tSD DATAI/O tHD VALID DATA DON’T CARE tHZOE Notes: 17. Data I/O is high impedance if OE = VIH. 18. If Chip Enable goes INACTIVE with WE = VIH, the output remains in a high-impedance state. 19. During the DON’T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied. 38-XXXXX Page - 8 - of 12 PRELIMINARY CG6257AM Switching Waveforms (continued) [18, 19] Write Cycle 3 (WE Controlled, OE LOW) tWC ADDRESS tSCE CE tBW BHE/BLE tAW tSA tHA tPWE WE tHD tSD DATAI/O DON’T CARE VALID DATA tLZWE tHZWE Write Cycle 4 (BHE/BLE Controlled, OE LOW) [18, 19] tWC ADDRESS CE tSCE tAW tHA tBW BHE/BLE tSA WE tPWE tSD DATA I/O 38-XXXXX DON’T CARE tHD VALID DATA Page - 9 - of 12 PRELIMINARY CG6257AM Truth Table[20] CE WE OE BHE BLE H X X X X X X X H L H L L L H L L H L L H L H L Inputs/Outputs Mode Power High Z Deselect/Power-Down Standby (ISB) H High Z Deselect/Power-Down Standby (ISB) L Data Out (I/O0 – I/O15) Read Active (ICC) H L Data Out (I/O0 – I/O7); High Z (I/O8 – I/O15) Read Active (ICC) L H High Z (I/O0 – I/O7); Data Out (I/O8 – I/O15) Read Active (ICC) H L H High Z Output Disabled Active (ICC) H H L High Z Output Disabled Active (ICC) H H L L High Z Output Disabled Active (ICC) L L X L L Data In (I/O0 – I/O15) Write Active (ICC) L L X H L Data In (I/O0 – I/O7); High Z (I/O8 – I/O15) Write Active (ICC) L L X L H High Z (I/O0 – I/O7); Data In (I/O8 – I/O15) Write Active (ICC) Note: 20. H = VIH, L = VIL, X = Don’t Care Ordering Information Speed (ns) Ordering Code Package Name Package Type Operating Range 70 CG6257AM BA48K 48-ball Fine Pitch BGA (6 mm × 8mm × 1.2 mm) Industrial 38-XXXXX Page - 10 - of 12 PRELIMINARY CG6257AM Package 48-Ball (6 mm x 8mm x 1.2 mm) FBGA BA48K BOTTOM VIEW TOP VIEW A1 CORNER Ø0.05 M C Ø0.25 M C A B Ø0.30±0.05(48X) A1 CORNER 1 2 3 4 5 6 6 4 3 2 C F D E F 2.625 8.00±0.10 E 0.75 B C 5.25 A B G G H H A 1.875 A 0.75 6.00±0.10 B 3.75 B 0.15 C 0.21±0.05 0.53±0.05 0.25 C 1 A D 8.00±0.10 5 6.00±0.10 0.15(4X) REFERENCE JEDEC MO-207 C 1.20 MAX 0.36 SEATING PLANE 51-85193-*A MoBL and More Battery Life are trademarks of Cypress Semiconductor Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders 38-XXXXX Page - 11 - of 12 © Weida Semiconductor, Inc., 2002. The information contained herein is subject to change without notice. Weida Semiconductor assumes no responsibility for the use of any circuitry other than circuitry embodied in a Weida Semiconductor product. Nor does it convey or imply any license under patent or other rights. Weida Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Weida Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Weida Semiconductor against all charges. PRELIMINARY CG6257AM Document Title: CG6257AM MoBL3® 4Mb (256K x 16) Pseudo Static RAM Document Number: 38-XXXXX REV. ** 38-XXXXX ECN NO. Issue Date Orig. of Change 10/21/03 MPR Description of Change New Datasheet Page - 12 - of 12