Spec. No. : C933F3 Issued Date : 2015.12.11 Revised Date : Page No. : 1/9 CYStech Electronics Corp. N-Channel Enhancement Mode Power MOSFET MTE2D4N06F3 BVDSS ID @VGS=10V, TC=25°C 60V RDSON(TYP) @ VGS=10V, ID=20A 60A 3.3mΩ RDSON(TYP) @ VGS=7V, ID=20A 3.5mΩ Features • Simple Drive Requirement • Fast Switching Characteristic • RoHS compliant package Symbol Outline MTE2D4N06F3 TO-263 G D S G：Gate D：Drain S：Source Ordering Information Device MTE2D4N06F3-0-T7-X Package Shipping TO-263 800 pcs / Tape & Reel (Pb-free lead plating and RoHS compliant package) Environment friendly grade : S for RoHS compliant products, G for RoHS compliant and green compound products Packing spec, T7 : 800 pcs / tape & reel, 13” reel Product rank, zero for no rank products Product name MTE2D4N06F3 CYStek Product Specification CYStech Electronics Corp. Spec. No. : C933F3 Issued Date : 2015.12.11 Revised Date : Page No. : 2/9 Absolute Maximum Ratings (TC=25°C, unless otherwise noted) Parameter Symbol Limits Drain-Source Voltage Gate-Source Voltage Continuous Drain Current @ TC=25°C(silicon limit) Continuous Drain Current @ TC=100°C(silicon limit) Continuous Drain Current @ TC=25°C(package limit) (Note 1) Pulsed Drain Current (Note 3) Continuous Drain Current @ TA=25°C (Note 2) Continuous Drain Current @ TA=70°C (Note 2) Avalanche Current (Note 3) Avalanche Energy @ L=1mH, ID=40A, RG=25Ω (Note 4) TC=25°C (Note 1) Power Dissipation TC=100°C (Note 1) TA=25°C (Note 2) Power Dissipation TA=70°C (Note 2) Operating Junction and Storage Temperature VDS VGS 60 ±30 188 133 60 480 15 12 120 800 330 165 2 1.3 -55~+175 ID IDM IDSM IAS EAS PD PDSM Tj, Tstg Unit V A mJ W °C Thermal Data Parameter Thermal Resistance, Junction-to-case, max Thermal Resistance, Junction-to-ambient, max, (Note 2) Symbol Rth,j-c Rth,j-a Value 0.45 62.5 Unit °C/W Note : 1.The power dissipation PD is based on TJ(MAX)=175°C, using junction-to-case thermal resistance, and is more useful in setting the upper dissipation limit for cases where additional heatsinking is used. 2.The value of RθJA is measured with the device mounted on 1 in²FR-4 board with 2 oz. copper, in a still air environment with TA=25°C. The power dissipation PDSM is based on RθJA and the maximum allowed junction temperature of 150°C. The value in any given application depends on the user’s specific board design, and the maximum temperature of 175°C may be used if the PCB allows it. 3. Pulse width limited by junction temperature TJ(MAX)=175°C. Ratings are based on low frequency and low duty cycles to keep initial TJ=25°C. 4. 100% tested by conditions of L=1mH, IAS=25A, VGS=15V, VDD=25V. 5. The static characteristics are obtained using <300μs pulses, duty cycle 0.5% maximum. 6. The RθJA is the sum of thermal resistance from junction to case RθJC and case to ambient. MTE2D4N06F3 CYStek Product Specification CYStech Electronics Corp. Spec. No. : C933F3 Issued Date : 2015.12.11 Revised Date : Page No. : 3/9 Characteristics (TC=25°C, unless otherwise specified) Symbol Static BVDSS VGS(th) GFS IGSS IDSS *RDS(ON) Min. Typ. Max. 60 2.0 - 40.8 3.3 3.5 4.0 ±100 1 25 4.5 5.5 124.4 22.5 54.0 47.6 55 88.2 40 5871 1011 335 2.9 - 0.66 41 53 60 480 0.9 - Dynamic *Qg *Qgs *Qgd *td(ON) *tr *td(OFF) *tf Ciss Coss Crss Rg Source-Drain Diode *IS *ISM *VSD *trr *Qrr - Unit V S nA μA mΩ Test Conditions VGS=0V, ID=250μA VDS = VGS, ID=250μA VDS =10V, ID=20A VGS=±30V VDS =48V, VGS =0V VDS =48V, VGS =0V, Tj=125°C VGS =10V, ID=20A VGS =7V, ID=20A nC ID=120A, VDS=30V, VGS=10V ns VDS=30V, ID=60A, VGS=10V, RG=4.7Ω pF VGS=0V, VDS=25V, f=1MHz Ω f=1MHz A V ns nC IS=1A, VGS=0V IF=20A, VGS=0V, dIF/dt=100A/μs *Pulse Test : Pulse Width ≤300μs, Duty Cycle≤2% MTE2D4N06F3 CYStek Product Specification Spec. No. : C933F3 Issued Date : 2015.12.11 Revised Date : Page No. : 4/9 CYStech Electronics Corp. Typical Characteristics Brekdown Voltage vs Ambient Temperature Typical Output Characteristics 1.4 200 BVDSS, Normalized Drain-Source Breakdown Voltage 10V, 9V, 8V ID, Drain Current(A) 160 7V 120 80 6V 40 1.2 1 0.8 0.6 ID=250μA, VGS=0V VGS=5.5V 0.4 0 0 1 2 3 4 VDS, Drain-Source Voltage(V) -75 -50 -25 5 Static Drain-Source On-State resistance vs Drain Current Reverse Drain Current vs Source-Drain Voltage 1.2 100 VSD, Source-Drain Voltage(V) R DS(ON) , Static Drain-Source On-State Resistance(mΩ) 1000 VGS=6V 7V 10V 10 1 Tj=25°C 0.8 0.6 Tj=150°C 0.4 0.2 1 0.01 0.1 1 10 ID, Drain Current(A) 100 0 4 8 12 16 IDR , Reverse Drain Current(A) 20 Drain-Source On-State Resistance vs Junction Tempearture Static Drain-Source On-State Resistance vs Gate-Source Voltage 100 2.8 90 R DS(ON) , Normalized Static DrainSource On-State Resistance R DS(ON) , Static Drain-Source OnState Resistance(mΩ) 0 25 50 75 100 125 150 175 200 Tj, Junction Temperature(°C) ID=20A 80 70 60 50 40 30 20 10 2.4 VGS=10V, ID=20A 2 1.6 1.2 0.8 0.4 RDS(ON) @Tj=25°C :3.3mΩ typ 0 0 0 MTE2D4N06F3 2 4 6 8 VGS, Gate-Source Voltage(V) 10 -75 -50 -25 0 25 50 75 100 125 150 175 200 Tj, Junction Temperature(°C) CYStek Product Specification CYStech Electronics Corp. Spec. No. : C933F3 Issued Date : 2015.12.11 Revised Date : Page No. : 5/9 Typical Characteristics(Cont.) NormalizedThreshold Voltage vs Junction Tempearture Capacitance vs Drain-to-Source Voltage VGS(th), Normalized Threshold Voltage 10000 Capacitance---(pF) Ciss C oss 1000 Crss 1.4 1.2 ID=1mA 1 0.8 0.6 ID=250μA 0.4 0.2 100 0 5 10 15 20 25 VDS, Drain-Source Voltage(V) -75 -50 -25 30 Forward Transfer Admittance vs Drain Current Gate Charge Characteristics 10 VGS, Gate-Source Voltage(V) GFS , Forward Transfer Admittance(S) 100 10 1 VDS=10V Pulsed Ta=25°C 0.1 0.01 0.001 8 6 4 VDS=30V ID=120A 2 0 0.01 0.1 1 ID, Drain Current(A) 10 0 100 20 40 60 80 100 120 Total Gate Charge---Qg(nC) 140 160 Maximum Drain Current vs Case Temperature Maximum Safe Operating Area 200 1000 ID, Maximum Drain Current(A) 10μs RDS(ON) Limited ID, Drain Current(A) 0 25 50 75 100 125 150 175 200 Tj, Junction Temperature(°C) 100μs 100 1ms 10ms 10 100ms DC 1 TC=25°C, Tj=175°, VGS=10V RθJC=0.45°C/W, Single P l 0.1 0.1 MTE2D4N06F3 1 10 100 VDS, Drain-Source Voltage(V) silicon limit 160 120 80 package limit 40 VGS=10V, RθJC=0.45°C/W 0 1000 25 50 75 100 125 150 TC , Case Temperature(°C) 175 200 CYStek Product Specification Spec. No. : C933F3 Issued Date : 2015.12.11 Revised Date : Page No. : 6/9 CYStech Electronics Corp. Typical Characteristics(Cont.) Typical Transfer Characteristics Single Pulse Maximum Power Dissipation 5000 200 4500 VDS=10V 3500 Power (W) ID, Drain Current (A) TJ(MAX) =175°C TC=25°C RθJC=0.45°C/W 4000 160 120 80 3000 2500 2000 1500 40 1000 500 0 0 2 4 6 8 VGS, Gate-Source Voltage(V) 10 0 0.0001 0.001 0.01 0.1 Pulse Width(s) 1 10 Transient Thermal Response Curves 1 r(t), Normalized Effective Transient Thermal Resistance D=0.5 0.1 0.2 1.RθJC(t)=r(t)*RθJC 2.Duty Factor, D=t1/t2 3.TJM-TC=PDM*RθJC(t) 4.RθJC=0.45 ° C/W 0.1 0.05 0.02 0.01 0.01 Single Pulse 0.001 1.E-05 MTE2D4N06F3 1.E-04 1.E-03 1.E-02 1.E-01 t1, Square Wave Pulse Duration(s) 1.E+00 1.E+01 CYStek Product Specification CYStech Electronics Corp. Spec. No. : C933F3 Issued Date : 2015.12.11 Revised Date : Page No. : 7/9 Reel Dimension Carrier Tape Dimension MTE2D4N06F3 CYStek Product Specification CYStech Electronics Corp. Spec. No. : C933F3 Issued Date : 2015.12.11 Revised Date : Page No. : 8/9 Recommended wave soldering condition Product Peak Temperature Soldering Time Pb-free devices 260 +0/-5 °C 5 +1/-1 seconds Recommended temperature profile for IR reflow Profile feature Average ramp-up rate (Tsmax to Tp) Preheat −Temperature Min(TS min) −Temperature Max(TS max) −Time(ts min to ts max) Time maintained above: −Temperature (TL) − Time (tL) Peak Temperature(TP) Time within 5°C of actual peak temperature(tp) Ramp down rate Time 25 °C to peak temperature Sn-Pb eutectic Assembly Pb-free Assembly 3°C/second max. 3°C/second max. 100°C 150°C 60-120 seconds 150°C 200°C 60-180 seconds 183°C 60-150 seconds 240 +0/-5 °C 217°C 60-150 seconds 260 +0/-5 °C 10-30 seconds 20-40 seconds 6°C/second max. 6 minutes max. 6°C/second max. 8 minutes max. Note : All temperatures refer to topside of the package, measured on the package body surface. MTE2D4N06F3 CYStek Product Specification Spec. No. : C933F3 Issued Date : 2015.12.11 Revised Date : Page No. : 9/9 CYStech Electronics Corp. TO-263 Dimension A F α1 2 Marking : E C Device Name Date Code B D 1 2 E2D4 N06 □□□□ α2 3 I G J K L α3 H Style : Pin 1.Gate 2.Drain 3.Source 3-Lead Plastic Surface Mounted Package CYStek Package Code : F3 Date Code : (From left to right) First Code : Year code, the last digit of Christinr year. For example, 2014→4, 2015→, 2016→6, …, etc. Second Code : Month code, Jan→A, Feb→B, Mar→C, Apr→D, May→E, Jun→F, Jul→G, Aug→H, Sep→J, Oct→K, Nov→L, Dec→M Third and fourth codes : production serial number, 01~99 *:Typical Inches Min. Max. 0.3800 0.4050 0.3300 0.3700 0.0550 0.5750 0.6250 0.1600 0.1900 0.0450 0.0550 0.0900 0.1100 0.0180 0.0290 DIM A B C D E F G H Millimeters Min. Max. 9.65 10.29 8.38 9.40 1.40 14.61 15.88 4.06 4.83 1.14 1.40 2.29 2.79 0.46 0.74 DIM I J K L α1 α2 α3 Inches Min. Max. 0.0500 0.0700 *0.1000 0.0450 0.0550 0.0200 0.0390 - Millimeters Min. Max. 1.27 1.78 *2.54 1.14 1.40 0.51 0.99 6° 8° 6° 8° 0° 5° Notes : 1.Controlling dimension : millimeters. 2.Maximum lead thickness includes lead finish thickness, and minimum lead thickness is the minimum thickness of base material. 3.If there is any question with packing specification or packing method, please contact your local CYStek sales office. Material : • Lead : Pure tin plated. • Mold Compound : Epoxy resin family, flammability solid burning class:UL94V-0. Important Notice: • All rights are reserved. Reproduction in whole or in part is prohibited without the prior written approval of CYStek. • CYStek reserves the right to make changes to its products without notice. • CYStek semiconductor products are not warranted to be suitable for use in Life-Support Applications, or systems. • CYStek assumes no liability for any consequence of customer product design, infringement of patents, or application assistance. MTE2D4N06F3 CYStek Product Specification