INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC • The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4737B HEF4737V LSI Quadruple static decade counters Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification HEF4737B HEF4737V Quadruple static decade counters The complementary MOS structure gives the devices very low stand-by and operating dissipation. Operating from a single supply voltage all outputs can drive one standard TTL input without interface circuitry under all specified operating conditions. DESCRIPTION The HEF4737B and HEF4737V are static quadruple decade counters for frequencies from 0 to 10 MHz. The counters are supplied with an extra overload flip-flop giving a total count capability of 19 999. The counter has the following inputs and outputs: a count input (CP), an asynchronous reset input (MR), an asynchronous preset input (PL), a transfer input (T), an output enable input (EO) (which controls the BCD outputs), the digit select inputs (SA, SB, SC) (which perform selection of the contents of the latches to the 3-state BCD outputs (O0 to O3)), and the carry outputs (CO2 to CO5) (which give the carry signals of the decades except from the first decade). The BCD digit outputs are LOCMOS 3-state outputs. The high impedance off-state feature allows common busing of the outputs. The counters are supplied with asynchronous reset and preset to 19 999 facilities making them suitable for counter and time base applications. All carry signals are available except from the first decade. Schmitt-trigger action in the inputs makes the circuit highly tolerant to slower input rise and fall times. Recommended supply voltage range for HEF4737B is 3 to 15 V and for HEF4737V is 4,5 to 12,5 V. HEF4737BP; HEF4737VP(N); 18-lead DIL plastic (SOT102-1) HEF4737BD; HEF4737VD(F); 18-lead DIL ceramic (SOT133B) ( ): Package Designator North America SUPPLY VOLTAGE Fig.1 Pinning diagram. RECOMMENDED OPERATING HEF4737B −0,5 to 18 3,0 to 15,0 V HEF4737V −0,5 to 18 4,5 to 12,5 V FAMILY DATA, IDD LIMITS category LSI PINNING CP count input MR asynchronous reset input PL asynchronous preset input T transfer input SA, SB, SC digit select inputs EO output enable input O0 to O3 BCD outputs CO2 to CO5 carry outputs January 1995 RATING See Family Specifications 2 Philips Semiconductors Product specification HEF4737B HEF4737V Quadruple static decade counters Fig.2 Block diagram. FUNCTIONAL DESCRIPTION Preset input (PL) Input signals This is an asynchronous preset. When MR is LOW a HIGH at the PL input will preset the counter to 19 999 independent of the level at the count input. Count input (CP) The signal to be counted is applied to this input. When PL and MR are LOW the contents of the counter increments by one at a LOW to HIGH transition of CP. Transfer input (T) A HIGH level applied to this input allows the information held by the counter to pass to the latches. Reset input (MR) Output enable input (EO) This is an asynchronous reset. A HIGH level applied to this input will reset the counter to zero independent of the level at the count input and preset input. January 1995 A HIGH level at this input enables the BCD outputs and information can be read out of the latches using the 3 Philips Semiconductors Product specification HEF4737B HEF4737V Quadruple static decade counters multiplexer. A LOW level at this input disables the BCD outputs making them floating (high impedance off-state). Output signals The carry outputs are active LOW outputs. Digit select inputs (SA, SB, SC) Carry output CO2 SA SB SC L L L selects D1 (LSD) H L L selects D2 L H L selects D3 H H L selects D4 X X H selects D5 (MSD) When the contents of the first two decades of the counter are both 9 then the CO2 output becomes LOW. It remains LOW until the next LOW to HIGH transition of the count input, i.e. until the contents of the first two decades are zero. CO2 is LOW when the contents of the counter are: 00 099, 00 199, 00 299 etc. Carry output CO3 When the contents of the first three decades of the counter are all 9 then the CO3 output becomes LOW. It remains LOW until the next LOW to HIGH transition of the count input, i.e. until the contents of the first three decades are zero. CO3 is LOW when the contents of the counter are 00 999, 01 999, 02 999 etc. Notes 1. H = HIGH state (the more positive voltage) 2. L = LOW state (the less positive voltage) 3. X = state is immaterial 4. When D5 is selected, the contents of D5 is available at O0 and O1, O2 and O3 are LOW. Carry output CO4 5. LSD = least significant divider When the contents of the first four decades of the counter are all 9 then the CO4 output becomes LOW. It remains LOW until the next LOW to HIGH transition of the count input, i.e. until the contents of the first four decades are zero. CO4 is LOW when the contents of the counter are 09 999 and 19 999. 6. MSD = most significant divider The carry signals CO2 , CO3 and CO4 are suppressed while the preset is active. A HIGH to the preset input sets the counter to 19 999 but the carry signals remain HIGH until preset input returns to LOW, then the carry outputs will also become LOW. Carry output CO5 When the content of the counter is 10 000 the CO5 output becomes LOW. It returns to HIGH when the content of the counter is zero. Digit outputs (O0 to O3) The digit outputs give the contents of the selected latch. The output is in the form of BCD, positive logic. January 1995 4 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... Philips Semiconductors Quadruple static decade counters January 1995 5 Product specification HEF4737B HEF4737V Fig.3 Timing diagram. Philips Semiconductors Product specification HEF4737B HEF4737V Quadruple static decade counters The values given at VDD = 15 V in the following d.c. and a.c. characteristics, are not applicable to the HEF4737V, because of its reduced supply voltage range. DC CHARACTERISTICS VSS = 0 V Tamb (°C) VDD V VOH V VOL V −40 SYMBOL + 25 + 85 MIN. MAX. MIN. MAX. MIN. MAX. − − − 0,3 − 1 Input leakage current at VI = 0 or VDD Output (sink) current LOW 10 ± IIN 15 4,75 0,4 10 0,5 15 IOL 5 4,6 current HIGH 10 9,5 15 13,5 5 2,5 − − − 0,3 − 1 µA 1,6 − 1,6 − 1,4 − mA 2,5 − 2,3 − 1,7 − mA 7,0 − 6,0 − 4,0 − mA 0,96 − 0,80 − 0,65 − mA 2,4 − 2,0 − 1,6 − mA 7,0 − 6,0 − 4,5 − mA 3,0 − 2,5 − 2,0 − mA − 1,6 − 1,6 − 12 µA − 1,6 − 1,6 − 12 µA 1,5 Output (source) µA −IOH Output (source) current HIGH −IOH 3-state output leakage current 10 VO = 0 or VDD 15 ± IOZ AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 15 pF; input transition times ≤ 20 ns VDD V SYMBOL MIN. TYPICAL EXTRAPOLATION FORMULA TYP. MAX. Propagation delays CP → On (D1 selected) HIGH to LOW LOW to HIGH CP → On (D5 selected) HIGH to LOW LOW to HIGH 5 640 ns 308 ns + (0,24 ns/pF) CL 120 240 ns 125 ns + (0,10 ns/pF) CL 15 90 180 ns 86 ns + (0,07 ns/pF) CL 5 320 640 ns 296 ns + (0,48 ns/pF) CL 10 tPHL 120 240 ns 110 ns + (0,20 ns/pF) CL 15 90 180 ns 82 ns + (0,15 ns/pF) CL 5 620 1240 ns 608 ns + (0,24 ns/pF) CL 10 tPLH 330 660 ns 325 ns + (0,10 ns/pF) CL 15 250 500 ns 246 ns + (0,07 ns/pF) CL 5 620 1240 ns 596 ns + (0,48 ns/pF) CL 330 660 ns 320 ns + (0,20 ns/pF) CL 250 500 ns 242 ns + (0,15 ns/pF) CL 10 10 tPHL tPLH 15 January 1995 320 6 Philips Semiconductors Product specification HEF4737B HEF4737V Quadruple static decade counters VDD V CP → CO2 HIGH to LOW LOW to HIGH SYMBOL MIN. 5 TYPICAL EXTRAPOLATION FORMULA TYP. MAX. 220 440 ns 208 ns + (0,24 ns/pF) CL 110 220 ns 105 ns + (0,10 ns/pF) CL 15 85 170 ns 81 ns + (0,07 ns/pF) CL 5 220 400 ns 196 ns + (0,48 ns/pF) CL 10 tPHL 110 220 ns 100 ns + (0,20 ns/pF) CL 15 85 170 ns 77 ns + (0,15 ns/pF) CL 5 350 700 ns 338 ns + (0,24 ns/pF) CL 10 tPLH Propagation delays CP → CO5 HIGH to LOW LOW to HIGH Sn → On HIGH to LOW LOW to HIGH T→ On HIGH to LOW LOW to HIGH MR → On HIGH to LOW PL → On LOW to HIGH MR → COn LOW to HIGH PL → COn HIGH to LOW 160 320 ns 155 ns + (0,10 ns/pF) CL 15 120 240 ns 116 ns + (0,07 ns/pF) CL 5 350 700 ns 326 ns + (0,48 ns/pF) CL 10 tPHL 160 320 ns 150 ns + (0,20 ns/pF) CL 15 120 240 ns 112 ns + (0,15 ns/pF) CL 5 200 400 ns 188 ns + (0,24 ns/pF) CL 10 tPLH 80 160 ns 75 ns + (0,10 ns/pF) CL 15 55 110 ns 51 ns + (0,07 ns/pF) CL 5 200 400 ns 176 ns + (0,48 ns/pF) CL 10 tPHL 80 160 ns 70 ns + (0,20 ns/pF) CL 15 55 110 ns 47 ns + (0,15 ns/pF) CL 5 220 440 ns 208 ns + (0,24 ns/pF) CL 10 tPLH 90 180 ns 85 ns + (0,10 ns/pF) CL 15 60 120 ns 56 ns + (0,07 ns/pF) CL 5 220 440 ns 196 ns + (0,48 ns/pF) CL 90 180 ns 80 ns + (0,20 ns/pF) CL 10 10 tPHL tPLH 15 60 120 ns 52 ns + (0,15 ns/pF) CL 5 490 980 ns 478 ns + (0,24 ns/pF) CL 200 400 ns 195 ns + (0,10 ns/pF) CL 10 tPHL 15 60 120 ns 56 ns + (0,07 ns/pF) CL 5 260 520 ns 236 ns + (0,48 ns/pF) CL 110 220 ns 100 ns + (0,20 ns/pF) CL 10 tPLH 15 85 170 ns 77 ns + (0,15 ns/pF) CL 5 350 700 ns 326 ns + (0,48 ns/pF) CL 160 320 ns 150 ns + (0,20 ns/pF) CL 10 tPLH 15 120 240 ns 112 ns + (0,15 ns/pF) CL 5 350 700 ns 338 ns + (0,24 ns/pF) CL 160 320 ns 155 ns + (0,10 ns/pF) CL 120 240 ns 116 ns + (0,07 ns/pF) CL 10 tPHL 15 January 1995 7 Philips Semiconductors Product specification HEF4737B HEF4737V Quadruple static decade counters VDD V Output transition SYMBOL MIN. TYPICAL EXTRAPOLATION FORMULA TYP. MAX. 5 35 70 ns 15 ns + (0,40 ns/pF) CL times; any output 10 18 36 ns 9 ns + (0,18 ns/pF) CL HIGH to LOW 15 15 30 ns 8 ns + (0,13 ns/pF) CL 5 50 100 ns 15 ns + (0,70 ns/pF) CL 30 60 ns 13 ns + (0,33 ns/pF) CL 25 50 ns 13 ns + (0,23 ns/pF) CL LOW to HIGH 10 tTHL tTLH 15 3-state propagation delays Output disable times EO → On HIGH 5 60 120 ns 35 70 ns 25 50 ns 60 120 ns 35 70 ns 15 25 50 ns 5 90 180 ns 40 80 ns 10 tPHZ 15 5 LOW 10 tPLZ Output enable times EO → On HIGH LOW 10 tPZH 15 30 60 ns 5 90 180 ns 40 80 ns 30 60 ns 10 tPZL 15 Maximum CP pulse width; LOW 5 10 tWCPL 15 Minimum MR pulse width; HIGH 5 10 tWMRH 15 Minimum PL pulse width; HIGH 5 10 tWPLH 15 Minimum T pulse 5 width; HIGH 10 tWTH 15 Maximum clock pulse frequency 80 ns 60 30 ns 50 25 ns 100 50 ns 50 25 ns 40 20 ns 120 60 ns 60 30 ns 50 25 ns 100 50 ns 40 20 ns 36 18 ns 5 10 15 January 1995 160 3 6 MHz 8 16 MHz 10 20 MHz fmax 8 Philips Semiconductors Product specification HEF4737B HEF4737V Quadruple static decade counters VDD V Dynamic power dissipation per package (P) 5 TYPICAL FORMULA FOR P (µW) 950 fi + ∑ (foCL) × VDD2 10 4 200 fi + ∑ (foCL) × VDD 15 11 200 fi + ∑ (foCL) × VDD 2 2 where fi = input freq. (MHz) fo = output freq. (MHz) CL = load cap. (pF) ∑ (foCL) = sum of outputs VDD = supply voltage (V) January 1995 9