BUF20820 SBOS330C − DECEMBER 2005 − REVISED OCTOBER 2006 18-Channel GAMMA VOLTAGE GENERATOR with Two Programmable VCOM Channels FEATURES APPLICATIONS D REPLACES RESISTOR-BASED GAMMA D 18-CHANNEL GAMMA CORRECTION D 2-CHANNEL PROGRAMMABLE VCOM: D D 100mA IOUT D D D D D D D ON-CHIP OTP MEMORY 10-BIT RESOLUTION DESCRIPTION RAIL-TO-RAIL OUTPUT The BUF20820 is a programmable voltage reference generator designed for gamma correction in TFT-LCD panels. It provides 18 programmable outputs for gamma correction and two channels for VCOM adjustment, each with 10-bit resolution. It offers on-chip One-Time Programmable (OTP) memory that allows the user to store the gamma voltages on-chip. This eliminates the need for an external EEPROM. LOW SUPPLY CURRENT: 900µA/ch SUPPLY VOLTAGE: 7V to 18V DIGITAL SUPPLY: 2.0V to 5.5V INDUSTRY-STANDARD, TWO-WIRE INTERFACE: 3.4MHz HIGH-SPEED MODE D HIGH ESD RATING: 4kV HBM, 1kV CDM, 200V MM This programmability replaces the traditional, timeconsuming process of changing resistor values to optimize the various gamma voltages and allows designers to determine the correct gamma voltages for a panel very quickly. Required voltage changes can also be easily implemented without hardware changes. D DEMO BOARD AND SOFTWARE AVAILABLE 2V−5.5V 7V−18V Digital Analog REFH BUF20820 REFH OUT OUT 1 … DAC Registers 2 DAC Registers 1 … … OTP Memory Program Command The BUF20820 uses TI’s latest, small-geometry analog CMOS process, which makes it a very competitive choice for full production, not just evaluation. Programming of each output occurs through an industrystandard, two-wire serial interface. Unlike existing programmable buffers, the BUF20820 offers a high-speed mode that allows clock speeds up to 3.4MHz. OUT 2 18 Output Channels plus Two VCOM Channels For lower or higher channel count, please contact your local sales or marketing representative. OUT 17 The BUF20820 is available in an HTSSOP-38 PowerPAD package. It is specified from −40°C to +85°C. OUT 18 BUF20820 RELATED PRODUCTS VCOM OUT1 VCOM OUT2 REFL OUT SDA Control IF SCL LD SOLUTIONS TFT-LCD REFERENCE DRIVERS DYNAMIC GAMMA CONTROL AO REFL FEATURES PRODUCT 18-Channel Programmable, Two VCOM 12-Channel Programmable Buffer, 10-Bit Programmable VCOM with Memory 10-Channel Gamma Correction Buffer, Int VCOM, 18V Operating Supply Voltage High-Speed VCOM, 1 and 2 Channels Complete LCD DC/DC Solution BUF20800 BUF12800 BUF01900 BUF11704 SN10501 TPS651xx Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a registered trademark of Texas Instruments. All other trademarks are the property of their respective owners. Copyright 2005−2006, Texas Instruments Incorporated ! ! www.ti.com "#$%&$% www.ti.com SBOS330C − DECEMBER 2005 − REVISED OCTOBER 2006 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ABSOLUTE MAXIMUM RATINGS(1) Supply Voltage, VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +19V Supply Voltage, VSD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6V Signal Input Terminals, SCL, SDA, AO, LD: Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5V to +6V Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10mA Output Short Circuit(2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to +95°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C ESD Rating: Human Body Model (HBM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4kV Charged-Device Model (CDM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1kV Machine Model (MM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200V (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not supported. (2) Short-circuit to ground. ORDERING INFORMATION(1) PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR BUF20820 HTSSOP-38 DCP PACKAGE MARKING BUF20820 (1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. 2 "#$%&$% www.ti.com SBOS330C − DECEMBER 2005 − REVISED OCTOBER 2006 ELECTRICAL CHARACTERISTICS Boldface limits apply over the specified temperature range, TA = −40°C to +85°C. At TA = +25°C, VS = 18V, VSD = 5V, VREFH = 17V, VREFL = 1V, RL = 1.5kΩ connected to ground, and CL = 200pF, unless otherwise noted. BUF20820 PARAMETER ANALOG Gamma Output Swing—High Gamma Output Swing—Low VCOM Buffer Output Swing—High VCOM Buffer Output Swing—Low Output Current REFH Input Range(1) REFL Input Range(1) Integral Nonlinearity Differential Nonlinearity Gain Error Program to Out Delay Output Accuracy over Temperature Input Resistance at VREFH and VREFL Load Regulation, All References 40mA, All Channels ANALOG POWER SUPPLY Operating Range(2) Total Analog Supply Current over Temperature DIGITAL Logic 1 Input Voltage Logic 0 Input Voltage Logic 0 Output Voltage Input Leakage Clock Frequency DIGITAL POWER SUPPLY Operating Voltage Range Digital Supply Current(3) over Temperature TEMPERATURE Specified Temperature Range Operating Temperature Range Storage Temperature Range Thermal Resistance, HTSSOP-38 Junction-to-Ambient Junction-to-Case INL DNL CONDITIONS MIN OUT1−9, REFH OUT, Sourcing 10mA, VREFH = 17.8V, Code 1023 OUT10−18, REFL OUT, Sourcing 10mA, VREFH = 17.8V, Code 1023 OUT1−9, REFH OUT, Sinking 10mA, VREFL = 0.2V, Code 00 OUT10−18, REFL OUT, Sinking 10mA, VREFL = 0.2V, Code 00 VCOM, Sourcing 100mA, VREFH = 17.8V VCOM, Sinking 100mA, VREFL = 0.2V 17.7 17.0 No Load, VREFH = 17V, VREFL = 1V No Load, VREFH = 17V, VREFL = 1V tD No Load, VREFH = 17V, VREFL = 1V RINH REG VS IS VIH VIL VOL fCLK VSD ISD VOUT = VS/2, IOUT = +5mA to −5mA Step VOUT = VS/2, ISINKING = 40mA, ISOURCING = 40mA TYP MAX 17.8 V 17.2 V 0.6 1.0 V 0.2 0.3 V 13 15.5 V 1 2.0 V See Typical Characteristics Curve 4 VS V GND VS − 4 V 0.3 1.5 Bits 0.3 1 Bits 0.12 % 5 µs ±20 ±50 mV ±25 mV 100 MΩ 0.5 1.5 mV/mA 0.5 1.5 mV/mA 7 No Load 18 18 28 28 V mA mA 0.15 ±0.01 0.3 × VSD 0.4 ±10 400 3.4 V V V µA kHz MHz 0.7 × VSD ISINK = 3mA Standard/Fast Mode High-Speed Mode 2.0 No-Load, Two-Wire Bus Inactive Junction Temperature < 125°C qJA qJC UNIT 25 100 −40 −40 −65 30 15 5.5 50 V µA µA +85 +95 +150 °C °C °C °C/W °C/W (1) See Applications Information section REFH and REFL Input Range. (2) Minimum analog supply voltage is 8.5V when programming OTP memory. (3) See typical characteristic curve, Digital Supply Current vs Two-Wire Bus Activity. 3 "#$%&$% www.ti.com SBOS330C − DECEMBER 2005 − REVISED OCTOBER 2006 PIN CONFIGURATIONS Top View HTSSOP VCOM OUT 2 1 38 VCOM OUT 1 REFH 2 37 REFL NC(1) 3 36 NC (1) NC(1) 4 35 NC (1) OUT1 5 34 REFL OUT OUT2 6 33 OUT18 OUT3 7 32 OUT17 OUT4 8 31 OUT16 30 OUT15 29 OUT14 28 GNDA(2) PowerPAD Lead−Frame Die Pad Exposed on Underside OUT5 9 OUT6 10 (2) 11 VS 12 27 VS OUT7 13 26 OUT13 OUT8 14 25 OUT12 OUT9 15 24 OUT11 REFH OUT 16 23 OUT10 VSD 17 22 GNDD(2) SCL 18 21 LD SDA 19 20 AO GNDA (1) NC denotes no connection. (2) GNDD and GNDA are internally connected and must be at the same voltage potential. 4 "#$%&$% www.ti.com SBOS330C − DECEMBER 2005 − REVISED OCTOBER 2006 TYPICAL CHARACTERISTICS At TA = +25°C, VS = 18V, VSD = 5V, VREFH = 17V, VREFL = 1V, RL = 1.5kΩ connected to ground, and CL = 200pF, unless otherwise noted. ANALOG SUPPLY CURRENT vs TEMPERATURE DIGITAL SUPPLY CURRENT vs TEMPERATURE 30 10 VS = 10V Digital Supply Current (µA) Analog Supply Current (mA) VS = 18V 8 VS = 10V 6 4 2 25 VSD = 5V 20 15 VSD = 3.3V 10 5 0 0 −40 −20 0 20 40 60 80 −40 100 −20 0 Temperature (_ C) 20 40 60 80 100 Temperature (_ C) Figure 1 Figure 2 OUTPUT VOLTAGE vs OUTPUT CURRENT FULL−SCALE OUTPUT SWING 18 17 Output Voltage (V) Output Voltage (5V/div) REFH = 17V REFL = 1V Code 3FF →000 Code 000 →3FF 16 OUT10−18 (sourcing), Code = 3FFh 15 VREFL = 0.2V, VREFH = 17V RLOAD Connected to GND OUT1−9, VCOM1−2 (sourcing) Code = 3FFh VREFL = 1V, VREFH = 17.8V 3 OUT1−9, VCOM1−2 (sinking) 2 Code = 000h VREFL = 1V, VREFH = 17.8V RLOAD Connected to GND OUT10−18 (sinking), Code = 000h VREFL = 0.2V, VREFH = 17V RLOAD Connected to 18V RLOAD Connected to 18V 1 0 Time (1µs/div) 0 10 20 30 40 50 60 70 80 90 100 Output Current (mA) Figure 3 Figure 4 DIFFERENTIAL NONLINEARITY ERROR vs INPUT CODE 0.6 0.4 0.4 DNL Error (LSB) INL Error (LSB) INTEGRAL NONLINEARITY ERROR vs INPUT CODE 0.6 0.2 0 −0.2 0.2 0 −0.2 −0.4 −0.4 −0.6 −0.6 0 200 400 600 Input Code Figure 5 800 1000 0 200 400 600 800 1000 Input Code Figure 6 5 "#$%&$% www.ti.com SBOS330C − DECEMBER 2005 − REVISED OCTOBER 2006 APPLICATIONS INFORMATION The BUF20820 programmable voltage reference allows fast and easy adjustment of 18 programmable reference outputs and two channels for VCOM adjustment, each with 10-bit resolution. It allows very simple, time-efficient adjustment of the gamma reference and VCOM voltages. The BUF20820 is programmed through a high-speed, standard, two-wire interface. The BUF20820 features a double-register structure for each DAC channel to simplify the implementation of dynamic gamma control. This design allows pre-loading of register data and rapid updating of all channels simultaneously. Buffers 1−9 are able to swing to within 200mV of the positive supply rail, and to within 0.6V of the negative supply rail. Buffers 10−18 are able to swing to within 0.8V of the positive supply rail and to within 200mV of the negative supply rail. The BUF20820 can be powered using an analog supply voltage from 7V to 18V, and a digital supply from 2V to 5.5V. The digital supply must be applied prior to or simultaneously with the analog supply to avoid excessive current and power consumption; damage to the device may occur if it is left connected only to the analog supply for extended periods of time. Figure 7 shows the power supply timing requirements. GND D VS Analog Supply: Data transfer is then initiated and eight bits of data are sent followed by an Acknowledge Bit. During data transfer, SDA must remain stable while SCL is HIGH. Any change in SDA while SCL is HIGH will be interpreted as a START or STOP condition. Once all data has been transferred, the master generates a STOP condition indicated by pulling SDA from LOW to HIGH while SCL is HIGH. The BUF20820 can act only as a slave device; therefore, it never drives SCL. SCL is only an input for the BUF20820. Table 1 and Table 2 summarize the address and command codes, respectively, for the BUF20820. ADDRESSING THE BUF20820 The address of the BUF20820 is 111010x, where x is the state of the A0 pin. When the A0 pin is LOW, the device will acknowledge on address 74h (1110100). If the A0 pin is HIGH, the device will acknowledge on address 75h (1110101). VSD Digital Supply: To address a specific device, the master initiates a START condition by pulling the data signal line (SDA) from a HIGH to a LOW logic level while SCL is HIGH. All slaves on the bus shift in the slave address byte, with the last bit indicating whether a read or write operation is intended. During the 9th clock pulse, the slave being addressed responds to the master by generating an Acknowledge and pulling SDA LOW. GND t1 Other valid addresses are possible through a simple mask change. Contact your TI representative for information. t1: 0s minimum delay between Digital Supply and Analog Supply. Figure 7. Power Supply Timing Requirements Figure 8 shows the BUF20820 in a typical configuration. In this configuration, the BUF20820 device address is 74h. The output of each digital-to-analog converter (DAC) is immediately updated as soon as data is received in the corresponding register (LD = 0). For maximum dynamic range, set VREFH = VS − 0.2V and VREFL = GND + 0.2V. TWO-WIRE BUS OVERVIEW The BUF20820 communicates through an industrystandard, two-wire interface to receive data in slave mode. This standard uses a two-wire, open-drain interface that supports multiple devices on a single bus. Bus lines are driven to a logic low level only. The device that initiates the communication is called a master, and the devices controlled by the master are slaves. The master generates the serial clock on the clock signal line (SCL), controls the bus access, and generates the START and STOP conditions. 6 Table 1. Quick-Reference Table of BUF20820 Addresses DEVICE/COMPONENT ADDRESS BUF20820 Address: A0 pin is LOW (device will acknowledge on address 74h) 1110100 A0 pin is HIGH (device will acknowledge on address 75h) 1110101 Table 2. Quick-Reference Table of Command Codes COMMAND CODE General Call Reset Address byte of 00h followed by a data byte of 06h. High-Speed Mode 00001xxx, with SCL ≤ 400kHz; where xxx are bits unique to the Hs-capable master. This byte is called the Hs master code. "#$%&$% www.ti.com SBOS330C − DECEMBER 2005 − REVISED OCTOBER 2006 BUF20820 (1) VCOM 1 1 VC OM OUT2 VS 2 REFH 3 (1) VCOM OU T1 38 V CO M2 REFL 37 VS NC NC 36 4 NC NC 35 5 OUT1 REFL OUT 34 6 OUT2 OUT18 33 7 OUT3 OUT17 32 8 OUT4 OUT16 31 9 OUT5 OUT15 30 10 OUT6 OUT14 29 11 GNDA (2) GNDA (2) 28 12 VS VS 27 (1) (1) (1) (1) Source Driver (1) (1) (1) VS 100nF 10µF (1) (1) (1) (1) VS 100nF (1) Source Driver Source Driver 10µF (1) 13 OUT7 OUT13 26 14 OUT8 OUT12 25 (1) (1) Source Driver (1) (1) 15 OUT9 OUT11 24 16 REFH OUT OUT10 23 17 VSD GND D(2) 22 18 SCL LD 21 19 SDA AO 20 (1) 3.3V 100nF 1µF Timing Controller Figure 8. Typical Application Configuration 7 "#$%&$% www.ti.com SBOS330C − DECEMBER 2005 − REVISED OCTOBER 2006 DATA RATES OUTPUT VOLTAGE The two-wire bus operates in one of three speed modes: Buffer output values are determined by the reference voltages (VREFH and VREFL) and the decimal value of the binary input code used to program that buffer. The value is calculated using Equation 1: D D D Standard: allows a clock frequency of up to 100kHz; Fast: allows a clock frequency of up to 400kHz; and High-speed mode (or Hs mode): allows a clock frequency of up to 3.4MHz. The BUF20820 is fully compatible with all three modes. No special action is required to use the device in Standard or Fast modes, but High-speed mode must be activated. To activate High-speed mode, send a special address byte of 00001xxx, with SCL = 400kHz, following the START condition; xxx are bits unique to the Hs-capable master, which can be any value. This byte is called the Hs master code. (Note that this is different from normal address bytes—the low bit does not indicate read/write status.) The BUF20820 will respond to the High-speed command regardless of the value of these last three bits. The BUF20820 will not acknowledge this byte; the communication protocol prohibits acknowledgement of the Hs master code. On receiving a master code, the BUF20820 will switch on its Hs mode filters, and communicate at up to 3.4MHz. Additional high-speed transfers may be initiated without resending the Hs mode byte by generating a repeat START without a STOP. The BUF20820 will switch out of Hs mode with the next STOP condition. GENERAL CALL RESET AND POWER-UP The BUF20820 responds to a General Call Reset, which is an address byte of 00h (0000 0000) followed by a data byte of 06h (0000 0110). The BUF20820 acknowledges both bytes. Upon receiving a General Call Reset, the BUF20820 performs a full internal reset, as though it had been powered off and then on. It always acknowledges the General Call address byte of 00h (0000 0000), but does not acknowledge any General Call data bytes other than 06h (0000 0110). VOUT + ƪ VREFH * VREFL 1024 ƫ Decimal Value of Code ) VREFL (1) The valid voltage ranges for the reference voltages are: 4V v V REFH v VS * 0.2V and 0.2V v VREFL v VS * 4V (2) The BUF20820 outputs are capable of a full-scale voltage output change in typically 5µs—no intermediate steps are required. OUTPUT LATCH Updating the DAC register is not the same as updating the DAC output voltage, because the BUF20820 features a double-buffered register structure. There are three methods for latching transferred data from the storage registers into the DACs to update the DAC output voltages. Method 1 requires externally setting the latch pin (LD) LOW, LD = LOW, which will update each DAC output voltage whenever its corresponding register is updated. Method 2 externally sets LD = HIGH to allow all DAC output voltages to retain their values during data transfer and until LD = LOW, which will then simultaneously update the output voltages of all DACs to the new register values. Use this method to transfer a future data set in advance to prepare for a very fast output voltage update. The BUF20820 automatically performs a reset upon power-up. As part of the reset, the BUF20820 is configured for all outputs to change to the programmed OTP memory values, or (VREFH − VREFL)/2 if the OTP values have not been programmed. Method 3 uses software control. LD is maintained HIGH, and all DACs are updated when the master writes a 1 in bit 15 and a 0 in bit 14 of any DAC register. The update will occur after receiving the 16-bit data for the currently-written register. The BUF20820 resets all outputs to the OTP memory values (or to (VREFH − VREFL)/2 if the OTP values have not been programmed) when the device address is sent, followed by a valid DAC address with bits D7 to D5 set to ‘100’. If these bits are set to ‘010’, only the DAC being addressed will be reset. The General Call Reset and the power-up reset will update the DAC regardless of the state of the latch pin. 8 "#$%&$% www.ti.com SBOS330C − DECEMBER 2005 − REVISED OCTOBER 2006 ACQUIRE OF OTP MEMORY A general acquire command will update all registers and DAC outputs to the values stored in OTP memory. DAC addresses 00000 to 10100 are valid and will be acknowledged. Table 3 shows the valid addresses. 4. Send a STOP condition on the bus. A single channel acquire command will update only the register and DAC output of the DAC corresponding to the DAC address used in the command. See Figure 9 for the timing diagrams for the acquire commands. General Acquire Command READ/WRITE OPERATIONS 1. Send a START condition on the bus. Single or multiple read and write operations can be done in a single communication transaction. Writing to a DAC register differs from writing to the OTP memory. Bits D15−D14 of the most significant byte of data will determine if data will be written to the DAC register or the OTP memory. See Figure 10 through Figure 12 for the timing diagrams and timing requirements for the read/write commands. 2. Send the device address and read/write bit = LOW. The BUF20820 will acknowledge this byte. 3. Send a DAC address byte. Bits D7−D5 must be set to 100. Bits D4−D0 are any valid DAC address. Only addresses 00000 to 10100 are valid and will be acknowledged. Table 3 shows the valid addresses. 4. Send a STOP condition on the bus. Following this command, all DAC registers and DAC outputs will change to the OTP memory values. Table 3. DAC Addresses DAC ADDRESS DAC_1 DAC_2 DAC_3 DAC_4 DAC_5 DAC_6 DAC_7 DAC_8 DAC_9 DAC_10 DAC_11 DAC_12 DAC_13 DAC_14 DAC_15 DAC_16 DAC_17 DAC_18 0 0000 0 0001 0 0010 0 0011 0 0100 0 0101 0 0110 0 0111 0 1000 0 1001 0 1010 0 1011 0 1100 0 1101 0 1110 0 1111 1 0000 1 0001 1 0010 1 0011 1 0100 VCOM OUT1 VCOM OUT2 Write Disable Bit Single Channel Acquire Command 1. Send a START condition on the bus. 2. Send the device address and read/write bit = LOW. The BUF20820 will acknowledge this byte. 3. Send a DAC address byte using the DAC address corresponding to the DAC output and register to update with the OTP memory value. Bits D7−D5 must be set to 010. Bits D4−D0 are the DAC address. Only Read/Write: DAC register The BUF20820 is able to read from a single DAC, or multiple DACs, or write to the register of a single DAC, or multiple DACs in a single communication transaction. DAC addresses begin with 00000, which corresponds to DAC_1, through 10011, which corresponds to VCOM OUT2. Write commands are performed by setting the read/write bit LOW. Setting the read/write bit HIGH will perform a read transaction. Writing: To write to a single DAC register: 1. Send a START condition on the bus. 2. Send the device address and read/write bit = LOW. The BUF20820 will acknowledge this byte. 3. Send a DAC or write disable bit address byte. Bits D7−D5 must be set to 0. Bits D4−D0 are the DAC address. Only addresses 00000 to 10100 are valid and will be acknowledged. Table 3 shows valid addresses. 4. Send two bytes of data for the specified DAC register. Begin by sending the most significant byte first (bits D15−D8, of which only bits D9 and D8 are used, and bits D15−D14 must not be 01), followed by the least significant byte (bits D7−D0). For address 10100, only D0 has meaning. This bit is the write disable bit. The register is updated after receiving the second byte. 5. Send a STOP condition on the bus. The BUF20820 will acknowledge each data byte. If the master terminates communication early by sending a STOP or START condition on the bus, the specified register will not be updated. Updating the DAC register is not the same as updating the DAC output voltage. See the Output Latch section. The process of updating multiple DAC registers begins the same as when updating a single register. However, instead of sending a STOP condition after writing the 9 "#$%&$% www.ti.com SBOS330C − DECEMBER 2005 − REVISED OCTOBER 2006 addressed register, the master continues to send data for the next register. The BUF20820 automatically and sequentially steps through subsequent registers as additional data is sent. The process continues until all desired registers have been updated or a STOP condition is sent. 5. Send correct device address and read/write bit = HIGH. The BUF20820 will acknowledge this byte. 6. Receive two bytes of data. They are for the specified DAC. The first received byte is the most significant byte (bits D15−D8, only bits D9 and D8 have meaning), the next byte is the least significant byte (bits D7−D0). 7. Acknowledge after receiving the first byte. 8. Do not acknowledge the second byte to end the read transaction. To write to multiple DAC registers: 1. Send a START condition on the bus. 2. Send the device address and read/write bit = LOW. The BUF20820 will acknowledge this byte. 3. Send either the DAC_1 address byte to start at the first DAC, or send the address byte for whichever DAC will be the first in the sequence of DACs to be updated. The BUF20820 will begin with this DAC and step through subsequent DACs in sequential order. 4. 5. Send the bytes of data; begin by sending the most significant byte (bits D15−D8, of which only bits D9 and D8 have meaning, and bits D15−D14 must not be 01), followed by the least significant byte (bits D7−D0). The first two bytes are for the DAC addressed in step 3 above. Its register is automatically updated after receiving the second byte. The next two bytes are for the following DAC. That DAC register is updated after receiving the fourth byte. This process continues until the registers of all following DACs have been updated. The last address, 10100, is the address of the write disable bit and cannot be accessed using this method. It must be written using the write to a single DAC register procedure. Send a STOP condition on the bus. The BUF20820 will acknowledge each byte. To terminate communication, send a STOP or START condition on the bus. Only DAC registers that have received both bytes of data will be updated. Reading: Communication may be terminated by sending a premature STOP or START condition on the bus, or by not sending the acknowledge. To Read Multiple DACs: 1. Send a START condition on the bus. 2. Send the device address and read/write bit = LOW. The BUF20820 will acknowledge this byte. 3. Send either the DAC_1 address byte to start at the first DAC, or send the address byte for whichever DAC will be the first in the sequence of DACs to be read. The BUF20820 will begin with this DAC and step through subsequent DACs in sequential order. 4. Send a START or STOP/START condition on the bus. 5. Send correct device address and read/write bit = HIGH. The BUF20820 will acknowledge this byte. 6. Receive two bytes of data. They are for the specified DAC. The first received byte is the most significant byte (bits D15−D8, only bits D9 and D8 have meaning), the next byte is the least significant byte (bits D7−D0). 7. Acknowledge after receiving each byte of data except for the last byte. The acknowledge bit of the last byte should be HIGH to end the read operation. 8. When all desired DACs have been read, send a STOP or START condition on the bus. Reading a DAC register will return the data stored in the DAC. This data can differ from the data stored in the DAC register. See the Output Latch section. To read the DAC value: 1. Send a START condition on the bus. 2. Send the device address and read/write bit = LOW. The BUF20820 will acknowledge this byte. 3. Send the DAC address byte. Bits D7−D5 must be set to 0; Bits D4−D0 are the DAC address. Only DAC addresses 00000 to 10100 are valid and will be acknowledged. For address 10100, only D0 has meaning. This bit is the write disable bit. 4. 10 Send a START or STOP/START condition on the bus. Communication may be terminated by sending a premature STOP or START condition on the bus, or by not sending the acknowledge. "#$%&$% www.ti.com SBOS330C − DECEMBER 2005 − REVISED OCTOBER 2006 Write: OTP Memory for the DAC Register The BUF20820 is able to write to the OTP memory of a single DAC, or multiple DACs in a single communication transaction. DAC addresses begin with 00000 (which corresponds to DAC_1) through 10011 (which corresponds to VCOM OUT2). To write to multiple OTP registers: 1. Send a START condition on the bus. 2. Send the device address and read/write bit = LOW. The BUF20820 will acknowledge this byte. 3. Send either the DAC_1 address byte to start at the OTP register of the first DAC, or send the address byte for whichever DAC will be the first in the sequence to be updated. The BUF20820 will begin with the OTP register of this DAC and step through subsequent registers in sequential order. 4. Send the bytes of data; begin by sending the most significant byte (bits D15−D8, of which only bits D9 and D8 have meaning, and bits D15−D14 must be 01), followed by the least significant byte (bits D7−D0). The first two bytes are for the OTP register of the DAC addressed in step 3 above. This OTP register is automatically updated after receiving the second byte. The next two bytes are for the OTP register of the following DAC (bits D15−D14 must again be 01). That DAC OTP register is updated after receiving the fourth byte. This process continues until the registers of all following DAC OTP registers have been updated. The last address, 10100, is the address of the write disable bit and cannot be accessed using this method. It must be written using the write to a single OTP register procedure. 5. Send a STOP condition on the bus. When programming the OTP memory, the analog supply voltage must be between 8.5V and 18V. Write commands are performed by setting the read/write bit LOW. To write to a single OTP register: 1. Send a START condition on the bus. 2. Send the device address and read/write bit = LOW. The BUF20820 will acknowledge this byte. 3. Send a DAC address byte. Bits D7−D5 must be set to 0. Bits D4−D0 are the DAC address. Only DAC addresses 00000 to 10100 are valid and will be acknowledged. See Table 3 for DAC addresses. 4. Send two bytes of data for the OTP register of the specified DAC. Begin by sending the most significant byte first (bits D15−D8, of which only bits D9 and D8 are data bits, and bits D15−D14 must be 01), followed by the least significant byte (bits D7−D0). For address 10100, only D0 has meaning. This bit is the write disable bit. The register is updated after receiving the second byte. 5. Send a STOP condition on the bus. The BUF20820 will acknowledge each data byte. If the master terminates communication early by sending a STOP or START condition on the bus, the specified OTP register will not be updated. Writing an OTP register will also update the DAC register and output voltage. The BUF20820 will acknowledge each byte. To terminate communication, send a STOP or START condition on the bus. Only DAC registers that have received both bytes of data will be programmed. OTP WRITE DISABLE Writing a ‘1’ in bit D0 of register 10100 disables all future writes. The state of this bit can be accessed the same as any other data bit. It is important to set this bit to 1 after the OTP registers have been programmed to prevent accidental changes to the OTP registers. Until bit D0 of register 10100 is set to 1, any OTP register bit can be changed from 0 to 1; however, once a bit is set to a 1, it cannot be set back to 0. 11 12 A3 A3 A2 A2 A1 A1 A0 A0 W W Ackn Ackn D7 D7 A6 A6 Device_out A5 A5 A4 A4 A3 A3 Device Address A2 A2 A1 A1 A0 A0 W W Write Ackn Ackn D7 D7 Ackn SDA_in SCL A4 A4 Write Operation A5 A5 Start A6 Device_out a) General Acquire Single channel acquire command. P4−P0 must specify any valid DAC addess. A6 Ackn SDA_in SCL Write Operation Write Start Device Address General acquire command. P4−P0 must specify any valid DAC addess. D5 D5 P4 P4 P3 P3 P2 P2 D6 D6 D5 D5 P4 P4 P3 P3 P2 P2 DAC address pointer. D7−D5 must be 010. D6 D6 DAC address pointer. D7−D5 must be 100. P1 P1 P1 P1 P0 P0 P0 P0 Ackn Ackn Ackn Ackn Ackn Ackn Stop Stop "#$%&$% SBOS330C − DECEMBER 2005 − REVISED OCTOBER 2006 www.ti.com b) Single-Channel Acquire Figure 9. Timing Diagram for Acquire Operation A3 A3 A2 A2 A0 A1 A1 Write A0 A0 W W A ck n A ck n Ackn A6 A6 Device_out A5 A5 A4 A4 A3 A3 Device Address A2 A2 A1 A1 A0 W W Ackn Ackn D7 D7 D6 D6 D5 D5 P4 P4 P3 P3 D6 D6 D5 D5 P4 P4 P3 P3 P2 P2 P1 P1 P2 P2 P0 P0 DAC address pointer. D7−D5 must be 000. Start DAC address pointer. D7−D5 must be 000. D7 D7 Write Operation Ackn SDA_in SCL A4 A4 Write Write Operation A5 A5 Device Address Start A6 Device_out a. Write Single DAC Write multiple DAC registers. P4−P0 specify start DAC address. A6 SDA_in SCL Start Write single DAC register. P4−P0 specify DAC address. Ackn Ackn Ackn P1 P1 D15 D15 P0 P0 D14 D14 D13 D13 D12 D12 D10 D10 D9 D9 D13 D13 D12 D12 D11 D11 D10 D10 D9 D9 D8 D8 Ackn Ackn Ackn D7 D7 D8 D8 A ck n A ck n D7 D7 D14 D15 D13 D13 D12 D12 D11 D11 D10 D10 D9 D9 D6 D6 D8 D8 D4 D4 Ackn Ackn Ackn D5 D5 D7 D7 D3 D3 D6 D1 D1 D4 D4 D0 D0 D3 D3 DAC LSbyte D5 D5 D4 D0 D0 A c kn A c kn Stop Ackn Ackn D3 D3 D1 D1 D0 D0 D14 D14 Ackn Ackn Ackn D13 D13 The whole DAC register D9−D0 is updated in this moment. D2 D2 D15 D15 Stop Ackn DAC (pointer + 1) MSbyte. D14 must be 0. DAC 20 LSbyte D4 D1 D1 Ackn The whole DAC register D9−D0 is updated in this moment. D2 D2 The whole DAC register D9−D0 is updated in this moment. D2 D2 D5 D5 D6 DAC (pointer) LSbyte D6 D6 If D15 = 0, the DACs are uploaded on the Latch pin. If D15 = 1, all the DACs are updated when the current DAC register is updated. D14 D15 DAC 20 (VCOM OUT2) MSbyte. D14 must be 0. If D15 = 0, the DACs are updated on the Latch pin. If D15 = 1, all DACs are updated when the current DAC register is updated. D14 D11 D11 Ackn If D15 = 0, the DACs are updated on the Latch pin. If D15 = 1, all DACs are updated when the current DAC register is updated. D15 D15 DAC MSbyte. D14 must be 0. DAC (pointer) MSbyte. D14 must be 0. D14 A ck n A ck n Ackn "#$%&$% www.ti.com SBOS330C − DECEMBER 2005 − REVISED OCTOBER 2006 b. Write Multiple DACs Figure 10. Timing Diagram for Write DAC Register 13 14 Device_out A2 A2 A1 A1 A0 A0 W W Ackn Ackn Write D7 D7 D6 D6 D5 D5 P4 P4 A5 A5 A6 A6 A4 A4 A3 A3 Device Address A2 A2 A1 A1 A0 A0 W W Ackn Ackn D7 D7 Ackn A3 A3 P2 P2 P1 P1 P0 P0 Ackn Ackn Ackn Start D6 D6 D5 D5 P4 P4 P3 P3 P2 P2 P1 P1 Start DAC address pointer. D7−D5 must be 000. P3 P3 DAC address pointer. D7−D5 must be 000. Read Operation A4 A4 Read Operation Ackn Start A5 A6 Write Read multiple DAC registers. P4−P0 specify start DAC address. A5 A6 Read single DAC register. P4−P0 specify DAC address. Start Device Address a. Read Single DAC SDA_in SCL Device_out SDA_in SCL A6 A6 P0 P0 A5 A5 Ackn Ackn Ackn A4 A4 A3 A3 Device Address Start A2 A2 A5 A5 A0 A0 Ackn Ackn D15 D15 A4 A4 A3 A3 Device Address R R Ackn A2 A2 D14 D14 A1 A1 D13 D13 A0 A0 D12 D12 Figure 11. Timing Diagram for Read DAC Register D14 D14 D15 D15 D13 D13 D12 D12 D11 D11 D10 D10 D9 D9 D8 D8 R R Read D11 D11 D9 D9 Ac kn Ac kn Ackn Ackn Ackn Ackn D10 D10 DACMSbyte. D15−D10 have no meaning. DAC 20 (VCOM OUT2) MSbyte. D15−D10 have no meaning. A6 A6 A1 A1 Read D15 D7 D7 Ackn Ackn D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 DACLSbyte. D2 D2 D6 D6 D14 D14 D5 D5 D13 D13 D11 D11 D4 D4 D3 D3 DAC 20 LSbyte. D12 D12 D2 D2 D10 D10 D1 D1 D9 D9 DAC (pointer) MSbyte. D15−D10 have no meaning. D15 D8 D8 Ackn D1 D1 D0 D0 D8 D8 A c kn No A ck n Ackn Ackn Ackn D0 D0 No Ackn Stop Stop "#$%&$% SBOS330C − DECEMBER 2005 − REVISED OCTOBER 2006 www.ti.com b. Read Multiple DACs Device_out SDA_in SCL Device_out SDA_in SCL a) Write Single OTP Register A2 A1 A1 A0 A0 A0 Write W W Ackn Ackn D7 D7 A5 A5 A6 A6 A4 A4 A3 A3 Device Address A2 A2 A1 A1 A0 W W Ackn Ackn D7 D7 Ackn A3 A2 Start A4 A3 Write Operation A5 A6 A4 Write multiple OTP registers. P4−P0 specify start DAC address. A5 A6 Ackn Write Start Device Address Write Operation Write single OTP register. P4−P0 specify DAC address. D5 D5 P4 P4 P3 P3 P2 P2 D0 D0 D5 D5 P4 P4 P3 P3 P2 P2 Start DAC address pointer. D7−D5 must be 000. D0 D0 DAC address pointer. D7−D5 must be 000. P1 P1 P1 P1 P0 P0 P0 P0 Ackn Ackn Ackn Ackn Ackn Ackn D15 D15 D15 D15 D13 D13 D12 D12 D11 D11 D10 D10 D14 D14 D13 D13 D12 D12 D10 D10 D9 D9 D9 D9 D8 D8 D8 D8 Ackn Ackn Ackn Ackn Ackn Ackn D7 D7 D7 D7 D14 D14 D15 D15 D13 D13 D12 D12 D11 D11 D10 D10 D9 D9 DAC20 (VCOMOUT2) MSbyte. D14−D10 have no meaning. D11 D11 DAC(pointer) MSByte. D15−D14 must be 01. D14 D14 DAC(pointer) MSByte. D15−D14 must be 01. D6 D6 D6 D6 D8 D8 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 t1 Ackn Ackn Ackn t2 Stop D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 Ackn Ackn D15 D15 D14 D14 Ackn Ackn Ackn D7 D7 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 Ackn Ackn D0 Ackn t2 D0 t1 Stop Thewhole DACregister D9−D0 is updated at this moment. t1: > 20µs beforefalling edge of clock. t2: minimum100µs, maximum2ms. D6 D6 DAC (pointer) LSbyte Write SupplyActive Write Signal Active D13 D13 Ackn DAC (pointer +1) MSbyte. D15−D14 must be 01. t2 The OTPregister D9−D0 is updated at this moment. D5 D5 DAC (pointer) LSbyte Write SupplyActive Write Signal Active t1 The OTPregister D9−D0 is updated at this moment. t1: > 20µs before falling edge of clock. t2: minimum100µs, maximum2ms. D5 D5 DAC (pointer) LSbyte Write SupplyActive Write Signal Active "#$%&$% www.ti.com SBOS330C − DECEMBER 2005 − REVISED OCTOBER 2006 b) Write Multiple OTP Registers Figure 12. Timing Diagram for Write OTP Register 15 "#$%&$% www.ti.com SBOS330C − DECEMBER 2005 − REVISED OCTOBER 2006 REPLACEMENT OF TRADITIONAL GAMMA BUFFER Traditional gamma buffers rely on a resistor string (often using expensive 0.1% resistors) to set the gamma voltages. During development, the optimization of these gamma voltages can be time consuming. Programming these gamma voltages with the BUF20820 can significantly reduce the time required for gamma voltage optimization. The final gamma values can be written into the internal OTP memory to replace a traditional gamma buffer solution. Figure 13a shows the traditional resistor string; Figure 13b shows the more efficient alternative method using the BUF20820. The BUF20820 uses the most advanced high-voltage CMOS process available today, which allows it to be competitive with traditional gamma buffers. Programmability offers the following advantages: D D D D D D a) Traditional It shortens development time significantly. It eliminates manufacturing variance between panels. It allows a single panel to be built for multiple customers, with loading of customer-dependent gamma curves during final production. This significantly lowers inventory cost and risk and simplifies inventory management. It allows demonstration of various gamma curves to LCD monitor makers by simply uploading a different set of gamma values. It provides a simple means of adjusting gamma curves during final production improve picture quality and accommodate changes in the panel manufacturing process or end-customer requirements. It decreases cost and space. b) BUF20820 Solution BUFxx704 BUF20820 VCOM OUT1 VCOM VCOM OUT2 Timing Controller OUT1 PC Register SDA SCL OUT2 Gamma References OUT17 OUT18 SDA Control Interface SCL LCD Panel Electronics Figure 13. Replacement of the Traditional Gamma Buffer 16 "#$%&$% www.ti.com SBOS330C − DECEMBER 2005 − REVISED OCTOBER 2006 PROGRAMMABLE VCOM The VCOM channels of the BUF20820 can swing to 2.5V from the positive supply rail while sourcing 100mA, and to 1V above the negative rail while sinking 100mA (see Figure 4, typical characteristic Output Voltage vs Output Current). The gamma and the VCOM values can be permanently stored in the internal OTP memory. The VCOM channels can be programmed independently from the gamma channels. Figure 14 shows the BUF20820 being used for VCOM voltages. BUF20820 VCOM OUT1 VCOM VCOM OUT2 Register OUT1 OUT2 VS and the REFL internal buffer to GND. However, there is a finite limit on how close they can swing before saturating. To avoid saturation of the internal REFH and REFL buffers, the REFH voltage should not be greater than VS −100mV and REFL voltage should not be lower than GND + 100mV. Figure 15 shows the swing capability of the REFH and REFL buffers. The other consideration when trying to maximize the output swing capability of the gamma buffers is the limitation in the swing range of output buffers (OUT1−18, VCOM1, and VCOM2), which depends on the load current. A typical load in the LCD application is 5−10mA. For example, if OUT1 is sourcing 10mA, the swing is typically limited to about VS − 200mV. The same applies to OUT18, which typically limits at GND + 200mV when sinking 10mA. An increase in output swing can only be achieved for much lighter loads. For example, a 3mA load typically allows the swing to be increased to approximately VS − 100mV and GND + 100mV. Connecting REFH directly to VS and REFL directly to GND does not damage the BUF20820. As discussed above however, the output stages of the REFH and REFL buffers will saturate. This condition is not desirable and can result in a small error in the measured output voltages of OUT1−18, VCOM OUT1, and VCOM OUT2. As described above, this method of connecting REFH and REFL does not help to maximize the output swing capability. Gamma References 18 17 OUT18 SDA Control Interface Output Voltage (V) OUT17 16 REFH OUT (sourcing), Code = 3FFh 15 VREFL = 1V, VREFH = 17.8V RLOAD Connected to GND 3 REFL OUT (sinking), Code = 000h VREFL = 0.2V, VREFH = 17V 2 R LOAD Connected to 18V SCL 1 0 0 10 20 30 40 50 60 70 80 90 100 Output Current (mA) Figure 15. Reference Buffer Output Voltage vs Output Current Figure 14. BUF20820 Used for Programmable VCOM REFH AND REFL INPUT RANGE Best performance and output swing range of the BUF20820 are achieved by applying REFH and REFL voltages that are slightly below the power-supply voltages. Most specifications have been tested at REFH = VS − 200mV and REFL = GND + 200mV. The REFH internal buffer is designed to swing very closely to CONFIGURATION FOR 20 GAMMA CHANNELS The VCOM outputs can be used as additional gamma references in order to achieve two additional gamma channels (20 total). The VCOM outputs will behave the same as the OUT1−9 outputs when sourcing or sinking smaller currents (see the Typical Characteristics, Figure 4). The VCOM outputs are better able to swing to the positive rail than to the negative rail. Therefore, it is better to use the VCOM outputs for higher reference voltages; see Figure 16. 17 "#$%&$% www.ti.com SBOS330C − DECEMBER 2005 − REVISED OCTOBER 2006 CONFIGURATION FOR 22 GAMMA CHANNELS In addition to the VCOM outputs, the REFH and REFL OUT outputs can also be used as fixed gamma references. The output voltage will be set by the REFH and REFL input voltages, respectively. Therefore, REFH OUT should be used for the highest voltage gamma reference, and REFL OUT for the lowest voltage gamma reference. A 22-channel solution can be created by using all 18 outputs, the two VCOM outputs, and both REFH/L OUT outputs for gamma references—see Figure 17. However, the REFH and REFL OUT buffers were designed to only drive light loads on the order of 5−10mA. Driving capacitive loads is not recommended with these buffers. In addition, the REFH and REFL buffers must not be allowed to saturate from sourcing/sinking too much current from REFH OUT or REFL OUT. Saturation of the REFH and REFL buffers results in errors in the voltages of OUT1−18 and VCOM OUT1−2. The BUF01900, which is anticipated to be released in Q1 ‘06, can be used to provide a programmable VCOM output. 15V 14.8V 2V−5.5V Digital Analog REFH BUF20820 REFH OUT 14.8V Source Driver VCOM OUT1 GMA 1 VCOM OUT2 GMA 2 DAC Registers 2 DAC Registers 1 Program Command OTP Memory OUT1 OUT2 GMA 3 GMA 4 2 VCOM Channels plus 18 Gamma Channels OUT17 GMA 19 OUT18 GMA 20 REFL OUT 0.2V SDA Control IF SCL LD A0 REFL 15V 0.2V Figure 16. 20-Gamma Channel Solution—2 VCOM Channels Used as Additional Gamma Channels 18 "#$%&$% www.ti.com SBOS330C − DECEMBER 2005 − REVISED OCTOBER 2006 15V 2V−5.5V Reference buffer and VCOM OUT outputs can be used for extra gamma channels. 14.8V Digital Analog (REFH OUT will be a fixed voltage.) REFH BUF20820 Source Driver REFH OUT 17V GMA 1 VCOM OUT1 GMA 2 VCOM OUT2 GMA 3 DAC Registers 2 Program Command OTP Memory DAC Registers 1 OUT 1 GMA 4 OUT 2 GMA 5 2 VCOM Channels plus 18 Output Channels OUT 17 GMA 20 OUT 18 GMA 21 REFL OUT 0.2V SDA GMA 22 Control IF SCL Panel LD A0 REFL Output of reference buffer can be used for an extra fixed gamma channel. 15V 0.2V VCOM 8V−18V 2V−5.5V Digital Analog BIAS BUF01900 Program Command Voltage Regulator 4 x OTP ROM Switch Control 10−Bit DAC VCOM Buffer VCOM OUT SDA SCL Control IF A0 Figure 17. 22-Gamma Channel Solution 19 "#$%&$% www.ti.com SBOS330C − DECEMBER 2005 − REVISED OCTOBER 2006 DYNAMIC GAMMA CONTROL Dynamic gamma control is a technique used to improve the picture quality in LCD TV applications. The brightness in each picture frame is analyzed and the gamma curves are adjusted on a frame-by-frame basis. The gamma curves are typically updated during the short vertical blanking period in the video signal. Figure 18 shows a block diagram using the BUF20820 for dynamic gamma control and VCOM output. while a picture is still being displayed. Because the data is only stored into the first register bank, the DAC output values remain unchanged—the display is unaffected. During the vertical sync period, the DAC outputs (and therefore, the gamma voltages) can be quickly updated either by using an additional control line connected to the LD pin, or through software—writing a ‘1’ in bit 15 of any DAC register. For the details on the operation of the double register input structure, see the Output Latch section. The BUF20820 is ideally suited for rapidly changing the gamma curves because of its unique topology: Example: Update all 18 gamma registers simultaneously via software. D D D double register input structure to the DAC; fast serial interface; Step 1: Check if LD pin is placed in HIGH state. simultaneous updating of all DACs by software. See the Read/Write Operations to write to all registers and the Output Latch sections. Step 2: Write DAC Registers 1−18 with bit 15 always ‘0’. The double register input structure saves programming time by allowing updated DAC values to be pre-loaded into the first register bank. Storage of this data can occur Step 3: Write any DAC register a second time with identical data. Make sure that bit 15 is ‘1’. All DAC channels will be updated simultaneously after receiving the last bit of data. (Note: this step may be eliminated by setting bit 15 of DAC 18 to ‘1’ in the previous step.) Histogram Gamma Adjustment Algorithm Digital Picture Data Black White SDA SCL BUF20820 Gamma References 1 through 18 Timing Controller/µController Source Driver Figure 18. Dynamic Gamma Control 20 Source Driver VCOM "#$%&$% www.ti.com SBOS330C − DECEMBER 2005 − REVISED OCTOBER 2006 TOTAL TI PANEL SOLUTION outputs, and other functions. The BUF20820, with its 20 total programmable DAC channels, provides great flexibility to the entire system by allowing the designer to change all these parameters via software. In addition to the BUF20820 programmable voltage reference, TI offers a complete set of ICs for the LCD panel market, including gamma correction buffers, various power-supply solutions, and audio power solutions. See Figure 19 for the total IC solution from TI. Figure 20 provides various ideas on how the BUF20820 can be used in applications. A micro-controller with two-wire serial interface controls the various DACs of the BUF20820. The BUF20820 can be used for: THE BUF20820 IN INDUSTRIAL APPLICATIONS D D D D D D The wide supply range, high output current, and very low cost make the BUF20820 attractive for a range of medium accuracy industrial applications such as programmable power supplies, multi-channel data acquisition systems, data-loggers, sensor excitation and linearization, power-supply generation, and others. Each DAC channel features 1LSB DNL and INL. sensor excitation programmable bias/reference voltages variable power-supplies high-current voltage output 4-20mA output set-point generators for control loops. NOTE: At power-up, the output voltages of the BUF20820 DACs are configured to the programmed OTP memory values, or (VREFH − VREFL)/2 if the OTP values have not been programmed. Many systems require different levels of biasing and power supply for various components as well as sensor excitation, control-loop set-points, voltage outputs, current VCOM Gamma Correction BUF20820 2.7 V−5 V TPS651xx LCD Supply 15 V 26 V −14 V 3.3 V TPA3005D2 TPA3008D2 Audio Speaker Driver n n Logic and Timing Controller Gate Driver Source Driver High−Resolution TFT−LCS Panel Figure 19. TI LCD Solution 21 "#$%&$% www.ti.com SBOS330C − DECEMBER 2005 − REVISED OCTOBER 2006 +18V Voltage Output High Current Voltage Output 0.3V to 17V +5V BUF2 0 8 2 0 +5V 2V to 16V, 100mA Sensor Excitation/Linearization Control Loop Set Point 4−20mA +5V Bias Voltage Generator 4−20mA Generator +2.5V Bias LED Driver Offset Adjustment INA Ref +4V +4.3V Comparator Threshold Supply Voltage Generator Ref Reference for MDAC +7.5V SDA SCL MDAC µC Figure 20. Industrial Applications for the BUF20820 22 "#$%&$% www.ti.com SBOS330C − DECEMBER 2005 − REVISED OCTOBER 2006 EVALUATION BOARD AND SOFTWARE An evaluation board is available for the BUF20820, as shown in Figure 21. The evaluation board features easy-to-use software that allows individual channel voltages to be set. Configurations can be quickly evaluated to determine optimal codes for a given application. Contact your local TI representative for more information regarding the evaluation board. Figure 21. BUF208x0 Evaluation Board 23 "#$%&$% www.ti.com SBOS330C − DECEMBER 2005 − REVISED OCTOBER 2006 GENERAL POWERPAD DESIGN CONSIDERATIONS The BUF20820 is available in a thermally-enhanced PowerPAD package. This package is constructed using a downset leadframe upon which the die is mounted, as shown in Figure 22(a) and Figure 22(b). This arrangement results in the lead frame being exposed as a thermal pad on the underside of the package; see Figure 22(c). This thermal pad has direct thermal contact with the die; thus, excellent thermal performance is achieved by providing a good thermal path away from the thermal pad. The PowerPAD package allows for both assembly and thermal management in one manufacturing operation. During the surface-mount solder operation (when the leads are being soldered), the thermal pad must be soldered to a copper area underneath the package. Through the use of thermal paths within this copper area, heat can be conducted away from the package into either a ground plane or other heat-dissipating device. Soldering the PowerPAD to the printed circuit board (PCB) is always required, even with applications that have low power dissipation. This provides the necessary thermal and mechanical connection between the lead frame die pad and the PCB. 3. Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area. This helps dissipate the heat generated by the BUF20820 IC. These additional vias may be larger than the 13-mil diameter vias directly under the thermal pad. They can be larger because they are not in the thermal pad area to be soldered; thus, wicking is not a problem. 4. Connect all holes to the internal plane that is at the same voltage potential as the GND pins. 5. When connecting these holes to the internal plane, do not use the typical web or spoke via connection methodology. Web connections have a high thermal resistance connection that is useful for slowing the heat transfer during soldering operations. This makes the soldering of vias that have plane connections easier. In this application, however, low thermal resistance is desired for the most efficient heat transfer. Therefore, the holes under the BUF20820 PowerPAD package should make their connection to the internal plane with a complete connection around the entire circumference of the plated-through hole. 6. The top-side solder mask should leave the terminals of the package and the thermal pad area with its eight holes exposed. The bottom-side solder mask should cover the holes of the thermal pad area. This masking prevents solder from being pulled away from the thermal pad area during the reflow process. 7. Apply solder paste to the exposed thermal pad area and all of the IC terminals. 8. With these preparatory steps in place, the BUF20820 IC is simply placed in position and run through the solder reflow operation as any standard surfacemount component. This preparation results in a properly installed part. The PowerPAD must be connected to the most negative supply voltage on the device, GNDA and GNDD. 1. 2. 24 Prepare the PCB with a top-side etch pattern. There should be etching for the leads as well as etch for the thermal pad. Place recommended holes in the area of the thermal pad. Ideal thermal land size and thermal via patterns (2x5) for the HTSSOP-38 DCP package can be seen in the technical brief, PowerPAD Thermally-Enhanced Package (SLMA002), available for download at www.ti.com. These holes should be 13 mils in diameter. Keep them small, so that solder wicking through the holes is not a problem during reflow. "#$%&$% www.ti.com SBOS330C − DECEMBER 2005 − REVISED OCTOBER 2006 DIE Side View (a) Thermal Pad DIE End View (b) Bottom View (c) The thermal pad is electrically isolated from all terminals in the package. Figure 22. Views of Thermally-Enhanced DCP Package ǒ T MAX * T A PD + q JA Ǔ (3) Where: PD = maximum power dissipation (W) TMAX = absolute maximum junction temperature (125°C) TA = free-ambient air temperature (°C) qJA = qJC + qCA qJC = thermal coefficient from junction-to-case (°C/W) qCA = thermal coefficient from case-to-ambient air (°C/W) 6 Maximum Power Dissipation (W) For a given qJA, the maximum power dissipation is shown in Figure 23, and is calculated by Equation 3: 5 4 3 2 1 0 −40 −20 0 20 40 60 80 100 TA, Free−Air Temperature (_C) Figure 23. Maximum Power Dissipation vs Free-Air Temperature (with PowerPAD soldered down) 25 PACKAGE OPTION ADDENDUM www.ti.com 12-Jan-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty BUF20820AIDCPR ACTIVE HTSSOP DCP 38 2000 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1 YEAR BUF20820AIDCPRE4 ACTIVE HTSSOP DCP 38 2000 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1 YEAR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 17-May-2007 TAPE AND REEL INFORMATION Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com Device BUF20820AIDCPR 17-May-2007 Package Pins DCP 38 Site Reel Diameter (mm) Reel Width (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) TAI 330 16 6.9 10.2 1.8 12 TAPE AND REEL BOX INFORMATION Device Package Pins Site Length (mm) Width (mm) Height (mm) BUF20820AIDCPR DCP 38 TAI 346.0 346.0 33.0 Pack Materials-Page 2 W Pin1 (mm) Quadrant 16 PKGORN T1TR-MS P IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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