CD74HC365-Q1, CD74HC366-Q1, CD74HCT365-Q1 www.ti.com SCHS382 – JANUARY 2010 HIGH-SPEED CMOS LOGIC HEX BUFFER/LINE DRIVER, THREE-STATE NON-INVERTING AND INVERTING Check for Samples: CD74HC365-Q1, CD74HC366-Q1, CD74HCT365-Q1 FEATURES • 1 • • • • • • • • • Qualified for Automotive Applications Buffered Inputs High Current Bus Driver Outputs Typical Propagation Delay tPLH, tPHL = 8ns at VCC = 5V, CL = 15pF, TA = 25°C Fanout (Over Temperature Range) – Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads – Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads Wide Operating Temperature Range . . . –40°C to 125°C Balanced Propagation Delay and Transition Times Significant Power Reduction Compared to LSTTL Logic ICs HC Types – 2V to 6V Operation – High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V HCT Types – 4.5V to 5.5V Operation – Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) – CMOS Input Compatibility, Il ≤ 1mA at VOL, VOH D PACKAGE (TOP VIEW) DESCRIPTION The CD74HC365-Q1, CD74HC366-Q1, and CD74HCT365-Q1 silicon gate CMOS three state buffers are general purpose high-speed non-inverting and inverting buffers. They have high drive current outputs which enable high speed operation even when driving large bus capacitances. These circuits possess the low power dissipation of CMOS circuitry, yet have speeds comparable to low power Schottky TTL circuits. Both circuits are capable of driving up to 15 low power Schottky inputs. The CD74HC365-Q1 and CD74HCT365-Q1 are non-inverting buffers, whereas the CD74HC366-Q1 is an inverting buffer. These devices have two three-state control inputs (OE1 and OE2) which are NORed together to control all six gates. The ’HCT365-Q1 logic families are speed, function and pin compatible with the standard LS logic family. ORDERING INFORMATION (1) PACKAGE (2) TA –40°C to 125°C (1) (2) SOIC – D Reel of 2500 ORDERABLE PART NUMBER TOP-SIDE MARKING CD74HC366QDRQ1 HC366Q CD74HC365QDRQ1 Product Preview CD74HCT365QDRQ1 Product Preview For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2010, Texas Instruments Incorporated CD74HC365-Q1, CD74HC366-Q1, CD74HCT365-Q1 SCHS382 – JANUARY 2010 www.ti.com FUNCTIONAL DIAGRAMS CD74HC365-Q1, CD74HCT365-Q1 CD74HC366-Q1 TRUTH TABLE (1) OUTPUTS (Y) INPUTS (1) 2 OE1 OE2 A HC/HCT365 HC366 L L L L H L L H H L X H X Z Z H X X Z Ζ H = High Voltage Level L = Low Voltage Level X = Don’t Care Z = High Impedance (OFF) State Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): CD74HC365-Q1 CD74HC366-Q1 CD74HCT365-Q1 CD74HC365-Q1, CD74HC366-Q1, CD74HCT365-Q1 www.ti.com SCHS382 – JANUARY 2010 LOGIC DIAGRAM NOTE: Inverter not included in CD74HC365-Q1, CD74HCT365-Q1 Figure 1. LOGIC DIAGRAM FOR THE HC/HCT365 AND HC366 (outputs for HC/HCT365 are complements of those shown, i.e., 1Y, 2Y, etc.) Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): CD74HC365-Q1 CD74HC366-Q1 CD74HCT365-Q1 3 CD74HC365-Q1, CD74HC366-Q1, CD74HCT365-Q1 SCHS382 – JANUARY 2010 www.ti.com ABSOLUTE MAXIMUM RATINGS (1) PARAMETER CONDITIONS VALUE VCC DC supply voltage -0.5V to +7V IIK DC input diode current, VI < -0.5V or VI > VCC + 0.5V ±20mA IOK DC output diode current VO < -0.5V or VO > VCC + 0.5V ±20mA DC drain current per output IO ICC DC VCC or ground current ESD Electrostatic discharge ±35mA VO > -0.5V or VO < VCC + 0.5V DC output source or sink current per output pin ±25mA ±50mA Human-Body Model 1.5kV Machine Model 200V Field_Induced_Charged Device Model 250V Latch up (1) Class I Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. THERMAL CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) PARAMETER qJA Thermal resistance (typical) (1) JT Maximum junction temperature Tstg Maximum storage temperature range Maximum lead temperature (soldering 10s) (1) MIN D (SOIC) package –65 (SOIC - lead tips only) MAX UNIT 73 °C/W 150 °C 150 °C 300 °C The package thermal impedance is calculated in accordance with JESD 51-7. RECOMMENDED OPERATING CONDITIONS HC Types MIN MAX 2 6 4.5 5.5 UNIT VCC Supply voltage VI DC Input voltage 0 VCC V VO DC Output voltage 0 VCC V TA Operating free-air temperature 125 °C HCT Types –40 2V Input Rise and Fall Time 4 Submit Documentation Feedback V 1000 4.5 V 500 6V 400 ns Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): CD74HC365-Q1 CD74HC366-Q1 CD74HCT365-Q1 CD74HC365-Q1, CD74HC366-Q1, CD74HCT365-Q1 www.ti.com SCHS382 – JANUARY 2010 ELECTRICAL CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) TEST CONDITIONS PARAMETER VI (V) IO (mA) - - 25°C VCC (V) -40°C TO 125°C MIN TYP MAX MIN MAX UNITS HC Types VIH High-level input voltage VIL Low-level input voltage - CMOS CMOS Low-level output voltage loads VOL - 1.5 - - - 3.15 - 6 4.2 - - 4.2 - 2 - - 0.5 - 0.5 4.5 - - 1.35 - 1.35 6 - - 1.8 - 1.8 1.9 - - 1.9 - 4.4 - - 4.4 - 6 5.9 - - 5.9 - -6 4.5 3.98 - - 3.7 - -7.8 6 5.48 - - 5.2 - 2 - - 0.1 - 0.1 0.02 4.5 - - 0.1 - 0.1 6 - - 0.1 - 0.1 6 4.5 - - 0.26 - 0.4 7.8 6 - - 0.26 - 0.4 VIH or VIL TTL - 2 VIH or VIL TTL 1.5 3.15 4.5 -0.02 High-level output voltage loads VOH - 2 4.5 V V V V II Input leakage current VCC or GND - 6 - - ±0.1 - ±1 mA ICC Quiescent device current VCC or GND 0 6 - - 8 - 160 mA VIH or VIL VO = VCC or GND 6 - - ±0.5 - ±10 mA IOZ Three-state leakage current HCT Types VIH High-level input voltage - - 4.5 to 5.5 2 - - 2 - V VIL Low-level input voltage - - 4.5 to 5.5 - - 0.8 - 0.8 V VOH High-level output voltage loads CMOS -0.02 4.5 4.4 - - 4.4 - -4 4.5 3.98 - - 3.7 - VOL Low-level output voltage loads CMOS 0.02 4.5 - - 0.1 - 0.1 4 4.5 - - 0.26 - 0.4 II Input leakage current VCC or GND - 5.5 - - ±0.1 - ±1 mA ICC Quiescent device current VCC or GND 0 5.5 - - 8 - 160 mA ΔICC Additional quiescent device current per input pin: 1 unit load (1) VCC - 2.1 - 4.5 to 5.5 - 100 360 - 490 mA IOZ Three-state leakage current VIH or VIL VO = VCC or GND 5.5 - - ±0.5 - ±10 mA (1) VIH or VIL TTL VIH or VIL TTL V V For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. HCT Input Loading INPUT Copyright © 2010, Texas Instruments Incorporated UNIT LOADS OE1 0.6 All Others 0.55 Submit Documentation Feedback Product Folder Link(s): CD74HC365-Q1 CD74HC366-Q1 CD74HCT365-Q1 5 CD74HC365-Q1, CD74HC366-Q1, CD74HCT365-Q1 SCHS382 – JANUARY 2010 www.ti.com SWITCHING CHARACTERISTICS Input tr, tf = 6ns PARAMETER 25°C TEST CONDITIONS VCC (V) CL = 50pF -40°C TO 125°C UNITS TYP MAX MAX 2 - 110 165 4.5 - 22 33 6 - 19 28 5 9 - - 2 - 150 225 4.5 - 31 45 6 - 26 38 5 12 - - 2 - 60 90 4.5 - 12 18 6 - 10 15 - - 10 10 pF HC Types HC365 tPLH, tPHL CL = 15pF Propagation delay, data to outputs HC366 CL = 50pF CL = 15pF tTLH, tTHL Output transition time CL = 50pF ns ns CI Input capacitance - CO Three-state output capacitance - - - 20 20 pF CPD Power dissipation capacitance (1) (2) - 5 40 - - pF 38 HCT Types CL = 50pF 4.5 - 25 CL = 15pF 5 9 - - CL = 50pF 4.5 - 27 41 CL = 15pF 5 11 - - Propagation delay, output enable and disable to outputs CL = 50pF 4.5 CL = 15pF 5 tTLH, tTHL Output transition time CL = 50pF CI Input capacitance CO Three-state output capacitance CPD Power dissipation capacitance (1) (2) HCT365 tPLH, tPHL Propagation delay, data to outputs HCT366 tPLH, tPHL (1) (2) 6 ns - 35 53 14 - - 4.5 - 12 18 ns - - - 10 10 pF - - - 20 20 pF - 5 42 - - pF ns CPD is used to determine the dynamic power consumption, per inverter. PD = VCC2 × fi (CPD + CL), where fi = input frequency, CL = output load capacitance, VCC = supply voltage Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): CD74HC365-Q1 CD74HC366-Q1 CD74HCT365-Q1 CD74HC365-Q1, CD74HC366-Q1, CD74HCT365-Q1 www.ti.com SCHS382 – JANUARY 2010 TEST CIRCUIT AND WAVEFORMS Figure 2. HC and HCU Transition Times and Propagation Delay Times, Combination Logic Figure 3. HCT Transition Times and Propagation Delay Times, Combination Logic Figure 4. HC Three-State Propagation Delay Waveform Figure 5. HCT Three-State Propagation Delay Waveform W W Figure 6. HC and HCT Three-State Propagation Delay Test Circuit Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): CD74HC365-Q1 CD74HC366-Q1 CD74HCT365-Q1 7 PACKAGE OPTION ADDENDUM www.ti.com 7-Jan-2011 PACKAGING INFORMATION Orderable Device CD74HC366QDRQ1 Status (1) ACTIVE Package Type Package Drawing SOIC D Pins Package Qty 16 2500 Eco Plan (2) Green (RoHS & no Sb/Br) Lead/ Ball Finish MSL Peak Temp CU NIPDAU Level-1-260C-UNLIM (3) Samples (Requires Login) Purchase Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. 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