TI LMZ14202 Simple switcher 6v to 42v, 2a power module in leaded smt-to package Datasheet

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LMZ14202
SNVS648J – JANUARY 2010 – REVISED OCTOBER 2015
LMZ14202 SIMPLE SWITCHER® 6V to 42V, 2A Power Module in Leaded SMT-TO Package
1 Features
2 Applications
•
•
•
•
1
•
•
•
•
•
•
•
•
•
Integrated Shielded Inductor
Simple PCB Layout
Flexible Start-Up Sequencing Using External SoftStart and Precision Enable
Protection Against Inrush Currents and Faults
Such as Input UVLO and Output Short Circuit
Junction Temperature Range: –40°C to 125°C
Single Exposed Pad and Standard Pinout for Easy
Mounting and Manufacturing
Fast Transient Response for Powering FPGAs
and ASICs
Low Output Voltage Ripple
Pin-to-Pin Compatible Family:
– LMZ14203/2/1 (42 V Maximum; 3 A, 2 A, 1 A)
– LMZ12003/2/1 (20 V Maximum; 3 A, 2 A, 1 A)
Fully Enabled for WEBENCH® Power Designer
Electrical Specifications
– 12-W Maximum Total Output Power
– Up to 2-A Output Current
– Input Voltage Range: 6 V to 42 V
– Output Voltage Range: 0.8 V to 6 V
– Efficiency up to 90%
Performance Benefits
– Operates at High Ambient Temperature With
No Thermal Derating
– High Efficiency Reduces System Heat
Generation
– Low Radiated Emissions (EMI) Tested With
EN55022 Class B Standard
– Low External Component Count
•
•
•
Point of Load Conversions from 12-V and 24-V
Input Rail
Time-Critical Projects
Space Constrained and High Thermal
Requirement Applications Easy-To-Use, 7-Pin
Package
PFM 7-Pin Package
Negative Output Voltage Applications
(See AN-2027) SNVA425
3 Description
The LMZ14202, SIMPLE SWITCHER® power module
is an easy-to-use step-down DC-DC that can drive up
to 2-A load with exceptional power conversion
efficiency, line and load regulation, and output
accuracy. The LMZ14202 is available in an innovative
package that enhances thermal performance and
allows for hand or machine soldering.
The LMZ14202 can accept an input voltage rail
between 6 V and 42 V and deliver an adjustable and
highly accurate output voltage as low as 0.8 V. The
LMZ14202 only requires three external resistors and
four external capacitors to complete the power
solution. The LMZ14202 is a reliable and robust
design with the following protection features: thermal
shutdown, input undervoltage lockout, output
overvoltage protection, short-circuit protection, output
current limit, and allows start-up into a prebiased
output. A single resistor adjusts the switching
frequency up to 1 MHz.
Device Information(1)(2)
PART NUMBER
PACKAGE
LMZ14202
TO-PMOD (7)
BODY SIZE (NOM)
10.16 mm × 9.85 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
(2) Peak reflow temperature equals 245°C. See SNAA214 for
more details.
Simplified Application Schematic
Efficiency 12-V Input at 25°C
100
VOUT
95
VOUT
CFF
RON
6.0
5.0
3.3
2.5
90
EFFICIENCY (%)
FB
SS
EN
GND
VIN
VIN
RON
LMZ14202
RFBT
Enable
85
1.8
1.5
1.2
80
75
70
65
60
CIN
CSS
RFBB
COUT
55
25°C
50
0
0.4
0.8
1.2
1.6
2
OUTPUT CURRENT (A)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMZ14202
SNVS648J – JANUARY 2010 – REVISED OCTOBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
6.1
6.2
6.3
6.4
6.5
6.6
3
3
4
4
4
6
Detailed Description ............................................ 11
7.1
7.2
7.3
7.4
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
11
11
11
13
Application and Implementation ........................ 14
8.1 Application Information............................................ 14
8.2 Typical Application ................................................. 14
9 Power Supply Recommendations...................... 21
10 Layout................................................................... 21
10.1 Layout Guidelines .................................................
10.2 Layout Example ....................................................
10.3 Power Dissipation and Board Thermal
Requirements...........................................................
10.4 Power Module SMT Guidelines ............................
21
22
23
23
11 Device and Documentation Support ................. 25
11.1
11.2
11.3
11.4
11.5
11.6
Device Support......................................................
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
25
25
25
25
25
25
12 Mechanical, Packaging, and Orderable
Information ........................................................... 25
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision I (August 2015) to Revision J
•
Added this new bullet to the Power Module SMT Guidelines section.................................................................................. 23
Changes from Revision H (June 2015) to Revision I
•
Page
Page
Changed the title of the document ......................................................................................................................................... 1
Changes from Revision G (March 2013) to Revision H
Page
•
Added Pin Configuration and Functions section, Handling Rating table, Feature Description section, Device
Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout
section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information
section ................................................................................................................................................................................... 1
•
Removed Easy-To-Use 7-Pin Package PFM 7-Pin Package image...................................................................................... 1
Changes from Revision F (October 2012) to Revision G
Page
•
Changed layout of National Data Sheet to TI format ........................................................................................................... 23
•
Added Power Module SMT Guidelines section .................................................................................................................... 23
2
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5 Pin Configuration and Functions
NDW Package
7-Pin TO-PMOD
Top View
VOUT
FB
SS
GND
EN
RON
VIN
7
6
5
4
3
2
1
Exposed Pad
Connect to GND
Pin Functions
PIN
NAME
NO.
TYPE
DESCRIPTION
EN
3
Analog
Enable. Input to the precision enable comparator. Rising threshold is 1.18 V nominal, 90 mV
hysteresis nominal. Maximum recommended input level is 6.5 V.
FB
6
Analog
Feedback. nternally connected to the regulation, overvoltage, and short-circuit comparators. The
regulation reference point is 0.8 V at this input pin. Connected the feedback resistor divider between
the output and ground to set the output voltage.
GND
4
Ground
Ground. Reference point for all stated voltages. Must be externally connected to thermal pad.
RON
2
Analog
ON-time resistor. An external resistor between this pin and the VIN pin sets the ON-time of the
application. Typical values range from 25 kΩ to 124 kΩ.
SS
5
Analog
Soft-start. An internal 8-µA current source charges an external capacitor to produce the soft-start
function. This node is discharged at 200 µA during disable, over-current, thermal shutdown and
internal UVLO conditions.
VIN
1
Power
Supply input. Nominal operating range is 6 V to 42 V . A small amount of internal capacitance is
contained within the package assembly. Additional external input capacitance is required between
this pin and exposed pad.
VOUT
7
Power
Output voltage. Output from the internal inductor. Connect the output capacitor between this pin and
exposed pad.
Ground
Exposed Pad — Internally connected to pin 4. Used to dissipate heat from the package during
operation. Must be electrically connected to pin 4 external to the package.
Thermal pad
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
TJ
(1) (2)
MIN
MAX
UNIT
VIN, RON to GND
–0.3
43.5
V
EN, FB, SS to GND
–0.3
Junction temperature
Peak reflow case temperature (30 s)
Tstg
(1)
(2)
Storage temperature
–65
7
V
150
°C
245
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
For soldering specifications, refer to the following document: www.ti.com/lit/snoa549c
6.2 ESD Ratings
V(ESD)
(1)
Electrostatic
discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
VALUE
UNIT
±2000
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VIN
Input voltage
6
42
EN
Enable voltage
0
6.5
V
V
TJ
Junction temperature
−40
125
°C
6.4 Thermal Information
LMZ14202
NDW
(TO-PMOD)
THERMAL METRIC (1)
UNIT
7 PINS
RθJA
Junction-to-ambient thermal
resistance
RθJC(top)
Junction-to-case (top) thermal
resistance
(1)
4-layer JEDEC Printed circuit board, 100 vias, No air
flow
19.3
°C/W
2-layer JEDEC Printed circuit board, No air flow
21.5
°C/W
No air flow
1.9
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics
Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of –40°C
to +125°C. Minimum and maximum limits are ensured through test, design or statistical correlation. Typical values represent
the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated the
following conditions apply: VVIN = 24 V, VVOUT = 3.3 V
PARAMETER
ENABLE CONTROL
TEST CONDITIONS
MIN (1)
TYP (2)
MAX (1)
UNIT
(3)
VEN
EN threshold trip point
VEN rising
VEN-HYS
EN threshold hysteresis
VEN falling
1.18
–40°C ≤ TJ ≤ 125°C
1.1
V
1.25
90
mV
8
µA
SOFT-START
ISS
SS source current
ISS-DIS
SS discharge current
VSS = 0 V
–40°C ≤ TJ ≤ 125°C
5
11
-200
µA
CURRENT LIMIT
ICL
Current limit threshold
d.c. average
2.6
–40°C ≤ TJ ≤ 125°C
2.3
A
3.65
ON/OFF TIMER
tON-MIN
ON timer minimum pulse
width
150
ns
tOFF
OFF timer pulse width
260
ns
REGULATION AND OVERVOLTAGE COMPARATOR
VFB
In-regulation feedback voltage
VSS > 0.8 V, IO = 2 A
0.795
–40°C ≤ TJ ≤ 125°C
VSS >+ 0.8 V, IO = 10 mA
VFB-OV
Feedback over-voltage
protection threshold
IFB
Feedback input bias current
(1)
(2)
(3)
4
0.775
0.786
0.815
0.802
0.818
V
V
0.92
V
5
nA
Minimum and maximum limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through
correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).
Typical numbers are at 25°C and represent the most likely parametric norm.
EN 55022:2006, +A1:2007, FCC Part 15 Subpart B: 2007. See AN-2024 LMZ1420x / LMZ1200x Evaluation Board (SNVA422) and
layout for information on device under test.
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Electrical Characteristics (continued)
Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of –40°C
to +125°C. Minimum and maximum limits are ensured through test, design or statistical correlation. Typical values represent
the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated the
following conditions apply: VVIN = 24 V, VVOUT = 3.3 V
PARAMETER
TEST CONDITIONS
IQ
Non-switching input current
VFB = 0.86 V
ISD
Shutdown quiescent current
VEN = 0 V
MIN (1)
TYP (2)
MAX (1)
UNIT
1
mA
25
μA
THERMAL CHARACTERISTICS
TSD
Thermal shutdown
Rising
165
°C
TSD-HYST
Thermal shutdown hysteresis
Falling
15
°C
8
mVP-P
PERFORMANCE PARAMETERS
ΔVO
Output voltage ripple
ΔVO/ΔVIN
Line regulation
12 V ≤ VVIN ≤ 42 V, IO = 2 A
ΔVO/IOUT
Load regulation
VVIN = 24 V
η
Efficiency
0.01%
1.5
VVIN = 24 V, VO = 3.3 V, IO = 1 A
86%
VVIN = 24 V, VO = 3.3 V, IO = 2 A
85%
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6.6 Typical Characteristics
Unless otherwise specified, the following conditions apply: VVIN = 24 V; CIN = 10 µF, X7R ceramic; CO = 100 µF X7R ceramic;
TA = 25°C.
100
1.2
95
1.0
2.5
1.8
1.5
1.2
85
80
75
DISSIPATION (W)
EFFICIENCY (%)
90
70
65
60
0.8
1.5
0.6
1.2
0.4
0.2
55
50
2.5
1.8
25°C
25°C
0
0.4
0.8
1.2
1.6
0
2
0
0.4
OUTPUT CURRENT (A)
Figure 1. Efficiency 6-V Input
1.2
95
6.0
5.0
3.3
2.5
85
75
5.0
3.3
1.8
1.5
1.2
80
6.0
1.0
DISSIPATION (W)
90
2
1.6
Figure 2. Dissipation 6-V Input
100
EFFICIENCY (%)
1.2
0.8
OUTPUT CURRENT (A)
70
65
60
2.5
1.8
0.8
0.6
1.5
1.2
0.4
0.2
55
25°C
50
0
0.4
0.8
1.2
1.6
25°C
0
2
0
0.4
1.2
0.8
1.6
2
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
Figure 4. Dissipation 12-V Input
Figure 3. Efficiency 12-V Input
100
1.8
95
EFFICIENCY (%)
85
80
DISSIPATION (W)
6.0
5.0
3.3
2.5
90
1.8
75
70
65
60
6
6.0
1.2
5.0
3.3
2.5
0.9
1.8
0.6
0.3
55
50
1.5
25°C
0
0.4
0.8
1.2
1.6
2
25°C
0
0
0.4
0.8
1.2
1.6
2
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
Figure 5. Efficiency 24-V Input
Figure 6. Dissipation 24-V Input
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Typical Characteristics (continued)
Unless otherwise specified, the following conditions apply: VVIN = 24 V; CIN = 10 µF, X7R ceramic; CO = 100 µF X7R ceramic;
TA = 25°C.
100
1.8
95
1.5
6.0
5.0
3.3
85
DISSIPATION (W)
EFFICIENCY (%)
90
80
75
70
65
60
6.0
5.0
0.9
3.3
0.6
0.3
55
50
1.2
25°C
0
0.8
0.4
1.2
1.6
25°C
0
2
0
0.4
OUTPUT CURRENT (A)
0.8
2
1.6
1.2
OUTPUT CURRENT (A)
Figure 7. Efficiency 36-V Input at 25°C
Figure 8. Dissipation 36-V Input
1.8
100
95
1.5
85
6.0
5.0
80
3.3
6.0
DISSIPATION (W)
EFFICIENCY (%)
90
75
70
65
60
5.0
3.3
0.9
0.6
0.3
55
50
1.2
25°C
0
0.8
0.4
1.2
1.6
25°C
0
2
0
OUTPUT CURRENT (A)
0.4
0.8
1.2
Figure 9. Efficiency 42-V Input
Figure 10. Dissipation 42-V Input
100
1.4
1.2
2.5
90
DISSIPATION (W)
2.5
EFFICIENCY (%)
2
1.6
OUTPUT CURRENT (A)
80
1.5
70
1.2
1.8
1.0
1.8
1.2
0.8
0.6
1.5
0.4
60
0.2
85°C
85°C
50
0
0.4
0.8
1.2
1.6
0.0
2
OUTPUT CURRENT (A)
0
0.4
0.8
1.2
1.6
2
OUTPUT CURRENT (A)
Figure 11. Efficiency 6-V Input, TA = 85°C
Figure 12. Dissipation 6-V Input, TA = 85°C
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Typical Characteristics (continued)
Unless otherwise specified, the following conditions apply: VVIN = 24 V; CIN = 10 µF, X7R ceramic; CO = 100 µF X7R ceramic;
TA = 25°C.
100
1.6
3.3
5.0
2.5
1.4
1.5
1.8
2.5
90
DISSIPATION (W)
EFFICIENCY (%)
1.2
80
1.8
70
1.2
1.5
3.3
1.0
0.8
1.2
5.0
0.6
0.4
60
85°C
0.2
85°C
50
0
0.4
0.8
1.2
1.6
0.0
2
0
0.4
0.8
1.2
1.6
OUTPUT CURRENT (A)
Figure 13. Efficiency 8 V Input, TA = 85°C
Figure 14. Dissipation 8-V Input, TA = 85°C
1.6
100
5.0
6.0
3.3
1.4
3.3
90
DISSIPATION (W)
1.2
EFFICIENCY (%)
2.0
OUTPUT CURRENT (A)
80
2.5
70
1.8
1.2
1.5
2.5
5.0
1.0
0.8
6.0
0.6
1.2
0.4
60
1.8
50
0
1.5
0.2
85°C
0.4
0.8
1.2
1.6
0.0
2
85°C
0
0.4
0.8
1.2
1.6
2.0
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
Figure 15. Efficiency 12-V Input, TA = 85°C
Figure 16. Dissipation 12-V Input, TA = 85°C
100
1.8
1.6
6.0
1.4
DISSIPATION (W)
EFFICIENCY (%)
90
80
2.5
1.8
70
5.0
3.3
1.0
3.3
0.8
5.0
0.6
1.8
0.4
60
2.5
0.2
85°C
85°C
50
0
0.4
0.8
1.2
1.6
0.0
2
OUTPUT CURRENT (A)
0
0.4
0.8
1.2
1.6
2
OUTPUT CURRENT (A)
Figure 17. Efficiency 24-V Input, TA = 85°C
8
6.0
1.2
Figure 18. Dissipation 24-V Input, TA = 85°C
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Typical Characteristics (continued)
Unless otherwise specified, the following conditions apply: VVIN = 24 V; CIN = 10 µF, X7R ceramic; CO = 100 µF X7R ceramic;
TA = 25°C.
100
2.0
1.8
90
1.6
80
DISSIPATION (W)
EFFICIENCY (%)
6.0
3.3
5.0
70
60
1.4
1.2
3.3
1.0
6.0
0.8
0.6
0.4
50
0
5.0
0.2
85°C
0.4
0.8
1.2
1.6
0.0
2
0
0.4
OUTPUT CURRENT (A)
1.2
1.6
2
OUTPUT CURRENT (A)
Figure 19. Efficiency 36-V Input, TA = 85°C
Figure 20. Dissipation 36-V Input, TA = 85°C
100
2.5
90
2.0
6.0
6.0
DISSIPATION (W)
DISSIPATION (W)
0.8
5.0
80
3.3
70
60
1.5
5.0
1.0
3.3
0.5
85°C
85°C
50
0.0
0
0.4
0.8
1.2
1.6
2
0
0.4
OUTPUT CURRENT (A)
0.8
1.2
1.6
2
OUTPUT CURRENT (A)
Figure 21. Efficiency 42-V Input, TA = 85°C
Figure 22. Dissipation 42-V Input, TA = 85°C
3.36
3.360
3.355
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
3.34
3.32
20 24
8
3.30
12
3.350
3.345
3.340
3.335
12
3.330
20
8
3.325
24
42
3.320
3.28
25°C
36
3.315
42
3.310
3.26
0
0.4
0.8
1.2
1.6
2
OUTPUT CURRENT (A)
36
85°C
0
0.4
0.8
1.2
1.6
2
OUTPUT CURRENT (A)
Figure 23. Line and Load Regulation
Figure 24. Line and Load Regulation, TA = 85°C
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Typical Characteristics (continued)
Unless otherwise specified, the following conditions apply: VVIN = 24 V; CIN = 10 µF, X7R ceramic; CO = 100 µF X7R ceramic;
TA = 25°C.
50 mV/Div
20 mV/Div
1.00 Ps/Div
0.5 A/Div
Figure 25. Output Ripple
VIN = 24 V, VO = 3.3 V, 2 A, BW = 200 MHz
200 Ps/Div
Figure 26. Transient Response
VIN = 24 V, VO = 3.3 V, 0.6-A to 2-A Step
2.5
3.5
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
12VIN
2
6VIN
36VIN
1.5
24VIN
1
JA = 19.6°C/W
0.5
3.3
3.1
SHORT CIRCUIT
2.9
ONSET
2.7
VOUT = 3.3V
0
50
25°C
2.5
60
70
80
90
100 110 120
5
0
AMBIENT TEMPERATURE (°C)
Figure 27. Thermal Derating, VOUT = 3.3 V
3.3
20
25
Figure 28. Current Limit, VOUT = 3.3 V
SHORT CIRCUIT
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
15
3.5
3.5
3.1
2.9
ONSET
2.7
3.3
SHORT CIRCUIT
3.1
2.9
ONSET
2.7
25°C
85°C
2.5
0
10
10
INPUT VOLTAGE (V)
10
20
30
40
2.5
0
50
10
20
30
40
50
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
Figure 29. Current Limit, VOUT = 3.3 V,
Figure 30. Current Limit, VOUT = 3.3 V, TA = 85°C
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7 Detailed Description
7.1 Overview
The LMZ14202 is a step-down DC-to-DC power module. It is typically used to convert a higher DC voltage to a
lower DC voltage with a maximum output current of 2 A.
7.2 Functional Block Diagram
Vin
VIN
1
Linear reg
CIN
Cvcc
5
SS
Css
CBST
3
EN
0.47 PF
RON
2
VOUT
RON
Timer
CFF
7
VO
10 PH
Co
6
FB
RFBT
RFBB
Regulator IC
Internal
Passives
GND
4
7.3 Feature Description
7.3.1 Constant On-Time Control (COT) Circuit Overview
Constant on-time control (COT) control is based on a comparator and an ON-time one-shot, with the output
voltage feedback compared with an internal 0.8-V reference. If the feedback voltage is below the reference, the
main MOSFET is turned on for a fixed ON-time determined by a programming resistor RDS(on) . RDS(on) is
connected to VIN such that ON-time is reduced with increasing input supply voltage. Following this ON-time, the
main MOSFET remains off for a minimum of 260 ns. If the voltage on the feedback pin falls below the reference
level again the ON-time cycle is repeated. Regulation is achieved in this manner.
7.3.2 Output Overvoltage Comparator
The voltage at FB is compared to a 0.92-V internal reference. If FB rises above 0.92 V the ON-time is
immediately terminated. This condition is known as over-voltage protection (OVP). It can occur if the input
voltage is increased very suddenly or if the output load is decreased very suddenly. Once OVP is activated, the
top MOSFET ON-times are inhibited until the condition clears. Additionally, the synchronous MOSFET remains
on until the inductor current falls to zero.
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Feature Description (continued)
7.3.3 Current Limit
Current limit detection is carried out during the OFF-time by monitoring the current in the synchronous MOSFET.
Referring to the Functional Block Diagram, when the top MOSFET is turned off, the inductor current flows
through the load, the PGND pin and the internal synchronous MOSFET. If this current exceeds 2.6 A (typical) the
current limit comparator disables the start of the next ON-time period. The next switching cycle occurs only if the
FB input is less than 0.8 V and the inductor current has decreased below 2.6 A. Inductor current is monitored
during the period of time the synchronous MOSFET is conducting. While the inductor current exceeds 2.6 A,
further ON-time intervals for the top MOSFET do not occur. Switching frequency is lower during current limit due
to the longer OFF-time.
NOTE
Current limit is dependent on both duty cycle and temperature as illustrated in the graphs
in Typical Characteristics section.
7.3.4 Thermal Protection
Do not allow the junction temperature of the LMZ14202 device to exceed its maximum ratings. Thermal
protection is implemented by an internal thermal shutdown circuit which activates at 165 °C (typical) causing the
device to enter a low power standby state. In this state the main MOSFET remains off causing VO to fall, and
additionally the CSS capacitor is discharged to ground. Thermal protection helps prevent catastrophic failures for
accidental device overheating. When the junction temperature returns to below 145 °C (typical hysteresis = 20
°C) the SS pin is released, VO rises smoothly, and normal operation resumes.
Applications requiring maximum output current especially those at high input voltage may require application
derating at elevated temperatures.
7.3.5 Zero Coil Current Detection
The current of the lower (synchronous) MOSFET is monitored by a zero coil current detection circuit which
inhibits the synchronous MOSFET when its current reaches zero until the next ON-time. This circuit enables the
DCM operating mode, which improves efficiency at light loads.
7.3.6 Prebiased Start-Up
The LMZ14202 starts up into a pre-biased output. This startup situation is common in multiple rail logic
applications where current paths may exist between different power rails during the startup sequence. Figure 31
is a scope capture that shows proper behavior during this event.
OUTPUT
VOLTAGE
2V PRE-BIAS
OUTPUT
CURRENT
ENABLE
3.3V OUTPUT
1.0 V/Div
1.0 A/Div
2.0 V/Div
1 ms/Div
Figure 31. Prebiased Start-Up
12
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7.4 Device Functional Modes
7.4.1 Discontinuous Conduction and Continuous Conduction Modes
At light-load, the regulator operates in discontinuous conduction mode (DCM). With load currents above the
critical conduction point, it operates in continuous conduction mode (CCM). When operating in DCM the
switching cycle begins at zero amps inductor current; increases up to a peak value, and then recedes back to
zero before the end of the OFF-time. During the period of time that inductor current is zero, all load current is
supplied by the output capacitor. The next ON-time period starts when the voltage on the FB pin falls below the
internal reference. The switching frequency is lower in DCM and varies more with load current as compared to
CCM. Conversion efficiency in DCM is maintained because conduction and switching losses are reduced with
the smaller load and lower switching frequency.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Validate and test
the design implementation to confirm system functionality.
8.1 Application Information
The LMZ14202 is a step-down DC-to-DC power module. It is typically used to convert a higher DC voltage to a
lower DC voltage with a maximum output current of 2 A. The following design procedure can be used to select
components for the LMZ14202. Alternately, the WEBENCH software may be used to generate complete designs.
WEBENCH software uses an iterative design procedure and accesses comprehensive databases of
components. For more details, go to www.ti.com/WEBENCH.
8.2 Typical Application
U1
EP
Enable
VIN
VOUT
FB
SS
GND
3.3VO @ 2A
7
6
5
EN
4
3
2
1
VIN
RON
LMZ14202TZ
8V to 42V
RENT
68.1k
CFF
0.022 PF
RFBT
3.32k
RON
61.9k
CIN2
10 PF
RENB
11.8k
CIN1
1 PF
CSS
0.022 PF
RFBB
1.07k
CO1
1 PF
CO2
100 PF
Figure 32. Evaluation Board Schematic Diagram
8.2.1 Design Requirements
For this example the following application parameters exist.
• VIN range: up to 42 V
• VOUT = 0.8 V to 5 V
• IOUT = 2 A
Refer to Table 2 for more information.
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Table 1. Component Value Combinations
VOUT (V)
RFBT (kΩ)
VIN (V)
RFBB (kΩ)
RDS(on) (kΩ)
1.07
61.9
42
47.5
30
100
MIN
MAX
7.5
42
5
5.62
3.3
3.32
2.5
2.26
1.8
1.87
1.5
1.5
1
1.13
28
1.2
4.22
8.45
22.6
19
0.8
0
39.2
24.9
18
32.4
25
6
21
Table 2. List of Materials
REF DES
DESCRIPTION
SIZE
MANUFACTURER
U1
SIMPLE SWITCHER
PFM-7
Texas Instruments
PART NUMBER
LMZ14202TZ
CIN1
1 µF, 50 V, X7R
1206
Taiyo Yuden
UMK316B7105KL-T
CIN2
10 µF, 50 V, X7R
1210
Taiyo Yuden
UMK325BJ106MM-T
CO1
1 µF, 50 V, X7R
1206
Taiyo Yuden
UMK316B7105KL-T
CO2
100 µF, 6.3 V, X7R
1210
Taiyo Yuden
JMK325BJ107MM-T
RFBT
3.32 kΩ
0603
Vishay Dale
CRCW06033K32FKEA
RFBB
1.07 kΩ
0603
Vishay Dale
CRCW06031K07FKEA
RDS(on)
61.9 kΩ
0603
Vishay Dale
CRCW060361k9FKEA
RENT
68.1 kΩ
0603
Vishay Dale
CRCW060368k1FKEA
RENB
11.8 kΩ
0603
Vishay Dale
CRCW060311k8FKEA
CFF
22 nF, ±10%, X7R, 16 V
0603
TDK
C1608X7R1H223K
CSS
22 nF, ±10%, X7R, 16 V
0603
TDK
C1608X7R1H223K
8.2.2 Detailed Design Procedure
8.2.2.1 Design Steps for the LMZ14202 Application
The LMZ14202 is fully supported by WEBENCH and offers the following: Component selection, electrical and
thermal simulations as well as the build-it board for a reduction in design time. The following list of steps can be
used to manually design the LMZ14202 application.
1.
2.
3.
4.
5.
6.
7.
8.
Select minimum operating VIN with enable divider resistors
Program VO with divider resistor selection
Program turnon time with soft-start capacitor selection
Select CO
Select CIN
Set operating frequency with RDS(on)
Determine module dissipation
Carefully consider thermal performance required when designing the PCB layout
8.2.2.1.1 Enable Divider, RENT and RENB Selection
The enable input provides a precise, 1.18-V band-gap rising threshold to allow direct logic drive or connection to
a voltage divider from a higher enable voltage such as VIN. The enable input also incorporates 90 mV (typical) of
hysteresis resulting in a falling threshold of 1.09 V. The maximum recommended voltage into the EN pin is 6.5 V.
For applications where the midpoint of the enable divider exceeds 6.5 V, a small Zener diode can be added to
limit this voltage.
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The function of this resistive divider is to allow the designer to choose an input voltage below which the circuit
becomes disabled. This implements the feature of programmable undervoltage lockout. This is often used in
battery powered systems to prevent deep discharge of the system battery. It is also useful in system designs for
sequencing of output rails or to prevent early turnon of the supply as the main input voltage rail rises at powerup. Applying the enable divider to the main input rail is often done in the case of higher input voltage systems
such as 24-V AC/DC systems where a lower boundary of operation must be established. In the case of
sequencing supplies, the divider is connected to a rail that becomes active earlier in the power-up cycle than the
LMZ14202 output rail. Choose the two resistors based on Equation 1.
RENT / RENB = (VIN UVLO/ 1.18 V) – 1
(1)
The LMZ14202 demonstration and evaluation boards use 11.8 kΩ for RENB and 68.1 kΩ for RENT resulting in a
rising UVLO of 8 V. This divider presents 6.25 V to the EN input when the divider input is raised to 42 V.
The EN pin is internally pulled up to VIN and can be left floating for always-on operation.
8.2.2.1.2 Output Voltage Selection
Output voltage is determined by a divider of two resistors connected between VO and ground. The midpoint of
the divider is connected to the FB input. The voltage at FB is compared to a 0.8-V internal reference. In normal
operation an ON-time cycle is initiated when the voltage on the FB pin falls below 0.8 V. The main MOSFET ONtime cycle causes the output voltage to rise and the voltage at the FB to exceed 0.8 V. As long as the voltage at
FB is above 0.8 V, ON-time cycles does not occur.
The regulated output voltage determined by the external divider resistors RFBT and RFBB is:
VO = 0.8 V × (1 + RFBT / RFBB)
(2)
Rearranging terms; the ratio of the feedback resistors for a desired output voltage is:
RFBT / RFBB = (VO / 0.8 V) - 1
(3)
Choose these resistors from values between 1 kΩ and 10 kΩ.
For VO = 0.8 V the FB pin can be connected to the output directly so long as an output preload resistor remains
that draws more than 20 µA. Converter operation requires this minimum load to create a small inductor ripple
current and maintain proper regulation when no load is present.
A feed-forward capacitor is placed in parallel with RFBT to improve load step transient response. Its value is
usually determined experimentally by load stepping between DCM and CCM conduction modes and adjusting for
best transient response and minimum output ripple.
A table of values for RFBT , RFBB , CFF and RDS(on) is included in the applications schematic.
8.2.2.1.3 Soft-Start Capacitor Selection
Programmable soft-start permits the regulator to slowly ramp to its steady state operating point after being
enabled, thereby reducing current inrush from the input supply and slowing the output voltage rise-time to
prevent overshoot.
Upon turnon, after all UVLO conditions have been passed, an internal 8 µA current source begins charging the
external soft-start capacitor. The soft-start time duration to reach steady state operation is given by the formula:
tSS = VREF × CSS / ISS = 0.8 V × CSS / 8 µA
(4)
This equation can be rearranged as follows:
CSS = tSS × 8 μA / 0.8 V
(5)
Use of a 0.022-μF capacitor results in 2.2-ms soft-start duration which is recommended as a minimum value.
As the soft-start input exceeds 0.8 V the output of the power stage comes into regulation. The soft-start capacitor
continues charging until it reaches approximately 3.8 V on the SS pin. Voltage levels between 0.8 V and 3.8 V
have no effect on other circuit operation. The following conditions reset the soft-start capacitor by discharging the
SS input to ground with an internal 200-μA current sink.
•
•
•
•
16
The enable input being pulled low
Thermal shutdown condition
Over-current fault
Internal VCC UVLO (approximately 4-V input to VIN)
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8.2.2.1.4 CO Selection
None of the required CO output capacitance is contained within the module. At a minimum, the output capacitor
must meet the worst-case minimum ripple current rating of 0.5 × ILR(P-P), as calculated in Equation 17 below.
Beyond the worst-case minimum, additional capacitance reduces output ripple as long as the ESR is low enough
to permit it. A minimum value of 10 μF is generally required. Expect to experiment when designing an application
to operate with a minimum value. Ceramic capacitors or other low ESR types are recommended. See AN-2024
LMZ1420x / LMZ1200x Evaluation Board (SNVA422) for more detail.
Equation 6 provides a good first-pass approximation of CO for load transient requirements:
CO ≥ ISTEP × VFB × L × VIN/ (4 × VO × (VIN – VO) × VOUT-TRAN)
(6)
Solving:
CO ≥ 2 A × 0.8 V × 10 μH × 24 V / (4 × 3.3 V × (24 V – 3.3 V ) × 33 mV) ≥ 43 μF
(7)
The LMZ14202 demonstration and evaluation boards are populated with a 100-µF 6.3-V X5R output capacitor.
Locations for extra output capacitors are provided. See See AN-2024 LMZ1420x / LMZ1200x Evaluation Board
(SNVA422) for locations.
8.2.2.1.5 Input Capacitance (CIN) Selection
The LMZ14202 module contains an internal 0.47-µF input ceramic capacitor. Additional input capacitance is
required external to the module to handle the input ripple current of the application. This input capacitance must
be very close to the module. Input capacitor selection is generally directed to satisfy the input ripple current
requirements rather than by capacitance value. Worst-case input ripple current rating is dictated by Equation 8:
ICIN(rms) @
1
D
´ IO ´
2
1- D
where
•
D ≊ VO / VIN
(8)
The worst-case ripple current occurs when the module is presented with full load current and when VIN = (2 ×
VO).
Recommended minimum input capacitance is 10-µF X7R ceramic with a voltage rating at least 25% higher than
the maximum applied input voltage for the application. TI also recommends to pay attention to the voltage and
temperature deratings of the capacitor selected.
NOTE
If the capacitor data sheet omits ripple current rating of the ceramic capacitors, contact the
capacitor manufacturer to obtain this rating.
If the system design requires a certain minimum value of input ripple voltage ΔVIN be maintained then Equation 9
may be used.
CIN ≥ IO × D × (1–D) / fSW-CCM × ΔVIN
(9)
If ΔVIN is 1% of VIN for a 24V input to 3.3V output application this equals 240 mV and fSW = 400 kHz.
CIN≥ 2 A × 3.3 V / 24V × (1– 3.3 V/24 V) / (400000 × 0.240 V)
≥ 2.5 μF
Additional bulk capacitance with higher ESR may be required to damp any resonant effects of the input
capacitance and parasitic inductance of the incoming supply lines.
8.2.2.1.6 RDS(on) Resistor Selection
Many designs begin with a desired switching frequency in mind. For that purpose Equation 10 can be used.
fSW(CCM) ≊ VO / (1.3 × 10-10 × RDS(on) )
(10)
This can be rearranged as
RDS(on) ≊ VO / (1.3 × 10 -10 × fSW(CCM))
(11)
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The selection of RON and fSW(CCM) must be confined by limitations in the ON-time and OFF-time for the Constant
On-Time Control (COT) Circuit Overview section.
The ON-time of the LMZ14202 timer is determined by the resistor RDS(on) and the input voltage VIN. It is
calculated as follows:
tON = (1.3 × 10-10 × RDS(on) ) / VIN
(12)
The inverse relationship of tON and VIN gives a nearly constant switching frequency as VIN is varied. Select an
RDS(on) level to fascilitate an ON-time at maximum VIN is greater than 150 ns. The ON-timer has a limiter to
ensure a minimum of 150 ns for tON. This function imits the maximum operating frequency, which is governed by
Equation 13:
fSW(max) = VO / (VIN(max) × 150 ns)
(13)
Use Equation 14 to select RDS(on) a particular operating frequency while maintaining the minimum ON-time of 150
ns.
RDS(on) ≥ VIN(max) × 150 ns / (1.3 × 10 -10)
(14)
If RDS(on) calculated in Equation 11 is less than the minimum value determined in Equation 14, select a lower
frequency. Alternatively, VIN(max) can also be limited to keep the frequency unchanged.
NOTE
The minimum OFF-time of 260 ns limits the maximum duty ratio. Select a larger RDS(on)
(lower fSW) for any application requiring large duty ratio.
8.2.2.1.6.1 Discontinuous Conduction and Continuous Conduction Mode Selection
Operating frequency in DCM can be calculated as follows:
fSW(DCM) ≊ VO × (VIN-1) × 10 μH × 1.18 × 1020 × IO/(VIN–VO) × RDS(on) 2
(15)
In CCM, current flows through the inductor through the entire switching cycle and never falls to zero during the
OFF-time. The switching frequency remains relatively constant with load current and line voltage variations. The
CCM operating frequency can be calculated using Equation 7 above.
Following is a comparison pair of waveforms of the showing both CCM (upper) and DCM operating modes.
500 mA/Div
2.00 Ps/Div
Figure 33. CCM and DCM Operating Modes
VIN = 24 V, VO = 3.3 V, IO = 2 A/0.32 A 2 μs/div
The approximate formula for determining the DCM/CCM boundary is as follows:
IDCB ≊ VO × (VIN– VO)/(2 × 10 μH × fSW(CCM) × VIN)
(16)
Following is a typical waveform showing the boundary condition.
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500 mA/Div
2.00 Ps/Div
Figure 34. Transition Mode Operation
VIN = 24 V, VO = 3.3 V, IO = 0.35 A 2 μsec/div
The inductor internal to the module is 10 μH. This value was chosen as a good balance between low and high
input voltage applications. The main parameter affected by the inductor is the amplitude of the inductor ripple
current (ILR). ILR can be calculated with:
ILR P-P = VO × (VIN– VO)/(10 µH × fSW × VIN)
where
•
VIN is the maximum input voltage and fSW is determined from Equation 10.
(17)
If the output current IO is determined by assuming that IO = IL, the higher and lower peak of ILR can be
determined. Be aware that the lower peak of ILR must be positive if CCM operation is required.
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8.2.3 Application Curves
100
2.5
95
OUTPUT CURRENT (A)
EFFICIENCY (%)
90
85
80
75
70
65
2
1.5
1
0.5
60
55
50
0
0.5
1
1.5
0
50
2
60
70
80
90
100 110 120
OUTPUT CURRENT (A)
AMBIENT TEMPERATURE (°C)
Figure 35. Efficiency VIN = 24 V VOUT = 5 V
Figure 36. Thermal Derating Curve
VIN = 24 V, VOUT = 5 V,
RADIATED EMISSIONS (dBPV/m)
80.0
70.0
60.0
50.0
EN 55022 CLASS B LIMIT
40.0
30.0
20.0
10.0
0.0
0
200
400
600
800
1000
FREQUENCY (MHz)
Figure 37. Radiated Emissions (EN 55022 Class B)
From Evaluation Board
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9 Power Supply Recommendations
The LMZ14202 device is designed to operate from an input voltage supply range between 4.5 V and 42 V. Use a
well-regulated input supply that can withstand maximum input current and maintain a stable voltage. The
resistance of the input supply rail must be low enough that an input current transient does not cause a high
enough drop at the LMZ14202 supply voltage that can cause a false UVLO fault triggering and system reset. If
the input supply is more than a few inches from the LMZ14202, additional bulk capacitance may be required in
addition to the ceramic bypass capacitors. The amount of bulk capacitance is not critical, but a 47-μF or 100-μF
electrolytic capacitor is a typical choice.
10 Layout
10.1 Layout Guidelines
PCB layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance of a
DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce and resistive voltage drop in
the traces. These can send erroneous signals to the DC-DC converter resulting in poor regulation or instability.
Good layout can be implemented by following a few simple design rules.
• Minimize area of switched current loops. Wehn considering EMI reduction, it is imperative to minimize the
high di/dt paths during PC board layout. The high-current loops that do not overlap have high di/dt content
that cause observable high frequency noise on the output pin if the input capacitor (CIN1) is placed at a
distance away from the LMZ14202. Therefore place CIN1 as close as possible to the LMZ14202 VIN and GND
exposed thermal pad. This placement minimizes the high di/dt area and reduce radiated EMI. Additionally,
ensure that grounding for both the input and output capacitor consists of a localized top side plane that
connects to the GND exposed thermal pad (EP).
• Have a single point ground. Route the ground connections for the feedback, soft-start, and enable
components to the GND pin of the device. This routing prevents any switched or load currents from flowing in
the analog ground traces. If not properly handled, poor grounding can result in degraded load regulation or
erratic output voltage ripple behavior. Provide the single point ground connection from pin 4 to the exposed
thremal pad.
• Minimize trace length to the FB pin. Place both feedback resistors, RFBT and RFBB, and the feed forward
capacitor CFF, close to the FB pin. Because the FB node is high impedance, maintain the copper area as
small as possible. To minimize noise, route the traces from RFBT, RFBB, and CFF away from the body of the
LMZ14202 device.
• Make input and output bus connections as wide as possible. Width reduces any voltage drops on the
input or output of the converter and maximizes efficiency. To optimize voltage accuracy at the load, ensure
that a separate feedback voltage sense trace is made to the load to correct for voltage drops and provide
optimum output accuracy.
• Provide adequate device heat-sinking. Use an array of heat-sinking vias to connect the exposed pad to the
ground plane on the bottom PCB layer. If the PCB has a plurality of copper layers, these thermal vias can
also be employed to make connection to inner layer heat-spreading ground planes. For best results use a 6 ×
6 via array with minimum via diameter of 10 mils (254 μm) thermal vias spaced 59 mils (1.5 mm). Ensure
enough copper area is used for heat-sinking to maintain the junction temperature below 125°C.
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10.2 Layout Example
VIN
LMZ14202
VIN
VO
VOUT
High
di/dt
Cin1
CO1
GND
Loop 2
Loop 1
Figure 38. Minimize Area of Current Loops in Buck Module
Top View
Thermal Vias
GND
GND
EPAD
1
2
3
4 5
6 7
VIN
EN
RON
SS
GND
VOUT
FB
CIN
VIN
COUT
VOUT
RON
RENT
RFBT
CSS
RENB
CFF
RFBB
GND Plane
Figure 39. PCB Layout Guide
Figure 40. EVM Board Layout - Top View
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Layout Example (continued)
Figure 41. EVM Board Layout - Bottom View
10.3 Power Dissipation and Board Thermal Requirements
When VIN = 24 V, VO = 3.3 V, IO = 2 A, TA(max) = 85°C , and TJ = 125°C, the device must achieve a thermal
resistance from case-to-ambient described by Equation 18.
RθCA < (TJ(max) – TA(max)) / PIC-LOSS – RθJC
(18)
Given the typical thermal resistance from junction to case to be 1.9 °C/W, use the 85°C power dissipation curves
in Typical Characteristics to estimate the PIC-LOSS for the application. In this application it is 1.5 W.
RθCA = (125 – 85) / (1.5 W – 1.9) = 24.8
(19)
To reach RθCA = 24.8, the PCB is required to dissipate heat effectively. With no airflow and no external heat, use
Equation 20 to estimate the required board area covered by 1 oz. copper on both the top and bottom metal
layers.
Board Area_cm2 = 500°C × cm2/W / RθJC
(20)
As a result, approximately 20.2 square cm of 1 oz copper on top and bottom layers is required for the PCB
design. The PCB copper heat sink must be connected to the exposed pad. Approximately thirty-six, 10 mils (254
μm) thermal vias spaced 59 mils (1.5 mm) apart must connect the top copper to the bottom copper. For an
example of a high thermal performance PCB layout, refer to the AN-2024 LMZ1420x / LMZ1200x Evaluation
Board (SNVA422) .
10.4 Power Module SMT Guidelines
The recommendations below are for a standard module surface mount assembly
• Land Pattern Follow the PCB land pattern with either soldermask defined or non-soldermask defined pads
• Stencil Aperture
– For the exposed die attach pad (DAP), adjust the stencil for approximately 80% coverage of the PCB land
pattern
– For all other I/O pads use a 1:1 ratio between the aperture and the land pattern recommendation
• Solder Paste Use a standard SAC Alloy such as SAC 305, type 3 or higher
• Stencil Thickness: 0.125 to 0.15 mm
• Reflow: Refer to solder paste supplier recommendation and optimized per board size and density
– Refer to AN SNAA214 for reflow information
– Maximum number of reflows allowed is one
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23
LMZ14202
SNVS648J – JANUARY 2010 – REVISED OCTOBER 2015
www.ti.com
Power Module SMT Guidelines (continued)
Figure 42. Sample Reflow Profile
Table 3. Sample Reflow Profile Table
24
Probe
Max Temp
(°C)
Reached
Max Temp
Time Above
235°C
Reached
235°C
Time Above
245°C
Reached
245°C
Time Above
260°C
Reached
260°C
#1
242.5
6.58
0.49
6.39
0.00
–
0.00
–
#2
242.5
7.10
0.55
6.31
0.00
7.10
0.00
–
#3
241.0
7.09
0.42
6.44
0.00
–
0.00
–
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LMZ14202
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SNVS648J – JANUARY 2010 – REVISED OCTOBER 2015
11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.1.2 Development Support
WEBENCH software uses an iterative design procedure and accesses comprehensive databases of
components. For more details, go to www.ti.com/WEBENCH.
11.2 Documentation Support
11.2.1 Related Documentation
This section contains additional document support.
• Design Summary LMZ1 and LMZ2 Power Modules, SNAA214
• AN-2027 Inverting Application for the LMZ14203 SIMPLE SWITCHER Power Module, SNVA425
• Evaluation Board Application Note AN-2024, SNVA422
• Absolute Maximum Ratings for Soldering, SNOA549
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
WEBENCH, SIMPLE SWITCHER are registered trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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25
PACKAGE OPTION ADDENDUM
www.ti.com
3-Sep-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LMZ14202TZ-ADJ/NOPB
ACTIVE
TO-PMOD
NDW
7
250
Green (RoHS
& no Sb/Br)
CU SN
Level-3-245C-168 HR
-40 to 125
LMZ14202
TZ-ADJ
LMZ14202TZE-ADJ/NOPB
ACTIVE
TO-PMOD
NDW
7
45
Green (RoHS
& no Sb/Br)
CU SN
Level-3-245C-168 HR
-40 to 125
LMZ14202
TZ-ADJ
LMZ14202TZX-ADJ/NOPB
ACTIVE
TO-PMOD
NDW
7
500
Green (RoHS
& no Sb/Br)
CU SN
Level-3-245C-168 HR
-40 to 125
LMZ14202
TZ-ADJ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
3-Sep-2015
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Sep-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
LMZ14202TZ-ADJ/NOPB
LMZ14202TZX-ADJ/NOP
B
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TOPMOD
NDW
7
250
330.0
24.4
10.6
14.22
5.0
16.0
24.0
Q2
TOPMOD
NDW
7
500
330.0
24.4
10.6
14.22
5.0
16.0
24.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Sep-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LMZ14202TZ-ADJ/NOPB
TO-PMOD
NDW
7
250
367.0
367.0
45.0
LMZ14202TZX-ADJ/NOPB
TO-PMOD
NDW
7
500
367.0
367.0
45.0
Pack Materials-Page 2
MECHANICAL DATA
NDW0007A
BOTTOM SIDE OF PACKAGE
TOP SIDE OF PACKAGE
TZA07A (Rev D)
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