TM MP8042 High Current, Dual Channel Power Half-Bridge The Future of Analog IC Technology TM INITIAL RELEASE – SPECIFICATIONS SUBJECT TO CHANGE DESCRIPTION FEATURES The MP8042 is a dual channel power halfbridge that can be configured as the output stage of a Class-D audio amplifier. Each channel can be driven independently as stereo single ended audio amplifiers, or driven complementary in a bridge tied load (BTL) audio amplifier configuration. • • • • • • • • • • • The MP8042 features a low current shutdown mode, standby mode, input under voltage protection, thermal shutdown and fault flag signal output. Both channels of the driver interface with standard logic signals. The MP8042 is available in a 20-pin TSSOP (with Exposed Pad) package. EVALUATION BOARD REFERENCE Board Number Dimensions EV8042DF-00B 3.5”X x 4.0”Y x 1.0”Z ±5A Peak Current Output Up to 600KHz Switching Frequency Protected Integrated Power 150mΩ Switches 30ns Switch Dead Time All Switches Current Limited Internal Under Voltage Protection Internal Thermal Protection 2.1mA Operating Current Fault Output Flag Stereo Single Ended: 20W/Channel, 4Ω Load Bridge Tied Load Output Power: 40W, 8Ω Load APPLICATIONS • • • Class D Audio Drivers Full or Half-Bridge Regulators Motor Drivers DC-DC Switching “MPS” and “The Future of Analog IC Technology” are Trademarks of Monolithic Power Systems, Inc. TYPICAL APPLICATION VCC VDD + GND D2 1N4148 CN1 U1 1 2 PWM1 STBY 3 4 5 PWM2 NC VDR1 AGND1 BST1 PWM1 PGND1 STBY PWM2 OUT1 MP8042 VDD1 20 19 VCC 18 D5 17 16 CN2 D4 OUT1 FAULT SHDN 6 7 8 9 10 FAULT NC SHDN VDD2 AGND2 OUT2 NC PGND2 VDR2 BST2 15 VCC 14 13 12 OUT2 D6 D7 11 D3 1N4148 MP8042 Rev. 0.9 5/23/2006 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2006 MPS. All Rights Reserved. 1 TM MP8042 – HIGH CURRENT, DUAL CHANNEL POWER HALF-BRIDGE INITIAL RELEASE – SPECIFICATIONS SUBJECT TO CHANGE ABSOLUTE MAXIMUM RATINGS (1) PACKAGE REFERENCE VDD1/2 Supply Voltage............................... 26V OUT1/2 Pin Voltage............ –0.3V to VDD + 0.3V OUT1/2 to BST1/2 ......................... –0.3V to +6V Voltage at All Other Pins ............... –0.3V to +6V Storage Temperature ..............–55°C to +150°C TOP VIEW NC 1 20 VDR1 AGND1 2 19 BST1 PWM1 3 18 PGND1 STBY 4 17 OUT1 PWM2 5 16 VDD1 FAULT 6 15 NC SHDN 7 14 VDD2 Thermal Resistance AGND2 8 13 OUT2 TSSOP20F ............................. 40 ....... 6.... °C/W NC 9 12 PGND2 VDR2 10 11 BST2 Recommended Operating Conditions VDD1/2 Supply Voltage................... 7.5V to 24V Peak Output Current...................... 6A Maximum Operating Temperature .............–40°C to +85°C (3) θJA θJC Notes: 1) Exceeding these ratings may damage the device. 2) The device is not guaranteed to function outside of its operating conditions. 3) Measured on approximately 1” square of 1 oz copper. EXPOSED PAD Part Number* Package Temperature MP8042DF TSSOP20F –40°C to +85°C * (2) For Tape & Reel, add suffix –Z (eg. MP8042DF–Z) For RoHS Compliant Packaging, add suffix –LF (eg. MP8042DF–LF–Z) ELECTRICAL CHARACTERISTICS VDD1 = VDD2 = 12V, VSHDN = 5V, TA = +25°C, unless otherwise specified. Parameters Symbol Condition VDD Operating Current VDD Shutdown Current VDD Operating Threshold, Low Min Typ Max Units 2.5 10 5.8 2.1 4.0 6.1 mA µA V 6.63 7.2 V ILOAD = 0A VSHDN = 0V VDD Operating Threshold, High 1.0 STBY Threshold, Low 1.85 STBY Threshold, High 1.0 SHDN Threshold, Low PWM1,2 Threshold, Low PWM1,2 Threshold, High PWM Input Bias Current OUT Current Limit (4) MP8042 Rev. 0.9 5/23/2006 1.5 VDD = 7.5V, High-Side and LowSide VPWM = 5, Sinking VPWM = 0, Sourcing www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2006 MPS. All Rights Reserved. V 2.0 1.2 1.9 SHDN Threshold, High OUT On Resistance (4) 1.2 1.69 1.83 1 V V 2.0 V 2.0 V V µA 0.15 Ω 5 5 A A 2 TM MP8042 – HIGH CURRENT, DUAL CHANNEL POWER HALF-BRIDGE INITIAL RELEASE – SPECIFICATIONS SUBJECT TO CHANGE ELECTRICAL CHARACTERISTICS (continued) VDD1 = VDD2 = 12V, VSHDN = 5V, TA = +25°C, unless otherwise specified. Parameters OUT Switching Frequency OUT Maximum Duty Cycle (5) OUT Rise/Fall Time (4) PWM Pulse Width Dead Time (4) Symbol Condition VPWM = 0 to 2V, 50% Duty Cycle VDD = 7.5V, VPWM = 2V, CBST = 100nF, fSW = 3.3KHz VPWM = 0V to 5V VPWM = 0V to 2V, High or Low Pulse IOUT= ±100mA PWM to OUT Delay Time Rising VPWM = 0V to 5V PWM to OUT Delay Time Falling Thermal Shutdown Temperature (4) Min Typ Max 0.6 Units MHz 99.5 % 10 ns 200 ns 30 ns 37 45 VPWM = 5 to 0V 54 65 TJ Rising, Hysteresis = 20°C 150 ns ns °C Notes: 4) Guaranteed by design, not production tested. 5) OUT drives low for 1.5µs every 300µs to charge the BST to SW capacitor. MP8042 Rev. 0.9 5/23/2006 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2006 MPS. All Rights Reserved. 3 TM MP8042 – HIGH CURRENT, DUAL CHANNEL POWER HALF-BRIDGE INITIAL RELEASE – SPECIFICATIONS SUBJECT TO CHANGE PIN FUNCTIONS Pin # 1 2 3 Name NC AGND1 PWM1 4 STBY 5 PWM2 6 FAULT Fault Output. A low output at FAULT indicates that the MP8042 has detected an over temperature, over current condition or the voltage to the driver is less than 5V. This output is open drain. 7 SHDN AGND2 NC VDR2 Shutdown Input. When low, both channels will be shut off. 8 9 10 11 12 13 14 15 16 17 18 19 20 Description No Connect. Analog Ground 1. Driver Logic Input 1. Drive PWM1 with the signal that controls the MP8042 OUT1. Drive PWM high to turn on the high side switch; drive PWM low to turn on the low-side switch. Standby Input. Default low (internal pull-down). If driven high, the output of drivers is determined by the PWM1/2. If driven low, the output of both drivers is high impedance. Driver Logic Input 2. Drive PWM2 with the signal that controls the MP8042 OUT2. Drive PWM high to turn on the high-side switch; drive PWM low to turn on the low-side switch. Analog Ground 2. No Connect. Gate Drive Supply Bypass 2. The voltage at VDR2 is supplied from an internal regulator from VDD2. VDR2 powers the internal circuitry and internal MOSFET gate drive for the OUT2 stage. Bypass VDR2 to AGND2 with a 0.1µF to 10µF capacitor. BST2 Bootstrap Supply 2. BST2 powers the high-side gate of the OUT2 stage. Connect a 0.1µF or greater capacitor between BST2 and OUT2. PGND2 Power Ground 2. Connect the exposed pad on bottom side to the ground plane. OUT2 Switched Output 2. Connect the output LC filter to OUT2. OUT2 is valid approximately 100µs after VDD2 goes high. VDD2 Power Supply Input 2. Connect VDD2 to the positive side of the input power supply. Bypass VDD2 to AGND2 as close to the IC as possible. NC No Connect. VDD1 Power Supply Input 1. Connect VDD1 to the positive side of the input power supply. Bypass VDD1 to GND1 as close to the IC as possible. OUT1 Switched Output 1. Connect the output LC filter to OUT1. OUT1 is valid approximately 100µs after VDD1 goes high. PGND1 Power Ground 1. Connect the exposed pad on bottom side to the ground plane. BST1 Bootstrap Supply 1. BST1 powers the high-side gate of the OUT1 stage. Connect a 0.1µF or greater capacitor between BST1 and OUT1. VDR1 Gate Drive Supply Bypass 1. The voltage at VDR1 is supplied from an internal regulator from VDD1. VDR1 powers the internal circuitry and internal MOSFET gate drive for the OUT1 stage. Bypass VDR1 to AGND1 with a 0.1µF to 10µF capacitor. MP8042 Rev. 0.9 5/23/2006 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2006 MPS. All Rights Reserved. 4 TM MP8042 – HIGH CURRENT, DUAL CHANNEL POWER HALF-BRIDGE INITIAL RELEASE – SPECIFICATIONS SUBJECT TO CHANGE TYPICAL PERFORMANCE CHARACTERISTICS VDD1 = VDD2 = 12V, VSHDN = 5V, TA = +25°C, unless otherwise specified. Normal Switch Waveform Short Circuit Negative Current Short Circuit Positive Current IL 5A/div. VSW 10V/div. IL 5A/div. VOUT1 10V/div. VSW 10V/div. VFAULT 2V/div. VOUT2 10V/div. VFAULT 2V/div. Input/Output Waveform Negative Pulse Input/Output Waveform Positive Pulse VOUT1 10V/div. VOUT1 10V/div. VPWM1 2V/div. VPWM1 2V/div. Output Rise-Time VOUT1 5V/div. 100ns/div. 100ns/div. 5ns/div. Output Fall-Time +5 100 +4 +3 1 f=1KHz 0.1 VOUT1 5V/div. +2 +1 0 -1 -2 -3 -4 0.01 5ns/div. MP8042 Rev. 0.9 5/23/2006 AMPLITUDE (dBr) THD+N (%) 10 0.01 0.1 1 POUT (W) 10 30 -5 10 100 1K 10K 20K FREQUENCY (Hz) www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2006 MPS. All Rights Reserved. 5 TM MP8042 – HIGH CURRENT, DUAL CHANNEL POWER HALF-BRIDGE INITIAL RELEASE – SPECIFICATIONS SUBJECT TO CHANGE TYPICAL PERFORMANCE CHARACTERISTICS (continued) VDD1 = VDD2 = 12V, VSHDN = 5V, TA = +25°C, unless otherwise specified. Start-up Shut-down VDD 10V/div. VPWM1 5V/div. IL 5A/div. VDD 10V/div. VOUT1 10V/div. VOUT1 10V/div. VSTBY 2V/div. VPWM1 5V/div. IL 5A/div. 50ms/div. Standby VOUT1 10V/div. 50ms/div. Standby VSTBY 2V/div. VOUT1 10V/div. MP8042 Rev. 0.9 5/23/2006 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2006 MPS. All Rights Reserved. 6 TM MP8042 – HIGH CURRENT, DUAL CHANNEL POWER HALF-BRIDGE INITIAL RELEASE – SPECIFICATIONS SUBJECT TO CHANGE OPERATION The MP8042 is a high voltage, dual channel power half- bridge that can be configured as the output of a Class D amplifier. The output is in phase with the input, and the dead time is optimized for symmetrical performance, regardless of load conditions. The shutdown pin ( SHDN ), when set low, causes both channels 1 and 2 to be shut off. When the standby pin ( STBY ) is pulled low, it causes the outputs of both channels to go into high impedance. However, when the voltage across the BST1/2 and OUT1/2 pins drops sufficiently low, the bottom MOSFET is turned on to refresh the external bootstrap capacitor. For a bootstrap capacitor of 100nF, the refresh time is approximately 300µs. In order to prevent erratic operation, two under voltage lockout (UVLO) circuits are used. One of them is to ensure that the supply for the bottom gate drive circuit is sufficiently high and the other is for the top gate driver. Fault Protection To protect the power MOSFETs, two layers of protection are provided. The first is the current limit, wherein if the current through either the top or the bottom MOSFET exceeds an internally preset value of 5A, that particular MOSFET is immediately shut down and the complementary MOSFET is turned on. If this fails to reset the current and there is an indication that the current is going to runaway, the current foldback will kick in. This ensures that the current is reset close to zero before resuming operation. Thermal monitoring is also integrated into the MP8042. If the die temperature rises above 150°C, both switches are turned off. The temperature must fall below 140°C before normal operation resumes. Fault Output The MP8042 includes an open drain, active low fault indicator output ( FAULT ). A fault will be indicated if one of the following conditions is detected: the current limit is tripped, the thermal shutdown is tripped, the UVLO for the bottom gate driver is tripped or the part is disabled. A fault on any channel causes the FAULT pin to be pulled low. However, only that fault channel has its output set to high impedance. Do not apply more than 6V to the FAULT pin. MP8042 Rev. 0.9 5/23/2006 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2006 MPS. All Rights Reserved. 7 TM MP8042 – HIGH CURRENT, DUAL CHANNEL POWER HALF-BRIDGE INITIAL RELEASE – SPECIFICATIONS SUBJECT TO CHANGE BLOCK DIAGRAM BST1 VDD1 HIGH-SIDE DRIVER PWM1 LOGIC CONTROL VDD1 VDR1 OVER CURRENT SENSE REGULATOR OUT1 AGND1 LOW-SIDE DRIVER SHDN FAULT HANDLING & CONTROL STBY PGND1 THERMAL SHUTDOWN FAULT BST2 VDD2 HIGH-SIDE DRIVER PWM2 LOGIC CONTROL VDD2 VDR2 REGULATOR OVER CURRENT SENSE OUT2 AGND2 LOW-SIDE DRIVER PGND2 Figure 1—Functional Block Diagram MP8042 Rev. 0.9 5/23/2006 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2006 MPS. All Rights Reserved. 8 TM MP8042 – HIGH CURRENT, DUAL CHANNEL POWER HALF-BRIDGE INITIAL RELEASE – SPECIFICATIONS SUBJECT TO CHANGE PACKAGE INFORMATION TSSOP20F 0.0256(0.650)TYP 0.004(0.090) 0.010(0.250) GATE PLANE 0.105 (2.67) 0.118 (3.00) pad width 0.169 0.177 0.244 0.260 (4.300) (4.500) (6.200) (6.600) 0.004(0.090) 0o -8o 0.018(0.450) 0.030(0.750) DETAIL "A" 0.039(1.000)REF 0.030(0.750) PIN 1 IDENT. SEE DETAIL "B" 0.150 (3.80) 0.165 (4.19) pad length 0.030(0.750) SEE DETAIL "A" 0.075(0.190) 0.012(0.300) 0.252 (6.400) 0.260 (6.600) 0.032(0.800) 0.041(1.050) 0.047(1.200) max 0.007(0.190) 0.012(0.300) 0.002(0.050) 0.006(0.150) 0.004(0.090) 0.008(0.200) 0.004(0.090) 0.006(0.160) SEATING PLANE 0.007(0.190) 0.010(0.250) DETAIL "B" NOTE: 1) Control dimension is in inches. Dimension in bracket is millimeters. NOTICE: The information in this document is subject to change without notice. Please contact MPS for current specifications. Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. MP8042 Rev. 0.9 5/23/2006 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2006 MPS. All Rights Reserved. 9