LINER LTC2107 16-bit, 210 msps adc Datasheet

DEMO MANUAL DC2183A
LTC2107
16-BIT, 210 Msps ADCs
Description
Demonstration circuit 2183A supports the LTC®2107, a
high speed and high dynamic range ADC. It was specially
designed for applications that require a single-ended ACcoupled input. DC2183 supports the LTC2107 using the
DDR LVDS output mode.
The LTC2107 characteristics are listed in Table 1. Depending on the version, the circuitry on the analog inputs
is optimized for analog input frequencies from 5MHz to
70MHz or 70MHz to 180MHz.
Refer to the LTC2107 data sheet for proper input networks
for different input frequencies.
Design files for this circuit board are available at
http://www.linear.com/demo/DC2183A
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Table 1: DC2183 Variants
DC2183 VARIANTS
ADC PART NUMBER
RESOLUTION
MAXIMUM SAMPLE RATE
INPUT FREQUENCY
2183A-A
LTC2107
16-BIT
210 Msps
5MHz to 70MHz
2183A-B
LTC2107
16-BIT
210 Msps
70MHz to 180MHz
Performance Summary
Specifications are at TA = 25°C
PARAMETER
CONDITIONS
MIN
Supply Voltage – DC2183
This supply must provide up to 800mA.
3.3
5.0
V
Analog Input Range
Depending on PGA setting
1.6
2.4
VP-P
Logic Input Voltages
Minimum Logic High
1.2
Maximum Logic Low
Logic Output Voltages (Differential)
TYP
MAX
UNITS
V
0.6
V
Nominal Logic Levels
(100Ω load, 3.5mA Mode, 1.25V common mode)
0.350
V
Minimum Logic Levels
(100Ω load, 3.5mA Mode, 1.25V common mode)
0.247
V
Sampling Frequency (Encode Clock Frequency)
Convert Clock Level (Single Ended)
Logic Levels (ENC– tied to GND)
Convert Clock Level (Differential)
Minimum Logic Levels
(ENC– not tied to GND, 1.2V common mode)
10
210
0
2.5
0.2
MHz
V
V
dc2183af
1
DEMO MANUAL DC2183A
Quick Start Procedure
DC2183 is easy to set up to evaluate the performance
of the LTC2107 A/D converter. Refer to Figure 1 for
proper measurement equipment set-up and follow the
procedure below:
Setup
The DC1371 Data Acquisition and Collection System was
supplied with the DC2183 board. Follow the DC1371 Quick
Start Guide to install the required software and for connecting the DC1371 to the DC2183 and to a PC.
3.3V
TO 5V
J1
SINGLE-ENDED
ANALOG INPUT.
ABSORPTIVE FILTER IS REQUIRED
FOR DATA SHEET PERFORMANCE
SINGLE-ENDED ENCODE CLOCK.
USE A LOW-JITTER SIGNAL GENERATOR WITH PROPER FILTERING
JUMPERS SHOWN IN THEIR DEFAULT POSITIONS
THE DC2183 CONNECTS TO THE DC1371 VIA AN FMC CONNECTOR
Figure 1. DC2183 Proper Measurement Equipment Setup
(zoom in for detail)
2
dc2183af
DEMO MANUAL DC2183A
quick Start Procedure
Hardware Setup
Jumpers:
SMAs:
The DC2183 demonstration circuit should have the following jumper settings as default positions (per Figure 1)
which configure the ADC in serial programming mode.
In the default configuration JP1-JP2 should be left in the
default locations. This will pull PAR/SER low, and the
required pins high through weak pull-up resistors so the
SPI commands can be sent from the PC. If JP1 is set to
PAR then jumpers JP1-JP2 can be configured manually.
J2:Analog Input. Apply a signal to J2 from a 50Ω driver.
Absorptive filters are required for data sheet performance.
J3:Encode Clock Input. Apply a clock signal to this SMA
connector from a 50Ω driver. A filter is required for data
sheet performance.
J4:Encode Clock Input For Differential Signals. By default
the DC2183 is defined to accept a single-ended clock signal. It can be modified to accept a differential clock signal
through J3 and J4. Some component changes are required,
see the Encode Clock section for more information.
MMCX Connectors:
J1: Optional Analog Input. As a default, this connector
is not populated. Standard MMCX connectors should be
used. To connect this connector to the input of the ADC,
populate R22 and remove J2 completely. By using this
connector, the DC2183 becomes fully compliant with the
FMC specification.
Turrets:
VIN:Positive Input Voltage for the ADC and Digital Buffers.
This voltage feeds a regulator that supplies the proper
voltages for the ADC and buffers. The voltage range for
this turret is 3.3V to 5V.
EXT REF:Optional Reference Voltage. This pin is connected
directly to the SENSE pin of the ADC. Connect EXT REF to
a 1.25V external reference and the external reference mode
is automatically selected. The external reference must be
1.25V ±25mV for proper operation. If no external voltage
is supplied, this pin will be pulled up to 2.5V through a
weak pull-up resistor.
GND: Ground Connection. This demo board only has a
single ground plane. This turret should be tied to the GND
terminal of the power supply being used.
JP1: PAR/SER: Selects Parallel or serial programming
mode (Default:Serial)
CMOS/LVDS: In Serial Programming Mode (SER), this
pin should be in the LVDS position to allow for serial data
transfer. (Default: LVDS or up) In the Parallel Programming Mode (PAR), this pin controls the Digital Output
Mode. When this pin is in the CMOS position, the Full-Rate
CMOS Output Mode is enabled. When this pin is in the
LVDS position, the Double Data Rate LVDS Output Mode
(with 3.5mA output current) is enabled. Note:When using
the DC1371, parallel mode DDR LVDS must be selected.
JP2: PGA:In Serial Programming Mode (SER), this pin is
pulled high through a weak pull-up resistor to allow serial
data transfer. In the Parallel Programming Mode (PAR),
this pin controls the Programmable Gain Amplifier frontend, PGA. In the 1x jumper position a front-end gain of
1x is selected, input range of 2.4VP-P. In the 3/2 jumper
position a front-end gain of 1.5x is selected, input range
of 1.6VP-P. (Default:3/2 or up)
RAND: In Serial Programming Mode (SER), this pin
is pulled high through a weak pull-up resistor to allow
serial data transfer. In the Parallel Programming Mode
(PAR), this pin becomes the Digital Output Randomization
Control Bit. When this pin is in the OFF position, digital
output randomization is disabled. When this pin is in the
ON position, digital output randomization is enabled. To
decode the randomized data, exclusive-OR each bit with
the least significant bit. This is done for you in PScope
when the randomizer option is toggled. (Default:ON or up).
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3
DEMO MANUAL DC2183A
quick Start Procedure
JP3: SHUTDOWN:In the RUN position this pin results in
normal operation of the ADC. In the SHDN position the
ADC is powered down and the digital outputs are set in
high impedance state. (Default:RUN or down)
JP4: EEPROM: EEPROM Write Protect. For factory use
only. Should be left in the enable (PROG) position.
JP5: Overflow Test Point:This is a test point for the differential overflow signal. This jumper can be installed to
provide a convenient way to probe the overflow signal.
(Default: removed)
JP6: Clock Term:This jumper provides termination voltages for various signaling standards. LVPECL, CML, and
LVDS termination voltages can be selected. The selected
voltage is then used to terminate the clock input through
50Ω resistors. By removing the jumper completely an external voltage can be applied directly to pin 5 of JP6 so an
arbitrary signaling scheme can be used. (Default:LVPECL)
Applying Power and Signals to the DC2183
Demonstration Circuit
If a DC1371 is used to acquire data from the DC2183,
the DC1371 must FIRST be connected to a powered USB
port and provided an external 5 Volts BEFORE applying
+3.3V to +5.0V across the pins marked VIN and GND on
the DC2183. DC2183 requires at least 3.3V for proper
operation. Regulators on the board produce the voltages
required for the ADC. The DC2183 demonstration circuit
requires up to 800mA. The DC2183 should not be removed
or connected to the DC1371 while power is applied.
4
Analog Input Network
Apply the analog input signal of interest to the SMA connector on the DC2183 demonstration circuit board marked
J2. In the default setup, the DC2183 has an SMA input that
is meant to be driven with a 50Ω source. The DC2183 is
populated with an input diplexer filter to provide a 50Ω
characteristic impedance over all frequencies. This can
be modified to produce different frequency responses
as needed.
In almost all cases, off-board absorptive filters will be
required on the analog input of the DC2183 to produce
data sheet SNR.
The off-board filter should be located close to the input
of the demo board to avoid reflections from impedance
discontinuities at the driven end of a long transmission line.
Most filters do not present 50Ω outside the passband. In
some cases, 3dB to 10dB pads may be required to make
the filter look more absorptive to obtain low distortion.
Encode Clock
Apply an encode clock to the SMA connector on the DC2183
demonstration circuit board marked J3. As a default the
DC2183 is populated to have a single ended clock input.
For the best noise performance, the encode input must
be driven with a very low jitter signal generator source.
The amplitude should be as large as possible up to 2VP–P
or 10dBm.
The DC2183 demo board is designed to accept single
ended signals as a default. To modify the DC2183 to accept a differential signal, remove C31 and populate R18
with a 0Ω resistor. Changing the position of JP6 to CML,
LVDS, or LVPECL selects the proper termination for your
input signal. These SMAs are positioned 0.5” apart to
accommodate LTC differential clock boards.
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DEMO MANUAL DC2183A
quick Start Procedure
Software
The DC1371 is controlled by the PScope System Software
which can be downloaded from the Linear Technology®
website at http://www.linear.com/software/. If a DC1371
was provided, follow the DC1371 Quick Start Guide and
the instructions below.
To start the data collection software, if PScope.exe is installed (by default) in \Program Files\LTC\PScope\, double
click the PScope icon or bring up the run window under
the start menu and browse to the PScope directory and
select PScope.
If the DC2183 demonstration circuit is properly connected
to the DC1371, PScope should automatically detect the
DC2183, and configure itself accordingly. If necessary,
the procedure below explains how to manually configure
PScope.
Under the Configure menu, go to ADC Configuration...
Check the Config Manually box and use the following
configuration options, see Figure 2:
Figure 2. ADC Configuration
If everything is hooked up properly, powered and a suitable convert clock is present, clicking the Collect button
should result in time and frequency plots displayed in
the PScope window. Additional information and help for
PScope is available in the DC1371 quick start guide and in
the online help available within the PScope program itself.
Manual Configuration settings:
Bits: 16
Alignment: 16
FPGA Ld: S2157
Channs: 1
Bipolar: Unchecked
Positive-Edge Clk: Unchecked
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5
DEMO MANUAL DC2183A
quick Start Procedure
Serial Programming
PScope has the ability to program the DC2183 board
serially through the DC1371. There are several options
available for the LTC2107 that are only available through
serial programming. PScope allows all of these features
to be tested.
These options are available by first clicking on the Set
Demo Bd Options icon on the PScope toolbar (Figure 3).
This menu allows any of the options available for the
LTC2107 to be programmed serially. The LTC2107 has
the following options:
Sleep Mode – Selects between normal operation and
sleep mode:
• Off (Default) – Entire ADC is powered, and active
• On – The entire ADC is powered down
Dither – Selects between internal dither being enabled
or disabled:
• Enabled (Default) – Internal dither enabled
Figure 3. PScope Toolbar
This will bring up the menu shown in Figure 4.
• Disabled – Internal dither disabled
Gain (PGS) – Selects input range of the ADC:
• 1.0 (Default) – Selects the 2.4V input range
• 1.5 – Selects the 1.6V input range
Duty Cycle Stabilizer – Enables or disables duty cycle
stabilizer:
• Stabilizer off (Default) – Duty cycle stabilizer disabled
• Stabilizer on – Duty cycle stabilizer enabled
ClkOut Invert – Selects the polarity of the CLKOUT signal:
• Disabled (Default) – Normal CLKOUT polarity
• Enabled – CLKOUT polarity is inverted
ClkOut Phase – Selects the phase delay of the CLKOUT signal:
• 0 deg (Default) – No CLKOUT delay
• 45 deg – CLKOUT delayed by 45 degrees
• 90 deg – CLKOUT delayed by 90 degrees
• 135 deg – CLKOUT delayed by 135 degrees
Keep Alive Osc – Enables or disables the internal keep
alive oscillator:
• Disabled (Default) – Keep alive oscillator is disabled
• Enabled – Keep alive oscillator is enabled
Figure 4. Demobd Configuration Options.
6
dc2183af
DEMO MANUAL DC2183A
Encode Termination – Enables or disables LVDS internal
termination:
• Disabled (Default) – Disables internal termination
ABP – Alternate Bit Polarity (ABP) mode:
• Disabled (Default) – Disables alternate bit polarity
• Enabled – Enables internal termination
• Enabled – Enables alternate bit polarity (Before enabling
ABP, be sure the part is in offset binary mode)
LVDS Current – Selects the LVDS output drive current:
Output Test – Selects digital output test patterns:
• 1.75mA - LVDS output driver current
• None (Default) – ADC data presented at output
• 2.1mA - LVDS output driver current
• All out = 1 – All digital outputs are 1
• 2.5mA - LVDS output driver current
• All out = 0 – All digital outputs are 0
• 3.0mA - LVDS output driver current
• Checkerboard – OF and D15-D0 alternate between 1
0101 0101 1010 0101 and 0 1010 1010 0101 1010
on alternating samples
• 3.5mA (Default) - LVDS output driver current
• 4.0mA - LVDS output driver current
• 4.5mA - LVDS output driver current
Two’s Complement – Enables two’s complement mode:
• Enabled (Default) – Selects two’s complement mode
• Disabled – Selects offset binary mode
• Alternating – Digital outputs alternate between all 1s
and all 0s on alternating samples
Once the desired settings are selected hit OK and PScope
will automatically update the register of the device on the
DC2183 demo board.
Randomizer – Enables data output randomizer:
• Disabled (Default) – Disables data output randomizer
• Enabled – Enables data output randomizer
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7
DEMO MANUAL DC2183A
Parts List
ITEM
QTY
REFERENCE
PART DESCRIPTION
MANUFACTURER/PART NUMBER
CAP., X7R, 0.1µF, 16V 10% 0402
AVX, 0402YC104KAT2A
Required Circuit Components
1
2
C1, C12
2
2
C2, C4
CAP., X5R, 100µF, 16V 20% 1210
TAIYO YUDEN, EMK325ABJ107MM-T
3
2
C3, C22
CAP., X5R, 1µF, 25V 10% 0603
TDK, C1608X5R1E105K080AC
4
3
C5, C6, C7, C31
CAP., X7R, 0.01µF, 16V 10% 0402
TDK, C1005X7R1C103K
5
5
C11, C14, C15, C23, C29
CAP., X5R, 0.1µF, 16V 10% 0402
AVX, 0402YD104KAT2A
6
1
C13
CAP., X5R, 2.2µF, 16V 20% 0603
AVX, 0603YD225MAT2A
7
4
C16, C19, C20, C24
CAP., X5R, 10µF, 16V 20% 1206
TDK, C3216X5R1C106M
8
1
C17
CAP., X5R, 2.2µF, 16V 20% 0402
TDK, C1005X5R1C225M050BC
9
0
C18, C30
CAP., OPT, 0402
OPTION
10
1
C21
CAP., X5R, 47µF, 16V 20% 1206
TDK, C3216X5R1C476M160AB
11
1
C25
CAP., X7R, 10µF, 16V 10% 0805
SAMSUNG, CL21B106KOQNNNE
12
2
C26, C27
CAP., COG, 2200pF, 25V 5% 0402
KEMET, C0402C222J3GACTU
13
0
C28
CAP., OPT, 0201
OPTION
14
1
E1
TEST POINT, TURRET, .061, PBF
MILL-MAX, 2308-2-00-80-00-00-07-0
15
2
E2, E3
TEST POINT, TURRET, .094, PBF
MILL-MAX, 2501-2-00-80-00-00-07-0
16
3
JP1, JP2, JP6
HEADER, 2X3 PIN, 0.079CC
SULLINS, NRPN032PAEN-RC
17
2
JP3, JP4
HEADER, 3 PIN 0.079 SINGLE ROW
SULLINS, NRPN031PAEN-RC
18
0
JP5
JUMPER, 2PINS, .079 CTR, OPTION
OPTION
19
0
J1
CON.,MMCX, RIGHT ANGLE, THRU-HOLE, OPTION
AMPHENOL CONNEX, 262105
20
1
J2
CON., SMA 50Ω EDGE-LAUNCH
AMPHENOL CONNEX, 132372
21
2
J3, J4
CON.,SMA JACK, STRAIGHT, THRU-HOLE
AMPHENOL CONNEX, 132134
22
0
L2
INDUCTOR, OPTION, 0603
OPTION
23
1
L3
FERRITE BEAD, 47ΩS@100mhz, 0603
MURATA, BLM18BB470SN1D
24
1
P1
BGA CONNECTOR, 40X10
SAMTEC, SEAM-40-02.0-S-10-2-A-K-TR
25
6
R1, R6, R7, R8, R14, R17
RES., CHIP, 1k, 1/16W, 5% 0402
VISHAY, CRCW04021K00JNED
26
1
R2, R9, R10
RES., CHIP, 0ΩS JUMPER, 1/16W, 0402
VISHAY, CRCW04020000Z0ED
27
3
R3, R4, R5
RES., CHIP, 4.99k, 1/16W, 1% 0402
VISHAY, CRCW04024K99FKED
28
2
R11, R12
RES., CHIP, 33.2ΩS, 1/16W, 1% 0402
VISHAY, CRCW040233R2FKED
29
2
R15, R16
RES., CHIP, 100ΩS, 1/16W, 5% 0402
VISHAY, CRCW0402100RJNED
30
0
R18, R20, R23
RES., CHIP, OPT, 0402
OPTION
31
1
R21
RES., CHIP, 49.9ΩS, 1/8W, 1% 0402
VISHAY, CRCW040249R9FKEDHP
32
0
R22
RES., CHIP, OPT, 0603
OPTION
33
4
R24, R29, R30, R31
RES., CHIP, 33ΩS, 1/16W, 5% 0402
VISHAY, CRCW040233R0JNED
34
0
R25
RES., CHIP, OPT, 0805
OPTION
35
2
R34, R36
RES., CHIP, 24.9ΩS, 1/16W, 1% 0402
VISHAY, CRCW040224R9FKED
36
1
R37
RES., CHIP, 200Ω, 1/20W, 1% 0201
VISHAY, CRCW0201200RFKED
37
2
T1, T3
TRANSFORMER, RF,SMT, 1:1BALUN
MACOM, MABA-007159-000000
MACOM, MABAES0060
38
1
T2
TRANSFORMER, RF 1:1 FLUX COUPLED, SMT
39
1
U2
IC, LDO LINEAR REGULATOR, 2.5V, DFN
LINEAR TECH., LT1965EDD-2.5#PBF
40
1
U3
IC, LDO LINEAR REGULATOR, 1.8V, DFN
LINEAR TECH., LT1965EDD-1.8#PBF
41
1
U4
IC, SERIAL EEPROM, TSSOP
MICROCHIP TECH., 24LC32A-I/ST
42
7
XJP1, XJP2, XJP3, XJP4,
XJP5, XJP6, XJP7
SHUNT, 2MM
SAMTEC, 2SN-BK-G
8
dc2183af
DEMO MANUAL DC2183A
ITEM
QTY
REFERENCE
PART DESCRIPTION
MANUFACTURER/PART NUMBER
DC2183A-A Required Circuit Components
1
1
DC2183A
DC2183A General BOM
2
1
C8
CAP., NP0, 4.7pF, 50V ± 0.25pF, 0402
TDK, C1005C0G1H4R7C
3
2
C9,C10
CAP., NP0, 8.2pF, 50V ± 0.25pF 0402
TDK, C1005C0G1H8R2C
4
1
L1
INDUCTOR, CERAMIC CHIP, 56nH, 2%, 0603
MURATA, LQP18MN56NG02D
5
2
R13,R19
RES., CHIP, 15Ω, 1/20W, 5% 0201
VISHAY, CRCW020115R0JNED
6
0
R26,R28
RES., CHIP, OPT, 0402
OPTION
7
2
R27,R32
RES., CHIP, 86.6, 1/10W, 1% 0603
VISHAY, CRCW060386R6FKEA
8
1
R33
RES., CHIP, 86.6, 1/16W, 1% 0402
VISHAY, CRCW040286R6FKED
9
1
U1
ADC, 16 BIT, 210 Msps, QFN
LINEAR TECH., LTC2107IUK#PBF
DC2183A-B Required Circuit Components
1
1
DC2183A
DC2183A General BOM
2
1
C8
CAP., NP0, 12pF, 50V 5% 0402
MURATA, GRM1555C1H120JA01D
3
2
C9,C10
CAP., NP0, 3.9pF, 50V ± 0.25pF 0402
TDK, C1005C0G1H3R9C
4
1
L1
INDUCTOR, CERAMIC CHIP, 18nH, 2%, 0603
MURATA, LQP18MN18NG02D
5
2
R13,R19
RES., CHIP, 10Ω, 1/20W, 5% 0201
VISHAY, CRCW020110R0JNED
6
2
R26,R28
RES., CHIP, 68.1Ω, 1/16W, 1% 0402
VISHAY, CRCW040268R1FKED
7
2
R27,R32
RES., CHIP, 43.2, 1/10W, 1% 0603
VISHAY, CRCW060343R2FKEA
8
1
R33
RES., CHIP, 105Ω, 1/16W, 1% 0402
VISHAY, CRCW0402105RFKED
9
1
U1
ADC, 16 BIT, 210 Msps, QFN
LINEAR TECH., LTC2107IUK#PBF
dc2183af
9
A
B
C
J2
J4
J3
1
JP3
1
1
R8
1K
2
PGA/SCK
VDD
SHDN
SHUTDOWN
CLK-
CLK+
AIN
R22
OPT
5
5
1X
1
3
JP2
3/2
R1
SHDN
RUN
R7
1K
VDD
OPT
0 OHMS
R18
R2
0.01uF
C6
6
4
2
1K
OFF
ON
3
5
CMOS
1
JP1
0.01uF
C7
LVDS
RAND/SDI
CS/LVDS
R6
1K
VDD
C10 *
5
4
6
4
2
1
SER
PAR
2
R17
1K
JP6
R10 0
R12
33.2
R11
33.2
4
6
3
5
4
C3
1.0uF
PAR/!SER
2
1
C30
OPT
T3
C13
2.2uF
1
2
3
OPT
0402
C18
1.0uF
C22
1206
20%
47uF
C21
VDD
R34
24.9
3
C15
0.1uF
OVDD
C29 0.1uF
R36
24.9
R37
200
0201
R20
OPT
0.1uF
C11
R23
OPT
C17
2.2uF
C14
0.1uF
C25
10uF
0805
DC2183A-A
DC2183A-B
ASSEMBLY TYPE
GND
VCM
GND
AIN-
AIN+
GND
VDD
VDD
VDD
GND
GND
210
210
Msps
R16 100
OVDD
U1*
CUSTOMER NOTICE
16
16
BITS
C27
2200pF
COG/NPO
SHDN
C26
2200pF
COG/NPO
42
C8
12pF
4.7pF
JP5
OPT
1
18nH
SIZE
OF+
IC NO.
43.2
86.6
R27,R32
25
26
27
28
29
30
31
32
33
34
35
36
1
SDO
56nH
L1
TP1
D5/D4N
D5/D4P
D7/6N
D7/6P
D9/8N
D9/8P
CLKOUTN
CLKOUTP
D11/D10N
D11/10P
D13/12N
CONTRACT NO.
3.9pF
8.2pF
C9,C10
SDO
OVDD
2
D13/12P
OF-
2
-
105
86.6
R33
PGA/SCK
RAND/SDI
CS/LVDS
REV
ECO
2
THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND
SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS.
DATE:
A
1
68.1
OPT
C.MAYOTT
10
15
R19,R13
D1/0-
D1/0+
D3/2-
D3/2+
D5/4-
D5/4+
D7/6-
D7/6+
D9/8-
D9/8+
Fin (MHz)
5< Fin <70
70< Fin <180
CLKOUT-
CLKOUT+
D11/10-
D11/10+
D13/12-
D13/12+
D15/14-
D15/14+
OF-
OF+
DATE
03-14-14
APPROVED
03-18-2014
1
SHEET
LTC2107
DEMO CIRCUIT 2183A
16-BIT, 210 Msps ADC
1 OF 2
2
REV
1630 McCarthy Blvd.
Milpitas, CA 95035
Phone: (408)432-1900
Fax: (408)434-0507
LTC Confidential-For Customer Use Only
R26,R28
PRODUCTION
DESCRIPTION
REVISION HISTORY
LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A
APPROVALS
CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS;
TECHNOLOGY
HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TO PCB DES. M.HAWKINS
VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL
ENG. C.MAYOTT TITLE: SCHEMATIC
APPLICATION. COMPONENT SUBSTITUTION AND PRINTED
CIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT
PERFORMANCE OR RELIABILITY. CONTACT LINEAR
TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE.
LTC2107IUK
PAR/!SER
SENSE
C28
OPT
0201
12
11
10
9
8
7
6
5
4
3
2
1
LTC2107IUK
U1
*ASSEMBLY OPTIONS TABLE
VDD
EXT
REF
E1
R14
1K
2
43
Figure 5. DC2183A Demo Circuit Schematic, Page 1
C31
0.01uF
5
4
MABA-007159-000000
LVDS
CML
R21
49.9
0201
R13*
0201
R19 *
R15 100
C8 *
C12
0.1uF
CLOCK TERM
C5
0.01uF
R28 *
1
2
3
LV PECL
OPT
0603
L2
C1
0.1uF
5
4
T2
MABAES0060
VDD
VDD
1
2
3
MABA-007159-000000
C9 *
2
R32 *
L1 *
R27 *
1
R26 *
48
T1
0
47
R33*
R9
3
41
1
4
40
J1 MMCX (OPTION)
1
3
39
D
PGA
RAND
GND
49
46
GND
GND
13
44
SCK
45
GND
ENC+
14
PAR/SER
ENC15
CS
GND
16
SDI
SDO
18
SHDN
17
OGND
OGND
19
OVDD
OVdd
20
OFP
D1/D0N
21
OFN
37
D15/14N
D3/D2P
38
D15/14P
D1/D0P
22
D3/D2N
23
10
24
5
A
B
C
D
DEMO MANUAL DC2183A
Schematic Diagram
dc2183af
A
B
C
D
E2
GND
E3
3.3V-5V
VIN
PG_M2C
GND
GND
HA00_P_CC
HA00_N_CC
GND
HA04_P
HA04_N
GND
HA08_P
HA08_N
GND
HA12_P
HA12_N
GND
HA15_P
HA15_N
GND
HA19_P
HA19_N
GND
HB02_P
HB02_N
GND
HB04_P
HB04_N
GND
HB08_P
HB08_N
GND
HB12_P
HB12_N
GND
HB16_P
HB16_N
GND
HB19_P
HB19_N
GND
VADJ
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
F23
F24
F25
F26
F27
F28
F29
F30
F31
F32
F33
F34
F35
F36
F37
F38
F39
F40
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
5
C24
10uF
16V
1206
VIN
SEAM-10X40PIN
P1F
SEAM-10X40PIN
GND
DP1_M2C_P
DP1_M2C_N
GND
GND
DP2_M2C_P
DP2_M2C_N
GND
GND
DP3_M2C_P
DP3_M2C_N
GND
GND
DP4_M2C_P
DP4_M2C_N
GND
GND
DP5_M2C_P
DP5_M2C_N
GND
GND
DP1_C2M_P
DP1_C2M_N
GND
GND
DP2_C2M_P
DP2_C2M_N
GND
GND
DP3_C2M_P
DP3_C2M_N
GND
GND
DP4_C2M_P
DP4_C2M_N
GND
GND
DP5_C2M_P
DP5_C2M_N
GND
VDD
6
7
8
OUT
OUT
SHDN SENSE
IN
IN
L3
FERRITE BEAD, 47 OHMS
3
4
C19
10uF
16V
1206
6
U3
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
H11
H12
H13
H14
H15
H16
H17
H18
H19
H20
H21
H22
H23
H24
H25
H26
H27
H28
H29
H30
H31
H32
H33
H34
H35
H36
H37
H38
H39
H40
SDA
OUT
OUT
SHDN SENSE
IN
IN
P1D
3
C20
10uF
16V
1206
OVDD
D1/0-
D5/4-
D9/8-
D13/12-
SEAM-10X40PIN
3
C4
100uF
16V
1210
CLKOUT+
CLKOUT-
DATA CLOCK
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
J11
J12
J13
J14
J15
J16
J17
J18
J19
J20
J21
J22
J23
J24
J25
J26
J27
J28
J29
J30
J31
J32
J33
J34
J35
J36
J37
J38
J39
J40
R25
OPT
VIN
3.3V_AUX
GND
CLK1_C2M_P
CLK1_C2M_N
GND
GND
HA03_P
HA03_N
GND
HA07_P
HA07_N
GND
HA11_P
HA11_N
GND
HA14_P
HA14_N
GND
HA18_P
HA18_N
GND
HA22_P
HA22_N
GND
HB01_P
HB01_N
GND
PB07_P
HB07_N
GND
HB11_P
HB11_N
GND
HB15_P
HB15_N
GND
HB18_P
HB18_N
GND
VIO_B_M2C
GND
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37
D38
D39
D40
GND
HA01_P_CC
HA01_N_CC
GND
GND
HA05_P
HA05_N
GND
HA09_P
HA09_N
GND
HA13_P
HA13_N
GND
HA16_P
HA16_N
GND
HA20_P
HA20_N
GND
HB03_P
HB03_N
GND
HB05_P
HB05_N
GND
HB09_P
HB09_N
GND
HB13_P
HB13_N
GND
HB21_P
HB21_N
GND
HB20_P
HB20_N
GND
VADJ
GND
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
K11
K12
K13
K14
K15
K16
K17
K18
K19
K20
K21
K22
K23
K24
K25
K26
K27
K28
K29
K30
K31
K32
K33
K34
K35
K36
K37
K38
K39
K40
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
E23
E24
E25
E26
E27
E28
E29
E30
E31
E32
E33
E34
E35
E36
E37
E38
E39
E40
U4
24LC32A
SDA
SCL
6
5
7
3
2
1
4.99K
R5
4.99K
R3
CONTRACT NO.
X12
X6
IC NO.
X11
X5
SIZE
X10
X4
2
THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND
SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS.
DATE:
A
2
X16
X15
X14
X13
03-18-2014
1
SHEET
LTC2107
DEMO CIRCUIT 2183A
16-BIT, 210 Msps ADC
2 OF 2
2
REV
1630 McCarthy Blvd.
Milpitas, CA 95035
Phone: (408)432-1900
Fax: (408)434-0507
LTC Confidential-For Customer Use Only
WP
PROG
EEPROM
JP4
R4
4.99K
3.3V_AUX
1
CHASSIS GROUND
X9
X8
X7
X3
X2
X1
TRANSFER STRIP
MOUNTING HOLES ON THERMAL
SCL
SDA
WP
A2
A1
A0
0.1uF
C23
SDA
SCL
LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A
APPROVALS
CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS;
TECHNOLOGY
HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TO PCB DES. M.HAWKINS
VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL
ENG. C.MAYOTT TITLE: SCHEMATIC
APPLICATION. COMPONENT SUBSTITUTION AND PRINTED
CIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT
PERFORMANCE OR RELIABILITY. CONTACT LINEAR
TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE.
CUSTOMER NOTICE
SEAM-10X40PIN
VREF_B_M2C
GND
GND
CLK1_M2C_P
CLK1_M2C_N
GND
HA02_P
HA02_N
GND
HA06_P
HA06_N
GND
HA10_P
HA10_N
GND
HA17_P_CC
HA17_N_CC
GND
HA21_P
HA21_N
GND
HA23_P
HA23_N
GND
HB00_P_CC
HB00_N_CC
GND
HB06_P_CC
HB06_N_CC
GND
HB10_P
HB10_N
GND
HB14_P
HB14_N
GND
HB17_P_CC
HB17_N_CC
GND
VIO_B_M2C
P1K
SEAM-10X40PIN
P1E
2
Figure 6. DC2183A Demo Circuit Schematic, Page 2
3
2
1
D1/0+
D5/4+
D9/8+
D13/12+
P1J
SEAM-10X40PIN
PG_C2M
GND
GND
GBTCLK0_M2C_P
GBTCLK0_M2C_N
GND
GND
LA01_P_CC
LA01_N_CC
GND
LA05_P
LA05_N
GND
LA09_P
LA09_N
GND
LA13_P
CS/LVDS
LA13_N
GND
LA17_P_CC
LA17_N_CC
SDO
GND
LA23_P
RAND/SDI
LA23_N
GND
LA26_P
LA26_N
PGA/SCK
GND
TCK
TDI
TDO
3P3VAUX
TMS
TRST_N
GA1
3P3V
GND
3P3V
GND
3P3V
LT1965EDD-1.8
SEAM-10X40PIN
7
C2
100uF
16V
1210
OF-
D3/2-
D7/6-
D11/10-
D15/14-
SCL
R31 33
R24 33
R30 33
R29 33
VREF_A_M2C
PRSNT_M2C_N
GND
CLK0_M2C_P
CLK0_M2C_N
GND
LA02_P
LA02_N
GND
LA04_P
LA04_N
GND
LA07_P
LA07_N
GND
LA11_P
LA11_N
GND
LA15_P
LA15_N
GND
LA19_P
LA19_N
GND
LA21_P
LA21_N
GND
LA24_P
LA24_N
GND
LA28_P
LA28_N
GND
LA30_P
LA30_N
GND
LA32_P
LA32_N
GND
VADJ
P1H
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
C33
C34
C35
C36
C37
C38
C39
C40
2
C16
10uF
16V
1206
VDD
D3/2+
D7/6+
D11/10+
D15/14+
OF+
GND
DP0_C2M_P
DP0_C2M_N
GND
GND
DP0_M2C_P
DP0_M2C_N
GND
GND
LA06_P
LA06_N
GND
GND
LA10_P
LA10_N
GND
GND
LA14_P
LA14_N
GND
GND
LA18_P_CC
LA18_N_CC
GND
GND
LA27_P
LA27_N
GND
GND
SCL
SDA
GND
GND
GA0
12P0V
GND
12P0V
GND
3P3V
GND
SEAM-10X40PIN
P1C
8
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
G12
G13
G14
G15
G16
G17
G18
G19
G20
G21
G22
G23
G24
G25
G26
G27
G28
G29
G30
G31
G32
G33
G34
G35
G36
G37
G38
G39
G40
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
1
LT1965EDD-2.5
U2
SEAM-10X40PIN
GND
CLK0_C2M_P
CLK0_C2M_N
GND
GND
LA00_P_CC
LA00_N_CC
GND
LA03_P
LA03_N
GND
LA08_P
LA08_N
GND
LA12_P
LA12_N
GND
LA16_P
LA16_N
GND
LA20_P
LA20_N
GND
LA22_P
LA22_N
GND
LA25_P
LA25_N
GND
LA29_P
LA29_N
GND
LA31_P
LA31_N
GND
LA33_P
LA33_N
GND
VADJ
GND
P1G
SEAM-10X40PIN
RES1
GND
GND
DP9_M2C_P
DP9_M2C_N
GND
GND
DP8_M2C_P
DP8_M2C_N
GND
GND
DP7_M2C_P
DP7_M2C_N
GND
GND
DP6_M2C_P
DP6_M2C_N
GND
GND
GBTCLK1_M2C_P
GBTCLK1_M2C_N
GND
GND
DP9_C2M_P
DP9_C2M_N
GND
GND
DP8_C2M_P
DP8_C2M_N
GND
GND
DP7_C2M_P
DP7_C2M_N
GND
GND
DP6_C2M_P
DP6_C2M_N
GND
GND
RES0
P1B
4
GND
P1A
GND
5
GND
9
GND
4
GND
5
GND
9
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
4
8
VCC
VSS
4
1
3
5
A
B
C
D
DEMO MANUAL DC2183A
Schematic Diagram
11
dc2183af
DEMO MANUAL DC2183A
DEMONSTRATION BOARD IMPORTANT NOTICE
Linear Technology Corporation (LTC) provides the enclosed product(s) under the following AS IS conditions:
This demonstration board (DEMO BOARD) kit being sold or provided by Linear Technology is intended for use for ENGINEERING DEVELOPMENT
OR EVALUATION PURPOSES ONLY and is not provided by LTC for commercial use. As such, the DEMO BOARD herein may not be complete
in terms of required design-, marketing-, and/or manufacturing-related protective considerations, including but not limited to product safety
measures typically found in finished commercial goods. As a prototype, this product does not fall within the scope of the European Union
directive on electromagnetic compatibility and therefore may or may not meet the technical requirements of the directive, or other regulations.
If this evaluation kit does not meet the specifications recited in the DEMO BOARD manual the kit may be returned within 30 days from the date
of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY THE SELLER TO BUYER AND IS IN LIEU
OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS
FOR ANY PARTICULAR PURPOSE. EXCEPT TO THE EXTENT OF THIS INDEMNITY, NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR
ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES.
The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user releases LTC from all claims
arising from the handling or use of the goods. Due to the open construction of the product, it is the user’s responsibility to take any and all
appropriate precautions with regard to electrostatic discharge. Also be aware that the products herein may not be regulatory compliant or
agency certified (FCC, UL, CE, etc.).
No License is granted under any patent right or other intellectual property whatsoever. LTC assumes no liability for applications assistance,
customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind.
LTC currently services a variety of customers for products around the world, and therefore this transaction is not exclusive.
Please read the DEMO BOARD manual prior to handling the product. Persons handling this product must have electronics training and
observe good laboratory practice standards. Common sense is encouraged.
This notice contains important safety information about temperatures and voltages. For further safety concerns, please contact a LTC application
engineer.
Mailing Address:
Linear Technology
1630 McCarthy Blvd.
Milpitas, CA 95035
Copyright © 2004, Linear Technology Corporation
12 Linear Technology Corporation
dc2183af
LT 0714 • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
 LINEAR TECHNOLOGY CORPORATION 2014