Microchip MCP3221A5T-I/OT Low power 12-bit a/d converter with i2c interface Datasheet

M
MCP3221
Low Power 12-Bit A/D Converter With I2C™ Interface
Features
Description
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The Microchip Technology Inc. MCP3221 is a successive approximation A/D converter with 12-bit resolution. Available in the SOT-23 package, this device
provides one single-ended input with very low power
consumption. Based on an advanced CMOS technology, the MCP3221 provides a low maximum conversion current and standby current of 250 µA and 1 µA,
respectively. Low current consumption, combined with
the small SOT-23 package, make this device ideal for
battery-powered and remote data acquisition
applications.
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12-bit resolution
±1 LSB DNL, ±2 LSB INL max.
250 µA max conversion current
5 nA typical standby current, 1 µA max.
I2C™ compatible serial interface
- 100 kHz I2C Standard Mode
- 400 kHz I2C Fast Mode
Up to 8 devices on a single 2-Wire bus
22.3 ksps in I2C Fast Mode
Single-ended analog input channel
On-chip sample and hold
On-chip conversion clock
Single-supply specified operation: 2.7V to 5.5V
Temperature range:
- Industrial: -40°C to +85°C
- Extended: -40°C to +125°C
Small SOT-23 package
Applications
•
•
•
•
•
Data Logging
Multi-zone Monitoring
Hand-Held Portable Applications
Battery-Powered Test Equipment
Remote or Isolated Data Acquisition
Communication to the MCP3221 is performed using a
2-wire, I2C compatible interface. Standard (100 kHz)
and Fast (400 kHz) I2C modes are available with the
device. An on-chip conversion clock enables independent timing for the I2C and conversion clocks. The
device is also addressable, allowing up to eight devices
on a single 2-wire bus.
The MCP3221 runs on a single supply voltage that
operates over a broad range of 2.7V to 5.5V. This
device also provides excellent linearity of ±1 LSB differential non-linearity and ±2 LSB integral non-linearity,
maximum.
Functional Block Diagram
VDD
Package Type
DAC
5-Pin SOT-23A
VSS 2
Comparator
5
SCL
MCP3221
VDD 1
VSS
AIN 3
AIN
–
Sample
and
Hold
12-bit SAR
+
Clock
Control Logic
I2C™ Interface
4 SDA
SCL
 2003 Microchip Technology Inc.
SDA
DS21732B-page 1
MCP3221
1.0
ELECTRICAL
CHARACTERISTICS
PIN FUNCTION TABLE
Name
Function
Absolute Maximum Ratings †
VDD
+2.7V to 5.5V Power Supply
VDD...................................................................................7.0V
VSS
Ground
Analog input pin w.r.t. VSS .......... ............. -0.6V to VDD +0.6V
AIN
Analog Input
SDA and SCL pins w.r.t. VSS........... .........-0.6V to VDD +1.0V
SDA
Serial Data In/Out
Storage temperature .....................................-65°C to +150°C
SCL
Serial Clock In
Ambient temp. with power applied ................-65°C to +125°C
Maximum Junction Temperature .......... .........................150°C
ESD protection on all pins (HBM) .................................≥ 4 kV
† Stresses above those listed under “Maximum ratings” may
cause permanent damage to the device. This is a stress rating
only and functional operation of the device at those or any
other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum
rating conditions for extended periods may affect device reliability.
DC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise noted, all parameters apply at VDD = 5.0V, VSS = GND, RPU = 2 kΩ
TAMB = -40°C to +85°C, I2C Fast Mode Timing: fSCL = 400 kHz (Note 3).
Parameters
Sym
Min
Typ
Max
Units
Conditions
DC Accuracy
Resolution
12
Integral Nonlinearity
INL
Differential Nonlinearity
DNL
—
bits
±0.75
±2
LSB
—
±0.5
±1
LSB
Offset Error
—
±0.75
±2
LSB
No missing codes
Gain Error
—
-1
±3
LSB
THD
—
-82
—
dB
VIN = 0.1V to 4.9V @ 1 kHz
Signal-to-Noise and Distortion
SINAD
—
72
—
dB
VIN = 0.1V to 4.9V @ 1 kHz
Spurious-Free Dynamic Range
SFDR
—
86
—
dB
VIN = 0.1V to 4.9V @ 1 kHz
VSS-0.3
—
VDD+0.3
V
2.7V ≤ VDD ≤ 5.5V
-1
—
+1
µA
Dynamic Performance
Total Harmonic Distortion
Analog Input
Input Voltage Range
Leakage Current
SDA/SCL (open-drain output):
Data Coding Format
Straight Binary
High-level input voltage
VIH
0.7 VDD
—
—
V
Low-level input voltage
VIL
—
—
0.3 VDD
V
VOL
—
—
0.4
V
IOL = 3 mA, RPU = 1.53 kΩ
VHYST
—
0.05 VDD
—
V
fSCL = 400 kHz only
Low-level output voltage
Hysteresis of Schmitt trigger inputs
Note 1:
2:
3:
4:
5:
“Sample time” is the time between conversions once the address byte has been sent to the converter.
Refer to Figure 5-6.
This parameter is periodically sampled and not 100% tested.
RPU = Pull-up resistor on SDA and SCL.
SDA and SCL = VSS to VDD at 400 kHz.
tACQ and tCONV are dependent on internal oscillator timing. See Figure 5-5 and Figure 5-6 for relation to
SCL.
DS21732B-page 2
 2003 Microchip Technology Inc.
MCP3221
DC ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: Unless otherwise noted, all parameters apply at VDD = 5.0V, VSS = GND, RPU = 2 kΩ
TAMB = -40°C to +85°C, I2C Fast Mode Timing: fSCL = 400 kHz (Note 3).
Parameters
Input leakage current
Output leakage current
Sym
Min
Typ
Max
Units
Conditions
ILI
-1
—
+1
µA
VIN = 0.1 VDD and 0.9 VDD
ILO
-1
—
+1
µA
VOUT = 0.1 VSS and 0.9 VDD
CIN,
COUT
—
—
10
pF
TAMB = 25°C, f = 1 MHz;
(Note 2)
CB
—
—
400
pF
SDA drive low, 0.4V
VDD
2.7
—
5.5
V
Conversion Current
IDD
—
175
250
µA
Standby Current
IDDS
—
0.005
1
µA
SDA, SCL = VDD
Active bus current
IDDA
—
—
120
µA
Note 4
Conversion Time
tCONV
—
8.96
—
µs
Note 5
Analog Input Acquisition Time
tACQ
—
1.12
—
µs
Note 5
Sample Rate
fSAMP
—
—
22.3
ksps
Pin capacitance
(all inputs/outputs)
Bus Capacitance
Power Requirements
Operating Voltage
Conversion Rate
Note 1:
2:
3:
4:
5:
fSCL = 400 kHz (Note 1)
“Sample time” is the time between conversions once the address byte has been sent to the converter.
Refer to Figure 5-6.
This parameter is periodically sampled and not 100% tested.
RPU = Pull-up resistor on SDA and SCL.
SDA and SCL = VSS to VDD at 400 kHz.
tACQ and tCONV are dependent on internal oscillator timing. See Figure 5-5 and Figure 5-6 for relation to
SCL.
TEMPERATURE SPECIFICATIONS
Electrical Characteristics: Unless otherwise noted, all parameters apply at VDD = 5.0V, VSS = GND.
Parameters
Symbol
Min
Typ
Max
Units
Industrial Temperature Range
TA
-40
—
+85
°C
Extended Temperature Range
TA
-40
—
+125
°C
Operating Temperature Range
TA
-40
—
+125
°C
Storage Temperature Range
TA
-65
—
+150
°C
θJA
—
256
—
°C/W
Conditions
Temperature Ranges
Thermal Package Resistances
Thermal Resistance, 5L-SOT23A
 2003 Microchip Technology Inc.
DS21732B-page 3
MCP3221
TIMING SPECIFICATIONS
Electrical Characteristics: All parameters apply at VDD = 2.7V - 5.5V, VSS = GND, TAMB = -40°C to +85°C.
Parameters
Sym
Min
Typ
Max
Units
Conditions
2
I C Standard Mode
Clock frequency
fSCL
0
—
100
kHz
Clock high time
THIGH
4000
—
—
ns
Clock low time
TLOW
4700
—
—
ns
TR
—
—
1000
ns
From V L to VIH (Note 1)
From V L to VIH (Note 1)
SDA and SCL rise time
TF
—
—
300
ns
THD:STA
4000
—
—
ns
START condition setup time
TSU:STA
4700
—
—
ns
Data input setup time
TSU:DAT
250
—
—
ns
STOP condition setup time
TSU:STO
4000
—
—
ns
STOP condition hold time
THD:STD
4000
—
—
ns
SDA and SCL fall time
START condition hold time
Output valid from clock
TAA
—
—
3500
ns
Bus free time
TBUF
4700
—
—
ns
Note 2
Input filter spike suppression
TSP
—
—
50
ns
SDA and SCL pins (Note 1)
I2C Fast Mode
Clock frequency
FSCL
0
—
400
kHz
Clock high time
THIGH
600
—
—
ns
Clock low time
TLOW
1300
—
—
ns
TR
20 + 0.1CB
—
300
ns
From V L to VIH (Note 1)
From V L to VIH (Note 1)
SDA and SCL rise time
TF
20 + 0.1CB
—
300
ns
THD:STA
600
—
—
ns
START condition setup time
TSU:STA
600
—
—
ns
Data input hold time
THD:DAT
0
—
0.9
ms
SDA and SCL fall time
START condition hold time
Data input setup time
TSU:DAT
100
—
—
ns
STOP condition setup time
TSU:STO
600
—
—
ns
STOP condition hold time
THD:STD
600
—
—
ns
Output valid from clock
TAA
—
—
900
ns
Bus free time
TBUF
1300
—
—
ns
Note 2
Input filter spike suppression
TSP
—
—
50
ns
SDA and SCL pins (Note 1)
Note 1:
2:
This parameter is periodically sampled and not 100% tested.
Time the bus must be free before a new transmission can start.
THIGH
TF
SCL
SDA
IN
SDA
OUT
FIGURE 1-1:
DS21732B-page 4
VHYS
TR
TSU:STA
TLOW
TSP
THD:DAT
TSU:DAT
TSU:STO
THD:STA
TAA
TBUF
Standard and Fast Mode Bus Timing Data.
 2003 Microchip Technology Inc.
MCP3221
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
INL (LSB)
Positive INL
Negative INL
0
100
INL (LSB)
FIGURE 2-1:
200
300
2
I C Bus Rate (kHz)
3.5
4
VDD (V)
4.5
FIGURE 2-4:
(VDD = 2.7V).
5
200
300
400
INL vs. Clock Rate
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
Positive INL
Negative NL
2.5
5.5
3
3.5
4
4.5
5
5.5
VDD (V)
FIGURE 2-2:
INL vs. VDD - I2C™
Standard Mode (fSCL = 100 kHz).
FIGURE 2-5:
INL vs. VDD - I2C™ Fast
Mode (fSCL = 400 kHz).
2
2
1.5
1.5
1
INL (LSB)
1
INL (LSB)
100
2
Negative INL
3
Negative INL
0
Positive NL
2.5
Positive INL
I C Bus Rate (kHz)
INL vs. Clock Rate.
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
400
INL (LSB)
INL (LSB)
Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, I2C Fast Mode Timing (SCL = 400 kHz), Continuous Conversion
Mode (fSAMP = 22.3 ksps), TA = +25°C.
0.5
0
-0.5
0.5
0
-0.5
-1
-1
-1.5
-1.5
-2
-2
0
1024
2048
Digital Code
FIGURE 2-3:
INL vs. Code
(Representative Part).
 2003 Microchip Technology Inc.
3072
4096
0
1024
2048
3072
4096
Digital Code
FIGURE 2-6:
INL vs. Code
(Representative Part, VDD = 2.7V).
DS21732B-page 5
MCP3221
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
Positive INL
INL (LSB)
INL (LSB)
Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, I2C Fast Mode Timing (SCL = 400 kHz), Continuous Conversion
Mode (fSAMP = 22.3 ksps), TA = +25°C.
Negative INL
-50
-25
0
25
50
75
100
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
125
Positive NL
Negative INL
-50
-25
0
Temperature (°C)
INL vs. Temperature.
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
FIGURE 2-10:
(VDD = 2.7V).
Positive DNL
DNL (LSB)
DNL (LSB)
FIGURE 2-7:
Negative DNL
0
100
200
300
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
400
100
DNL (LSB)
FIGURE 2-11:
(VDD = 2.7V).
DNL (LSB)
4.5
VDD (V)
FIGURE 2-9:
DNL vs. VDD - I2C™
Standard Mode (fSCL = 100 kHz).
200
300
400
2
Negative DNL
DS21732B-page 6
125
I C Bus Rate (kHz)
DNL vs. Clock Rate.
3.5
100
Negative DNL
0
Positive DNL
2.5
75
Positive DNL
2
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
50
INL vs. Temperature
I C Bus Rate (kHz)
FIGURE 2-8:
25
Temperature (°C)
5.5
DNL vs. Clock Rate
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
Positive DNL
Negative DNL
2.5
3
3.5
4
4.5
5
5.5
VDD (V)
FIGURE 2-12:
DNL vs. VDD - I2C™ Fast
Mode (fSCL = 400 kHz).
 2003 Microchip Technology Inc.
MCP3221
Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, I2C Fast Mode Timing (SCL = 400 kHz), Continuous Conversion
Mode (fSAMP = 22.3 ksps), TA = +25°C.
DNL (LSB)
DNL (LSB)
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
0
1024
2048
3072
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
0
4096
1024
2048
Digital Code
Positive DNL
Negative DNL
-50
-25
0
25
50
75
100
125
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
Positive DNL
Negative DNL
-50
-25
Temperature (°C)
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
-0.9
-1
DNL vs. Temperature.
Fast Mode
(fSCL=100 kHz)
2.5
3
3.5
4.5
5
VDD (V)
FIGURE 2-15:
FIGURE 2-17:
(VDD = 2.7V).
Standard Mode
(fSCL=400 kHz)
4
Gain Error vs. VDD.
 2003 Microchip Technology Inc.
0
25
50
75
100
125
Temperature (°C)
Offset Error (LSB)
Gain Error (LSB)
FIGURE 2-14:
4096
FIGURE 2-16:
DNL vs. Code
(Representative Part, VDD = 2.7V).
DNL (LSB)
DNL (LSB)
FIGURE 2-13:
DNL vs. Code
(Representative Part).
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
3072
Digital Code
5.5
DNL vs. Temperature
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
fSCL = 100 kHz & 400 kHz
2.5
FIGURE 2-18:
3
3.5
4
VDD (V)
4.5
5
5.5
Offset Error vs. VDD.
DS21732B-page 7
MCP3221
Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, I2C Fast Mode Timing (SCL = 400 kHz), Continuous Conversion
Mode (fSAMP = 22.3 ksps), TA = +25°C.
3
Offset Error (LSB)
Gain Error (LSB)
2
VDD = 2.7V
1
0
-1
-2
VDD = 5V
-3
-50
-25
0
25
50
75
100
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
125
VDD = 5V
VDD = 2.7V
-50
-25
0
Temperature (°C)
Gain Error vs. Temperature.
100
90
80
70
60
50
40
30
20
10
0
FIGURE 2-22:
Temperature.
VDD = 5V
SINAD (dB)
SNR (dB)
FIGURE 2-19:
VDD = 2.7V
1
10
75
100
125
VDD = 5V
VDD = 2.7V
1
10
Input Frequency (kHz)
SNR vs. Input Frequency.
FIGURE 2-23:
SINAD vs. Input Frequency.
80
VDD = 5V
70
60
SINAD (dB)
THD (dB)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
50
Offset Error vs.
100
90
80
70
60
50
40
30
20
10
0
Input Frequency (kHz)
FIGURE 2-20:
25
Temperature (°C)
VDD = 5V
VDD = 2.7V
50
VDD = 2.7V
40
30
20
10
0
1
10
-40
Input Frequency (kHz)
FIGURE 2-21:
DS21732B-page 8
THD vs. Input Frequency.
-30
-20
-10
0
Input Signal Level (dB)
FIGURE 2-24:
Level.
SINAD vs. Input Signal
 2003 Microchip Technology Inc.
MCP3221
12
11.95
11.9
11.85
11.8
11.75
11.7
11.65
11.6
11.55
11.5
12
11.5
VDD = 2.7V
11
ENOB (rms)
ENOB (rms)
Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, I2C Fast Mode Timing (SCL = 400 kHz), Continuous Conversion
Mode (fSAMP = 22.3 ksps), TA = +25°C.
VDD = 5V
10.5
10
9.5
9
2.5
3
3.5
4
4.5
5
5.5
1
10
VDD (V)
FIGURE 2-25:
100
90
80
70
60
50
40
30
20
10
0
Input Frequency (kHz)
FIGURE 2-28:
ENOB vs. VDD.
ENOB vs. Input Frequency.
10
VDD = 5V
fSAMP = 5 6 ksps
Amplitude (dB)
SFDR (dB)
-10
VDD = 2.7V
-30
-50
-70
-90
-110
-130
1
0
10
500
FIGURE 2-26:
SFDR vs. Input Frequency.
1000
1500
2000
2500
Frequency (Hz)
Input Frequency (kHz)
FIGURE 2-29:
Spectrum Using I2C™
Standard Mode (Representative Part, 1 kHz
Input Frequency).
250
10
200
-30
IDD (µA)
Amplitude (dB)
-10
-50
-70
-90
150
100
50
-110
0
-130
0
2000
4000
6000
Frequency (Hz)
8000
10000
FIGURE 2-27:
Spectrum Using I2C™ Fast
Mode (Representative Part, 1 kHz Input
Frequency).
 2003 Microchip Technology Inc.
2.5
3
3.5
4
4.5
5
5.5
VDD (V)
FIGURE 2-30:
IDD (Conversion) vs. VDD.
DS21732B-page 9
MCP3221
200
180
160
140
120
100
80
60
40
20
0
100
90
80
70
60
50
40
30
20
10
0
IDDA (µA)
IDD (µA)
Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, I2C Fast Mode Timing (SCL = 400 kHz), Continuous Conversion
Mode (fSAMP = 22.3 ksps), TA = +25°C.
VDD = 5V
VDD = 2.7V
0
100
200
300
2
I C Clock Rate (kHz)
FIGURE 2-31:
Rate.
0
IDDA (µA)
IDD (µA)
VDD = 5V
150
VDD = 2.7V
50
0
-50
-25
0
25
50
75
100
100
125
VDD = 5V
VDD = 2.7V
-50
-25
0
25
50
75
100
125
Temperature (°C)
IDD (Conversion) vs.
FIGURE 2-35:
Temperature.
100
90
80
70
60
50
40
30
20
10
0
IDDA (Active Bus) vs.
60
50
IDDS (pA)
IDDA (µA)
400
IDDA (Active Bus) vs. Clock
100
90
80
70
60
50
40
30
20
10
0
Temperature (°C)
FIGURE 2-32:
Temperature.
200
300
2
I C Clock Rate (kHz)
FIGURE 2-34:
Rate.
250
100
VDD = 2.7V
400
IDD (Conversion) vs. Clock
200
VDD = 5V
40
30
20
10
0
2.5
3
3.5
4
4.5
5
5.5
2.5
3
VDD (V)
FIGURE 2-33:
DS21732B-page 10
IDDA (Active Bus) vs. VDD.
3.5
4
4.5
5
5.5
VDD (V)
FIGURE 2-36:
IDDS (Standby) vs. VDD.
 2003 Microchip Technology Inc.
MCP3221
Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, I2C Fast Mode Timing (SCL = 400 kHz), Continuous Conversion
Mode (fSAMP = 22.3 ksps), TA = +25°C.
2.1
Test Circuits
1000
100
VDD = 5V
IDDS (nA)
10
1
0.1
10 µF
0.01
0.1 µF
2 kΩ
0.001
0.0001
-50
-25
0
25
50
75
100
Temperature (°C)
FIGURE 2-37:
Temperature.
AIN
125
VIN
2 kΩ
VDD SDA
MCP3221
VSS SCL
IDDS (Standby) vs.
VCM = 2.5V
2
Analog Input Leakage (nA)
1.8
1.6
FIGURE 2-39:
1.4
Typical Test Configuration.
1.2
1
0.8
0.6
0.4
0.2
0
-50
-25
0
25
50
75
100
125
Temperature (°C)
FIGURE 2-38:
Temperature.
Analog Input Leakage vs.
 2003 Microchip Technology Inc.
DS21732B-page 11
MCP3221
3.0
PIN FUNCTIONS
TABLE 3-1:
PIN FUNCTION TABLE
Name
3.1
Function
VDD
+2.7V to 5.5V Power Supply
VSS
Ground
AIN
Analog Input
SDA
Serial Data In/Out
SCL
Serial Clock In
VDD and VSS
The VDD pin, with respect to VSS, provides power to the
device as well as a voltage reference for the conversion
process. Refer to Section 6.4, “Device Power and
Layout Considerations”, for tips on power and
grounding.
3.2
Analog Input (AIN)
AIN is the input pin to the sample-and-hold circuitry of
the Successive Approximation Register (SAR) converter. Care should be taken in driving this pin. Refer to
Section 6.1, “Driving the Analog Input”. For proper conversions, the voltage on this pin can vary from VSS to
VDD.
DS21732B-page 12
3.3
Serial Data (SDA)
SDA is a bidirectional pin used to transfer addresses
and data into and out of the device. Since it is an opendrain terminal, the SDA bus requires a pull-up resistor
to VDD (typically 10 kΩ for 100 kHz and 2 kΩ for
400 kHz SCL clock speeds). Refer to Section 6.2,
“Connecting to the I2C Bus”, for more information.
For normal data transfer, SDA is allowed to change only
during SCL low. Changes during SCL high are reserved
for indicating the START and STOP conditions. Refer to
Section 5.1, “I2C Bus Characteristics”.
3.4
Serial Clock (SCL)
SCL is an input pin used to synchronize the data transfer to and from the device on the SDA pin and is an
open-drain terminal. Therefore, the SCL bus requires a
pull-up resistor to VDD (typically 10 kΩ for 100 kHz and
2 kΩ for 400 kHz SCL clock speeds. Refer to
Section 6.2, “Connecting to the I2C Bus”).
For normal data transfer, SDA is allowed to change
only during SCL low. Changes during SCL high are
reserved for indicating the START and STOP
conditions. Refer to Section 6.1, “Driving the Analog
Input”.
 2003 Microchip Technology Inc.
MCP3221
4.0
DEVICE OPERATION
4.2
The MCP3221 employs a classic SAR architecture.
This architecture uses an internal sample and hold
capacitor to store the analog input while the conversion
is taking place. At the end of the acquisition time, the
input switch of the converter opens and the device uses
the collected charge on the internal sample-and-hold
capacitor to produce a serial 12-bit digital output code.
The acquisition time and conversion is self-timed using
an internal clock. After each conversion, the results are
stored in a 12-bit register that can be read at any time.
Communication with the device is accomplished with a
2-wire, I2C interface. Maximum sample rates of
22.3 ksps are possible with the MCP3221 in a continuous-conversion mode and an SCL clock rate of
400 kHz.
4.1
Digital Output Code
The digital output code produced by the MCP3221 is a
function of the input signal and power supply voltage,
VDD. As the VDD level is reduced, the LSB size is
reduced accordingly. The theoretical LSB size is shown
below.
EQUATION
V DD
LSB SIZE = -----------4096
VDD = Supply voltage
The output code of the MCP3221 is transmitted serially
with MSB first. The format of the code is straight binary.
Conversion Time (tCONV)
The conversion time is the time required to obtain the
digital result once the analog input is disconnected
from the holding capacitor. With the MCP3221, the
specified conversion time is typically 8.96 µs. This time
is dependent on the internal oscillator and is
independent of SCL.
4.3
Acquisition Time (tACQ)
The acquisition time is the amount of time the sample
cap array is acquiring charge.
The acquisition time is, typically, 1.12 µs. This time is
dependent on the internal oscillator and independent of
SCL.
4.4
Sample Rate
Sample rate is the inverse of the maximum amount of
time that is required from the point of acquisition of the
first conversion to the point of acquisition of the second
conversion.
The sample rate can be measured either by single or
continuous conversions. A single conversion includes
a Start Bit, Address Byte, Two Data Bytes and a Stop
bit. This sample rate is measured from one Start Bit to
the next Start Bit.
For continuous conversions (requested by the Master
by issuing an acknowledge after a conversion), the
maximum sample rate is measured from conversion to
conversion or a total of 18 clocks (two data bytes and
two Acknowledge bits). Refer to Section 5-2, “Device
Addressing”.
Output Code
1111 1111 1111
1111 1111 1110
(4095)
(4094)
0000 0000 0011 (3)
0000 0000 0010 (2)
0000 0000 0001 (1)
0000 0000 0000 (0)
.5 LSB
1.5 LSB
2.5 LSB
FIGURE 4-1:
AIN
VDD-1.5 LSB
VDD-2.5 LSB
Transfer Function.
 2003 Microchip Technology Inc.
DS21732B-page 13
MCP3221
4.5
Differential Non-Linearity (DNL)
In the ideal A/D converter transfer function, each code
has a uniform width. That is, the difference in analog
input voltage is constant from one code transition point
to the next. Differential nonlinearity (DNL) specifies the
deviation of any code in the transfer function from an
ideal code width of 1 LSB. The DNL is determined by
subtracting the locations of successive code transition
points after compensating for any gain and offset
errors. A positive DNL implies that a code is longer than
the ideal code width, while a negative DNL implies that
a code is shorter than the ideal width.
4.6
Integral Non-Linearity (INL)
Integral nonlinearity (INL) is a result of cumulative DNL
errors and specifies how much the overall transfer
function deviates from a linear response. The method
of measurement used in the MCP3221 A/D converter
to determine INL is the “end-point” method.
4.7
Offset Error
Offset error is defined as a deviation of the code transition points that are present across all output codes.
This has the effect of shifting the entire A/D transfer
function. The offset error is measured by finding the difference between the actual location of the first code
transition and the desired location of the first transition.
The ideal location of the first code transition is located
at 1/2 LSB above VSS.
4.8
Gain Error
The gain error determines the amount of deviation from
the ideal slope of the A/D converter transfer function.
Before the gain error is determined, the offset error is
measured and subtracted from the conversion result.
The gain error can then be determined by finding the
location of the last code transition and comparing that
location to the ideal location. The ideal location of the
last code transition is 1.5 LSBs below full-scale or VDD.
4.9
Conversion Current (IDD)
The average amount of current over the time required
to perform a 12-bit conversion.
4.10
Active Bus Current (IDDA)
The average amount of current over the time required
to monitor the I2C bus. Any current the device consumes while it is not being addressed is referred to as
“Active Bus” current.
4.11
Standby Current (IDDS)
The average amount of current required while no conversion is occurring and while no data is being output
(i.e., SCL and SDA lines are quiet).
4.12
I2C Standard Mode Timing
I2C specification where the frequency of SCL is
100 kHz.
4.13
I2C Fast Mode Timing
I2C specification where the frequency of SCL is
400 kHz.
DS21732B-page 14
 2003 Microchip Technology Inc.
MCP3221
5.0
SERIAL COMMUNICATIONS
5.1
I2C Bus Characteristics
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a START or STOP condition.
Accordingly, the following bus conditions have been
defined (refer to Figure 5-1).
5.1.1
BUS NOT BUSY (A)
Both data and clock lines remain high.
5.1.2
START DATA TRANSFER (B)
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a START condition. All
commands must be preceded by a START condition.
5.1.3
STOP DATA TRANSFER (C)
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a STOP condition. All
operations must be ended with a STOP condition.
5.1.4
DATA VALID (D)
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the clock signal’s high period.
The data on the line must be changed during the low
period of the clock signal. There is one clock pulse per
bit of data.
SCL
(A)
(B)
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
data bytes transferred between the START and STOP
conditions is determined by the master device and is
unlimited.
5.1.5
ACKNOWLEDGE
Each receiving device, when addressed, is obliged to
generate an acknowledge bit after the reception of
each byte. The master device must generate an extra
clock pulse which is associated with this acknowledge
bit.
The device that acknowledges has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable-low during the high
period of the acknowledge-related clock pulse. Setup
and hold times must be taken into account. During
reads, a master device must signal an end of data to
the slave by not generating an acknowledge bit on the
last byte that has been clocked out of the slave (NAK).
In this case, the slave (MCP3221) will release the bus
to allow the master device to generate the STOP
condition.
The MCP3221 supports a bidirectional, 2-wire bus and
data transmission protocol. The device that sends data
onto the bus is the transmitter and the device receiving
data is the receiver. The bus has to be controlled by a
master device which generates the serial clock (SCL),
controls the bus access and generates the START and
STOP conditions, while the MCP3221 works as a slave
device. Both master and slave devices can operate as
either transmitter or receiver, but the master device
determines which mode is activated.
(D)
(D)
(C)
(A)
SDA
START
CONDITION
FIGURE 5-1:
DATA
ADDRESS OR
ACKNOWLEDGE ALLOWED
TO CHANGE
VALID
STOP
CONDITION
Data Transfer Sequence on the Serial Bus.
 2003 Microchip Technology Inc.
DS21732B-page 15
MCP3221
Device Addressing
5.3
The address byte is the first byte received following the
START condition from the master device. The first part
of the control byte consists of a 4-bit device code,
which is set to 1010 for the MCP3221. The device code
is followed by three address bits: A2, A1 and A0. The
default address bits are 1001. Contact the Microchip
factory for additional address bit options. The address
bits allow up to eight MCP3221 devices on the same
bus and are used to determine which device is
accessed.
The eighth bit of the slave address determines if the
master device wants to read conversion data or write to
the MCP3221. When set to a ‘1’, a read operation is
selected. When set to a ‘0’, a write operation is
selected. There are no writable registers on the
MCP3221. Therefore, this bit must be set to a ’1’ in
order to initiate a conversion.
The MCP3221 is a slave device that is compatible with
the I2C 2-wire serial interface protocol. A hardware
connection diagram is shown in Figure 6-2. Communication is initiated by the microcontroller (master
device), which sends a START bit followed by the
address byte.
On completion of the conversion(s) performed by the
MCP3221, the microcontroller must send a STOP bit to
end communication.
The last bit in the device address byte is the R/W bit.
When this bit is a logic ‘1’, a conversion will be executed. Setting this bit to logic ‘0’ will also result in an
“acknowledge” (ACK) from the MCP3221, with the
device then releasing the bus. This can be used for
device polling. Refer to Section 6.3, “Device Polling”,
for more information.
START
Executing a Conversion
This section will describe the details of communicating
with the MCP3221 device. Initiating the sample-andhold acquisition, reading the conversion data and
executing multiple conversions will be discussed.
5.3.1
INITIATING THE SAMPLE AND
HOLD
The acquisition and conversion of the input signal
begins with the falling edge of the R/W bit of the
address byte. At this point, the internal clock initiates
the sample, hold and conversion cycle, all of which are
internal to the ADC.
tACQ + tCONV is
initiated here
Address Byte
SCL
1
2
3
4
SDA
1
0
0
1 A2 A1 A0 R/W
Start
Bit
FIGURE 5-3:
Address Byte.
6
7
8
9
Address bits
Initiating the Conversion,
tACQ + tCONV is
initiated here
READ/WRITE
Lower Data Byte (n)
17 18 19 20 21 22 23 24 25 26
R/W A
SLAVE ADDRESS
Device bits
5
ACK
5.2
0
1
0
Device Code
1
0
1
Address Bits(1)
SDA
D8
D7 D6 D5 D4 D3 D2 D2 D0
ACK
1
ACK
SCL
FIGURE 5-4:
Initiating the Conversion,
Continuous Conversions.
Note 1: Contact Microchip for additional address bits.
FIGURE 5-2:
DS21732B-page 16
Device Addressing.
 2003 Microchip Technology Inc.
MCP3221
5.3.2
The input signal will initially be sampled with the first
falling edge of the clock following the transmission of a
logic-high R/W bit. Additionally, with the rising edge of
the SCL, the ADC will transmit an acknowledge bit
(ACK = 0). The master must release the data bus during this clock pulse to allow the MCP3221 to pull the
line low (refer to Figure 5-3).
READING THE CONVERSION DATA
Once the MCP3221 acknowledges the address byte,
the device will transmit four ‘0’ bits followed by the upper
four data bits of the conversion. The master device will
then acknowledge this byte with an ACK = Low. With the
following 8 clock pulses, the MCP3221 will transmit the
lower eight data bits from the conversion. The master
then sends an ACK = high, indicating to the MCP3221
that no more data is requested. The master can then
send a stop bit to end the transmission.
For consecutive samples, sampling begins on the falling edge of the LSB of the conversion result, which is
two bytes long. Refer to Figure 5-6 a for timing diagram.
tACQ + tCONV is
initiated here
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
SCL
S
T
A
R
T
1
S
SDA
0
0
FIGURE 5-5:
A
2
1
Device bits
5.3.3
Upper Data Byte
Address Byte
A
1
A
C
K
R
/
W
A
0
0
0
0
0
D D D
11 10 9
S
T
O
P
Lower Data Byte
A
C D
K 7
D
8
D
6
D
5
D
4
D
3
D
2
D
1
N
A
K
D
0
P
Address bits
Executing a Conversion.
CONSECUTIVE CONVERSIONS
For consecutive samples, sampling begins on the falling edge of the LSB of the conversion result. See
Figure 5-6 for timing.
tACQ + tCONV is
initiated here
tACQ + tCONV is
initiated here
fSAMP = 22.3 ksps (fCLK = 400 kHz)
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
SCL
S
T
A
R
T
SDA
S
1
0
0
1 A2 A1 A0
Device bits
FIGURE 5-6:
Upper Data Byte (n)
Address Byte
R
/
W
A
C
K
0
0
0
0
D D D
11 10 9
Lower Data Byte (n)
D
8
A
C
K
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
C
K
0
Address bits
Continuous Conversion.
 2003 Microchip Technology Inc.
DS21732B-page 17
MCP3221
6.0
APPLICATIONS INFORMATION
6.1
Driving the Analog Input
The MCP3221 has a single-ended analog input (AIN).
For proper conversion results, the voltage at the AIN
pin must be kept between VSS and VDD. If the converter
has no offset error, gain error, INL or DNL errors, and
the voltage level of AIN is equal to or less than
VSS + 1/2 LSB, the resultant code will be 000h. Additionally, if the voltage at AIN is equal to or greater than
VDD - 1.5 LSB, the output code will be FFFh.
The analog input model is shown in Figure 6-1. In this
diagram, the source impedance (RSS) adds to the internal sampling switch (RS) impedance, directly affecting
the time required to charge the capacitor (CSAMPLE).
Consequently, a larger source impedance increases
the offset error, gain error and integral linearity errors of
the conversion. Ideally, the impedance of the signal
source should be near zero. This is achievable with an
operational amplifier, such as the MCP6022, which has
a closed-loop output impedance of tens of ohms.
VDD
RSS
Sampling
Switch
VT = 0.6V
AIN
CPIN
7 pF
VA
VT = 0.6V
SS
RS = 1 kΩ
CSAMPLE
= DAC capacitance
= 20 pF
ILEAKAGE
±1 nA
VSS
Legend
VA
RSS
AIN
CPIN
VT
ILEAKAGE
SS
RS
CSAMPLE
=
=
=
=
=
=
=
=
=
FIGURE 6-1:
6.2
signal source
source impedance
analog input pad
analog input pin capacitance
threshold voltage
leakage current at the pin
due to various junctions
sampling switch
sampling switch resistor
sample/hold capacitance
Analog Input Model, AIN.
Connecting to the I2C Bus
The I2C bus is an open-collector bus, requiring pull-up
resistors connected to the SDA and SCL lines. This
configuration is shown in Figure 6-2.
The number of devices connected to the bus is limited
only by the maximum bus capacitance of 400 pF. A
possible configuration using multiple devices is shown
in Figure 6-3.
SDA SCL
VDD
PICmicro®
Microcontroller
PIC16F876
Microcontroller
RPU
RPU MCP3221
SDA
AIN
SCL
24LC01
EEPROM
Analog
Input
Signal
MCP3221
12-bit ADC
TC74
Temperature
Sensor
RPU is typically: 10 kΩ for fSCL = 100 kHz
2 kΩ for fSCL = 400 kHz
FIGURE 6-2:
Bus.
DS21732B-page 18
Pull-up Resistors on I2C
FIGURE 6-3:
Bus.
Multiple Devices on I2C™
 2003 Microchip Technology Inc.
MCP3221
6.3
Device Polling
In some instances, it may be necessary to test for
MCP3221 presence on the I2C bus without performing
a conversion. This operation is described in Figure 6-4.
Here we are setting the R/W bit in the address byte to
a zero. The MCP3221 will then acknowledge by pulling
SDA low during the ACK clock and then release the
bus back to the I2C master. A stop or repeated start bit
can then be issued from the master and I2C
communication can continue.
Address Byte
1 2 3 4 5 6 7 8 9
SDA
1 0 0
1
Start
Bit Device bits
Use of an analog ground plane is recommended in
order to keep the ground potential the same for all
devices on the board. Providing VDD connections to
devices in a “star” configuration can also reduce noise
by eliminating current return paths and associated
errors (Figure 6-6). For more information on layout tips
when using the MCP3221 or other ADC devices, refer
to AN688, “Layout Tips for 12-Bit A/D Converter
Applications”.
ACK
SCL
Digital and analog traces should be separated as much
as possible on the board, with no traces running underneath the device or the bypass capacitor. Extra precautions should be taken to keep traces with highfrequency signals (such as clock lines) as far as
possible from analog traces.
A2 A1A0 0
R/W
Address bits
VDD
Connection
Start
Bit
MCP3221 response
FIGURE 6-4:
6.4
6.4.1
Device Power and Layout
Considerations
Device 3
POWERING THE MCP3221
VDD supplies the power to the device as well as the reference voltage. A bypass capacitor value of 0.1 µF is
recommended. Adding a 10 µF capacitor in parallel is
recommended to attenuate higher frequency noise
present in some systems.
VDD
0.1 µF
VDD
AIN
MCP3221
Device 2
FIGURE 6-6:
VDD traces arranged in a
‘Star’ configuration in order to reduce errors
caused by current return paths.
6.4.3
VDD
10 µF
Device 4
Device 1
Device Polling.
SCL
SDA
RPU RPU
To
Microcontroller
USING A REFERENCE FOR
SUPPLY
The MCP3221 uses VDD as both power and a reference. In some applications, it may be necessary to use
a stable reference to achieve the required accuracy.
Figure 6-7 shows an example using the MCP1541 as a
4.096V, 2% reference.
6.4.2
Powering the MCP3221.
LAYOUT CONSIDERATIONS
When laying out a printed circuit board for use with
analog components, care should be taken to reduce
noise wherever possible. A bypass capacitor from VDD
to ground should always be used with this device and
should be placed as close as possible to the device pin.
A bypass capacitor value of 0.1 µF is recommended.
 2003 Microchip Technology Inc.
VDD
1 µF
MCP1541
CL
4.096V
Reference
AIN
VDD
SCL
MCP3221
SDA
RPU
To
Microcontroller
FIGURE 6-5:
0.1 µF
VDD
FIGURE 6-7:
Stable Power and
Reference Configuration.
DS21732B-page 19
MCP3221
7.0
PACKAGING INFORMATION
7.1
Package Marking Information
5-Pin SOT-23A (EIAJ SC-74) Device
3
2
1
cdef
4
Part Number
5
Address Option
SOT-23
MCP3221A0T-I/OT
000
EE
MCP3221A1T-I/OT
001
EH
MCP3221A2T-I/OT
010
EB
MCP3221A3T-I/OT
011
EC
MCP3221A4T-I/OT
100
ED
MCP3221A5T-I/OT
101
S1 *
MCP3221A6T-I/OT
110
EF
MCP3221A7T-I/OT
111
EG
MCP3221A0T-E/OT
000
GE
MCP3221A1T-E/OT
001
GH
MCP3221A2T-E/OT
010
GB
MCP3221A3T-E/OT
011
GC
MCP3221A4T-E/OT
100
GD
MCP3221A5T-E/OT
101
GA *
MCP3221A6T-E/OT
110
GF
MCP3221A7T-E/OT
111
GG
* Default option. Contact Microchip Factory for other
address options.
Legend:
Note:
*
1
2
3
4
Part Number code + temperature range
Part Number code + temperature range
Year and work week
Lot ID
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line thus limiting the number of available characters
for customer specific information.
Standard device marking consists of Microchip part number, year code, week code, and traceability
code.
DS21732B-page 20
 2003 Microchip Technology Inc.
MCP3221
5-Lead Plastic Small Outline Transistor (OT) (SOT23)
E
E1
p
B
p1
n
D
1
α
c
A
φ
L
β
Units
Dimension Limits
n
p
Number of Pins
Pitch
Outside lead pitch (basic)
Overall Height
Molded Package Thickness
Standoff §
Overall Width
Molded Package Width
Overall Length
Foot Length
Foot Angle
Lead Thickness
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
* Controlling Parameter
§ Significant Characteristic
MIN
p1
A
A2
A1
E
E1
D
L
φ
c
B
α
β
.035
.035
.000
.102
.059
.110
.014
0
.004
.014
0
0
A2
A1
INCHES*
NOM
5
.038
.075
.046
.043
.003
.110
.064
.116
.018
5
.006
.017
5
5
MAX
.057
.051
.006
.118
.069
.122
.022
10
.008
.020
10
10
MILLIMETERS
NOM
5
0.95
1.90
0.90
1.18
0.90
1.10
0.00
0.08
2.60
2.80
1.50
1.63
2.80
2.95
0.35
0.45
0
5
0.09
0.15
0.35
0.43
0
5
0
5
MIN
MAX
1.45
1.30
0.15
3.00
1.75
3.10
0.55
10
0.20
0.50
10
10
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0 254mm) per side.
JEDEC Equivalent: MO-178
Drawing No. C04-091
 2003 Microchip Technology Inc.
DS21732B-page 21
MCP3221
NOTES:
DS21732B-page 22
 2003 Microchip Technology Inc.
MCP3221
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
XX
X
/XX
Device
Address
Options
Temperature
Range
Package
Device:
Examples:
a)
b)
MCP3221T: 12-Bit 2-Wire Serial A/D Converter
(Tape and Reel)
c)
d)
Temperature Range:
Address Options:
Package:
I = -40°C to +85°C
E = -40°C to +125°C
XX
e)
A2
A1
A0
A0
=
0
0
0
A1
=
0
0
1
A2
=
0
1
0
A3
=
0
1
1
A4
=
1
0
0
A5 *
=
1
0
1
A6
=
1
1
0
A7
=
1
1
1
f)
g)
h)
a)
b)
c)
* Default option. Contact Microchip factory for other
address options
d)
OT = SOT-23, 5-lead (Tape and Reel)
e)
f)
g)
h)
MCP3221A0T-I/OT: Industrial, A0 Address,
Tape and Reel
MCP3221A1T-I/OT: Industrial, A1 Address,
Tape and Reel
MCP3221A2T-I/OT: Industrial, A2 Address,
Tape and Reel
MCP3221A3T-I/OT: Industrial, A3 Address,
Tape and Reel
MCP3221A4T-I/OT: Industrial, A4 Address,
Tape and Reel
MCP3221A5T-I/OT: Industrial, A5 Address,
Tape and Reel
MCP3221A6T-I/OT: Industrial, A6 Address,
Tape and Reel
MCP3221A7T-I/OT: Industrial, A7 Address,
Tape and Reel
MCP3221A0T-E/OT: Extended, A0 Address,
Tape and Reel
MCP3221A1T-E/OT: Extended, A1 Address,
Tape and Reel
MCP3221A2T-E/OT: Extended, A2 Address,
Tape and Reel
MCP3221A3T-E/OT: Extended, A3 Address,
Tape and Reel
MCP3221A4T-E/OT: Extended, A4 Address,
Tape and Reel
MCP3221A5T-E/OT: Extended, A5 Address,
Tape and Reel
MCP3221A6T-E/OT: Extended, A6 Address,
Tape and Reel
MCP3221A7T-IE/OT: Extended, A7 Address,
Tape and Reel
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and
recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1.
2.
3.
Your local Microchip sales office
The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277
The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
 2003 Microchip Technology Inc.
DS21732B-page 23
MCP3221
NOTES:
DS21732B-page 24
 2003 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data
Sheets. Most l kely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is intended through suggestion only
and may be superseded by updates. It is your respons bility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microchip Technology Incorporated with respect
to the accuracy or use of such information, or infringement of
patents or other intellectual property rights arising from such
use or otherwise. Use of Microchip’s products as critical
components in life support systems is not authorized except
with express written approval by Microchip. No licenses are
conveyed, implicitly or otherwise, under any intellectual
property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, MPLAB, PIC, PICmicro, PICSTART, PRO MATE and
PowerSmart are registered trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
FilterLab, microID, MXDEV, MXLAB, PICMASTER, SEEVAL
and The Embedded Control Solutions Company are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Accuron, Application Maestro, dsPICDEM, dsPICDEM.net,
ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, InCircuit Serial Programming, ICSP, ICEPIC, microPort,
Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM,
PICC, PICkit, PICDEM, PICDEM.net, PowerCal, PowerInfo,
PowerMate, PowerTool, rfLAB, rfPIC, Select Mode,
SmartSensor, SmartShunt, SmartTel and Total Endurance are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
Serialized Quick Turn Programming (SQTP) is a service mark
of Microchip Technology Incorporated in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2003, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999
and Mountain View, California in March 2002.
The Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals,
non-volatile memory and analog products. In
addition, Microchip’s quality system for the
design and manufacture of development
systems is ISO 9001 certified.
DS21732B-page 25
 2003 Microchip Technology Inc.
M
WORLDWIDE SALES AND SERVICE
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05/30/03
DS21732B-page 26
 2003 Microchip Technology Inc.