ICST ICS620-01 Digital still camera clock source Datasheet

ICS620-01
Digital Still Camera Clock Source
PRELIMINARY INFORMATION
I C R O C LOC K
Description
Features
The ICS620-01 is a low cost, low jitter, high
performance clock synthesizer for digital still
cameras. Using analog Phase-Locked Loop
(PLL) techniques, the device uses a
14.318 MHz crystal input to produce multiple
output clocks required in the camera. It
provides selectable NTSC/PAL clock, a
selectable processor clock, a selectable CCD
clock, and a selectable interface clocks. Most
clocks are generated to a very low ppm
synthesis error rate.
• Packaged in 28 pin, 150 mil wide SSOP (QSOP)
• Provides all clocks necessary for many digital still
camera systems
• All clocks are frequency locked together
• Interface clock for USB, P1394, or UART
• Saves space over multiple crystals and oscillators
• Clocks power down when all select pins are low
• Full CMOS outputs also compatible with TTL levels
• +3.3 V or +5 V operation
• Low power, sub-micron CMOS process
• Custom versions available
All clocks can be turned off using a power
down mode. Custom versions with userdefined frequencies and power down modes
are available in 6-8 weeks.
Block Diagram
NSEL1:0
PSEL1:0
CSEL1:0
ISEL1:0
2
2
2
2
X1
X2
Crystal
Oscillator
PLL Clock
Synthesis
Circuitry
PLL Clock
Synthesis
Circuitry
PLL Clock
Synthesis
Circuitry
PLL Clock
Synthesis
Circuitry
14.31818
MHz
crystal
MDS 620-01 B
1
÷2
÷2
÷2
Output
Buffer
NTSC/PAL Clock 1
Output
Buffer
NTSC/PAL Clock 2
Output
Buffer
Processor Clock 1
Output
Buffer
Processor Clock 2
Output
Buffer
CCD Clock 1
Output
Buffer
CCD Clock 2
Output
Buffer
Interface Clock 1
Output
Buffer
Interface Clock 2
Revision 072098
Printed 12/4/00
Integrated Circuit Systems • 1271 Parkmoor Ave.•San Jose•CA•95126•(408)295-9800tel•(408)295-9818fax
ICS620-01
Digital Still Camera Clock Source
PRELIMINARY INFORMATION
I C R O C LOC K
Pin
Assignment
CSEL0
NC
X2
X1
VDD
NSEL1
VDD
VDD
NSEL0
GND
GND
CLKI2
CLKI1
CLKP2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Processor Clock Select (MHz)
PSEL1
0
0
1
1
PSEL0 CLKP1 CLKP2
0
Power down both
1
20.50
10.25
0
23.96
11.98
1
24.5455 12.2727
Clock C Frequency Select Table (MHz)
CSEL1
ISEL0
NC
CLKN1
ISEL1
GND
CLKN2
VDD
PSEL0
GND
CLKC1
CLKC2
PSEL1
CLKP1
CSEL1 CSEL0
CLKC1
CLKC2
Actual error
0
0
Power Down - both outputs stop low
0
M
14.31818
7.15909
0 ppm
0
1
9.81818
4.90909
0 ppm
M
0
7.3728
3.6864
31 ppm high
M
M
27
13.5
0 ppm
M
1
8
4
0.017% high
1
0
28
14
0 ppm
1
M
24.54545
12.272725 11 ppm high
1
1
32
16
0.017% high
Key: 0 = connect to ground, 1 = connect to VDD,
M = leave unconnected (floating).
Interface Clock Select (MHz)
ISEL1 ISEL0 CLKI1 CLKI2
0
0
Power down both
0
1
36.864 18.432
1
0
24.576 8.192
1
1
48
12
Pin Descriptions
Pin #
1
2, 26
3
4
5, 7, 8, 21
6
9
10, 11, 19, 23
12
13
14
15
16
17
18
20
22
24
25
27
28
Name
CSEL0
NC
X2
X1
VDD
NSEL1
NSEL0
GND
CLKI2
CLKI1
CLKP2
CLKP1
PSEL1
CLKC2
CLKC1
PSEL0
CLKN2
ISEL1
CLKN1
ISEL0
CSEL1
Type
TI
XO
XI
P
I
TI
P
O
O
O
O
I
O
O
I
O
I
O
I
TI
NTSC/PAL Clock Select (MHz)
NSEL1 NSEL0 CLKN1 CLKN2
Error
0
0
Power down
0
M
8.8672 4.43361 2 ppm low
0
1
27
13.5
0 ppm
1
0
35.4688 17.7344 2 ppm low
1
M
7.1591 3.5795
0 ppm
1
1
28.6364 14.3182 0 ppm
Description
C clock SELect pin 0.
No Connect. Nothing is connected internally to this pin.
Crystal connection. Connect to a 14.31818 MHz crystal or input clock.
Crystal connection. Connect to a 14.31818 MHz crystal, or leave unconnected for clock.
Connect to +3.3V or +5V. Must be same voltage on all pins.
NTSC/PAL SELect pin 1.
NTSC/PAL SELect pin 0.
Connect to Ground.
Interface CLocK output 2.
Interface CLocK output 1.
Processor CLocK output 2.
Processor CLocK output 1.
Processor clock SELect pin 1.
C CLocK output 2.
C CLocK output 1.
Processor clock SELect pin 0.
NTSC/PAL CLocK output 2.
Interface clock SELect pin 1.
NTSC/PAL CLocK output 1. Output may stop high or low during power down.
Interface clock SELect pin 0.
C clock SELect pin 1.
Key: I = Input, O = Output, P = Power supply connection, TI = tri-level input (automatically biased to M level if unconnected).
Internal pull-ups are on pins 6, 16, 20, 24, and 27.
MDS 620-01 B
2
Revision 072098
Printed 12/4/00
Integrated Circuit Systems • 1271 Parkmoor Ave.•San Jose•CA•95126•(408)295-9800tel•(408)295-9818fax
ICS620-01
Digital Still Camera Clock Source
PRELIMINARY INFORMATION
I C R O C LOC K
Electrical Specifications
Parameter
Conditions
Minimum
Typical
Maximum
Units
7
VDD+0.5
70
260
150
V
V
°C
°C
°C
5.5
V
V
V
V
V
V
V
V
V
mA
mA
kΩ
pF
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD
Inputs and Clock Outputs
Ambient Operating Temperature
Soldering Temperature
Storage temperature
Referenced to GND
Referenced to GND
-0.5
0
Max of 10 seconds
-65
DC CHARACTERISTICS
Operating Voltage, VDD
Input High Voltage, VIH
Input Low Voltage, VIL
Input High Voltage, VIH
Input Mid-level Voltage
Input Low Voltage, VIL
Output High Voltage, VOH
Output High Voltage, VOH
Output Low Voltage, VOL
Operating Supply Current, IDD
Short Circuit Current
On-Chip Pull-up Resistor
Input Capacitance
Pins 6, 16, 20, 24, 27
Pins 6, 16, 20, 24, 27
Pins 1, 9, 28
Pins 1, 9, 28
Pins 1, 9, 28
IOH=-4mA
IOH=-25mA
IOL=25mA
No Load
Each output
Pins 6, 16, 20, 24, 27
All inputs but X1
3
2
0.8
VDD-0.5
Leave pin unconnected or tri-stated
0.5
VDD-0.4
2.4
0.4
TBD
±70
250
7
AC CHARACTERISTICS
Input Frequency
Output Clock Rise Time
Output Clock Fall Time
Output Clock Duty Cycle
Absolute Jitter
14.31818
0.8 to 2.0V
2.0 to 0.8V
at VDD/2
45
49 to 51
TBD
TBD
TBD
55
MHz
ns
ns
%
ps
Note:
1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged exposure
to levels above the operating limits but below the Absolute Maximums may affect device reliability.
External Components
The ICS620-01 requires some inexpensive external components for proper operation. Decoupling capacitors of 0.1µF should be
connected on VDD pins 5, 7+8, and 21 to ground, as close to the ICS620-01 as possible. A series termination resistor of 33Ω should
be used for each clock output. The 14.31818 MHz crystal should be parallel resonant with an accuracy of 30ppm or better. For
tuning, the formula 2•(CL -6) gives the value of each capacitor that should be connected between X1 and ground and X2 and ground,
where C L = the crystal load (or “correlation”) capacitance.
MDS 620-01 B
3
Revision 072098
Printed 12/4/00
Integrated Circuit Systems • 1271 Parkmoor Ave.•San Jose•CA•95126•(408)295-9800tel•(408)295-9818fax
ICS620-01
Digital Still Camera Clock Source
PRELIMINARY INFORMATION
I C R O C LOC K
Package Outline and Package Dimensions
28 pin SSOP
Inches
E
H
h x 45°
D
Symbol
Min
Max
Min
Max
A
0.061
0.068
1.55
1.73
b
0.008
0.012
0.203
0.305
c
0.007
0.010
0.190
0.254
D
0.385
0.400
9.780 10.160
E
0.150
0.160
3.810
4.064
H
0.230
0.245
5.840
6.223
e
Q
e
b
.025 BSC
h
A
c
Millimeters
Q
0.635 BSC
0.016
0.004
0.01
0.410
0.127
0.254
Ordering Information
Part/Order Number
ICS620-01R
ICS620-01RT
Marking
ICS620-01R
ICS620-01R
Package
28 pin SSOP
Add Tape & Reel
Temperature
0-70°C
-
While the information presented herein has been checked for both accuracy and reliability, ICS Incorporated assumes no responsibility for either its use or for the infringement of
any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
MDS 620-01 B
4
Revision 072098
Printed 12/4/00
Integrated Circuit Systems • 1271 Parkmoor Ave.•San Jose•CA•95126•(408)295-9800tel•(408)295-9818fax
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