Intersil ISL31486E Fault protected, extended cmr, rs-485/rs-422 transceivers with cable invert Datasheet

ISL31480E, ISL31483E, ISL31485E, ISL31486E
The ISL3148xE are fault protected, 5V powered
differential transceivers that exceed the RS-485 and
RS-422 standards for balanced communication. The
RS-485 transceiver pins (driver outputs and receiver
inputs) are protected against faults up to ±60V.
Additionally, the extended common mode range allows
these transceivers to operate in environments with
common mode voltages up to ±25V (>2X the RS-485
requirement), making this RS-485 family one of the
most robust on the market.
Features
Transmitters deliver an exceptional 2.5V (typical)
differential output voltage into the RS-485 specified 54Ω
load. This yields better noise immunity than standard
RS-485 ICs, or allows up to six 120Ω terminations in star
network topologies.
• Full Fail-safe (Open, Short, Terminated) RS-485
Receivers
Receiver (Rx) inputs feature a “Full Fail-Safe” design,
which ensures a logic high Rx output if Rx inputs are
floating, shorted, or on a terminated but undriven (idle)
bus.
The ISL31483E, ISL31485E and ISL31486E include cable
invert functions that reverse the polarity of the Rx and/or
Tx bus pins in case the cable is misconnected. Unlike
competing devices, Rx full fail-safe operation is
maintained even when the Rx input polarity is switched.
The ISL31480E and ISL31486E feature a logic supply
(VL) pin that sets the VOH of the Rx outputs, and the
switching points of the logic input pins, to be compatible
with a lower supply voltage (down to 1.8V) in mixed
voltage systems. See Table 1 on page 2 for key features
and configurations by device number.
Exceptional Rx Operates at
1Mbps Even With ±25V
Common Mode Voltage
30
15
10
5
RO
0
June 25, 2010
FN7638.0
• 1/4 Unit Load (UL) for up to 128 Devices on the Bus
• High Rx IOL for Opto-Couplers in Isolated Designs
• Hot Plug Circuitry - Tx and Rx Outputs Remain
Three-State During Power-up/Power-down
• Slew Rate Limited RS-485 Data Rate . . . . . . 1Mbps
• Low Quiescent Supply Current . . . . . . . . . . . 2.3mA
Ultra Low Shutdown Supply Current . . . . . . . . 10µA
Applications*(see page 19)
• Utility Meters/Automated Meter Reading Systems
• High Node Count Systems
• PROFIBUS® and Field Bus Networks, and Factory
Automation
• Security Camera Networks
• Building Lighting and Environmental Control Systems
• Industrial/Process Control Networks
Transceivers Deliver Superior
Common Mode Range vs.
Standard RS-485 Devices
25
COMMON MODE RANGE
VOLTAGE (V)
A
20
-5
• Logic Supply (VL) Pin (ISL31480E, ISL31486E)
Simplifies Interface to Lower Voltage Logic Devices
VID = ±1V
B
25
• Fault Protected RS-485 Bus Pins. . . . . . up to ±60V
• Extended Common Mode Range . . . . . . . . . . ±25V
More Than Twice the Range Required for RS-485
• Cable Invert Pins (Except ISL31480)
Corrects for Reversed Cable Connections While
Maintaining Rx Full Fail-safe Functionality
12
0
-7
-12
-20
-25
TIME (400ns/DIV)
1
STANDARD RS-485 CLOSEST
TRANSCEIVER COMPETITOR
ISL3148XE
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2010. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL31480E, ISL31483E, ISL31485E, ISL31486E
Fault Protected, Extended CMR, RS-485/RS-422
Transceivers with Cable Invert
ISL31480E, ISL31483E, ISL31485E, ISL31486E
TABLE 1. SUMMARY OF FEATURES
PART
NUMBER
HALF/FULL
DUPLEX
DATA
RATE
(Mbps)
SLEWRATE
LIMITED?
EN
PINS?
HOT
PLUG
VL
PIN?
Coming
Soon
ISL31480E
Half
1
Yes
Yes
Yes
Yes
No
2.3
Yes
10
ISL31483E
Full
1
Yes
Yes
Yes
No
Yes
2.3
Yes
14
ISL31485E
Half
1
Yes
Tx Only
Yes
No
Yes
2.3
No
8
Coming
Soon
ISL31486E
Half
1
Yes
Yes
Yes
Yes
Yes
2.3
Yes
10, 12, 14
POLARITY
LOW
REVERSAL QUIESCENT POWER
PINS?
ICC (mA)
SHDN?
PIN
COUNT
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
TEMP. RANGE
(°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
Coming Soon
ISL31480EIRTZ
480E
-40 to +85
10 Ld TDFN
L10.3x3A
Coming Soon
ISL31480EIUZ
1480E
-40 to +85
10 Ld MSOP
M10.118
ISL31483EIBZ
ISL31483 EIBZ
-40 to +85
14 Ld SOIC
M14.15
ISL31485EIBZ
31485 EIBZ
-40 to +85
8 Ld SOIC
M8.15
Coming Soon
ISL31486EIBZ
ISL31486 EIBZ
-40 to +85
14 Ld SOIC
M14.15
Coming Soon
ISL31486EIRTZ
486E
-40 to +85
12 Ld TDFN
L12.4x3A
Coming Soon
ISL31486EIUZ
1486E
-40 to +85
10 Ld MSOP
M10.118
NOTES:
1. Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL31480E, ISL31483E, ISL31485E, and
ISL31486E. For more information on MSL please see techbrief TB363.
Pin Configurations
ISL31485E
(8 LD SOIC)
TOP VIEW
ISL31483E
(14 LD SOIC)
TOP VIEW
RINV 1
RO 2
R
RE 3
DE 4
DI 5
D
14 VCC
RO 1
13 VCC
INV 2
12 A
DE 3
11 B
DI 4
8 VCC
7 B/Z
6 A/Y
D
5 GND
10 Z
GND 6
9 Y
GND 7
8 DINV
2
R
FN7638.0
June 25, 2010
ISL31480E, ISL31483E, ISL31485E, ISL31486E
Pin Descriptions
PIN ISL31480E ISL31483E ISL31485E
NAME
PIN #
PIN #
PIN #
ISL31486E ISL31486E ISL31486E
(14 LD)
(10 LD)
(12 LD)
PIN #
PIN #
PIN #
FUNCTION
RO
2
2
1
1
1
1
Receiver output. On the ISL31480E,
or if INV or RINV is low, then: If
A - B ≥ -10mV, RO is high; if A - B ≤
-200mV, RO is low. If INV or RINV is
high, then: If B - A ≥ -10mV, RO is
high; if B - A ≤ -200mV, RO is low.
In all cases, RO = High if A and B
are unconnected (floating), or
shorted together, or connected to
an undriven, terminated bus (i.e.,
Rx is always failsafe open, shorted,
and idle, even if polarity is
inverted).
RE
4
3
N/A
2
2
2
Receiver output enable. RO is
enabled when RE is low; RO is high
impedance when RE is high.
Internally pulled low.
DE
3
4
3
4
4
4
Driver output enable. The driver
outputs, Y and Z, are enabled by
bringing DE high, and they are high
impedance when DE is low.
Internally pulled high (to VL on
ISL31480E and ISL31486E; to VCC
on other versions).
DI
5
5
4
5
5
6
Driver input. On the ISL31480E, or
if INV or DINV is low, a low on DI
forces output Y low and output Z
high, while a high on DI forces
output Y high and output Z low.
The output states relative to DI
invert if INV or DINV is high.
GND
6
6, 7
5
7, 8
6
8, 9
Ground connection.This is also the
potential of the TDFN EPAD.
A/Y
8
N/A
6
9
7
11
±60V Fault Protected
RS-485/RS-422 level I/O pin. On
the ISL31480E, or if INV is low, A/Y
is the non-inverting receiver input
and non-inverting driver output. If
INV is high, A/Y is the inverting
receiver input and the inverting
driver output. Pin is an input if
DE = 0; pin is an output if DE = 1.
B/Z
9
N/A
7
10
8
12
±60V Fault Protected
RS-485/RS-422 level I/O pin. On
the ISL31480E, or if INV is low, B/Z
is the inverting receiver input and
inverting driver output. If INV is
high, B/Z is the non-inverting
receiver input and the noninverting driver output. Pin is an
input if DE = 0; pin is an output if
DE = 1.
A
N/A
12
N/A
N/A
N/A
N/A
±60V Fault Protected
RS-485/RS-422 level input. If RINV
is low, then A is the non-inverting
receiver input. If RINV is high, then
A is the inverting receiver input.
3
FN7638.0
June 25, 2010
ISL31480E, ISL31483E, ISL31485E, ISL31486E
Pin Descriptions (Continued)
PIN ISL31480E ISL31483E ISL31485E
NAME
PIN #
PIN #
PIN #
ISL31486E ISL31486E ISL31486E
(14 LD)
(10 LD)
(12 LD)
PIN #
PIN #
PIN #
FUNCTION
B
N/A
11
N/A
N/A
N/A
N/A
±60V Fault Protected
RS-485/RS-422 level input. If RINV
is low, then B is the inverting
receiver input. If RINV is high, then
B is the non-inverting receiver
input.
Y
N/A
9
N/A
N/A
N/A
N/A
±60V Fault Protected
RS-485/RS-422 level output. If
DINV is low, then Y is the noninverting driver output. If DINV is
high, then Y is the inverting driver
output
Z
N/A
10
N/A
N/A
N/A
N/A
±60V Fault Protected
RS-485/RS-422 level. If DINV is
low, then Z is the inverting driver
output. If DINV is high, then Z is
the non-inverting driver output
VCC
10
13, 14
8
11
9
13
System power supply input (4.5V
to 5.5V).
VL
1
N/A
N/A
12
10
14
Logic-Level Supply input (1.62V to
VCC) which powers all the
TTL/CMOS inputs and the RO
output (logic pins). VL sets the VIH
and VIL levels for logic input pins,
and sets the VOH level for the RO
pin. Power up this supply after VCC,
and keep VL ≤ VCC. To minimize
input current, logic input pins that
are strapped high externally should
connect to VL, but they may be
connected to VCC if necessary.
INV
N/A
N/A
2
3
3
3
Receiver and driver polarity
selection input. When driven high
this pin swaps the polarity of the
driver output and receiver input
pins. If unconnected (floating) or
connected low, normal RS-485
polarity conventions apply.
Internally pulled low.
RINV
N/A
1
N/A
N/A
N/A
N/A
Receiver polarity selection input.
When driven high this pin swaps
the polarity of the receiver input
pins. If unconnected (floating) or
connected low, normal RS-485
polarity conventions apply.
Internally pulled low.
DINV
N/A
8
N/A
N/A
N/A
N/A
Driver polarity selection input.
When driven high this pin swaps
the polarity of the driver output
pins. If unconnected (floating) or
connected low, normal RS-485
polarity conventions apply.
Internally pulled low.
PD
TDFN
ONLY
N/A
N/A
EPAD
N/A
N/A
TDFN exposed thermal pad
(EPAD). Connect to GND.
NC
7
N/A
N/A
6
N/A
5, 7, 10
4
No Internal Connection.
FN7638.0
June 25, 2010
ISL31480E, ISL31483E, ISL31485E, ISL31486E
Truth Tables
RECEIVING
INPUTS
TRANSMITTING
INPUTS
OUTPUTS
OUTPUT
RE
DE (Half
Duplex)
DE (Full
Duplex)
A-B
INV or
RINV
RO
0
0
X
≥ -0.01V
0
1
RE
DE
DI
INV or
DINV
Y
Z
X
1
1
0
1
0
0
0
X
≤ -0.2V
0
0
X
1
0
0
0
1
0
0
X
≤ 0.01V
1
1
X
1
1
1
0
1
0
0
X
≥ 0.2V
1
0
X
1
0
1
1
0
0
0
X
X
1
0
0
X
X
High-Z
High-Z
Inputs
Open or
Shorted
1
0
X
X
1
0
0
X
X
High-Z*
1
1
1
X
X
High-Z
High-Z* High-Z*
NOTE: *Low Power Shutdown Mode (See Note 13),
except for ISL31485E.
NOTE: *Low Power Shutdown Mode (See Note 13), except
for ISL31485E.
Typical Operating Circuits
ISL31486E HALF DUPLEX EXAMPLE (MSOP PIN NUMBERS SHOWN)
+5V +1.8V
+1.8V +5V
+
0.1µF
10
VL
3
INV
1 RO
+
0.1µF
9
+
0.1µF
A/Y 7
2 RE
RT
B/Z 8
RT
8 B/Z
VL
RO 1
R
RE 2
7 A/Y
DE 4
4 DE
5 DI
D
D
GND
6
+
0.1µF
10
VCC
VCC
R
9
GND
DI 5
INV
3
6
THE IC ON THE LEFT HAS THE CABLE CONNECTIONS
SWAPPED, SO THE INV PIN IS STRAPPED HIGH TO
INVERT ITS RX AND TX POLARITY
5
FN7638.0
June 25, 2010
ISL31480E, ISL31483E, ISL31485E, ISL31486E
Typical Operating Circuits (Continued)
ISL34183E FULL DUPLEX EXAMPLE (SOIC PIN NUMBERS SHOWN)
+5V
+5V
+
0.1µF
13, 14
1
VCC
RINV
B 11
2 RO
R
A 12
+
0.1µF
RT
13, 14
9 Y
VCC
10 Z
D
3 RE
DE 4
4 DE
5 DI
8
DI 5
Y 9
Z 10
D
DINV
GND
6, 7
RT
RE 3
11 B
12 A
GND
R
RO 2
1
RINV
DINV 8
6, 7
THE IC ON THE LEFT HAS THE CABLE CONNECTIONS
SWAPPED, SO THE INV PINS (1, 8) ARE STRAPPED
HIGH TO INVERT ITS RX AND TX POLARITY
6
FN7638.0
June 25, 2010
ISL31480E, ISL31483E, ISL31485E, ISL31486E
Table of Contents
Ordering Information ......................................................................................................................... 2
Pin Configuration ................................................................................................................................ 3
Pin Descriptions .................................................................................................................................. 3
Truth Tables ........................................................................................................................................ 6
Typical Operating Circuits.................................................................................................................... 6
Absolute Maximum Ratings ................................................................................................................ 9
Thermal Information .......................................................................................................................... 9
Recommended Operating Conditions .................................................................................................. 9
Electrical Specifications ..................................................................................................................... 9
Test Circuits and Waveforms ............................................................................................................. 12
Application Information .................................................................................................................... 15
Receiver (Rx) Features ....................................................................................................................
Driver (Tx) Features ........................................................................................................................
High Overvoltage (Fault) Protection Increases Ruggedness ...................................................................
Widest Common Mode Voltage (CMV) Tolerance Improves Operating Range............................................
Cable Invert (Polarity Reversal) Function ............................................................................................
Logic Supply (VL Pin).......................................................................................................................
High VOD Improves Noise Immunity and Flexibility..............................................................................
Hot Plug Function ............................................................................................................................
Data Rate, Cables, and Terminations .................................................................................................
Built-In Driver Overload Protection ....................................................................................................
Low Power Shutdown Mode ..............................................................................................................
15
15
15
15
15
16
16
17
17
17
17
Typical Performance Curves ............................................................................................................. 18
Die Characteristics ............................................................................................................................ 19
Revision History ................................................................................................................................ 20
Products ............................................................................................................................................ 20
Package Outline Drawing ................................................................................................................. 21
Package Outline Drawing ................................................................................................................. 22
Package Outline Drawing ................................................................................................................. 23
Package Outline Drawing ................................................................................................................. 24
Package Outline Drawing ................................................................................................................. 25
7
FN7638.0
June 25, 2010
ISL31480E, ISL31483E, ISL31485E, ISL31486E
Absolute Maximum Ratings
Thermal Information
VCC to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V
Input Voltages
DI, INV, RINV, DINV, DE, RE . . . . . . -0.3V to (VCC + 0.3V)
Input/Output Voltages
A/Y, B/Z, A, B, Y, Z . . . . . . . . . . . . . . . . . . . . . . . . ±60V
A/Y, B/Z, A, B, Y, Z (Transient Pulse Through 100Ω,
Note 19) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±80V
RO (ISL31480E, ISL31486E) . . . . . . . -0.3V to (VL +0.3V)
RO (ISL31483E, ISL31485E) . . . . . . -0.3V to (VCC +0.3V)
Short Circuit Duration
Y, Z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Indefinite
ESD Rating . . . . . . . . . . . . . . . . . . See Specification Table
Latch-up per JESD78, Level 2, Class A . . . . . . . . . . +125°C
Thermal Resistance (Typical)
θJA (°C/W) θJC (°C/W)
8 Ld SOIC Package (Notes 4, 6) . .
116
47
10 Ld MSOP Package (Notes 4, 6) .
135
50
10 Ld TDFN Package (Notes 5, 7) .
58
7
12 Ld TDFN Package (Notes 5, 7) .
35
3
14 Ld SOIC Package (Notes 4, 6). .
88
38
Maximum Junction Temperature (Plastic Package) . +150°C
Maximum Storage Temperature Range . . -65°C to +150°C
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Supply Voltage (VCC) . . . . . . . . . . . .
Logic Supply Voltage (VL) . . . . . . . . .
Temperature Range . . . . . . . . . . . . . .
Bus Pin Common Mode Voltage Range .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. . . . . . . . . 5V
. . 1.62V to VCC
-40°C to +85°C
. -25V to +25V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.
NOTE:
4. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief
TB379 for details.
5. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach”
features. See Tech Brief TB379 for details.
6. For θJC, the “case temp” location is taken at the package top center.
7. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications Test Conditions: VCC = 4.5V to 5.5V, VL = VCC; Unless Otherwise Specified. Typicals are at
VCC = 5V, TA = +25°C (Note 8). Boldface limits apply over the operating temperature
range, -40°C to +85°C.
PARAMETER
SYMBOL
TEST CONDITIONS
TEMP
MIN
(°C) (Note 16)
TYP
MAX
(Note 16) UNITS
DC CHARACTERISTICS
Driver Differential VOUT
(No load)
VOD1
Driver Differential VOUT
(Loaded, Figure 1A)
VOD2
Full
-
-
VCC
V
RL = 100Ω (RS-422)
Full
2.4
3.2
-
V
RL = 54Ω (RS-485)
Full
1.5
2.5
VCC
V
RL = 54Ω (PROFIBUS, VCC ≥ 5V)
Full
2.0
2.5
-
V
RL = 21Ω (Six 120Ω terminations for
Star Configurations, VCC ≥ 4.75V)
Full
0.8
1.3
-
V
Full
-
-
0.2
V
VCC
V
Change in Magnitude of
Driver Differential VOUT
for Complementary
Output States
ΔVOD
RL = 54Ω or 100Ω (Figure 1A)
Driver Differential VOUT
with Common Mode Load
(Figure 1B)
VOD3
RL = 60Ω, -7V ≤ VCM ≤ 12V
Full
1.5
2.1
RL = 60Ω, -25V ≤ VCM ≤ 25V
(VCC ≥ 4.75V)
Full
1.7
2.3
RL = 21Ω, -15V ≤ VCM ≤ 15V
(VCC ≥ 4.75V)
Full
0.8
1.1
-
V
RL = 54Ω or 100Ω
Full
-1
-
3
V
RL = 60Ω or 100Ω, -20V ≤ VCM ≤ 20V
Full
-2.5
-
5
V
Driver Common-Mode
VOUT (Figure 1)
VOC
8
V
FN7638.0
June 25, 2010
ISL31480E, ISL31483E, ISL31485E, ISL31486E
Electrical Specifications Test Conditions: VCC = 4.5V to 5.5V, VL = VCC; Unless Otherwise Specified. Typicals are at
VCC = 5V, TA = +25°C (Note 8). Boldface limits apply over the operating temperature
range, -40°C to +85°C. (Continued)
Change in Magnitude of
Driver Common-Mode
VOUT for Complementary
Output States
DVOC
RL = 54Ω or 100Ω (Figure 1A)
Full
-
-
0.2
-
250
mA
83
mA
Logic Input High Voltage
IOSD
DE = VCC, -25V ≤ VO ≤ 25V (Note 10)
Full
-250
IOSD1
At First Fold-back, 22V ≤ VO ≤ -22V
Full
-83
IOSD2
At Second Fold-back, 35V ≤ VO ≤ -35V
Full
-13
13
mA
DE, DI, RE, INV,
RINV, DINV
VL = VCC If
Applicable
Full
2.5
-
-
V
VIH2
DE, DI, RE, INV,
(Only ISL31480E,
ISL31486E)
2.7V ≤ VL ≤ 3V
Full
2
-
-
V
2.3V ≤ VL < 2.7V
Full
1.7
-
-
V
1.6V ≤ VL < 2.3V
Full
0.7*VL
-
-
V
VL = VCC If
Applicable
Full
-
-
0.8
V
VIH4
VIL1
DE, DI, RE, INV,
RINV, DINV
VIL2
DE, DI, RE, INV,
(Only ISL31480E,
ISL31486E)
VIL3
VIL4
Logic Input Current
IIN1
Input/Output Current
(A/Y, B/Z)
IIN2
Input Current (A, B)
(Full Duplex Versions
Only)
Output Leakage Current
(Y, Z) (Full Duplex
Versions Only)
Receiver Differential
Threshold Voltage
V
VIH1
VIH3
Logic Input Low Voltage
TYP
MAX
(Note 16) UNITS
SYMBOL
Driver Short-Circuit
Current
TEST CONDITIONS
TEMP
MIN
(°C) (Note 16)
PARAMETER
IIN3
IOZD
VTH
2.7V ≤ VL ≤ 3V
Full
-
-
0.8
V
2.3V ≤ VL < 2.7V
Full
-
-
0.65
V
1.6V ≤ VL < 2.3V
Full
-
-
0.3*VL
V
Full
-1
-
1
µA
DE, RE, INV, RINV, DINV
Full
-15
6
15
µA
DE = 0V,
VCC = 0V or 5.5V
VIN = 12V
Full
-
110
250
µA
DI
VCC = 0V or 5.5V
RE = 0V, DE = 0V,
VCC = 0V or 5.5V
µA
800
µA
VIN = ±60V
(Note 20)
Full
-6
±0.7
6
mA
VIN = 12V
Full
-
90
125
µA
VIN = -7V
Full
-100
-70
-
µA
VIN = ±25V
Full
-500
±200
500
µA
VIN = ±60V
(Note 20)
Full
-3
±0.5
3
mA
VIN = 12V
Full
-
20
200
µA
-100
-5
-
µA
-500
±40
500
µA
VIN = ±60V
(Note 20)
Full
-3
±0.15
3
mA
A-B for ISL31480E or if INV or
RINV = 0; B-A if INV or RINV = 1,
-25V ≤ VCM ≤ 25V
Full
-200
-100
-10
mV
25
-
25
-
mV
VOH1
VID = -10mV,
VL = VCC If
Applicable
9
-
±240
Full
Receiver Output High
Voltage
VOH5
-75
-800
Full
-25V ≤ VCM ≤ 25V
VOH4
-200
Full
VIN = -7V
DVTH
VOH3
Full
VIN = ±25V
Receiver Input Hysteresis
VOH2
VIN = -7V
VIN = ±25V
VID = -10mV,
Only ISL31480E,
ISL31486E
IO = -2mA
Full
VCC - 0.5
4.75
-
V
IO = -8mA
Full
2.8
4.2
-
V
VL ≥ 2.7V,
IO = -1.5mA
Full
VL-0.3
-
V
VL ≥ 2.3V,
IO = -1mA
Full
VL-0.3
-
V
VL ≥ 1.6V,
IO = -500mA
Full
VL-0.25
-
V
FN7638.0
June 25, 2010
ISL31480E, ISL31483E, ISL31485E, ISL31486E
Electrical Specifications Test Conditions: VCC = 4.5V to 5.5V, VL = VCC; Unless Otherwise Specified. Typicals are at
VCC = 5V, TA = +25°C (Note 8). Boldface limits apply over the operating temperature
range, -40°C to +85°C. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
TEMP
MIN
(°C) (Note 16)
TYP
MAX
(Note 16) UNITS
Receiver Output Low
Voltage
VOL
IO = 6mA, VL ≥ 1.6V, VID = -200mV
Full
-
0.27
0.4
V
Receiver Output Low
Current
IOL
VO = 1V, VL ≥ 1.6V, VID = -200mV
Full
15
22
-
mA
Three-State (High
Impedance) Receiver
Output Current
IOZR
0V ≤ VO ≤ VL (If Applicable) or VCC
(Note 19)
Full
-1
0.01
1
µA
Receiver Short-Circuit
Current
IOSR
0V ≤ VO ≤ VCC, VL = VCC if applicable
Full
±12
-
±110
mA
ICC
DE = VCC, RE = 0V or VCC, DI = 0V or
VCC
Full
-
2.3
4.5
mA
DE = 0V, RE = VCC, DI = 0V or VCC
(Note 19)
Full
-
10
50
µA
Human Body Model
(Tested per JESD22-A114E)
25
-
±2
-
kV
Machine Model
(Tested per JESD22-A115-A)
25
-
±700
-
V
SUPPLY CURRENT
No-Load Supply Current
(Note 9)
Shutdown Supply
Current
ISHDN
ESD PERFORMANCE
All Pins
DRIVER SWITCHING CHARACTERISTICS
Driver Differential Output
Delay
tPLH, tPHL RD = 54Ω,
CD = 50pF
(Figure 2)
No CM Load
Full
-
70
125
ns
-25V ≤ VCM ≤ 25V
Full
-
-
350
ns
RD = 54Ω,
CD = 50pF
(Figure 2)
No CM Load
Full
-
4.5
15
ns
-25V ≤ VCM ≤ 25V
Full
-
-
25
ns
RD = 54Ω,
CD = 50pF
(Figure 2)
No CM Load
Full
70
230
300
ns
-25V ≤ VCM ≤ 25V
Full
70
-
400
ns
Driver Differential Output
Skew
tSKEW
Driver Differential Rise or
Fall Time
tR, tF
Maximum Data Rate
fMAX
CD = 820pF, VL ≥ 1.6V (Figure 4)
Full
1
4
-
Mbps
Driver Enable to Output
High
tZH
SW = GND (Figure 3), (Note 11)
Full
-
-
350
ns
Driver Enable to Output
Low
tZL
SW = VCC (Figure 3), (Note 11)
Full
-
-
300
ns
Driver Disable from
Output Low
tLZ
SW = VCC (Figure 3)
Full
-
-
120
ns
Driver Disable from
Output High
tHZ
SW = GND (Figure 3)
Full
-
-
120
ns
Time to Shutdown
tSHDN
Full
60
160
600
ns
Driver Enable from
tZH(SHDN) SW = GND (Figure 3),
Shutdown to Output High
(Notes 13, 14, 19)
(Notes 13, 19)
Full
-
-
2000
ns
Driver Enable from
Shutdown to Output Low
Full
-
-
2000
ns
tZL(SHDN) SW = VCC (Figure 3),
(Notes 13, 14, 19)
RECEIVER SWITCHING CHARACTERISTICS
Maximum Data Rate
Receiver Input to Output
Delay
-25V ≤ VCM ≤ 25V (Figure 5)
Full
1
15
-
Mbps
-15V ≤ VCM ≤ 15V, VL ≥ 1.6V
(Figure 5)
Full
1
12
-
Mbps
tPLH, tPHL -25V ≤ VCM ≤ 25V (Figure 5)
Full
-
90
150
ns
fMAX
10
FN7638.0
June 25, 2010
ISL31480E, ISL31483E, ISL31485E, ISL31486E
Electrical Specifications Test Conditions: VCC = 4.5V to 5.5V, VL = VCC; Unless Otherwise Specified. Typicals are at
VCC = 5V, TA = +25°C (Note 8). Boldface limits apply over the operating temperature
range, -40°C to +85°C. (Continued)
PARAMETER
SYMBOL
Receiver Skew | tPLH tPHL |
tSKD
TEMP
MIN
(°C) (Note 16)
TEST CONDITIONS
TYP
MAX
(Note 16) UNITS
(Figure 5)
Full
-
4
10
ns
Receiver Enable to
Output Low
tZL
RL = 1kΩ, CL = 15pF, SW = VCC
(Figure 6), (Notes 12, 19)
Full
-
-
50
ns
Receiver Enable to
Output High
tZH
RL = 1kΩ, CL = 15pF, SW = GND
(Figure 6), (Notes 12, 19)
Full
-
-
50
ns
Receiver Disable from
Output Low
tLZ
RL = 1kΩ, CL = 15pF, SW = VCC
(Figure 6) (Note 19)
Full
-
-
50
ns
Receiver Disable from
Output High
tHZ
RL = 1kΩ, CL = 15pF, SW = GND
(Figure 6) (Note 19)
Full
-
-
50
ns
Time to Shutdown
tSHDN
Full
60
160
600
ns
Receiver Enable from
tZH(SHDN) RL = 1kΩ, CL = 15pF, SW = GND
(Figure 6), (Notes 13, 15, 19)
Shutdown to Output High
(Notes 13, 19)
Full
-
-
2000
ns
Receiver Enable from
Shutdown to Output Low
Full
-
-
2000
ns
tZL(SHDN) RL = 1kΩ, CL = 15pF, SW = VCC
(Figure 6), (Notes 13, 15, 19)
NOTES:
8. All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device
ground unless otherwise specified.
9. Supply current specification is valid for loaded drivers when DE = 0V.
10. Applies to peak current. See “Typical Performance Curves” beginning on page 18 for more information
11. Keep RE = 0 to prevent the device from entering SHDN.
12. The RE signal high time must be short enough (typically <100ns) to prevent the device from entering SHDN.
13. Transceivers (except on the ISL31485E) are put into shutdown by bringing RE high and DE low. If the inputs are in this state
for less than 60ns, the parts are guaranteed not to enter shutdown. If the inputs are in this state for at least 600ns, the parts
are guaranteed to have entered shutdown. See “Low Power Shutdown Mode” on page 17.
14. Keep RE = VCC, and set the DE signal low time >600ns to ensure that the device enters SHDN.
15. Set the RE signal high time >600ns to ensure that the device enters SHDN.
16. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established
by characterization and are not production tested.
17. See Figure 9 for more information, and for performance over-temperature.
18. Tested according to TIA/EIA-485-A, Section 4.2.6 (±80V for 15ms at a 1% duty cycle).
19. Does not apply to the ISL31485E. The ISL31485E has no Rx enable function, and thus no SHDN function.
20. See “Caution” statement in the “Recommended Operating Conditions” section on page 9.
Test Circuits and Waveforms
VL OR VCC
RL/2
DE
DI
VL OR
VCC
Z
VOD
D
DI
Z
RL/2
VCM
VOD
D
Y
Y
VOC
RL/2
VOC
FIGURE 1A. VOD AND VOC
375Ω
RL/2
DE
375Ω
FIGURE 1B. 1B
FIGURE 1. DC DRIVER TEST CIRCUITS
11
FN7638.0
June 25, 2010
ISL31480E, ISL31483E, ISL31485E, ISL31486E
Test Circuits and Waveforms (Continued)
DI
50%
LOWER OF
3V OR VL
50%
0V
VL OR VCC
tPHL
tPLH
375Ω*
DE
OUT (Z)
VOH
OUT (Y)
VOL
Z
DI
RD
CD
D
Y
SIGNAL
GENERATOR
375Ω*
VCM
90%
DIFF OUT (Y - Z)
*ONLY USED FOR COMMON
MODE LOAD TESTS
+VOD
90%
10%
10%
tR
-VOD
tF
SKEW = |tPLH - tPHL|
FIGURE 2A. TEST CIRCUIT
FIGURE 2B. MEASUREMENT POINTS
FIGURE 2. DRIVER PROPAGATION DELAY AND DIFFERENTIAL TRANSITION TIMES
DE
Z
DI
110Ω
VCC
D
SIGNAL
GENERATOR
SW
Y
GND
DE
CL
NOTE 13
50%
0V
tZH, tZH(SHDN)
tHZ
OUTPUT HIGH
NOTE 13
PARAMETER
OUTPUT
RE
DI
SW
CL
(pF)
tHZ
Y/Z
X
1/0
GND
50
tLZ
Y/Z
X
0/1
VCC
50
tZH
Y/Z
0 (Note 12)
1/0
GND
100
tZL
Y/Z
0 (Note 12)
0/1
VCC
100
tZH(SHDN)
Y/Z
1 (Note 15)
1/0
GND
100
tZL(SHDN)
Y/Z
1 (Note 15)
0/1
VCC
100
FIGURE 3A. TEST CIRCUIT
50%
LOWER OF
3V OR VL
VOH - 0.5V
2.3V
OUT (Y, Z)
VOH
0V
tZL, tZL(SHDN)
tLZ
NOTE 13
VCC
OUT (Y, Z)
2.3V
OUTPUT LOW
VOL + 0.5V V
OL
FIGURE 3B. MEASUREMENT POINTS
FIGURE 3. DRIVER ENABLE AND DISABLE TIMES
VL OR VCC
DE
+
Z
DI
54Ω
D
CD
Y
LOWER OF
3V OR VL
DI
0V
VOD
-
DIFF OUT (Y - Z)
SIGNAL
GENERATOR
FIGURE 4A. TEST CIRCUIT
+VOD
-VOD
0V
FIGURE 4B. MEASUREMENT POINTS
FIGURE 4. DRIVER DATA RATE
12
FN7638.0
June 25, 2010
ISL31480E, ISL31483E, ISL31485E, ISL31486E
Test Circuits and Waveforms (Continued)
RE
B
R
A
SIGNAL
GENERATOR
B
15pF
RO
VCM + 750mV
VCM
VCM
VCM - 750mV
A
tPLH
SIGNAL
GENERATOR
tPHL
VCC OR VL
50%
RO
VCM
50%
0V
FIGURE 5A. TEST CIRCUIT
FIGURE 5B. MEASUREMENT POINTS
FIGURE 5. RECEIVER PROPAGATION DELAY AND DATA RATE
VL
OR
VCC
RE
B
A
R
1kΩ
RO
SIGNAL
GENERATOR
15pF
SW
GND
RE
50%
50%
LOWER OF
3V OR VL
0V
PARAMETER
DE
A
SW
tHZ
0
+1.5V
GND
tLZ
0
-1.5V
VL / VCC
tZH (Note 12)
0
+1.5V
GND
tZL (Note 12)
0
-1.5V
VL / VCC
tZH(SHDN) (Note 16)
0
+1.5V
GND
tZL(SHDN) (Note 16)
0
-1.5V
VL / VCC
FIGURE 6A. TEST CIRCUIT
NOTE 13
tZH, tZH(SHDN)
NOTE 13
tHZ
OUTPUT HIGH
VOH - 0.5V
1.5V
RO
VOH
0V
tZL, tZL(SHDN)
tLZ
NOTE 13
RO
VL
OR
VCC
1.5V
VOL + 0.5V
VOL
OUTPUT LOW
FIGURE 6B. MEASUREMENT POINTS
FIGURE 6. RECEIVER ENABLE AND DISABLE TIMES
13
FN7638.0
June 25, 2010
ISL31480E, ISL31483E, ISL31485E, ISL31486E
Application Information
Driver (Tx) Features
RS-485 and RS-422 are differential (balanced) data
transmission standards used for long haul or noisy
environments. RS-422 is a subset of RS-485, so RS-485
transceivers are also RS-422 compliant. RS-422 is a
point-to-multipoint (multidrop) standard, which allows
only one driver and up to 10 (assuming one unit load
devices) receivers on each bus. RS-485 is a true
multipoint standard, which allows up to 32 one unit load
devices (any combination of drivers and receivers) on
each bus. To allow for multipoint operation, the RS-485
specification requires that drivers must handle bus
contention without sustaining any damage.
The RS-485/RS-422 driver is a differential output device
that delivers at least 1.5V across a 54Ω load (RS-485),
and at least 2.4V across a 100Ω load (RS-422). The
drivers feature low propagation delay skew to maximize
bit width, and to minimize EMI, and all drivers are threestatable via the active high DE input.
Another important advantage of RS-485 is the extended
common mode range (CMR), which specifies that the
driver outputs and receiver inputs withstand signals that
range from +12V to -7V. RS-422 and RS-485 are
intended for runs as long as 4000’, so the wide CMR is
necessary to handle ground potential differences, as well
as voltages induced in the cable by external fields.
Note: The available smaller pitch packages (e.g., MSOP
and TDFN) may not meet the creepage and clearance
(C&C) requirements for ±60V levels. The user is advised
to determine his C&C requirements before selecting a
package type.
The ISL3148xE is a family of ruggedized RS-485
transceivers that improves on the RS-485 basic
requirements, and therefore increases system reliability.
The CMR increases to ±25V, while the RS-485 bus pins
(receiver inputs and driver outputs) include fault
protection against voltages and transients up to ±60V.
Additionally, larger than required differential output
voltages (VOD) increase noise immunity.
Receiver (Rx) Features
These devices utilize a differential input receiver for
maximum noise immunity and common mode rejection.
Input sensitivity is better than ±200mV, as required by
the RS-422 and RS-485 specifications.
Receiver input (load) current surpasses the RS-422
specification of 3mA, and is four times lower than the
RS-485 “Unit Load (UL)” requirement of 1mA maximum.
Thus, these products are known as “one-quarter UL”
transceivers, and there can be up to 128 of these devices
on a network while still complying with the RS-485
loading specification.
The Rx functions with common mode voltages as great
as ±25V, making them ideal for industrial, or long
networks where induced voltages are a realistic concern.
All the receivers include a “full fail-safe” function that
guarantees a high level receiver output if the receiver
inputs are unconnected (floating), shorted together, or
connected to a terminated bus with all the transmitters
disabled (i.e., an idle bus).
Rx outputs feature high drive levels (typically 22mA @
VOL = 1V) to ease the design of optically coupled
isolated interfaces. Except for the ISL31485E, Rx
outputs are three-statable via the active low RE input.
The Rx includes noise filtering circuitry to reject high
frequency signals, and typically rejects pulses narrower
than 50ns (equivalent to 20Mbps).
14
The driver outputs are slew rate limited to minimize EMI,
and to minimize reflections in unterminated or
improperly terminated networks.
High Overvoltage (Fault) Protection
Increases Ruggedness
The ±60V (referenced to the IC GND) fault protection on
the RS-485 pins, makes these transceivers some of the
most rugged on the market. This level of protection
makes the ISL3148xE perfect for applications where
power (e.g., 24V and 48V supplies) must be routed in the
conduit with the data lines, or for outdoor applications
where large transients are likely to occur. When power is
routed with the data lines, even a momentary short
between the supply and data lines will destroy an
unprotected device. The ±60V fault levels of this family
are at least five times higher than the levels specified
for standard RS-485 ICs. The ISL3148xE protection is
active whether the Tx is enabled or disabled, and even if
the IC is powered down.
If transients or voltages (including overshoots and
ringing) greater then ±60V are possible, then additional
external protection is required.
Widest Common Mode Voltage (CMV)
Tolerance Improves Operating Range
RS-485 networks operating in industrial complexes, or
over long distances, are susceptible to large CMV
variations. Either of these operating environments may
suffer from large node-to-node ground potential
differences, or CMV pickup from external electromagnetic
sources, and devices with only the minimum required
+12V to -7V CMR may malfunction. The ISL3148xE’s
extended ±25V CMR is the widest available, allowing
operation in environments that would overwhelm lesser
transceivers. Additionally, the Rx will not phase invert
(erroneously change state) even with CMVs of ±40V, or
differential voltages as large as 40V.
Cable Invert (Polarity Reversal) Function
With large node count RS-485 networks, it is common for
some cable data lines to be wired backwards during
installation. When this happens the node is unable to
communicate over the network. Once a technician finds
the miswired node, he must then rewire the connector
which is time consuming.
FN7638.0
June 25, 2010
ISL31480E, ISL31483E, ISL31485E, ISL31486E
The ISL31483E, ISL31485E, and ISL31486E simplify this
task by including cable invert pins (INV, DINV, RINV) that
allow the technician to invert the polarity of the Rx input
and/or the Tx output pins simply by moving a jumper to
change the state of the invert pin(s). When the invert
pin(s) is low, the IC operates like any standard RS-485
transceiver and the bus pins have their normal polarity
definition of A and Y being noninverting, and B and Z
being inverting. With the invert pin high, the
corresponding bus pins reverse their polarity, so B and Z
are now noninverting and A and Y become inverting.
Intersil’s unique cable invert function is superior to that
found on competing devices because the Rx full failsafe
function is maintained even when the Rx polarity is
reversed. Competitor devices implement the Rx invert
function simply by inverting the Rx output. This means
that with the Rx inputs floating or shorted together, the
Rx appropriately delivers a logic 1 in normal polarity, but
outputs a logic low when the IC is operated in the
inverted mode. Intersil’s innovative Rx design guarantees
that with the Rx inputs floating, or shorted together
(VID=0V), the Rx output remains high regardless of the
state of the invert pins.
The full duplex ISL31483E includes two invert pins that
allow for separate control of the Rx and Tx polarities. If
only the Rx cable is miswired, then only the RINV pin
need be driven to a logic 1. If the Tx cable is miswired,
then DINV must be connected to a logic high. The two
half duplex versions have only one logic pin (INV) that,
when high, switches the polarity of both the Tx and the
Rx blocks.
VCC = +5V
RO
DI
GND
VCC = +1.8V
VOH = 5V
RXD
VIH ≥ 2V
VOH ≈ 1.8V
ISL31483E
TXD
GND
UART/PROCESSOR
VCC = +5V
VCC = +1.8V
VL
RO
DI
GND
ISL31480E
ESD
DIODE
VOH = 1.8V
RXD
VIH = 1.1V
VOH ≈ 1.8V
ESD
DIODE
TXD
GND
UART/PROCESSOR
FIGURE 7. USING VL PIN TO ADJUST LOGIC LEVELS
TABLE 2. VIH AND VIL vs. VL FOR VCC = 5V
VL (V)
VIH (V)
VIL (V)
1.6
1.0
0.6
1.8
1.1
0.7
Logic Supply (VL Pin)
2.3
1.3
0.9
Note: Power up VCC before powering up the VL supply,
and keep VL ≤ VCC.
2.7
1.4
1.1
3.3
1.6
1.3
The ISL31480E and ISL31486E include a VL pin that
powers the logic inputs (Tx input and control pins) and the
Rx output. These pins interface with “logic” devices such as
UARTs, ASICs, and µcontrollers, and today many of these
devices use power supplies significantly lower than 5V.
Thus, a 5V output level from this transceiver IC might
seriously overdrive and damage the logic device input (see
Figure 7). Similarly, the logic device’s low VOH might not
exceed the VIH of a 5V powered transceiver input.
Connecting the VL pin to the power supply of the logic
device - as shown in Figure 7 - limits the ISL3148xE’s RO
pin VOH to the VL voltage, and reduces the Tx and control
input switching points to values compatible with the logic
device output levels. Tailoring the logic pin input switching
points and output levels to the supply voltage of the UART,
ASIC, or µcontroller eliminates the need for a level
shifter/translator between the two ICs.
VL can be anywhere from VCC down to 1.62V, and the
transceivers easily operate at the 1Mbps data rate over
this range as long as the VCM doesn’t exceed ±15V.
Table 2 indicates typical VIH and VIL values for various
VL voltages so the user can ascertain whether or not a
particular VL voltage meets his/her needs.
15
The VL supply current (IL) is typically less than 6µA. All
of the DC VL current is due to current through the DE
input internal pull-up resistor when the pin is driven to
the low input state.
Transceiver logic inputs that are externally tied high in an
application should use the VL supply for the high voltage
level to minimize input currents. Except for DI, all logic
inputs have 800kΩ pull-up (DE) or pull-down (all other
pins) resistors, so connecting an input to the lower voltage
VL supply minimizes current. The DE pull-up internally
connects to VL, so connecting the DE pin to VCC induces an
input current of (VCC - VL)/800kΩ.
High VOD Improves Noise Immunity and
Flexibility
The ISL3148xE driver design delivers larger differential
output voltages (VOD) than the RS-485 standard
requires, or than most RS-485 transmitters can deliver.
The typical ±2.5V VOD provides more noise immunity
than networks built using many other transceivers.
Another advantage of the large VOD is the ability to drive
more than two bus terminations, which allows for
FN7638.0
June 25, 2010
ISL31480E, ISL31483E, ISL31485E, ISL31486E
utilizing the ISL3148xE in “star” and other
multi-terminated, nonstandard network topologies.
Figure 9, details the transmitter’s VOD vs IOUT
characteristic, and includes load lines for four (30Ω) and
six (20Ω) 120Ω terminations. The figure shows that the
driver typically delivers ±1.3V into six terminations, and
the “Electrical Specification” table guarantees a VOD of
±0.8V at 21Ω over the full temperature range. The
RS-485 standard requires a minimum 1.5V VOD into two
terminations, but the ISL3148xE deliver RS-485 voltage
levels with 2x to 3x the number of terminations.
Hot Plug Function
When a piece of equipment powers up, there is a period
of time where the processor or ASIC driving the RS-485
control lines (DE, RE) is unable to ensure that the
RS-485 Tx and Rx outputs are kept disabled. If the
equipment is connected to the bus, a driver activating
prematurely during power-up may crash the bus. To
avoid this scenario, the ISL3148xE devices incorporate a
“Hot Plug” function. Circuitry monitoring VCC ensures
that, during power-up and power-down, the Tx and Rx
outputs remain disabled, regardless of the state of DE
and RE, if VCC is less than ≈3.5V. This gives the
processor/ASIC a chance to stabilize and drive the
RS-485 control lines to the proper states. Figure 8
illustrates the power-up and power-down performance of
the ISL3148xE compared to an RS-485 IC without the
Hot Plug feature.
RE = GND
2.8V
2.5
VCC
0
5.0
RL = 1kΩ
2.5
0
5.0
A/Y
ISL3148XE
RL = 1kΩ
RO
ISL3148XE
RECEIVER OUTPUT (V)
DRIVER Y OUTPUT (V)
3.5V
VCC (V)
DE, DI = VCC
5.0
2.5
0
TIME (40µs/DIV)
FIGURE 8. HOT PLUG PERFORMANCE (ISL3148XE)
vs ISL83088E WITHOUT HOT PLUG
CIRCUITRY
Data Rate, Cables, and Terminations
RS-485/RS-422 are intended for network lengths up to
4000’, but the maximum system data rate decreases as
the transmission length increases. These 1Mbps versions
can operate at full data rates with lengths up to 800’
(244m). Jitter is the limiting parameter at this data rate,
so employing encoded data streams (e.g., Manchester
coded or Return-to-Zero) may allow increased
transmission distances.
16
Twisted pair is the cable of choice for RS-485/RS-422
networks. Twisted pair cables tend to pick up noise and
other electromagnetically induced voltages as common
mode signals, which are effectively rejected by the
differential receivers in these ICs.
Proper termination is imperative to minimize reflections, and
terminations are recommended unless power dissipation is
an overriding concern. In point-to-point, or point-tomultipoint (single driver on bus like RS-422) networks, the
main cable should be terminated in its characteristic
impedance (typically 120Ω) at the end farthest from the
driver. In multi-receiver applications, stubs connecting
receivers to the main cable should be kept as short as
possible. Multipoint (multi-driver) systems require that the
main cable be terminated in its characteristic impedance at
both ends. Stubs connecting a transceiver to the main cable
should be kept as short as possible.
Built-In Driver Overload Protection
As stated previously, the RS-485 specification requires
that drivers survive worst case bus contentions
undamaged. These transceivers meet this requirement
via driver output short circuit current limits, and on-chip
thermal shutdown circuitry.
The driver output stages incorporate a double foldback
short circuit current limiting scheme which ensures that
the output current never exceeds the RS-485
specification, even at the common mode and fault
condition voltage range extremes. The first foldback
current level (≈70mA) is set to ensure that the driver
never folds back when driving loads with common mode
voltages up to ±25V. The very low second foldback
current setting (≈9mA) minimizes power dissipation if
the Tx is enabled when a fault occurs.
In the event of a major short circuit condition, devices
also include a thermal shutdown feature that disables
the drivers whenever the die temperature becomes
excessive. This eliminates the power dissipation,
allowing the die to cool. The drivers automatically
re-enable after the die temperature drops about 15°C.
If the contention persists, the thermal shutdown/reenable cycle repeats until the fault is cleared. Receivers
stay operational during thermal shutdown.
Low Power Shutdown Mode
These CMOS transceivers all use a fraction of the power
required by competitive devices, but they also include a
shutdown feature (except the ISL31485E) that reduces
the already low quiescent ICC to a 10µA trickle. These
devices enter shutdown whenever the receiver and driver
are simultaneously disabled (RE = VCC and
DE = GND) for a period of at least 600ns. Disabling both
the driver and the receiver for less than 60ns guarantees
that the transceiver will not enter shutdown.
Note that receiver and driver enable times increase when
the transceiver enables from shutdown. Refer to Notes
11, 12, 13, 14 and 15, at the end of the “Electrical
Specification” table on page 11, for more information.
FN7638.0
June 25, 2010
ISL31480E, ISL31483E, ISL31485E, ISL31486E
DRIVER OUTPUT CURRENT (mA)
90
RD = 20Ω
80
VCC = 5V, TA = +25°C; Unless Otherwise Specified.
RD = 30Ω
+25°C
70
RD = 54Ω
+85°C
60
50
40
RD = 100Ω
30
20
10
0
0
1
2
3
4
DIFFERENTIAL OUTPUT VOLTAGE (V)
5
DIFFERENTIAL OUTPUT VOLTAGE (V)
Typical Performance Curves
3.6
3.4
RD = 100Ω
3.2
3.0
2.8
2.6
RD = 54Ω
2.4
2.2
-40
-25
0
25
50
TEMPERATURE (°C)
75 85
FIGURE 10. DRIVER DIFFERENTIAL OUTPUT
VOLTAGE vs TEMPERATURE
FIGURE 9. DRIVER OUTPUT CURRENT vs
DIFFERENTIAL OUTPUT VOLTAGE
2.45
2.40
DE = VCC, RE = X
2.35
ICC (mA)
2.30
2.25
DE = GND, RE = GND
2.20
2.15
2.10
2.05
2.00
-40
-25
0
25
50
TEMPERATURE (°C)
75 85
FIGURE 11. SUPPLY CURRENT vs TEMPERATURE
800
60
VOL, +25°C
50
600
VOL, +85°C
BUS PIN CURRENT (µA)
RECEIVER OUTPUT CURRENT (mA)
70
40
30
20
10
0
-10
0
Y or Z
-200
A/Y or B/Z
VOH, +25°C
-600
-30
0
200
-400
VOH, +85°C
-20
400
1
2
3
4
RECEIVER OUTPUT VOLTAGE (V)
FIGURE 12. RECEIVER OUTPUT CURRENT vs
RECEIVER OUTPUT VOLTAGE
17
5
-70
-50
-30
-10 0 10
30
50
70
BUS PIN VOLTAGE (V)
FIGURE 13. BUS PIN CURRENT vs BUS PIN VOLTAGE
FN7638.0
June 25, 2010
ISL31480E, ISL31483E, ISL31485E, ISL31486E
Typical Performance Curves
85
VCC = 5V, TA = +25°C; Unless Otherwise Specified. (Continued)
4.0
RD = 54Ω, CD = 50pF
RD = 54Ω, CD = 50pF
PROPAGATION DELAY (ns)
80
3.5
70
SKEW (ns)
75
tPLH
65
tPHL
60
3.0
2.5
55
|tPLH - tPHL|
75 85
VOLTAGE (V)
FIGURE 14. DRIVER DIFFERENTIAL PROPAGATION
DELAY vs TEMPERATURE
25
20
15
10
5
0
5
0
-5
-10
-15
-20
-25
A
B
VID = ±1V
RO
RO
A
B
TIME (400ns/DIV)
FIGURE 16. ±25V RECEIVER PERFORMANCE
0
50
25
TEMPERATURE (°C)
-25
75 85
FIGURE 15. DRIVER DIFFERENTIAL SKEW vs
TEMPERATURE
RD = 54Ω, CD = 50pF
5
DI
5
0
3
2
1
0
-1
-2
-3
0
RO
DRIVER INPUT (V)
0
50
25
TEMPERATURE (°C)
-25
2.0
-40
DRIVER OUTPUT (V) RECEIVER OUTPUT (V)
50
-40
A/Y - B/Z
TIME (400ns/DIV)
FIGURE 17. DRIVER AND RECEIVER WAVEFORMS
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP) AND TDFN EPAD:
GND
PROCESS:
Si Gate BiCMOS
18
FN7638.0
June 25, 2010
ISL31480E, ISL31483E, ISL31485E, ISL31486E
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to
web to make sure you have the latest Rev.
DATE
REVISION
06/25/10
FN7638.0
CHANGE
Initial Release
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The
Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones,
handheld products, and notebooks. Intersil's product families address power management and analog signal
processing functions. Go to www.intersil.com/products for a complete list of Intersil product families.
*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device
information page on intersil.com: ISL31480E, ISL31483E, ISL31485E, ISL31486E
To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff
FITs are available from our website at http://rel.intersil.com/reports/search.php
19
FN7638.0
June 25, 2010
ISL31480E, ISL31483E, ISL31485E, ISL31486E
Mini Small Outline Plastic Packages (MSOP)
N
M10.118 (JEDEC MO-187BA)
10 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
E1
E
INCHES
SYMBOL
-B-
INDEX
AREA
1 2
0.20 (0.008)
A B C
TOP VIEW
4X θ
0.25
(0.010)
R1
R
GAUGE
PLANE
A
SEATING
PLANE -C-
A2
A1
b
-He
D
0.10 (0.004)
4X θ
L
SEATING
PLANE
C
-A0.20 (0.008)
C
C
a
SIDE VIEW
CL
E1
0.20 (0.008)
C D
-B-
END VIEW
MILLIMETERS
MAX
MIN
MAX
NOTES
A
0.037
0.043
0.94
1.10
-
A1
0.002
0.006
0.05
0.15
-
A2
0.030
0.037
0.75
0.95
-
b
0.007
0.011
0.18
0.27
9
c
0.004
0.008
0.09
0.20
-
D
0.116
0.120
2.95
3.05
3
E1
0.116
0.120
2.95
3.05
4
e
L1
MIN
0.020 BSC
0.50 BSC
-
E
0.187
0.199
4.75
5.05
-
L
0.016
0.028
0.40
0.70
6
L1
0.037 REF
0.95 REF
-
N
10
10
7
R
0.003
-
0.07
-
-
R1
0.003
-
0.07
-
-
θ
5o
15o
5o
15o
-
α
0o
6o
0o
6o
Rev. 0 12/02
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-187BA.
2. Dimensioning and tolerancing per ANSI Y14.5M-1994.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs and are measured at Datum Plane. Mold flash, protrusion
and gate burrs shall not exceed 0.15mm (0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions
and are measured at Datum Plane. - H - Interlead flash and
protrusions shall not exceed 0.15mm (0.006 inch) per side.
5. Formed leads shall be planar with respect to one another within
0.10mm (.004) at seating Plane.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).
10. Datums -A -H- .
and - B -
to be determined at Datum plane
11. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only
20
FN7638.0
June 25, 2010
ISL31480E, ISL31483E, ISL31485E, ISL31486E
Package Outline Drawing
L10.3x3A
10 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE
Rev 5, 3/10
3.00
A
2.0 REF
6
PIN 1
INDEX AREA
8X 0.50 BSC
B
5
1
6
PIN 1
INDEX AREA
10X 0 . 30
3.00
1.50
0.15
(4X)
10
0.10 M C A B
0.05 M C
5
4 10 X 0.25
TOP VIEW
2.30
( 2.30 )
BOTTOM VIEW
0 .80 MAX
SEE DETAIL "X"
0.10 C
C
(2.90)
SEATING PLANE
0.08 C
(1.50)
SIDE VIEW
(10 X 0.50)
5
0 . 2 REF
C
( 8X 0 .50 )
( 10X 0.25 )
0 . 00 MIN.
0 . 05 MAX.
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to ASME Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
Angular ±2.50°
4.
Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5.
Tiebar shown (if present) is a non-functional feature.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7.
21
Compliant to JEDEC MO-229-WEED-3 except exposed pad length (2.30mm).
FN7638.0
June 25, 2010
ISL31480E, ISL31483E, ISL31485E, ISL31486E
Thin Dual Flat No-Lead Plastic Package (TDFN)
L12.4x3A
12 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-229-WGED-4 ISSUE C)
2X
0.15 C A
A
D
MILLIMETERS
2X
0.15 C B
SYMBOL
0.70
A1
-
A3
E
b
6
INDEX
AREA
D2
B
//
A
SIDE VIEW
C
SEATING
PLANE
0.10
0.08
A3
7
8
-
-
0.05
-
0.23
0.30
5,8
4.00 BSC
3.15
3.30
3.40
7,8
3.00 BSC
1.55
e
1.70
1.80
7,8
0.50 BSC
-
k
0.20
-
-
-
L
0.30
0.40
0.50
8
N
12
2
Nd
6
3
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd refers to the number of terminals on D.
2
4. All dimensions are in millimeters. Angles are in degrees.
NX k
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
E2
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
(DATUM A)
E2/2
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
NX L
N
N-1
NX b
e
8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.
5
(Nd-1)Xe
REF.
BOTTOM VIEW
NX (b)
C
NOTES
0.80
Rev. 0 1/06
D2/2
1
C
MAX
0.75
NOTES:
D2
(DATUM B)
8
0.18
E
E2
NOMINAL
0.20 REF
D
TOP VIEW
6
INDEX
AREA
MIN
A
0.10
M C A B
CL
(A1)
L
5
e
SECTION "C-C" TERMINAL TIP
FOR EVEN TERMINAL/SIDE
22
FN7638.0
June 25, 2010
ISL31480E, ISL31483E, ISL31485E, ISL31486E
Package Outline Drawing
M14.15
14 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 1, 10/09
4
0.10 C A-B 2X
8.65
A 3
6
14
DETAIL"A"
8
0.22±0.03
D
6.0
3.9
4
0.10 C D 2X
0.20 C 2X
7
PIN NO.1
ID MARK
5
0.31-0.51
B 3
(0.35) x 45°
4° ± 4°
6
0.25 M C A-B D
TOP VIEW
0.10 C
1.75 MAX
H
1.25 MIN
0.25
GAUGE PLANE C
SEATING PLANE
0.10 C
0.10-0.25
1.27
SIDE VIEW
(1.27)
DETAIL "A"
(0.6)
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSEY14.5m-1994.
3. Datums A and B to be determined at Datum H.
(5.40)
4. Dimension does not include interlead flash or protrusions.
Interlead flash or protrusions shall not exceed 0.25mm per side.
5. The pin #1 indentifier may be either a mold or mark feature.
(1.50)
6. Does not include dambar protrusion. Allowable dambar protrusion
shall be 0.10mm total in excess of lead width at maximum condition.
7. Reference to JEDEC MS-012-AB.
TYPICAL RECOMMENDED LAND PATTERN
23
FN7638.0
June 25, 2010
ISL31480E, ISL31483E, ISL31485E, ISL31486E
Small Outline Plastic Packages (SOIC)
M8.15 (JEDEC MS-012-AA ISSUE C)
N
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
0.25(0.010) M
H
B M
INCHES
E
SYMBOL
-B-
1
2
3
L
SEATING PLANE
-A-
A
D
h x 45°
-C-
e
A1
B
0.25(0.010) M
C
0.10(0.004)
C A M
MIN
MAX
MIN
MAX
NOTES
A
0.0532
0.0688
1.35
1.75
-
A1
0.0040
0.0098
0.10
0.25
-
B
0.013
0.020
0.33
0.51
9
C
0.0075
0.0098
0.19
0.25
-
D
0.1890
0.1968
4.80
5.00
3
E
0.1497
0.1574
3.80
4.00
4
e
α
B S
0.050 BSC
1.27 BSC
-
H
0.2284
0.2440
5.80
6.20
-
h
0.0099
0.0196
0.25
0.50
5
L
0.016
0.050
0.40
1.27
6
N
α
NOTES:
MILLIMETERS
8
0°
8
8°
0°
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
7
8°
Rev. 1 6/05
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications
at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by
Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any
infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any
patent or patent rights of Intersil or its subsidiaries.
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24
FN7638.0
June 25, 2010