TI ADS7841EG4 12-bit, 4-channel serial output sampling analog-to-digital converter Datasheet

ADS7841
ADS
784
ADS
784
1
1
SBAS084B – JULY 2001
12-Bit, 4-Channel Serial Output Sampling
ANALOG-TO-DIGITAL CONVERTER
FEATURES
DESCRIPTION
● SINGLE SUPPLY: 2.7V to 5V
The ADS7841 is a 4-channel, 12-bit sampling Analog-toDigital Converter (ADC) with a synchronous serial interface. The resolution is programmable to either 8 bits or 12
bits. Typical power dissipation is 2mW at a 200kHz throughput rate and a +5V supply. The reference voltage (VREF) can
be varied between 100mV and VCC, providing a corresponding input voltage range of 0V to VREF. The device includes
a shutdown mode which reduces power dissipation to under
15µW. The ADS7841 is tested down to 2.7V operation.
● 4-CHANNEL SINGLE-ENDED OR
2-CHANNEL DIFFERENTIAL INPUT
● UP TO 200kHz CONVERSION RATE
● ±1LSB MAX INL AND DNL
● NO MISSING CODES
● 72dB SINAD
● SERIAL INTERFACE
● DIP-16 OR SSOP-16 PACKAGE
● ALTERNATE SOURCE FOR MAX1247
● ADS7841ES: +125°C Version
Low power, high speed, and on-board multiplexer make the
ADS7841 ideal for battery-operated systems such as personal digital assistants, portable multi-channel data loggers,
and measurement equipment. The serial interface also provides low-cost isolation for remote data acquisition. The
ADS7841 is available in a DIP-16 or a SSOP-16 package
and is specified over the –40°C to +125°C(1) temperature
range.
APPLICATIONS
●
●
●
●
●
DATA ACQUISITION
TEST AND MEASUREMENT
INDUSTRIAL PROCESS CONTROL
PERSONAL DIGITAL ASSISTANTS
BATTERY-POWERED SYSTEMS
NOTE: (1) ES grade only.
SAR
DCLK
CS
CH0
CH1
CH2
Comparator
Four
Channel
Multiplexer
Serial
Interface
and
Control
CDAC
CH3
SHDN
DIN
DOUT
MODE
COM
BUSY
VREF
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright © 2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
www.ti.com
ELECTROSTATIC
DISCHARGE SENSITIVITY
ABSOLUTE MAXIMUM RATINGS(1)
+VCC to GND ........................................................................ –0.3V to +6V
Analog Inputs to GND ............................................ –0.3V to +VCC + 0.3V
Digital Inputs to GND ........................................................... –0.3V to +6V
Power Dissipation .......................................................................... 250mW
Maximum Junction Temperature ................................................... +150°C
Operating Temperature Range .................................. –40°C to +125°C(2)
Storage Temperature Range ......................................... –65°C to +150°C
Lead Temperature (soldering, 10s) ............................................... +300°C
NOTES: (1) Stresses above those listed under “Absolute Maximum Ratings”
may cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability. (2) ADS7841ES
0nly. All other grades are: –40°C to +85°C.
PACKAGE/ORDERING INFORMATION
PRODUCT
MINIMUM
RELATIVE
ACCURACY
(LSB)
MAXIMUM
GAIN
ERROR
(LSB)
SPECIFICATION
TEMPERATURE
RANGE
±2
"
±2
±1
"
±1
±2
±4
"
"
±3
"
"
±4
–40°C to +85°C
"
–40°C to +85°C
–40°C to +85°C
"
–40°C to +85°C
–40°C to +125°C
ADS7841E
"
ADS7841P
ADS7841EB
"
ADS7841PB
ADS7841ES
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
PACKAGE
PACKAGE
DESIGNATOR
PACKAGE
DRAWING
NUMBER
SSOP-16
"
DIP-16
SSOP-16
"
DIP-16
SSOP-16
DBQ
"
N
DBQ
"
N
DBQ
322
"
180
322
"
180
322
ORDERING
NUMBER(1)
TRANSPORT
MEDIA
ADS7841E
Rails
ADS7841E/2K5 Tape and Reel
ADS7841P
Rails
ADS7841EB
Rails
ADS7841EB/2K5 Tape and Reel
ADS7841PB
Rails
ADS7841ES/2K5 Tape and Reel
NOTES: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K5 indicates 2500 devices per reel). Ordering 2500 pieces
of “ADS7841E/2K5” will get a single 2500-piece Tape and Reel.
PIN CONFIGURATIONS
Top View
DIP
SSOP
+VCC
1
16
DCLK
+VCC
1
16
DCLK
CH0
2
15
CS
CH0
2
15
CS
CH1
3
14
DIN
CH1
3
14
DIN
CH2
4
13
BUSY
CH2
4
13
BUSY
12
DOUT
CH3
5
COM
ADS7841
ADS7841
12
DOUT
CH3
5
6
11
MODE
COM
6
11
MODE
SHDN
7
10
GND
SHDN
7
10
GND
VREF
8
9
+VCC
VREF
8
9
+VCC
PIN DESCRIPTIONS
2
PIN
NAME
DESCRIPTION
1
2
3
4
5
6
+VCC
CH0
CH1
CH2
CH3
COM
7
8
9
10
11
SHDN
VREF
+VCC
GND
MODE
12
13
14
15
16
DOUT
BUSY
DIN
CS
DCLK
Power Supply, 2.7V to 5V
Analog Input Channel 0
Analog Input Channel 1
Analog Input Channel 2
Analog Input Channel 3
Ground Reference for Analog Inputs. Sets zero code voltage in single-ended mode. Connect this pin to ground or ground reference
point.
Shutdown. When LOW, the device enters a very low power shutdown mode.
Voltage Reference Input
Power Supply, 2.7V to 5V
Ground
Conversion Mode. When LOW, the device always performs a 12-bit conversion. When HIGH, the resolution is set by the MODE bit in
the CONTROL byte.
Serial Data Output. Data is shifted on the falling edge of DCLK. This output is high impedance when CS is HIGH.
Busy Output. This output is high impedance when CS is HIGH.
Serial Data Input. If CS is LOW, data is latched on rising edge of DCLK.
Chip Select Input. Controls conversion timing and enables the serial input/output register.
External Clock Input. This clock runs the SAR conversion process and synchronizes serial data I/O.
ADS7841
SBAS084B
ELECTRICAL CHARACTERISTICS: +5V
At TA = TMIN to TMAX, +VCC = +5V, VREF = +5V, fSAMPLE = 200kHz, and fCLK = 16 • fSAMPLE = 3.2MHz, unless otherwise noted.
ADS7841E, P
PARAMETER
ANALOG INPUT
Full-Scale Input Span
Absolute Input Range
CONDITIONS
MIN
Positive Input - Negative Input
0
Positive Input
–0.2
Negative Input
–0.2
Capacitance
Leakage Current
VREF
+VCC +0.2
+1.25
✻
✻
✻
TYP
±2
✻
✻
✻
✻
68
72
0.1
DCLK Static
70
76
+VCC
5
40
2.5
0.001
3.0
–0.3
3.5
100
3
✻
✻
✻
✻
✻
✻
✻
68
72
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
Clk Cycles
Clk Cycles
kHz
ns
ns
ps
–72
dB
dB
dB
dB
✻
V
GΩ
µA
µA
µA
✻
✻
✻
✻
✻
V
V
V
V
✻
✻
✻
✻
✻
✻
✻
✻
✻
V
µA
µA
µA
mW
+125
°C
✻
✻
✻
✻
Bits
Bits
LSB(1)
LSB
LSB
LSB
LSB
LSB
µVrms
dB
✻
✻
3
4.5
+85
–78
71
79
120
✻
✻
5.25
900
✻
✻
±4
✻
✻
–76
✻
✻
0.4
–40
✻
✻
5.5
+0.8
550
300
2
±0.8
✻
✻
✻
✻
✻
✻
✻
✻
Straight Binary
PWR SUPPLY REQUIREMENTS
+VCC
Specified Performance
4.75
Quiescent Current
fSAMPLE = 12.5kHz
Power-Down Mode(3), CS = +VCC
Power Dissipation
TEMPERATURE RANGE
Specified Performance
–80
72
81
✻
✻
CMOS
| IIH | ≤ +5µA
| IIL | ≤ +5µA
IOH = –250µA
IOL = 250µA
±1
±1
✻
✻
±3
✻
✻
–72
V
V
V
pF
nA
200
✻
✻
✻
–78
71
79
120
✻
✻
✻
✻
200
10kHz
10kHz
10kHz
50kHz
UNITS
✻
✻
500
30
100
MAX
✻
✻
12
3
TYP
11
±0.5
±3
1.0
±4
1.0
0.1
30
70
at
at
at
at
✻
✻
✻
✻
0.15
5Vp-p
5Vp-p
5Vp-p
5Vp-p
✻
✻
✻
12
±0.8
=
=
=
=
MIN
200
12
VIN
VIN
VIN
VIN
ADS7841ES
MAX
✻
12
fSAMPLE = 12.5kHz
DCLK Static
DIGITAL INPUT/OUTPUT
Logic Family
Logic Levels
VIH
VIL
VOH
VOL
Data Format
MIN
200
SAMPLING DYNAMICS
Conversion Time
Acquisition Time
Throughput Rate
Multiplexer Settling Time
Aperture Delay
Aperture Jitter
REFERENCE INPUT
Range
Resistance
Input Current
MAX
25
SYSTEM PERFORMANCE
Resolution
No Missing Codes
Integral Linearity Error
Differential Linearity Error
Offset Error
Offset Error Match
Gain Error
Gain Error Match
Noise
Power-Supply Rejection
DYNAMIC CHARACTERISTICS
Total Harmonic Distortion(2)
Signal-to-(Noise + Distortion)
Spurious-Free Dynamic Range
Channel-to-Channel Isolation
ADS7841EB, PB
TYP
✻
✻
✻ Same specifications as ADS7841E, P.
NOTE: (1) LSB means Least Significant Bit. With VREF equal to +5.0V, one LSB is 1.22mV. (2) First five harmonics of the test frequency. (3) Auto power-down mode
(PD1 = PD0 = 0) active or SHDN = GND.
ADS7841
SBAS084B
3
ELECTRICAL CHARACTERISTICS: +2.7V
At TA = –40°C to +85°C, +VCC = +2.7V, VREF = +2.5V, fSAMPLE = 125kHz, and fCLK = 16 • fSAMPLE = 2MHz, unless otherwise noted.
ADS7841E, P
PARAMETER
ANALOG INPUT
Full-Scale Input Span
Absolute Input Range
CONDITIONS
MIN
Positive Input - Negative Input
Positive Input
Negative Input
0
–0.2
–0.2
TYP
Capacitance
Leakage Current
POWER SUPPLY REQUIREMENTS
+VCC
Quiescent Current
✻
✻
✻
TYP
0.15
0.1
30
70
±2
±0.5
±3
1.0
±4
1.0
✻
✻
✻
✻
10kHz
10kHz
10kHz
50kHz
–77
71
78
100
68
72
0.1
✻
✻
✻
✻
–72
70
76
+VCC
DCLK Static
5
13
2.5
0.001
+VCC • 0.7
–0.3
+VCC • 0.8
✻
✻
✻
✻
40
3
5.5
+0.8
✻
✻
✻
280
220
–40
dB
dB
dB
dB
✻
V
GΩ
µA
µA
µA
✻
✻
✻
V
V
V
V
✻
3.6
650
✻
✻
✻
3
1.8
Power Dissipation
Clk Cycles
Clk Cycles
kHz
ns
ns
ps
–76
✻
✻
0.4
2.7
Bits
Bits
LSB(1)
LSB
LSB
LSB
LSB
LSB
µVrms
dB
✻
Straight Binary
Specified Performance
–79
72
80
✻
✻
CMOS
| IIH | ≤ +5µA
| IIL | ≤ +5µA
IOH = –250µA
IOL = 250µA
±1
±1
✻
✻
±3
✻
✻
125
at
at
at
at
V
V
V
pF
µA
✻
500
30
100
2.5Vp-p
2.5Vp-p
2.5Vp-p
2.5Vp-p
✻
✻
✻
✻
12
=
=
=
=
UNITS
✻
✻
3
VIN
VIN
VIN
VIN
MAX
12
±0.8
fSAMPLE = 12.5kHz
Power-Down Mode(3), CS = +VCC
TEMPERATURE RANGE
Specified Performance
VREF
+VCC +0.2
+0.2
12
fSAMPLE = 12.5kHz
DCLK Static
DIGITAL INPUT/OUTPUT
Logic Family
Logic Levels
VIH
VIL
VOH
VOL
Data Format
MIN
12
SAMPLING DYNAMICS
Conversion Time
Acquisition Time
Throughput Rate
Multiplexer Settling Time
Aperture Delay
Aperture Jitter
REFERENCE INPUT
Range
Resistance
Input Current
MAX
25
±1
SYSTEM PERFORMANCE
Resolution
No Missing Codes
Integral Linearity Error
Differential Linearity Error
Offset Error
Offset Error Match
Gain Error
Gain Error Match
Noise
Power-Supply Rejection
DYNAMIC CHARACTERISTICS
Total Harmonic Distortion(2)
Signal-to-(Noise + Distortion)
Spurious-Free Dynamic Range
Channel-to-Channel Isolation
ADS7841EB, PB
+85
✻
✻
✻
✻
✻
V
µA
µA
µA
mW
✻
°C
✻ Same specifications as ADS7841E, P.
NOTE: (1) LSB means Least Significant Bit. With VREF equal to +2.5V, one LSB is 610mV. (2) First five harmonics of the test frequency. (3) Auto power-down mode
(PD1 = PD0 = 0) active or SHDN = GND.
4
ADS7841
SBAS084B
TYPICAL CHARACTERISTICS: +5V
At TA = +25°C, +VCC = +5V, VREF = +5V, fSAMPLE = 200kHz, and fCLK = 16 • fSAMPLE = 3.2MHz, unless otherwise noted.
FREQUENCY SPECTRUM
(4096 Point FFT; fIN = 10.3kHz, –0.2dB)
0
0
–20
–20
–40
–40
Amplitude (dB)
Amplitude (dB)
FREQUENCY SPECTRUM
(4096 Point FFT; fIN = 1,123Hz, –0.2dB)
–60
–80
–60
–80
–100
–100
–120
–120
0
25
50
75
100
0
25
50
75
100
Frequency (kHz)
Frequency (kHz)
SIGNAL-TO-NOISE RATIO AND SIGNAL-TO(NOISE+DISTORTION) vs INPUT FREQUENCY
SPURIOUS-FREE DYNAMIC RANGE AND TOTAL
HARMONIC DISTORTION vs INPUT FREQUENCY
74
–85
85
SNR
SFDR
–80
80
SINAD
71
THD
75
–75
70
–70
70
69
68
10
1
100
10
Input Frequency (kHz)
Input Frequency (kHz)
EFFECTIVE NUMBER OF BITS
vs INPUT FREQUENCY
CHANGE IN SIGNAL-TO-(NOISE+DISTORTION)
vs TEMPERATURE
12.0
0.6
0.4
11.8
Delta from +25°C (dB)
Effective Number of Bits
–65
100
65
1
11.6
11.4
11.2
0.2
0.0
–0.2
–0.4
fIN = 10kHz, –0.2dB
–0.6
11.0
1
10
Input Frequency (kHz)
ADS7841
SBAS084B
100
–40
–20
0
20
40
60
80
100
Temperature (°C)
5
THD (dB)
72
SFDR (dB)
SNR and SINAD (dB)
73
TYPICAL CHARACTERISTICS: +2.7V
At TA = +25°C, +VCC = +2.7V, VREF = +2.5V, fSAMPLE = 125kHz, and fCLK = 16 • fSAMPLE = 2MHz, unless otherwise noted.
FREQUENCY SPECTRUM
(4096 Point FFT; fIN = 10.6kHz, –0.2dB)
0
0
–20
–20
–40
–40
Amplitude (dB)
–60
–80
–100
–80
–100
–120
–120
0
15.6
31.3
46.9
62.5
0
15.6
31.3
46.9
62.5
Frequency (kHz)
Frequency (kHz)
SIGNAL-TO-NOISE RATIO AND SIGNAL-TO(NOISE+DISTORTION) vs INPUT FREQUENCY
SPURIOUS-FREE DYNAMIC RANGE AND TOTAL
HARMONIC DISTORTION vs INPUT FREQUENCY
78
90
SNR
–90
85
74
–85
SFDR
80
–80
70
SFDR (dB)
SNR and SINAD (dB)
–60
66
SINAD
62
75
–75
70
–70
THD
65
–65
60
–60
55
–55
58
54
50
1
10
Input Frequency (kHz)
100
–50
1
10
100
Input Frequency (kHz)
EFFECTIVE NUMBER OF BITS
vs INPUT FREQUENCY
CHANGE IN SIGNAL-TO-(NOISE+DISTORTION)
vs TEMPERATURE
12.0
0.4
11.5
0.2
Delta from +25°C (dB)
Effective Number of Bits
fIN = 10kHz, –0.2dB
11.0
10.5
10.0
–0.2
–0.4
–0.6
9.5
–0.8
9.0
1
10
Input Frequency (kHz)
6
0.0
100
–40
–20
0
20
40
60
80
100
Temperature (˚C)
ADS7841
SBAS084B
THD (dB)
Amplitude (dB)
FREQUENCY SPECTRUM
(4096 Point FFT; fIN = 1,129Hz, –0.2dB)
TYPICAL CHARACTERISTICS: +2.7V (Cont.)
At TA = +25°C, +VCC = +2.7V, VREF = +2.5V, fSAMPLE = 125kHz, and fCLK = 16 • fSAMPLE = 2MHz, unless otherwise noted.
POWER DOWN SUPPLY CURRENT
vs TEMPERATURE
400
140
350
120
Supply Current (nA)
Supply Current (µA)
SUPPLY CURRENT vs TEMPERATURE
300
250
200
150
100
80
60
40
100
20
–40
–20
0
20
40
60
80
100
–40
–20
0
40
60
80
100
DIFFERENTIAL LINEARITY ERROR vs CODE
1.00
1.00
0.75
0.75
0.50
0.50
DLE (LSB)
ILE (LSB)
INTEGRAL LINEARITY ERROR vs CODE
0.25
0.00
–0.25
0.25
0.00
–0.25
–0.50
–0.50
–0.75
–0.75
–1.00
000H
–1.00
000H
FFFH
800H
FFFH
800H
Output Code
Output Code
CHANGE IN GAIN vs TEMPERATURE
CHANGE IN OFFSET vs TEMPERATURE
0.15
0.6
0.10
0.4
Delta from +25˚C (LSB)
Delta from +25˚C (LSB)
20
Temperature (˚C)
Temperature (˚C)
0.05
0.00
–0.05
–0.10
0.2
0.0
–0.2
–0.4
–0.15
–0.6
–40
–20
0
20
40
Temperature (˚C)
ADS7841
SBAS084B
60
80
100
–40
–20
0
20
40
60
80
100
Temperature (˚C)
7
TYPICAL CHARACTERISTICS: +2.7V (Cont.)
At TA = +25°C, +VCC = +2.7V, VREF = +2.5V, fSAMPLE = 125kHz, and fCLK = 16 • fSAMPLE = 2MHz, unless otherwise noted.
REFERENCE CURRENT vs TEMPERATURE
18
12
16
Reference Current (µA)
Reference Current (µA)
REFERENCE CURRENT vs SAMPLE RATE
14
10
8
6
4
14
12
10
8
2
6
0
0
25
50
75
100
–40
125
–20
0
20
40
60
80
100
Temperature (˚C)
Sample Rate (kHz)
SUPPLY CURRENT vs +VCC
MAXIMUM SAMPLE RATE vs +VCC
1M
320
300
Sample Rate (Hz)
Supply Current (µA)
fSAMPLE = 12.5kHz
280
VREF = +VCC
260
240
220
100k
10k
VREF = +VCC
200
1k
180
2
2.5
3
3.5
+VCC (V)
8
4
4.5
5
2
2.5
3
3.5
4
4.5
5
+VCC (V)
ADS7841
SBAS084B
THEORY OF OPERATION
The input current on the analog inputs depends on the
conversion rate of the device. During the sample period, the
source must charge the internal sampling capacitor (typically 25pF). After the capacitor has been fully charged, there
is no further input current. The rate of charge transfer from
the analog source to the converter is a function of conversion rate.
The ADS7841 is a classic Successive Approximation Register (SAR) ADC. The architecture is based on capacitive
redistribution that inherently includes a sample-and-hold
function. The converter is fabricated on a 0.6µs CMOS
process.
The basic operation of the ADS7841 is shown in Figure 1.
The device requires an external reference and an external
clock. It operates from a single supply of 2.7V to 5.25V. The
external reference can be any voltage between 100mV and
+VCC. The value of the reference voltage directly sets the
input range of the converter. The average reference input
current depends on the conversion rate of the ADS7841.
A2
A1
A0
CH0
0
0
1
+IN
1
0
1
0
1
0
1
1
0
CH1
CH2
CH3
COM
–IN
+IN
–IN
+IN
–IN
+IN
–IN
TABLE I. Single-Ended Channel Selection (SGL/DIF HIGH).
The analog input to the converter is differential and is
provided via a four-channel multiplexer. The input can be
provided in reference to a voltage on the COM pin (which
is generally ground) or differentially by using two of the four
input channels (CH0 - CH3). The particular configuration is
selectable via the digital interface.
A2
A1
A0
CH0
CH1
0
0
1
+IN
–IN
CH2
CH3
1
0
1
–IN
+IN
0
1
0
+IN
–IN
1
1
0
–IN
+IN
COM
TABLE II. Differential Channel Control (SGL/DIF LOW).
ANALOG INPUT
Figure 2 shows a block diagram of the input multiplexer on
the ADS7841. The differential input of the converter is
derived from one of the four inputs in reference to the COM
pin or two of the four inputs. Table I and Table II show the
relationship between the A2, A1, A0, and SGL/DIF control
bits and the configuration of the analog multiplexer. The
control bits are provided serially via the DIN pin, see the
Digital Interface section of this data sheet for more details.
A2-A0
(Shown 001B)
CH0
CH1
CH2
+IN
CH3
Converter
–IN
When the converter enters the hold mode, the voltage
difference between the +IN and –IN inputs (as shown in
Figure 2) is captured on the internal capacitor array. The
voltage on the –IN input is limited between –0.2V and
1.25V, allowing the input to reject small signals that are
common to both the +IN and –IN input. The +IN input has
a range of –0.2V to +VCC + 0.2V.
COM
SGL/DIF
(Shown HIGH)
FIGURE 2. Simplified Diagram of the Analog Input.
+2.7V to +5V
ADS7841
1µF +
to
10µF
0.1µF
Single-ended
or differential
analog inputs
1
+VCC
DCLK 16
2
CH0
CS 15
3
CH1
DIN 14
4
CH2
BUSY 13
5
CH3
DOUT 12
6
COM
MODE 11
7
SHDN
GND 10
8
VREF
+VCC
Serial/Conversion Clock
Chip Select
Serial Data In
Serial Data Out
9
0.1µF
FIGURE 1. Basic Operation of the ADS7841.
ADS7841
SBAS084B
9
REFERENCE INPUT
The voltage into the VREF input is not buffered and directly
drives the Capacitor Digital-to-Analog Converter (CDAC)
portion of the ADS7841. Typically, the input current is
13µA with a 2.5V reference. This value will vary by
microamps depending on the result of the conversion. The
reference current diminishes directly with both conversion
rate and reference voltage. As the current from the reference
is drawn on each bit decision, clocking the converter more
quickly during a given conversion period will not reduce
overall current drain from the reference.
The external reference sets the analog input range. The
ADS7841 will operate with a reference in the range of
100mV to +VCC. Keep in mind that the analog input is the
difference between the +IN input and the –IN input, see
Figure 2. For example, in the single-ended mode, a 1.25V
reference, and with the COM pin grounded, the selected input
channel (CH0 - CH3) will properly digitize a signal in the
range of 0V to 1.25V. If the COM pin is connected to 0.5V,
the input range on the selected channel is 0.5V to 1.75V.
There are several critical items concerning the reference input
and its wide voltage range. As the reference voltage is reduced, the analog voltage weight of each digital output code
is also reduced. This is often referred to as the LSB (least
significant bit) size and is equal to the reference voltage
divided by 4096. Any offset or gain error inherent in the ADC
will appear to increase, in terms of LSB size, as the reference
voltage is reduced. For example, if the offset of a given
converter is 2LSBs with a 2.5V reference, then it will typically
be 10LSBs with a 0.5V reference. In each case, the actual
offset of the device is the same, 1.22mV.
DIGITAL INTERFACE
Figure 3 shows the typical operation of the ADS7841’s
digital interface. This diagram assumes that the source of the
digital signals is a microcontroller or digital signal processor
with a basic serial interface (note that the digital inputs are
over-voltage tolerant up to 5.5V, regardless of +VCC). Each
communication between the processor and the converter
consists of eight clock cycles. One complete conversion can
be accomplished with three serial communications, for a
total of 24 clock cycles on the DCLK input.
Likewise, the noise or uncertainty of the digitized output will
increase with lower LSB size. With a reference voltage of
100mV, the LSB size is 24µV. This level is below the
internal noise of the device. As a result, the digital output
code will not be stable and vary around a mean value by a
number of LSBs. The distribution of output codes will be
gaussian and the noise can be reduced by simply averaging
consecutive conversion results or applying a digital filter.
The first eight clock cycles are used to provide the control
byte via the DIN pin. When the converter has enough
information about the following conversion to set the input
multiplexer appropriately, it enters the acquisition (sample)
mode. After three more clock cycles, the control byte is
complete and the converter enters the conversion mode. At
this point, the input sample-and-hold goes into the hold
mode. The next twelve clock cycles accomplish the actual
Analog-to-Digital conversion. A thirteenth clock cycle is
needed for the last bit of the conversion result. Three more
clock cycles are needed to complete the last byte (DOUT
will be LOW). These will be ignored by the converter.
With a lower reference voltage, care should be taken to
provide a clean layout including adequate bypassing, a clean
(low-noise, low-ripple) power supply, a low-noise reference,
and a low-noise input signal. Because the LSB size is lower,
the converter will also be more sensitive to nearby digital
signals and electromagnetic interference.
CS
tACQ
DCLK
DIN
1
S
8
A2
A1
8
1
1
8
A0 MODE SGL/
DIF PD1 PD0
(START)
Idle
Acquire
Conversion
Idle
BUSY
DOUT
11
(MSB)
10
9
8
7
6
5
4
3
2
1
0
Zero Filled...
(LSB)
FIGURE 3. Conversion Timing, 24-Clocks per Conversion, 8-Bit Bus Interface. No DCLK delay required with dedicated
serial port.
10
ADS7841
SBAS084B
Control Byte
MODE pin is HIGH, then the MODE bit determines the
number of bits for each conversion, either 12 bits (LOW) or
8 bits (HIGH).
Also shown in Figure 3 is the placement and order of the
control bits within the control byte. Tables III and IV give
detailed information about these bits. The first bit, the ‘S’ bit,
must always be HIGH and indicates the start of the control
byte. The ADS7841 will ignore inputs on the DIN pin until
the start bit is detected. The next three bits (A2 - A0) select
the active input channel or channels of the input multiplexer
(see Tables I and II and Figure 2).
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
S
A2
A1
A0
Bit 3
Bit 2
MODE SGL/DIF
Bit 1
Bit 0
(LSB)
PD1
PD0
The SGL/DIF bit controls the multiplexer input mode: either
single-ended (HIGH) or differential (LOW). In single-ended
mode, the selected input channel is referenced to the COM
pin. In differential mode, the two selected inputs provide a
differential input. See Tables I and II and Figure 2 for more
information. The last two bits (PD1 - PD0) select the powerdown mode, as shown in Table V. If both inputs are HIGH,
the device is always powered up. If both inputs are LOW,
the device enters a power-down mode between conversions.
When a new conversion is initiated, the device will resume
normal operation instantly—no delay is needed to allow the
device to power up and the very first conversion will be
valid.
TABLE III. Order of the Control Bits in the Control Byte.
DESCRIPTION
16-Clocks per Conversion
S
Start Bit. Control byte starts with first HIGH bit on
DIN. A new control byte can start every 15th clock
cycle in 12-bit conversion mode or every 11th clock
cycle in 8-bit conversion mode.
A2 - A0
Channel Select Bits. Along with the SGL/DIF bit,
these bits control the setting of the multiplexer input,
see Tables I and II.
3
MODE
12-Bit/8-Bit Conversion Select Bit. If the MODE pin
is HIGH, this bit controls the number of bits for the
next conversion: 12-bits (LOW) or 8-bits (HIGH). If
the MODE pin is LOW, this bit has no function and
the conversion is always 12 bits.
2
SGL/DIF
Single-Ended/Differential Select Bit. Along with bits
A2 - A0, this bit controls the setting of the multiplexer
input, see Tables I and II.
The control bits for conversion n+1 can be overlapped with
conversion ‘n’ to allow for a conversion every 16 clock
cycles, as shown in Figure 4. This figure also shows possible
serial communication occurring with other serial peripherals
between each byte transfer between the processor and the
converter. This is possible provided that each conversion
completes within 1.6ms of starting. Otherwise, the signal
that has been captured on the input sample-and-hold may
droop enough to affect the conversion result. In addition, the
ADS7841 is fully powered while other serial communications are taking place.
PD1 - PD0
Power-Down Mode Select Bits. See Table V for
details.
BIT
NAME
7
6-4
1-0
PD1
PD0
0
0
Power-down between conversions. When each
conversion is finished, the converter enters a low
power mode. At the start of the next conversion,
the device instantly powers up to full power. There
is no need for additional delays to assure full
operation and the very first conversion is valid.
Description
0
1
Reserved for Future Use
1
0
Reserved for Future Use
1
1
No power-down between conversions, device always powered.
TABLE IV. Descriptions of the Control Bits within the
Control Byte.
The MODE bit and the MODE pin work together to determine the number of bits for a given conversion. If the
MODE pin is LOW, the converter always performs a 12-bit
conversion regardless of the state of the MODE bit. If the
TABLE V. Power-Down Selection.
CS
DCLK
1
DIN
8
1
8
S
1
8
1
S
CONTROL BITS
CONTROL BITS
BUSY
DOUT
11 10 9
8
7
6
5
4
3
2
1
0
11 10 9
FIGURE 4. Conversion Timing, 16-Clocks per Conversion, 8-bit Bus Interface. No DCLK delay required with dedicated
serial port.
ADS7841
SBAS084B
11
Digital Timing
microcontrollers and digital signal processors as they are
generally not capable of providing 15 clock cycles per serial
transfer. However, this method could be used with Field
Programmable Gate Arrays (FPGAs) or Application Specific Integrated Circuits (ASICs). Note that this effectively
increases the maximum conversion rate of the converter
beyond the values given in the specification tables, which
assume 16 clock cycles per conversion.
Figure 5 and Tables VI and VII provide detailed timing for
the digital interface of the ADS7841.
15-Clocks per Conversion
Figure 6 provides the fastest way to clock the ADS7841.
This method will not work with the serial interface of most
SYMBOL
DESCRIPTION
MIN
UNITS
SYMBOL
DESCRIPTION
MIN
tACQ
Acquisition Time
1.5
TYP
MAX
µs
tACQ
Acquisition Time
900
TYP
MAX
UNITS
tDS
DIN Valid Prior to DCLK Rising
100
ns
tDS
DIN Valid Prior to DCLK Rising
50
ns
tDH
DIN Hold After DCLK HIGH
10
ns
tDH
DIN Hold After DCLK HIGH
10
ns
ns
tDO
DCLK Falling to DOUT Valid
200
ns
tDO
DCLK Falling to DOUT Valid
100
ns
tDV
CS Falling to DOUT Enabled
200
ns
tDV
CS Falling to DOUT Enabled
70
ns
tTR
CS Rising to DOUT Disabled
200
ns
tTR
CS Rising to DOUT Disabled
70
tCSS
CS Falling to First DCLK Rising
ns
tCSS
CS Falling to First DCLK Rising
tCSH
CS Rising to DCLK Ignored
0
ns
tCSH
CS Rising to DCLK Ignored
0
ns
tCH
DCLK HIGH
200
ns
tCH
DCLK HIGH
150
ns
tCL
DCLK LOW
200
ns
tCL
DCLK LOW
150
tBD
DCLK Falling to BUSY Rising
200
ns
tBD
DCLK Falling to BUSY Rising
tBDV
CS Falling to BUSY Enabled
200
ns
tBDV
CS Falling to BUSY Enabled
70
ns
tBTR
CS Rising to BUSY Disabled
200
ns
tBTR
CS Rising to BUSY Disabled
70
ns
100
TABLE VI. Timing Specifications (+VCC = +2.7V to 3.6V,
TA = –40°C to +85°C, CLOAD = 50pF).
ns
50
ns
ns
100
ns
TABLE VII. Timing Specifications (+VCC = +4.75V to
+5.25V, TA = –40°C to +85°C, CLOAD = 50pF).
CS
tCSS
tCL
tCH
tBD
tBD
tCSH
tD0
DCLK
tDS
tDH
DIN
PD0
tBDV
tBTR
BUSY
tDV
tTR
DOUT
11
10
FIGURE 5. Detailed Timing Diagram.
CS
DCLK
15
1
DIN
S
SGL/
A2 A1 A0 MODE DIF PD1 PD0
1
S
15
SGL/
A2 A1 A0 MODE DIF PD1 PD0
1
S
A2
5
4
A1 A0
BUSY
DOUT
11 10
9
8
7
6
5
4
3
2
1
0
11 10
9
8
7
6
3
2
FIGURE 6. Maximum Conversion Rate, 15-Clocks per Conversion.
12
ADS7841
SBAS084B
Data Format
The ADS7841 output data is in straight binary format, as
shown in Figure 7. This figure shows the ideal output code
for the given input voltage and does not include the effects
of offset, gain, or noise.
FS = Full-Scale Voltage = VREF
1LSB = VREF/4096
1LSB
11...111
Output Code
11...110
11...101
gible. If the conversion rate is decreased by simply slowing
the frequency of the DCLK input, the two modes remain
approximately equal. However, if the DCLK frequency is
kept at the maximum rate during a conversion, but conversion are simply done less often, then the difference between
the two modes is dramatic. Figure 8 shows the difference
between reducing the DCLK frequency (“scaling” DCLK to
match the conversion rate) or maintaining DCLK at the
highest frequency and reducing the number of conversion
per second. In the later case, the converter spends an increasing percentage of its time in power-down mode (assuming
the auto power-down mode is active).
If DCLK is active and CS is LOW while the ADS7841 is in
auto power-down mode, the device will continue to dissipate
some power in the digital logic. The power can be reduced
to a minimum by keeping CS HIGH. The differences in
supply current for these two cases are shown in Figure 9.
00...010
00...001
00...000
FS – 1LSB
0V
Input Voltage(1) (V)
Note 1: Voltage at converter input, after
multiplexer: +IN – (–IN). See Figure 2.
Operating the ADS7841 in auto power-down mode will
result in the lowest power dissipation, and there is no
conversion time “penalty” on power-up. The very first
conversion will be valid. SHDN can be used to force an
immediate power-down.
FIGURE 7. Ideal Input Voltages and Output Codes.
1000
8-Bit Conversion
Supply Current (µA)
The ADS7841 provides an 8-bit conversion mode that can
be used when faster throughput is needed and the digital
result is not as critical. By switching to the 8-bit mode, a
conversion is complete four clock cycles earlier. This could
be used in conjunction with serial interfaces that provide a
12-bit transfer or two conversions could be accomplished
with three 8-bit transfers. Not only does this shorten each
conversion by four bits (25% faster throughput), but each
conversion can actually occur at a faster clock rate. This is
because the internal settling time of the ADS7841 is not as
critical, settling to better than 8 bits is all that is needed. The
clock rate can be as much as 50% faster. The faster clock
rate and fewer clock cycles combine to provide a 2x increase
in conversion rate.
fCLK = 16 • fSAMPLE
100
fCLK = 2MHz
10
TA = 25°C
+VCC = +2.7V
VREF = +2.5V
PD1 = PD0 = 0
1
1k
10k
100k
1M
fSAMPLE (Hz)
FIGURE 8. Supply Current vs Directly Scaling the Frequency of DCLK with Sample Rate or Keeping
DCLK at the Maximum Possible Frequency.
POWER DISSIPATION
When operating at full-speed and 16-clocks per conversion
(see Figure 4), the ADS7841 spends most of its time acquiring or converting. There is little time for auto power-down,
assuming that this mode is active. Thus, the difference
between full power mode and auto power-down is negli-
ADS7841
SBAS084B
14
TA = 25°C
+VCC = +2.7V
VREF = +2.5V
fCLK = 16 • fSAMPLE
PD1 = PD0 = 0
12
Supply Current (µA)
There are three power modes for the ADS7841: full power
(PD1 - PD0 = 11B), auto power-down (PD1 - PD0 = 00B),
and shutdown (SHDN LOW). The affects of these modes
varies depending on how the ADS7841 is being operated. For
example, at full conversion rate and 16 clocks per conversion, there is very little difference between full power mode
and auto power-down. Likewise, if the device has entered
auto power-down, a shutdown (SHDN LOW) will not lower
power dissipation.
10
8
6
CS LOW
(GND)
4
2
CS HIGH (+VCC)
0
0.09
0.00
1k
10k
100k
1M
fSAMPLE (Hz)
FIGURE 9. Supply Current vs State of CS.
13
LAYOUT
For optimum performance, care should be taken with the
physical layout of the ADS7841 circuitry. This is particularly true if the reference voltage is low and/or the conversion rate is high.
The basic SAR architecture is sensitive to glitches or sudden
changes on the power supply, reference, ground connections, and digital inputs that occur just prior to latching the
output of the analog comparator. Thus, during any single
conversion for an n-bit SAR converter, there are n “windows” in which large external transient voltages can easily
affect the conversion result. Such glitches might originate
from switching power supplies, nearby digital logic, and
high power devices. The degree of error in the digital output
depends on the reference voltage, layout, and the exact
timing of the external event. The error can change if the
external event changes in time with respect to the DCLK
input.
With this in mind, power to the ADS7841 should be clean
and well bypassed. A 0.1µF ceramic bypass capacitor should
be placed as close to the device as possible. In addition, a
1µF to 10µF capacitor and a 5Ω or 10Ω series resistor may
be used to low-pass filter a noisy supply.
14
The reference should be similarly bypassed with a 0.1µF
capacitor. Again, a series resistor and large capacitor can be
used to low-pass filter the reference voltage. If the reference
voltage originates from an op amp, make sure that it can
drive the bypass capacitor without oscillation (the series
resistor can help in this case). The ADS7841 draws very
little current from the reference on average, but it does place
larger demands on the reference circuitry over short periods
of time (on each rising edge of DCLK during a conversion).
The ADS7841 architecture offers no inherent rejection of
noise or voltage variation in regards to the reference input.
This is of particular concern when the reference input is tied
to the power supply. Any noise and ripple from the supply
will appear directly in the digital results. While high frequency noise can be filtered out as discussed in the previous
paragraph, voltage variation due to line frequency (50Hz or
60Hz) can be difficult to remove.
The GND pin should be connected to a clean ground point.
In many cases, this will be the “analog” ground. Avoid
connections which are too near the grounding point of a
microcontroller or digital signal processor. If needed, run a
ground trace directly from the converter to the power supply
entry point. The ideal layout will include an analog ground
plane dedicated to the converter and associated analog
circuitry.
ADS7841
SBAS084B
PACKAGE OPTION ADDENDUM
www.ti.com
6-Jul-2009
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
ADS7841E
ACTIVE
SSOP/
QSOP
DBQ
16
ADS7841E/2K5
ACTIVE
SSOP/
QSOP
DBQ
ADS7841E/2K5G4
ACTIVE
SSOP/
QSOP
ADS7841EB
ACTIVE
ADS7841EB/2K5
75
Lead/Ball Finish
MSL Peak Temp (3)
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
DBQ
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
SSOP/
QSOP
DBQ
16
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
ACTIVE
SSOP/
QSOP
DBQ
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
ADS7841EB/2K5G4
ACTIVE
SSOP/
QSOP
DBQ
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
ADS7841EBG4
ACTIVE
SSOP/
QSOP
DBQ
16
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
ADS7841EG4
ACTIVE
SSOP/
QSOP
DBQ
16
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
ADS7841ES
ACTIVE
SSOP/
QSOP
DBQ
16
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
ADS7841ES/2K5
OBSOLETE
SSOP/
QSOP
DBQ
16
TBD
Call TI
Call TI
ADS7841ES/2K5G4
OBSOLETE
SSOP/
QSOP
DBQ
16
TBD
Call TI
Call TI
ADS7841ESG4
ACTIVE
SSOP/
QSOP
DBQ
16
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
ADS7841P
ACTIVE
PDIP
N
16
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
N / A for Pkg Type
ADS7841PB
ACTIVE
PDIP
N
16
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
N / A for Pkg Type
ADS7841PBG4
ACTIVE
PDIP
N
16
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
N / A for Pkg Type
ADS7841PG4
ACTIVE
PDIP
N
16
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
N / A for Pkg Type
75
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
6-Jul-2009
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF ADS7841 :
• Automotive: ADS7841-Q1
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
Diameter Width
(mm) W1 (mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
ADS7841E/2K5
SSOP/
QSOP
DBQ
16
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
ADS7841EB/2K5
SSOP/
QSOP
DBQ
16
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Mar-2008
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ADS7841E/2K5
SSOP/QSOP
DBQ
16
2500
346.0
346.0
29.0
ADS7841EB/2K5
SSOP/QSOP
DBQ
16
2500
346.0
346.0
29.0
Pack Materials-Page 2
IMPORTANT NOTICE
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Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products
Amplifiers
Data Converters
DLP® Products
DSP
Clocks and Timers
Interface
Logic
Power Mgmt
Microcontrollers
RFID
RF/IF and ZigBee® Solutions
amplifier.ti.com
dataconverter.ti.com
www.dlp.com
dsp.ti.com
www.ti.com/clocks
interface.ti.com
logic.ti.com
power.ti.com
microcontroller.ti.com
www.ti-rfid.com
www.ti.com/lprf
Applications
Audio
Automotive
Broadband
Digital Control
Medical
Military
Optical Networking
Security
Telephony
Video & Imaging
Wireless
www.ti.com/audio
www.ti.com/automotive
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/medical
www.ti.com/military
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
www.ti.com/wireless
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