NXP ADC1610S125HN/C1 Single 16-bit adc 125 msps cmos or lvds ddr digital output Datasheet

ADC1610S125
Single 16-bit ADC 125 Msps
CMOS or LVDS DDR digital outputs
Rev. 01 — 28 May 2009
Objective data sheet
1. General description
The ADC1610S is a single channel 16-bit Analog-to-Digital Converter (ADC) optimized for
high dynamic performances and low power consumption at a sample rate of 125 Msps.
Pipelined architecture and output error correction ensure the ADC1610S is accurate
enough to guarantee zero missing codes over the entire operating range. Supplied from a
single 3 V source, it can handle output logic levels from 1.8 V to 3.3 V in CMOS mode,
because of a separate digital output supply. It supports the Low Voltage Differential
Signalling (LVDS) Double Data Rate (DDR) output standard. An integrated Serial
Peripheral Interface (SPI) allows the user to easily configure the ADC. The device also
includes a programmable gain amplifier with a flexible input voltage range. With excellent
dynamic performance from the baseband to input frequencies of 170 MHz or more, the
ADC1610S is ideal for use in communications, imaging and medical applications.
2. Features
n
n
n
n
n
n
SNR, 73 dB
SFDR, 90 dBc
Sample rate, 125 Msps
16-bit pipelined ADC core
Single 3 V supply
Flexible input voltage range: 1 V to 2 V
(p-p) with 6 dB programmable fine gain
n CMOS or LVDS DDR digital outputs
n INL ±4 LSB, DNL ±0.95 LSB (typical)
n
n
n
n
n
n
Input bandwidth, 600 MHz
Power dissipation, 570 mW
SPI Interface
Duty cycle stabilizer
Fast OuT-of-Range (OTR) detection
Offset binary, 2’s complement, gray
code
n Power-down and Sleep modes
n HVQFN40 package
3. Applications
n Wireless and wired broadband communications
n Spectral analysis
n Portable instrumentation
n Ultrasound equipment
n Imaging systems
ADC1610S125
NXP Semiconductors
Single 16-bit ADC 125 Msps
4. Ordering information
Table 1.
Ordering information
Type number
fs (Msps) Package
Name
ADC1610S125HN/C1 125
Description
Version
HVQFN40 plastic thermal enhanced very thin quad flat package; no
leads; 40 terminals; body 6 × 6 × 0.85 mm
SOT618-1
CS
SDIO/ODS
SCLK/DFS
5. Block diagram
ADC1610S
ERROR
CORRECTION AND
DIGITAL
PROCESSING
SPI INTERFACE
OTR
PGA
CMOS:
DAV
or
LVDS/DDR:
DAVP
DAVM
INP
T/H
INPUT
STAGE
ADC CORE
16-BIT
PIPELINED
OUTPUT
DRIVERS
INM
PWD/OE
REFT
REFB
SENSE
VCM
SYSTEM
REFERENCE AND
POWER
MANAGEMENT
VREF
CLKP
CLKM
VDDO
VDDA
AGND
CLOCK INPUT
STAGE AND DUTY
CYCLE CONTROL
CMOS:
D15 to D0
or
LVDS/DDR:
D15P, D15M
to D0P, D0M
005aaa104
Fig 1. Block diagram
ADC1610S125_1
Objective data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 01 — 28 May 2009
2 of 33
ADC1610S125
NXP Semiconductors
Single 16-bit ADC 125 Msps
6. Pinning information
31 D0_D1_M
32 D0_D1_P
33 VDDO
34 DAVM
35 DAVP
36 SCLK/DFS
37 SDIO/DCS
38 CS
39 SENSE
40 VREF
terminal 1
index area
31 D1
32 D0
33 VDDO
34 n.c.
35 DAV
36 SCLK/DFS
37 SDIO/DCS
38 CS
terminal 1
index area
39 SENSE
40 VREF
6.1 Pinning
REFB
1
30 D2_D3_P
REFB
1
30 D2
REFT
2
29 D2_D3_M
REFT
2
29 D3
AGND
3
28 D4_D5_P
AGND
3
28 D4
VCM
4
27 D4_D5_M
VCM
4
27 D5
VDDA
5
VDDA
5
26 D6
AGND
6
AGND
6
25 D7
INM
7
24 D8_D9_P
INM
7
24 D8
INP
8
23 D8_D9_M
INP
8
23 D9
AGND
9
22 D10_D11_P
AGND
9
22 D10
VDDA 10
21 D10_D11_M
VDDA 10
21 D11
Transparent top view
Fig 2.
D12_D13_P 20
D12_D13_M 19
25 D6_D7_M
D14_D15_P 18
D14_D15_M 17
OTR 16
PWD/OE 15
DEC 14
CLKM 13
005aaa105
CLKP 12
VDDA 11
D12 20
D13 19
D14 18
D15 17
OTR 16
PWD/OE 15
DEC 14
CLKM 13
CLKP 12
VDDA 11
ADC1610S
HVQFN40
26 D6_D7_P
ADC1610S
HVQFN40
005aaa106
Transparent top view
Pin configuration with CMOS digital outputs
selected
Fig 3.
Pin configuration with LVDS/DDR digital
outputs selected
6.2 Pin description
Table 2.
Pin description (CMOS digital outputs)
Symbol
Pin
Type [1]
Description
REFB
1
O
bottom reference
REFT
2
O
top reference
AGND
3
G
analog ground
VCM
4
O
common-mode output voltage
VDDA
5
P
analog power supply
AGND
6
G
analog ground
INM
7
I
complementary analog input
INP
8
I
analog input
AGND
9
G
analog ground
VDDA
10
P
analog power supply
VDDA
11
P
analog power supply
CLKP
12
I
clock input
CLKM
13
I
complementary clock input
DEC
14
O
regulator decoupling node
PWD/OE
15
I
power-down, active HIGH; output enable, active LOW
OTR
16
O
out-of-range
ADC1610S125_1
Objective data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 01 — 28 May 2009
3 of 33
ADC1610S125
NXP Semiconductors
Single 16-bit ADC 125 Msps
Table 2.
Pin description (CMOS digital outputs)
Symbol
Pin
Type [1]
Description
D15
17
O
data output bit 15 (MSB)
D14
18
O
data output bit 14
D13
19
O
data output bit 13
D12
20
O
data output bit 12
D11
21
O
data output bit 11
D10
22
O
data output bit10
D9
23
O
data output bit 9
D8
24
O
data output bit 8
D7
25
O
data output bit 7
D6
26
O
data output bit 6
D5
27
O
data output bit 5
D4
28
O
data output bit 4
D3
29
O
data output bit 3
D2
30
O
data output bit 2
D1
31
O
data output bit 1
D0
32
O
data output bit 0 (LSB)
VDDO
33
P
output power supply
n.c.
34
-
not connected
DAV
35
O
data valid output clock
SCLK/DFS
36
I
SPI clock / data format select
SDIO/ODS
37
I/O
SPI data IO / output data standard
CS
38
I
SPI chip select
SENSE
39
I
reference programming pin
VREF
40
I/O
voltage reference input/output
[1]
P: power supply; G: ground; I: input; O: output; I/O: input/output.
Table 3.
Pin description (LVDS/DDR) digital outputs)
Symbol
Pin [1]
Type [2]
Description
D14_D15_M
17
O
differential output data D14 and D15 multiplexed, complement
D14_D15_P
18
O
differential output data D14 and D15 multiplexed, true
D12_D13_M
19
O
differential output data D12 and D13 multiplexed, complement
D12_D13_P
20
O
differential output data D12 and D13 multiplexed, true
D10_D11_M
21
O
differential output data D10 and D11multiplexed, complement
D10_D11_P
22
O
differential output data D10 and D11 multiplexed, true
D8_D9_M
23
O
differential output data D8 and D9 multiplexed, complement
D8_D9_P
24
O
differential output data D8 and D9 multiplexed, true
D6_D7_M
25
O
differential output data D6 and D7 multiplexed, complement
D6_D7_P
26
O
differential output data D6 and D7 multiplexed, true
D4_D5_M
27
O
differential output data D4 and D5 multiplexed, complement
D4_D5_P
28
O
differential output data D4 and D5 multiplexed, true
D2_D3_M
29
O
differential output data D2 and D3 multiplexed, complement
D2_D3_P
30
O
differential output data D2 and D3 multiplexed, true
D0_D1_M
31
O
differential output data D0 and D1 multiplexed, complement
ADC1610S125_1
Objective data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 01 — 28 May 2009
4 of 33
ADC1610S125
NXP Semiconductors
Single 16-bit ADC 125 Msps
Table 3.
Pin description …continued (LVDS/DDR) digital outputs)
Symbol
Pin [1]
Type [2]
Description
D0_D1_P
32
O
differential output data D0 and D1 multiplexed, true
DAVM
34
O
data valid output clock, complement
DAVP
35
O
data valid output clock, true
[1]
Pins 1 to 16 and pins 36 to 40 are the same for both CMOS and LVDS DDR outputs (see Table 2)
[2]
P: power supply; G: ground; I: input; O: output; I/O: input/output.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
VDDA
analog supply voltage
VDDO
output supply voltage
∆VCC
supply voltage difference
Tstg
Min
Max
Unit
<tbd>
<tbd>
V
<tbd>
<tbd>
V
<tbd>
<tbd>
V
storage temperature
−55
+125
°C
Tamb
ambient temperature
−40
+85
°C
Tj
junction temperature
-
<tbd>
°C
VDDA − VDDO
8. Thermal characteristics
Table 5.
Symbol
Rth(j-a)
Rth(j-c)
[1]
Thermal characteristics
Parameter
Conditions
Typ
Unit
thermal resistance from junction to ambient
[1]
<tbd>
K/W
thermal resistance from junction to case
[1]
<tbd>
K/W
In compliance with JEDEC test board, in free air.
ADC1610S125_1
Objective data sheet
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Rev. 01 — 28 May 2009
5 of 33
ADC1610S125
NXP Semiconductors
Single 16-bit ADC 125 Msps
9. Static characteristics
Table 6.
Static characteristics
Typical values measured at VDDA = 3 V, VDDO = 1.8 V, Tamb = 25 °C and CL = 5 pF; min. and max. values are across the full
temperature range Tamb = −40 °C to +85 °C at VDDA = 3 V, VDDO = 1.8 V; VINP − VINM = −1 dBFS; internal reference mode;
applied to CMOS and LVDS interface; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
2.85
3.0
3.4
V
1.65
1.8
3.6
V
Supplies
VDDA
analog supply voltage
VDDO
output supply voltage
LVDS DDR mode
2.85
3.0
3.6
V
IDDA
analog supply current
fclk = 125 Msps; fi =70 MHz
-
185
-
mA
IDDO
output supply current
CMOS mode;
fclk = 125 Msps; fi =70 MHz
-
20
-
mA
LVDS DDR mode:
fclk = 125 Msps; fi =70 MHz
-
45
-
mA
-
570
-
mW
Power-down mode
-
2
-
mW
Sleep mode
-
40
-
mW
peak-to-peak
0.2
0.8
<tbd>
V
0.3VDDA
-
0.7VDDA V
-
0
-
LOW-medium level
-
0.3VDDA
-
medium-HIGH level
-
0.6VDDA
-
P
CMOS mode
power dissipation
Clock inputs: pins CLKP and CLKM
AC coupled; LVPECL, LVDS and sine wave
Vi(clk)dif
differential clock input voltage
LVCMOS
VI
input voltage
Logic Inputs: pin PWD/OE
VIL
LOW-level input voltage
V
VIH
HIGH-level input voltage
-
VDDA
-
V
IIL
LOW-level input current
<tbd>
-
<tbd>
µA
IIH
HIGH-level input current
−10
-
+10
µA
Serial Peripheral Interface: pins CS, SDIO/ODS, SCLK/DFS
VIL
LOW-level input voltage
0
-
0.3VDDA V
VIH
HIGH-level input voltage
0.7VDDA
-
VDDA
V
IIL
LOW-level input current
−10
-
+10
µA
IIH
HIGH-level input current
−50
-
+50
µA
CI
input capacitance
-
4
-
pF
Digital Outputs: CMOS mode - pins D13 to D0, OTR, DAV
Output levels, VDDO = 3V
VOL
LOW-level output voltage
IOL = <tbd>
AGND
-
0.2VDDO V
VOH
HIGH-level output voltage
IOH = <tbd>
0.8VDDO
-
VDDO
V
IOL
LOW-level output current
3-state; output level = 0 V
-
<tbd>
-
µA
IOH
HIGH-level output current
3-state; output level = VDDA
-
<tbd>
-
µA
CO
output capacitance
high impedance; OE = HIGH
-
3
-
pF
ADC1610S125_1
Objective data sheet
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Rev. 01 — 28 May 2009
6 of 33
ADC1610S125
NXP Semiconductors
Single 16-bit ADC 125 Msps
Table 6.
Static characteristics …continued
Typical values measured at VDDA = 3 V, VDDO = 1.8 V, Tamb = 25 °C and CL = 5 pF; min. and max. values are across the full
temperature range Tamb = −40 °C to +85 °C at VDDA = 3 V, VDDO = 1.8 V; VINP − VINM = −1 dBFS; internal reference mode;
applied to CMOS and LVDS interface; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Output levels, VDDO = 1.8 V
VOL
LOW-level output voltage
IOL = <tbd>
AGND
-
0.2VDDO V
VOH
HIGH-level output voltage
IOH = <tbd>
0.8VDDO
-
VDDO
V
Digital Outputs, LVDS mode - pins D13P, D13M to D0P, D0M, DAVP and DAVM
Output levels, VDDO = 3 V only, Rload = 100 Ω
VO(offset)
output offset voltage
output buffer current set to
3.5 mA
-
1.2
-
V
VO(dif)
differential output voltage
output buffer current set to
3.5 mA
-
350
-
mV
CO
output capacitance
-
<tbd>
-
pF
µA
Analog inputs: pins INP and INM
II
Input current
−5
-
+5
RI
input resistance
-
<tbd>
-
Ω
CI
input capacitance
-
5
-
pF
VI(cm)
common-mode input voltage
0.9
1.5
2
V
Bi
input bandwidth
-
600
-
MHz
VI(dif)
differential input voltage
1
-
2
V
VINP = VINM
peak-to-peak
Common mode output voltage: pin VCM
VO(cm)
common-mode output voltage
-
0.5VDDA
-
V
IO(cm)
common-mode output current
-
<tbd>
-
µA
output
-
0.5 to 1
-
V
input
0.5
-
1
V
-
±4
-
LSB
guaranteed no missing codes
-
±0.95
-
LSB
I/O reference voltage: pin VREF
VVREF
voltage on pin VREF
Accuracy
INL
integral non-linearity
DNL
differential non-linearity
Eoffset
offset error
-
±2
-
mV
EG
gain error
-
±0.5
-
%FS
-
35
-
dBc
Supply
PSRR
power supply rejection ratio
100 mV (p-p) on VDDA
ADC1610S125_1
Objective data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 01 — 28 May 2009
7 of 33
ADC1610S125
NXP Semiconductors
Single 16-bit ADC 125 Msps
10. Dynamic characteristics
10.1 Dynamic characteristics
Table 7.
Dynamic characteristics
Typical values measured at VDDA = 3 V, VDDO = 1.8 V, Tamb = 25 °C and CL = 5 pF; min. and max. values are across the full
temperature range Tamb = −40 °C to +85 °C at VDDA = 3 V, VDDO = 1.8 V; VINP − VINM = −1 dBFS; internal reference mode;
applied to CMOS and LVDS interface; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fi = 3 MHz
-
95
-
dBc
fi = 30 MHz
-
92
-
dBc
fi = 70 MHz
-
89
-
dBc
fi = 170 MHz
-
88
-
dBc
fi = 3 MHz
-
90
-
dBc
fi = 30 MHz
-
89
-
dBc
fi = 70 MHz
-
88
-
dBc
fi = 170 MHz
-
87
-
dBc
fi = 3 MHz
-
87
-
dBc
fi = 30 MHz
-
86
-
dBc
fi = 70 MHz
-
83
-
dBc
fi = 170 MHz
-
79
-
dBc
fi = 3 MHz
-
11.8
-
bits
fi = 30 MHz
-
11.7
-
bits
fi = 70 MHz
-
11.6
-
bits
fi = 170 MHz
-
11.5
-
bits
fi = 3 MHz
-
73
-
dBFS
fi = 30 MHz
-
72.2
-
dBFS
fi = 70 MHz
-
71.6
-
dBFS
fi = 170 MHz
-
71
-
dBFS
fi = 3 MHz
-
74
-
dBFS
fi = 30 MHz
-
73.5
-
dBFS
fi = 70 MHz
-
73.4
-
dBFS
fi = 170 MHz
-
73.3
-
dBFS
Analog signal processing
α2H
α3H
THD
ENOB
SNR
second harmonic level
third harmonic level
total harmonic distortion
effective number of bits
signal-to-noise ratio
at −20 dBFS
SFDR
IMD
spurious-free dynamic range
Intermodulation distortion
fi = 3 MHz
-
90
-
dBc
fi = 30 MHz
-
89
-
dBc
fi = 70 MHz
-
88
-
dBc
fi = 170 MHz
-
87
-
dBc
fi = 3 MHz
-
93
-
dBc
fi = 30 MHz
-
92
-
dBc
fi = 70 MHz
-
91
-
dBc
fi = 170 MHz
-
90
-
dBc
ADC1610S125_1
Objective data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 01 — 28 May 2009
8 of 33
ADC1610S125
NXP Semiconductors
Single 16-bit ADC 125 Msps
10.2 Clock and digital output timing
Table 8.
Dynamic characteristics
Typical values measured at VDDA = 3 V, VDDO = 1.8 V, Tamb = 25 °C and CL = 5 pF; min. and max. values are across the full
temperature range Tamb = −40 °C to +85 °C at VDDA = 3 V, VDDO = 1.8 V; VINP − VINM = −1 dBFS; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Clock timing input: pins CLKP and CLKM
fclk
clock frequency
60
-
125
MHz
tlat(data)
data latency time
-
14
-
clk/cy
δclk
clock duty cycle
30
50
70
%
45
50
55
%
td(s)
sampling delay time
-
0.8
-
ns
twake
wake-up time
-
<tbd>
-
ns
DATA
-
3.9
-
ns
DAV
-
4.2
-
ns
-
4.3
-
ns
-
3.5
-
ns
0.5
-
2.4
ns
0.5
-
2.4
ns
0.5
-
2.4
ns
DATA
-
3.9
-
ns
DAV
-
4.2
-
ns
DCS_EN = 1
DCS_EN = 0
CMOS mode timing output: pins D13 to D0 and DAV
propagation delay
tPD
tsu
set-up time
th
hold time
rise time
tr
[1]
DATA
DAV
fall time
tf
[1]
DATA
LVDS DDR mode timing output: pins D13P, D13M to D0P, D0M, DAVP and DAVM
propagation delay
tPD
[1]
Measured between 20 % to 80 % of VDDO; rise time measured from −50 mV to +50 mV; fall time measured from +50mV to −50mV.
10.3 SPI timings
Table 9.
Characteristics
Typical values measured at VDDA = 3 V, VDDO = 1.8 V, Tamb = 25 °C and CL = 5 pF.
Min. and max. values are across the full temperature range Tamb = −40 °C to +85 °C at VDDA = 3V, VDDO = 1.8 V
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
SPI timings
tw(SCLK)
SCLK pulse width
40
-
-
ns
tw(SCLKH)
SCLK HIGH pulse width
16
-
-
ns
tw(SCLKL)
SCLK LOW pulse width
16
-
-
ns
tsu
set-up time
th
fclk(max)
hold time
data to SCLKH
5
-
-
ns
CS to SCLKH
5
-
-
ns
data to SCLKH
2
-
-
ns
CS to SCLKH
2
-
-
ns
-
-
25
MHz
maximum clock frequency
ADC1610S125_1
Objective data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 01 — 28 May 2009
9 of 33
ADC1610S125
NXP Semiconductors
Single 16-bit ADC 125 Msps
11. Application information
11.1 Device control
The ADC1610S can be controlled via the SPI (SPI control mode) or directly via the I/O
pins (PIN control mode).
11.1.1 SPI and PIN control modes
The device enters PIN control mode at power-up, and remains in this mode as long as pin
CS is held HIGH. In PIN control mode, the SPI pins SDIO, CS and SCLK are used as
static control pins. SPI settings are ignored.
SPI control mode is enabled by forcing pin CS LOW. It is not possible to toggle between
PIN control and SPI control modes. Once SPI control mode has been enabled, the device
will remain in this mode until it is powered down. The transition from PIN control mode to
SPI control mode is illustrated in Figure 4.
CS
SCLK/DFS
SDIO/ODS
PIN control mode
Data Format
2's complement
SPI control mode
Data Format
offset binary
LVDS DDR
R/W
CMOS
W1
W0
A12
005aaa039
Fig 4. Control mode selection.
When the device enters SPI control mode, the output data standard (CMOS or LVD DDR)
is not determined by the state of the relevant SPI control bit (LVDS/CMOS; see Table 21),
but by the level on pin SDIO at the instant a transition is triggered by a falling edge on CS
(SDIO = LOW = CMOS).
11.1.2 Operating mode selection
The active ADC1610S operating mode (Power-up, Power-down or Sleep) can be selected
via the SPI interface (see Table 18) or using pins PWD and OE in PIN control mode, as
described in Table 10.
Table 10.
Operating mode selection via pin PWD/OE
PWD/OE
Operating mode
Output high-Z
0
Power-down
yes
1/3VDDA
Sleep
yes
2/3VDDA
Power-up
yes
VDDA
Power-up
no
11.1.3 Selecting the output data standard
The output data standard (CMOS or LVDS DDR) can be selected via the SPI interface
(see Table 21) or using pin ODS in PIN control mode. LVDS DDR is selected when ODS is
HIGH, otherwise CMOS is selected.
ADC1610S125_1
Objective data sheet
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Rev. 01 — 28 May 2009
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ADC1610S125
NXP Semiconductors
Single 16-bit ADC 125 Msps
11.1.4 Selecting the output data format
The output data format can be selected via the SPI interface (offset binary, 2’s
complement or gray code; see Table 21) or using pin DFS in PIN control mode (offset
binary or 2’s complement). Offset binary is selected when DFS is LOW. When DFS is
HIGH, 2’s complement is selected.
11.2 Analog inputs
11.2.1 Input stage
The analog input of the ADC1610S supports a differential or a single-ended input drive.
Optimal performance is achieved using differential inputs with the common-mode input
voltage (VI(cm)) on pins INP and INM set to 0.5VDDA.
The full scale analog input voltage range is configurable between 1 V (p-p) and 2 V (p-p)
via a programmable internal reference (see Section 11.3 and Table 20 further details).
The equivalent circuit of the sample and hold input stage, including ESD protection and
circuit and package parasitics, is shown in Figure 5.
Package
ESD
Parasitics
Switch
INP
Ron = 14 Ω
8
internal
clock
4 pF
Sampling
Capacitor
Switch
INM
Ron = 14 Ω
7
internal
clock
4 pF
Sampling
Capacitor
005aaa043
Fig 5.
Input sampling circuit
The sample phase occurs when the internal clock (derived from the clock signal on pin
CLKP/CLKM) is HIGH. The voltage is then held on the sampling capacitors. When the
clock signal goes LOW, the stage enters the hold phase and the voltage information is
transmitted to the ADC core.
11.2.2 Anti-kickback circuitry
Anti-kickback circuitry (R-C filter in Figure 6 is needed to counteract the effects of charge
injection generated by the sampling capacitance.
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ADC1610S125
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Single 16-bit ADC 125 Msps
The RC filter is also used to filter noise from the signal before it reaches the sampling
stage. The value of the capacitor should be chosen to maximize noise attenuation without
degrading the settling time excessively.
R
INP
C
R
INM
005aaa073
Fig 6.
Anti-kickback circuit
The component values are determined by the input frequency and should be selected so
as not to affect the input bandwidth.
Table 11.
RC coupling versus input frequency - recommended values
Input frequency
R
C
3 MHz
25 ohms
12 pF
70 MHz
12 ohms
8 pF
170 MHz
12 ohms
8 pF
11.2.3 Transformer
The configuration of the transformer circuit is determined by the input frequency. The
configuration shown in Figure 7 would be suitable for a baseband application.
ADT1-1WT
100 nF
Analog
lnput
25 Ω
100 nF
INP
25 Ω
12 pF
100 nF
100 nF
25 Ω
25 Ω
INM
VCM
100 nF
100 nF
005aaa044
Fig 7.
Single transformer configuration suitable for baseband applications
The configuration shown in Figure 8 is recommended for high frequency applications. In
both cases, the choice of transformer will be a compromise between cost and
performance.
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ADC1610S125
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Single 16-bit ADC 125 Msps
ADT1-1WT
Analog
lnput
ADT1-1WT
100 nF
12 Ω
50 Ω
50 Ω
50 Ω
50 Ω
INP
8.2 pF
12 Ω
100 nF
INM
VCM
100 nF
100 nF
005aaa045
Fig 8.
Dual transformer configuration suitable for high frequency application
11.3 System reference and power management
11.3.1 Internal/external references
The ADC1610S has a stable and accurate built-in internal reference voltage. This
reference voltage can be set internally, externally or via the SPI (programmable in 1 dB
steps between 0 dB and −6 dB via control bits INTREF when bit INTREF_EN = 1; see
Table 20). The equivalent reference circuit is shown in Figure 9.
REFT
REFERENCE
AMP
VREF
BUFFER
REFB
BANDGAP
REFERENCE
ADC CORE
SENSE
SELECTION
LOGIC
005aaa046
Fig 9.
Single transformer configuration suitable for baseband applications
If bit INTREF_EN is set to 0, the reference voltage will be determined either internally or
externally as detailed in Table 12.
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Single 16-bit ADC 125 Msps
Table 12.
Reference selection
Selection
SPI bit
INTREF_EN
SENSE pin
VREF pin
full scale (p-p)
internal
0
AGND
330 pF capacitor to
AGND
2V
internal
0
pin VREF connected to pin SENSE and
via a 330 pF capacitor to AGND
external
0
VDDA
external voltage between
0.5 V and 1 V[1]
1 V to 2 V
internal via SPI
1
pin VREF connected to pin SENSE and
via 330 pF capacitor to AGND
1 V to 2 V
[1]
1V
The voltage on pin VREF is doubled internally to generate the internal reference voltage.
Figure 10 to Figure 13 illustrate how to connect the SENSE and VREF pins to select the
required reference voltage source.
VREF
REFT
VREF
REFT
SENSE
REFB
330 pF
330 pF
REFB
SENSE
005aaa048
005aaa047
Fig 10. Internal reference, 2 V (p-p) full scale
VREF
Fig 11. Internal reference, 1 V (p-p) full scale
REFT
VREF
0.1 µF
V
330 pF
SPI SETTINGS
INTREF_EN = 1, active
INTREF = XXX
REFB
SENSE
Fig 12. Internal reference via SPI, 1 V to 2 V (p-p)
full scale
005aaa050
Fig 13. External reference, 1 V to 2 V (p-p) full scale
ADC1610S125_1
Objective data sheet
REFB
SENSE
VDDA
005aaa049
REFT
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Single 16-bit ADC 125 Msps
11.3.2 Gain control
The gain is programmable between 0 dB to −6 dB in 1 dB steps via the SPI (see
Table 20). This makes it possible to improve the Spurious-Free Dynamic Range (SFDR) of
the ADC1610S. The corresponding full scale input voltage range varies between 2 V (p-p)
and 1 V (p-p), as shown in Table 13:
Table 13.
Reference SPI Gain Control
INTREF
Gain
full scale (p-p)
000
0 dB
2V
001
−1 dB
1.78 V
010
−2 dB
1.59 V
011
−3 dB
1.42 V
100
−4 dB
1.26 V
101
−5 dB
1.12 V
110
−6 dB
1V
111
reserved
x
11.3.3 Common-mode output voltage (VO(cm))
A 0.1 µF filter capacitor should be connected between pin VCM and ground to ensure a
low-noise common-mode output voltage. When AC-coupled, pin VCM can then be used to
set the common-mode reference for the analog inputs, for instance via a transformer
middle point.
PACKAGE
ESD
PARASITICS
COMMON MODE
REFERENCE
1.5 V
VCM
0.1 µF
ADC CORE
005aaa051
Fig 14. Equivalent schematic of the common-mode reference circuit
11.3.4 Biasing
The common-mode input voltage (VI(cm)) on pins INP and INM should be set externally to
0.5VDDA for optimal performance and should always be between 0.9 V and 2 V.
The graph in Figure 15 illustrates how the SFDR and SNR characteristics vary with
changes in the common-mode input voltage.
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Single 16-bit ADC 125 Msps
dB
SFDR (x MHz)
SNR (x MHz)
2V
0.9 V
VI(cm)
005aaa052
Fig 15. SFDR and SNR performances versus VI(cm)
11.4 Clock input
11.4.1 Drive modes
The ADC1610S can be driven differentially (SINE, LVPECL or LVDS) without the
performance being affected by the choice of configuration. It can also be driven by a
single-ended LVCMOS signal connected to pin CLKP (CLKM should be connected to
ground via a capacitor) or CLKM (CLKP should be connected to ground via a capacitor).
LVCMOS
Clock lnput
CLKP
CLKP
CLKM
LVCMOS
Clock lnput
CLKM
005aaa053
Fig 16. LVCMOS Single-ended clock input
CLKP
Sine
Clock lnput
Sine
Clock lnput
CLKM
CLKP
CLKM
005aaa054
Fig 17. Sine differential clock input
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Single 16-bit ADC 125 Msps
CLKP
LVDS
Clock lnput
CLKM
005aaa055
Fig 18. LVDS differential clock input
11.4.2 Equivalent input circuit
The equivalent circuit of the input clock buffer is shown in Figure 19. The common-mode
voltage of the differential input stage is set via internal 5 kΩ resistors.
PACKAGE
ESD
PARASITICS
CLKP
Vcm(clk)
SE_SEL
SE_SEL
5k
5k
CLKM
005aaa056
Fig 19. Equivalent input circuit
Single-ended or differential clock inputs can be selected via the SPI interface (see
Table 19). If single-ended is enabled, the input pin (CLKM or CLKP) is selected via control
bit SE_SEL.
If single-ended is implemented without setting SE_SEL to the appropriate value, the
unused pin should be connected to ground via a capacitor.
11.4.3 Duty cycle stabilizer
The duty cycle stabilizer can improve the overall performances of the ADC by
compensating the duty cycle of the input clock signal. When the duty cycle stabilizer is
active (bit DCS_EN = 1; see Table 19), the circuit can handle signals with duty cycles of
between 30 % and 70 % (typical). When the duty cycle stabilizer is disabled
(DCS_EN = 0), the input clock signal should have a duty cycle of between 45 % and
55 %.
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Single 16-bit ADC 125 Msps
11.4.4 Clock input divider
The ADC1610S contains an input clock divider that divides the incoming clock by a factor
of 2 (when bit CLKDIV = 1; see Table 19). This feature allows the user to deliver a higher
clock frequency with better jitter performance, leading to a better SNR result once
acquisition has been performed.
11.5 Digital outputs
11.5.1 Digital output buffers: CMOS mode
The digital output buffers can be configured as CMOS by setting bit LVDS/CMOS to 0 (see
Table 21).
Each digital output has a dedicated output buffer. The equivalent circuit of the CMOS
digital output buffer is shown in Figure 20. The buffer is powered by a separate
AGND/VDDO to ensure 1.8 V to 3.4 V compatibility and is isolated from the ADC core.
Each buffer can be loaded by a maximum of 10 pF.
VDDO
PARASITICS
LOGIC
DRIVER
ESD
PACKAGE
50 Ω
Dx
AGND
005aaa112
Fig 20. CMOS digital output buffer
The output resistance is 50 Ω and is the combination of the an internal resistor and the
equivalent output resistance of the buffer. There is no need for an external damping
resistor. The drive strength of both data and DAV buffers can be programmed via the SPI
in order to adjust the rise and fall times of the output digital signals (see Table 28):
11.5.2 Digital output buffers: LVDS DDR mode
The digital output buffers can be configured as LVDS DDR by setting bit LVDS/CMOS to 1
(see Table 21).
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Single 16-bit ADC 125 Msps
VCCO
3.5 mA
typ
−
+
DnP/Dn + 1P
DnM/Dn + 1M
100 Ω
RECEIVER
−
+
AGND
005aaa123
Fig 21. LVDS DDR digital output buffer - externally terminated
Each output should be terminated externally with a 100 Ω resistor (typical) at the receiver
side (Figure 21) or internally via SPI control bits LVDS_INTTER (see Figure 22 and
Table 30).
VCCO
3.5 mA
typ
−
+
DxP/Dx + 1P
100 Ω
+
DxM/Dx + 1M
RECEIVER
−
AGND
005aaa124
Fig 22. LVDS DDR digital output buffer - internally terminated
The default LVDS DDR output buffer current is set to 3.5 mA. It can be programmed via
the SPI (bits DAVI and DATAI; see Table 29) in order to adjust the output logic voltage
levels.
11.5.3 DAta Valid (DAV) output clock
A DSV output clock signal is provided that can be used to capture the data delivered by
the ADC1610S. Detailed timing diagrams for CMOS and LVDS DDR modes are provided
in Figure 23 and Figure 24 respectively.
11.5.4 Out-of-Range (OTR)
An out-of-range signal is provided on pin OTR. By default, pin OTR goes HIGH fourteen
clock cycles after an OTR event has occurred. The OTR response can be speeded up by
enabling Fast OTR (bit FASTOTR = 1; see Table 27). When Fast OTR is enabled, OTR
goes HIGH four clock cycles after the OTR event. The Fast OTR detection threshold
(below full scale) can be programmed via bits FASTOTR_DET.
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Single 16-bit ADC 125 Msps
11.5.5 Digital offset
By default, the ADC1610S delivers output code that corresponds to the analog input.
However it is possible to add a digital offset to the output code via the SPI (bits
DIG_OFFSET; see Table 23).
11.5.6 Test patterns
For test purposes, the ADC1610S can be configured to transmit one of a number of
predefined test patterns (via bits TESTPAT_SEL; see Table 24). A custom test pattern can
be defined by the user (TESTPAT_USER; see Table 25 and Table 26) and is selected
when TESTPAT_SEL = 101. The selected test pattern will be transmitted regardless of the
analog input.
11.5.7 Output codes versus input voltage
Table 14.
Output codes
VINP − VINM
Offset binary
2’s complement
OTR pin
< −1
0000 0000 0000 0000
1000 0000 0000 0000
1
−1
0000 0000 0000 0000
1000 0000 0000 0000
0
−0.99996948
0000 0000 0000 0001
1000 0000 0000 0001
0
−0.99993896
0000 0000 0000 0010
1000 0000 0000 0010
0
−0.99990845
0000 0000 0000 0011
1000 0000 0000 0011
0
−0.99987793
0000 0000 0000 0100
1000 0000 0000 0100
0
....
....
....
0
−0.00006104
01 1111 1111 1110
1111 1111 1111 1110
0
−0.00003052
01 1111 1111 1111
1111 1111 1111 1111
0
0
10 0000 0000 0000
0000 0000 0000 0000
0
+0.00003052
10 0000 0000 0001
0000 0000 0000 0001
0
+0.00006104
10 0000 0000 0010
0000 0000 0000 0010
0
....
....
....
0
+0.99987793
1111 1111 1111 1011
0111 1111 1111 1011
0
+0.99990845
1111 1111 1111 1100
0111 1111 1111 1100
0
+0.99993896
1111 1111 1111 1101
0111 1111 1111 1101
0
+0.99996948
1111 1111 1111 1110
0111 1111 1111 1110
0
+1
1111 1111 1111 1111
0111 1111 1111 1111
0
> +1
1111 1111 1111 1111
0111 1111 1111 1111
1
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ADC1610S125
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Single 16-bit ADC 125 Msps
11.6 Timings summary
11.6.1 CMOS mode timings
N
N+1
td(s)
N+2
tclk
CLKP
CLKM
tPD
(N − 14)
(N − 13)
(N − 12)
(N − 11)
DATA
tsu
tPD
th
DAV
tclk
005aaa060
Fig 23. CMOS mode timing
11.6.2 LVDS DDR mode timing
N
N+1
td(s)
N+2
tclk
CLKP
CLKM
tPD
(N − 14)
(N − 13)
(N − 12)
(N − 11)
Dx_Dx + 1_P
Dx
Dx + 1
Dx
Dx + 1
Dx
Dx + 1
Dx
Dx + 1
Dx
Dx + 1
Dx_Dx + 1_M
tsu th tsu th
tPD
DAVP
DAVM
tclk
005aaa061
Fig 24. LDVS DDR mode timing
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Single 16-bit ADC 125 Msps
11.7 Serial Peripheral Interface (SPI)
11.7.1 Register description
The ADC1610S serial interface is a synchronous serial communications port that allows
for easy interfacing with many commonly-used microprocessors. It provides access to the
registers that control the operation of the chip.
This interface is configured as a 3-wire type (SDIO as bidirectional pin)
Pin SCLK is the serial clock input and CS is the chip select pin.
Each read/write operation is initiated by a LOW level on CS. A minimum of three bytes will
be transmitted (two instruction bytes and at least one data byte). The number of data
bytes is determined by the value of bits W1 and W2 (see Table 16).
Table 15.
Instruction bytes for the SPI
MSB
LSB
Bit
7
6
5
4
3
2
1
0
Description
R/W[1]
W1[2]
W0[2]
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
[1]
Bit R/W indicates whether it is a read (1) or a write (0) operation.
[2]
Bits W1 and W0 indicate the number of bytes to be transferred after the instruction byte (see Table 16).
Table 16.
Number of data bytes to be transferred after the instruction bytes
W1
W0
Number of bytes transmitted
0
0
1 byte
0
1
2 bytes
1
0
3 bytes
1
1
4 bytes or more
Bits A12 to A0 indicate the address of the register being accessed. In the case of a
multiple byte transfer, this address is the first register to be accessed. An address counter
is incriminated to access subsequent addresses.
The steps involved in a data transfer are as follows:
1. A falling edge on CS in combination with a rising edge on SCLK determine the start of
communications.
2. The first phase is the transfer of the 2-byte instruction.
3. The second phase is the transfer of the data which can vary in length but will always
be a multiple of 8 bits. The MSB is always sent first (for instruction and data bytes).
4. A rising edge on CS indicates the end on data transmission.
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ADC1610S125
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Single 16-bit ADC 125 Msps
CS
SCLK
SDIO
R/W W1 W0 A12 A11 A10 A9
A8
A7
A6
A5
A4
A3
A2 A1
Instruction bytes
A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
Register N (data)
Register N + 1 (data)
005aaa062
Fig 25. SPI mode timing
11.7.2 Default modes at start-up
During circuit initialization, it does not matter which output data standard has been
selected. At power-up, the device defaults to PIN control mode.
A falling edge on CS will trigger a transition to SPI control mode. When the ADC1610S
enters SPI control mode, the output data standard (CMOS/LVDS DDR) is determined by
the level on pin SDIO (see Figure 26). Once in SPI control mode, the output data standard
can be changed via bit LVDS/CMOS in Table 21.
When the ADC1610S enters SPI control mode, the output data format (2’s complement or
offset binary) is determined by the level on pin SCLK (grey code can only be selected via
the SPI). Once in SPI control mode, the output data format can be changed via bit
DATA_FORMAT in Table 21.
CS
SCLK
(Data Format)
SDIO
(CMOS LVDS DDR)
Offset binary, LVDS DDR
default mode at startup
005aaa063
Fig 26. Default mode at start-up: SCLK LOW = offset binary; SDIO HIGH = LVDS DDR
CS
SCLK
(Data Format)
SDIO
(CMOS LVDS DDR)
2's complement, CMOS
default mode at startup
005aaa064
Fig 27. Default mode at start-up: SCLK HIGH = 2’s complement; SDIO LOW = CMOS
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ADC1610S125
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Single 16-bit ADC 125 Msps
11.7.3 Register allocation map
Table 17.
Register allocation map
Addr Register name
Hex
R/W Bit definition
0005 Reset and
operating mode
Bit 7
Default
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
R/W SW_
RST
-
-
-
-
-
OP_MODE
0006 Clock
R/W -
-
-
SE_SEL DIFF/SE
-
CLKDIV
0008 Internal reference
R/W -
-
-
-
INTREF_
EN
INTREF
0011 Output data
standard.
R/W -
-
-
LVDS/
CMOS
OUTBUF
-
0012 Output clock
R/W -
-
-
-
DAVINV
DAVPHASE
0013 Offset
R/W -
-
DIG_OFFSET
0014 Test pattern 1
R/W -
-
-
0015 Test pattern 2
R/W TESTPAT_USER
0000
0000
0016 Test pattern 2
R/W TESTPAT_USER
0000
0000
0017 Fast OTR
R/W
-
-
-
-
FASTOTR
0020 CMOS output
R/W
-
-
-
-
DAV_DRV
0021 LVDS DDR O/P 1
R/W
-
-
DAVI_
x2_EN
DAVI
0022 LVDS DDR O/P 2
R/W
-
-
Table 18.
-
-
-
Bit 0
Bin
0000
0000
DCS_EN 0000
0001
0000
0000
DATA_FORMAT
0000
0000
0000
1110
0000
0000
-
TESTPAT_SEL
0000
0000
FASTOTR_DET
0000
0000
DATA_DRV
0000
1110
DATAI_x DATAI
2_EN
0000
0000
BIT/BYTE_ LVDS_INTTER
WISE
0000
0000
Reset and operating mode control register (address 0005h) bit description
Bit
Symbol
Access
7
SW_RST
R/W
Value
Description
reset digital section
0
no reset
1
performs a reset of the digital section
6 to 2 reserved
1 to 0 OP_MODE
R/W
operating mode
00
Normal (Power-up)
01
Power-down
10
Sleep
11
Normal (Power-up)
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ADC1610S125
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Single 16-bit ADC 125 Msps
Table 19.
Bit
Clock control register (address 0006h)bit description
Symbol
Access Value
Description
R/W
single-ended clock input pin select
7 to 5 reserved
4
3
SE_SEL
DIFF/SE
2
reserved
1
CLKDIV
0
DCS_EN
Table 20.
Bit
0
CLKM
1
CLKP
R/W
differential/single ended clock input select
0
fully differential
1
single-ended
R/W
clock input divide by 2
0
disabled
1
enabled
R/W
duty cycle stabilizer
0
disabled
1
enabled
Internal reference control register (address 0008h) bit description
Symbol
Access
Value
Description
7 to 4 reserved
3
INTREF_EN
2 to 0 INTREF
Table 21.
Bit
R/W
programmable internal reference enable
0
disable
1
active
R/W
programmable internal reference
000
0 dB (FS = 2 V)
001
−1 dB (FS = 1.78 V)
010
−2 dB (FS = 1.59 V)
011
−3 dB (FS = 1.42 V)
100
−4 dB (FS = 1.26 V)
101
−5 dB (FS = 1.12 V)
110
−6 dB (FS = 1 V)
111
reserved
Output data standard control register (address 0011h) bit description
Symbol
Access
Value
Description
7 to 5 reserved
4
3
2
LVDS/CMOS
OUTBUF
R/W
output data standard: LVDS DDR or CMOS
0
CMOS
1
LVDS DDR
R/W
output buffers enable
0
output enabled
1
output disabled (high Z)
reserved
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ADC1610S125
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Single 16-bit ADC 125 Msps
Table 21.
Bit
Output data standard control register (address 0011h) bit description …continued
Symbol
1 to 0 DATA_FORMAT
Table 22.
Bit
Access
Value
Description
R/W
output data format
00
offset binary
01
2’s complement
10
gray code
11
offset binary
Output clock register (address 0012h) bit description
Symbol
Access
Value Description
7 to 4 reserved
3
DAVINV
2 to 0 DAVPHASE
Table 23.
Bit
R/W
output clock data valid (DAV) polarity
0
normal
1
inverted
R/W
DAV phase select
000
output clock shifted (ahead) by 3 ns
001
output clock shifted (ahead) by 2.5 ns
010
output clock shifted (ahead) by 2 ns
011
output clock shifted (ahead) by 1.5 ns
100
output clock shifted (ahead) by 1 ns
101
output clock shifted (ahead) by 0.5 ns
110
default value as defined in timing section
111
output clock shifted (delayed) by 0.5 ns
Offset register (address 0013h) bit description
Symbol
Access
Value
Description
7 to 6 reset
5 to 0 DIG_OFFSET
R/W
digital offset adjustment
011111
...
...
000000
0
...
...
100000
ADC1610S125_1
Objective data sheet
+31 LSB
−32 LSB
© NXP B.V. 2009. All rights reserved.
Rev. 01 — 28 May 2009
26 of 33
ADC1610S125
NXP Semiconductors
Single 16-bit ADC 125 Msps
Table 24.
Bit
Test pattern register 1 (address 0014h) bit description
Symbol
Access Value
Description
R/W
digital test pattern select
7 to 3 reserved
2 to 0 TESTPAT_SEL
Table 25.
Bit
7 to 0 TESTPAT_USER
Bit
7 to 0 TESTPAT_USER
Bit
001
mid scale
010
−FS
011
+FS
100
toggle ‘1111..1111’/’0000..0000’
101
custom test pattern
110
‘1010..1010.’
111
‘010..1010’
Access Value
Description
R/W
custom digital test pattern (bits 15 to 8)
Test pattern register 3 (address 0016h) bit description
Symbol
Table 27.
off
Test pattern register 2 (address 0015h) bit description
Symbol
Table 26.
000
Access Value
Description
R/W
custom digital test pattern (bits 7 to 0)
Fast OTR register (address 0017h) bit description
Symbol
Access Value
Description
R/W
fast Out-of-Range (OTR) detection
7 to 4 reset
3
FASTOTR
0
disabled
1
2 to 0 FASTOTR_DET
R/W
enabled
set fast OTR detect level
000
−20.56 dB
001
−16.12 dB
010
−11.02 dB
011
−7.82 dB
100
−5.49 dB
101
−3.66 dB
110
−2.14 dB
111
−0.86 dB
ADC1610S125_1
Objective data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 01 — 28 May 2009
27 of 33
ADC1610S125
NXP Semiconductors
Single 16-bit ADC 125 Msps
Table 28.
Bit
CMOS output register (address 0020h) bit description
Symbol
Access
Value
Description
7 to 4 reserved
3 to 2 DAV_DRV
R/W
drive strength for DAV CMOS output buffer
00
low
01
medium
10
high
11
1 to 0 DATA_DRV
Table 29.
Bit
R/W
very high
drive strength for DATA CMOS output buffer
00
low
01
medium
10
high
11
very high
LVDS DDR output register 1 (address 0021h) bit description
Symbol
Access
DAVI_x2_EN
R/W
Value
Description
7 to 6
5
4 to 3 DAVI
double LVDS current for DAV LVDS buffer
0
disabled
1
enabled
R/W
LVDS current for DAV LVDS buffer
00
3.5 mA
01
4.5 mA
10
1.25 mA
11
2
DATAI_x2_EN
1 to 0 DATAI
Table 30.
Bit
R/W
2.5 mA
double LVDS current for DATA LVDS buffer
0
disabled
1
enabled
R/W
LVDS current for DATA LVDS buffer
00
3.5 mA
01
4.5 mA
10
1.25 mA
11
2.5 mA
LVDS DDR output register 2 (address 0022h) bit description
Symbol
Access Value Description
7 to 4 reserved
3
BIT/BYTE_WISE R/W
DDR mode for LVDS output
0
bit wise (even data bits output on DAV rising edge /
odd data bits output on DAV falling edge)
1
byte wise (MSB data bits output on DAV rising
edge / LSB data bits output on DAV falling edge)
ADC1610S125_1
Objective data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 01 — 28 May 2009
28 of 33
ADC1610S125
NXP Semiconductors
Single 16-bit ADC 125 Msps
Table 30.
Bit
LVDS DDR output register 2 (address 0022h) bit description …continued
Symbol
Access Value Description
2 to 0 LVDS_INTTER
R/W
internal termination for LVDS buffer (DAV and DATA)
000
no internal termination
001
300 Ω
010
180 Ω
011
110 Ω
100
150 Ω
101
100 Ω
110
81 Ω
111
60 Ω
11.7.4 Serial timing interface
SPI timing is shown in Figure 28.
tsu
tsu
th
CS
tw(SCLKL)
th
tw(SCLKH)
tw(SCLK)
SCLK
SDIO
R/W
W1
W0
A12
A11
D2
D1
D0
005aaa065
Fig 28. SPI timing
SPI timing characteristics are detailed in Table 9.
ADC1610S125_1
Objective data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 01 — 28 May 2009
29 of 33
ADC1610S125
NXP Semiconductors
Single 16-bit ADC 125 Msps
12. Package outline
HVQFN40: plastic thermal enhanced very thin quad flat package; no leads;
40 terminals; body 6 x 6 x 0.85 mm
A
B
D
SOT618-1
terminal 1
index area
A
E
A1
c
detail X
C
e1
1/2 e
e
20
y
y1 C
v M C A B
w M C
b
11
L
21
10
e
e2
Eh
1/2 e
1
30
terminal 1
index area
40
31
Dh
X
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A(1)
max.
A1
b
c
D(1)
Dh
E(1)
Eh
e
e1
e2
L
v
w
y
y1
mm
1
0.05
0.00
0.30
0.18
0.2
6.1
5.9
4.25
3.95
6.1
5.9
4.25
3.95
0.5
4.5
4.5
0.5
0.3
0.1
0.05
0.05
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT618-1
---
MO-220
---
EUROPEAN
PROJECTION
ISSUE DATE
01-08-08
02-10-22
Fig 29. Package outline SOT618-1 (HVQFN40)
ADC1610S125_1
Objective data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 01 — 28 May 2009
30 of 33
ADC1610S125
NXP Semiconductors
Single 16-bit ADC 125 Msps
13. Revision history
Table 31.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
ADC1610S125_1
20090528
Objective data sheet
-
-
ADC1610S125_1
Objective data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 01 — 28 May 2009
31 of 33
ADC1610S125
NXP Semiconductors
Single 16-bit ADC 125 Msps
14. Legal information
14.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
14.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
14.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
14.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
15. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
ADC1610S125_1
Objective data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 01 — 28 May 2009
32 of 33
ADC1610S125
NXP Semiconductors
Single 16-bit ADC 125 Msps
16. Contents
1
2
3
4
5
6
6.1
6.2
7
8
9
10
10.1
10.2
10.3
11
11.1
11.1.1
11.1.2
11.1.3
11.1.4
11.2
11.2.1
11.2.2
11.2.3
11.3
11.3.1
11.3.2
11.3.3
11.3.4
11.4
11.4.1
11.4.2
11.4.3
11.4.4
11.5
11.5.1
11.5.2
11.5.3
11.5.4
11.5.5
11.5.6
11.5.7
11.6
11.6.1
11.6.2
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Thermal characteristics. . . . . . . . . . . . . . . . . . . 5
Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
Clock and digital output timing . . . . . . . . . . . . . 9
SPI timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Application information. . . . . . . . . . . . . . . . . . 10
Device control . . . . . . . . . . . . . . . . . . . . . . . . . 10
SPI and PIN control modes . . . . . . . . . . . . . . 10
Operating mode selection. . . . . . . . . . . . . . . . 10
Selecting the output data standard . . . . . . . . . 10
Selecting the output data format. . . . . . . . . . . 11
Analog inputs . . . . . . . . . . . . . . . . . . . . . . . . . 11
Input stage . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Anti-kickback circuitry . . . . . . . . . . . . . . . . . . . 11
Transformer. . . . . . . . . . . . . . . . . . . . . . . . . . . 12
System reference and power management . . 13
Internal/external references . . . . . . . . . . . . . . 13
Gain control . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Common-mode output voltage (VO(cm)) . . . . . 15
Biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Drive modes . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Equivalent input circuit . . . . . . . . . . . . . . . . . . 17
Duty cycle stabilizer . . . . . . . . . . . . . . . . . . . . 17
Clock input divider . . . . . . . . . . . . . . . . . . . . . 18
Digital outputs . . . . . . . . . . . . . . . . . . . . . . . . . 18
Digital output buffers: CMOS mode . . . . . . . . 18
Digital output buffers: LVDS DDR mode . . . . . 18
DAta Valid (DAV) output clock. . . . . . . . . . . . . 19
Out-of-Range (OTR) . . . . . . . . . . . . . . . . . . . . 19
Digital offset . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Test patterns . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Output codes versus input voltage . . . . . . . . . 20
Timings summary . . . . . . . . . . . . . . . . . . . . . . 21
CMOS mode timings. . . . . . . . . . . . . . . . . . . . 21
LVDS DDR mode timing . . . . . . . . . . . . . . . . . 21
11.7
11.7.1
11.7.2
11.7.3
11.7.4
12
13
14
14.1
14.2
14.3
14.4
15
16
Serial Peripheral Interface (SPI). . . . . . . . . . .
Register description . . . . . . . . . . . . . . . . . . . .
Default modes at start-up. . . . . . . . . . . . . . . .
Register allocation map . . . . . . . . . . . . . . . . .
Serial timing interface. . . . . . . . . . . . . . . . . . .
Package outline . . . . . . . . . . . . . . . . . . . . . . . .
Revision history . . . . . . . . . . . . . . . . . . . . . . .
Legal information . . . . . . . . . . . . . . . . . . . . . .
Data sheet status . . . . . . . . . . . . . . . . . . . . . .
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . .
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact information . . . . . . . . . . . . . . . . . . . .
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22
22
23
24
29
30
31
32
32
32
32
32
32
33
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 28 May 2009
Document identifier: ADC1610S125_1
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