TI LMV7231 Lmv7231 hex window comparator with 1.5% precision and 400mv reference Datasheet

LMV7231
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SNOSB45E – FEBRUARY 2010 – REVISED MARCH 2013
LMV7231 Hex Window Comparator with 1.5% Precision and 400mV Reference
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FEATURES
DESCRIPTION
•
The LMV7231 is a 1.5% accurate Hex Window
Comparator which can be used to monitor power
supply voltages. The device uses an internal 400mV
reference for the comparator trip value. The
comparator set points can be set via external resistor
dividers. The LMV7231 has 6 outputs (CO1-CO6)
that signal an under-voltage or over-voltage event for
each power supply input. An output (AO) is also
provided to signal when any of the power supply
inputs have an over-voltage or under-voltage event.
This ability to signal an under-voltage or over-voltage
event for the individual power supply inputs, in
addition to an output to signal such an event on any
of the power supply inputs adds unparalleled system
protection capability.
1
2
•
•
•
•
•
•
•
•
•
(For VS = 3.3V ±10%, Typical Unless Otherwise
Noted)
High Accuracy Voltage Reference: 400 mV
Threshold Accuracy: ±1.5% (max)
Wide Supply Voltage Range +2.2V to +5.5V
Input/Output Voltage Range Above V+
Internal Hysteresis: 6mV
Propagation Delay: 2.6 µs to 5.6 µs
Supply Current 7.7 µA Per Channel
24 Lead WQFN Package
Temperature Range: -40°C to 125°C
APPLICATIONS
•
•
•
•
•
The LMV7231’s +2.2V to +5.5V power supply voltage
range, low supply current, and input/output voltage
range above V+ make it ideal for a wide range of
power supply monitoring applications. Operation is
ensured over the -40°C to +125°C temperature
range. The device is available in a 24-pin WQFN
package.
Power Supply Voltage Detection
Battery Monitoring
Handheld Instruments
Relay Driving
Industrial Control Systems
Typical Application Circuit
Input = 9V - 42V
R1
115k
VIN
C1
C3
1.0 PF
0.1 PF
VCC
C5
LM25007
ON/OFF
C4
0.1PF
BST
0.01 PF L1 100 PH
R6
C6
121k
2200
pF
SW
RON/SD
D1
RCL
R5
200k
VOUT = 5V
R2
3k
C7
0.01 PF
FB
C2
22 PF
RTN
R3
3k
V+ = 3.3V
C8
COPOL
V+
Controller
(FPGA)
0.1 PF
+
-
*
*
CO1
+IN1
R8
10
+
V+
R11
10k
R7
1.15k
Ch. 1
R10
10k
COPOL
UV1 OV1
CO6
C9
*optional
-IN1
R9
95.3
REF
Ch. 6
+IN6
-IN6
UV6 OV6
AOSEL
OV1
OV2
OV3
OV4
OV5
OV6
V+ R12
10k
AO
*
UV1
UV2
UV3
UV4
UV5
UV6
* Open
Drain
RESERVED
REF
REF
REF
LMV7231
GND
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010–2013, Texas Instruments Incorporated
LMV7231
SNOSB45E – FEBRUARY 2010 – REVISED MARCH 2013
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1) (2)
ESD Tolerance (3)
Human Body Model
2000V
Machine Model
200V
Supply Voltage
6V
6V to (GND − 0.3V)
Voltage at Input/Output Pin
Output Current
10mA
Total Package Current
50mA
−65°C to +150°C
Storage Temp Range
Junction Temperature (4)
150°C
For soldering specifications: http://www.ti.com/lit/SNOA549
(1)
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test
conditions, see the Electrical Characteristics.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of
JEDEC) Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC).
The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is
PD = (TJ(MAX) - TA) / θJA. All numbers apply for packages soldered directly onto a PC board.
(2)
(3)
(4)
Operating Ratings (1)
Supply Voltage
2.2V to 5.5V
Junction Temperature Range
(2)
Package Thermal Resistance, θJA
(1)
−40°C to +125°C
24 Lead WQFN
38°C/W
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test
conditions, see the Electrical Characteristics.
The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is
PD = (TJ(MAX) - TA) / θJA. All numbers apply for packages soldered directly onto a PC board.
(2)
+3.3V Electrical Characteristics
Unless otherwise specified, all limits ensured for TA = 25°C, V+ = 3.3V ±10%, GND = 0V, and RL > 1MΩ. Boldface limits
apply for TA = –10°C to +70°C.
Symbol
Parameter
Condition
Min (1)
Typ (2)
Max (1)ns
Units
400
406
408.6
mV
394
401
403.2
mV
VTHR
Threshold: Input Rising
RL = 10kΩ
394
391.4
VTHF
Threshold: Input Falling
RL = 10kΩ
386
383.8
VHYST
Hysteresis (VTHR − VTHF)
RL = 10kΩ
3.9
6.0
8.8
mV
–5
–15
0.05
5
15
nA
160
200
250
mV
0.4
1
μA
IBIAS
Input Bias Current
VIN = V+, GND, and 5.5V
VOL
Output Low Voltage
IL = 5mA
IOFF
Output Leakage Current
VOUT = V+, 5.5V and
40mV of overdrive
tPDHL1
High-to-Low Propagation Delay (+IN
falling)
10mV of overdrive
tPDHL2
High-to-Low Propagation Delay (-IN
rising)
10mV of overdrive
(1)
(2)
2
2.6
6
5.4
10
μs
μs
Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlations using the
Statistical Quality Control (SQC) method.
Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
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+3.3V Electrical Characteristics (continued)
Unless otherwise specified, all limits ensured for TA = 25°C, V+ = 3.3V ±10%, GND = 0V, and RL > 1MΩ. Boldface limits
apply for TA = –10°C to +70°C.
Symbol
Parameter
Min (1)
Condition
tPDLH1
Low-to-High Propagation Delay (+IN
rising)
10mV of overdrive
tPDLH2
Low-to-High Propagation Delay (-IN
falling)
10mV of overdrive
tr
Output Rise Time
CL= 10pF, RL= 10kΩ
tf
Output Fall Time
CL = 100pF, RL = 10kΩ
IIN(1)
Typ (2)
Max (1)ns
5.6
10
2.8
6
Units
μs
μs
μs
0.5
0.25
0.3
μs
Digital Input Logic “1” Leakage Current
0.2
1
μA
IIN(0)
Digital Input Logic “0” Leakage Current
0.2
1
μA
VIH
Digital Input Logic “1” Voltage
VIL
Digital Input Logic “0” Voltage
IS
Power Supply Current
VTHPSS
(3)
0.70 × V+
V
46
No loading (outputs high)
V+ Ramp Rate = 1.1ms
V+ Step = 2.5V to 4.5V
VTH Power Supply Sensitivity (3)
0.30 × V+
V
60
84
μA
+400
V+ Ramp Rate = 1.1ms
V+ Step = 4.5V to 2.5V
–400
μV
μV
VTH Power Supply Sensitivity is defined as the temporary shift in the internal voltage reference due to a step on the V+ pin.
CO5
CO4
CO3
CO2
CO1
V+
CONNECTION DIAGRAM
-IN1
CO6
+IN1
AO
-IN2
AOSEL
LMV7231
+IN2
COPOL
+IN6
-IN6
+IN5
-IN5
RESERVED
-IN4
GND
+IN3
+IN4
-IN3
Figure 1. 24-Pin WQFN Package (Top View)
See Package RTW0024A
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PIN DESCRIPTIONS
Pin
4
Symbol
Type
1
-IN1
Analog Input
Negative input for window comparator 1.
2
+IN1
Analog Input
Positive input for window comparator 1.
3
-IN2
Analog Input
Negative input for window comparator 2.
4
+IN2
Analog Input
Positive input for window comparator 2.
5
-IN3
Analog Input
Negative input for window comparator 3.
6
+IN3
Analog Input
Positive input for window comparator 3.
7
-IN4
Analog Input
Negative input for window comparator 4.
8
+IN4
Analog Input
Positive input for window comparator 4.
9
-IN5
Analog Input
Negative input for window comparator 5.
10
+IN5
Analog Input
Positive input for window comparator 5.
11
-IN6
Analog Input
Negative input for window comparator 6.
12
+IN6
Analog Input
Positive input for window comparator 6.
13
RESERVED
Digital Input
Connect to GND.
14
GND
Power
15
COPOL
Digital Input
The state of this pin determines whether the CO1-CO6 pins are active
“HIGH” or “LOW”. When tied LOW the CO1-CO6 outputs will go LOW to
indicate an out of window comparison.
16
AOSEL
Digital Input
The state of this pin determines whether the AO pin is active on an overvoltage or under-voltage event. When tied LOW the AO output will be
active upon an over-voltage event.
17
AO
Open-Drain NMOS
Digital Output
This output is the ANDED combination of either the over-voltage
comparator outputs or the under-voltage comparator outputs and is
controlled by the state of the AOSEL. AO pin is active “LOW”.
18
CO6
Open-Drain NMOS
Digital Output
Window comparator 6 NMOS open-drain output.
19
CO5
Open-Drain NMOS
Digital Output
Window comparator 5 NMOS open-drain output.
20
CO4
Open-Drain NMOS
Digital Output
Window comparator 4 NMOS open-drain output.
21
CO3
Open-Drain NMOS
Digital Output
Window comparator 3 NMOS open-drain output.
22
CO2
Open-Drain NMOS
Digital Output
Window comparator 2 NMOS open-drain output.
23
CO1
Open-Drain NMOS
Digital Output
Window comparator 1 NMOS open-drain output.
24
V+
Power
DAP
DAP
Thermal Pad
Description
Ground reference pin for the power supply voltage.
Power supply pin.
Die Attach Paddle (DAP) connect to GND.
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Block Diagram
COPOL
*
+ IN1
+
-
*
+
-
+ IN2
+
A
*
OV1
-IN2
-
+IN3
+
CO3
*
B
*
UV2
+
CO2
*
Ref
- IN1
CO1
*
UV1
B
CO4
*
*
A
OV 2
B
UV 3
A
OV 3
CO5
*
*
CO6
*
+
-IN3
OV1
-
AOSEL
OV 2
+IN4
+
B
UV4
-
OV 3
OV 4
OV 5
OV6
+
- IN4
-
+IN5
+
A
AO
OV4
*
UV1
UV2
B
UV5
UV3
* Open
Drain
UV4
-
UV5
+
-IN5
-
+IN6
+
A
OV 5
B
UV6
A
OV6
UV6
+
- IN6
-
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Typical Performance Characteristics
V+ = 3.3V and TA =25°C unless otherwise noted.
−In Input Rising Threshold Distribution
RELATIVE FREQUENCY (%)
RELATIVE FREQUENCY (%)
+In Input Rising Threshold Distribution
40
35
30
25
20
15
10
5
0
396 397 398 399 400 401 402 403 404
40
35
30
25
20
15
10
5
0
396 397 398 399 400 401 402 403 404
INPUT RISING THRESHOLD (mV)
Figure 2.
Figure 3.
+In Input Falling Threshold Distribution
−In Input Falling Threshold Distribution
RELATIVE FREQUENCY (%)
RELATIVE FREQUENCY (%)
INPUT RISING THRESHOLD (mV)
40
35
30
25
20
15
10
5
0
390 391 392 393 394 395 396 397 398
40
35
30
25
20
15
10
5
0
390 391 392 393 394 395 396 397 398
INPUT FALLING THRESHOLD (mV)
Figure 4.
Figure 5.
+In Hysteresis Distribution
−In Hysteresis Distribution
RELATIVE FREQUENCY (%)
RELATIVE FREQUENCY (%)
INPUT FALLING THRESHOLD (mV)
50
45
40
35
30
25
20
15
10
5
0
4.0
4.5
5.0
5.5
6.0
6.5
7.0
7.5
8.0
4.0
HYSTERESIS (mV)
4.5
5.0
5.5
6.0
6.5
7.0
7.5
8.0
HYSTERESIS (mV)
Figure 6.
6
50
45
40
35
30
25
20
15
10
5
0
Figure 7.
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Typical Performance Characteristics (continued)
+
V = 3.3V and TA =25°C unless otherwise noted.
405
404
403
402
401
400
399
398
397
396
395
Input Rising Threshold Voltage
vs.
Supply Voltage
INPUT RISING THRESHOLD VOLTAGE (mV)
INPUT RISING THRESHOLD VOLTAGE (mV)
Input Rising Threshold Voltage
vs.
Temperature
+IN
-IN
-40 -20
0
20
40
60
80 100 120
405
404
403
402
401
400
399
398
397
396
395
+IN
-IN
2
4
5
6
SUPPLY VOLTAGE (V)
Figure 9.
Input Falling Threshold Voltage
vs.
Temperature
Input Falling Threshold Voltage
vs.
Supply Voltage
400
399
398
397
396
395
394
393
392
391
390
-IN
+IN
-40 -20
0
20
40
60
80 100 120
400
399
398
397
396
395
394
393
392
391
390
-IN
+IN
2
-40 -20
5
Figure 11.
Hysteresis
vs.
Temperature
Hysteresis
vs.
Supply Voltage
20
6
+IN
HYSTERESIS (mV)
-IN
0
4
Figure 10.
+IN
10
9
8
7
6
5
4
3
2
1
0
3
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
HYSTERESIS (mV)
3
Figure 8.
INPUT FALLING THRESHOLD VOLTAGE (mV)
INPUT FALLING THRESHOLD VOLTAGE (mV)
TEMPERATURE (°C)
40
60
80 100 120
10
9
8
7
6
5
4
3
2
1
0
-IN
2
3
4
5
6
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
Figure 12.
Figure 13.
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Typical Performance Characteristics (continued)
+
V = 3.3V and TA =25°C unless otherwise noted.
Supply Current
vs.
Supply Voltage and Temperature
Supply Current
vs.
Output Sink Current
50
125°C
85°C
50
SUPPLY CURRENT (PA)
SUPPLY CURRENT (éA)
TA = 25°C
49
60
25°C
40
30
-40°C
20
10
0
48
47
46
5.5V
45
44
3.3V
43
42
41
1
2
3
4
5
2.2V
40
0
6
1
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (PA)
SUPPLY CURRENT (PA)
5.5V
3.3V
2.2V
32
31
53
10
5.5V
51
3.3V
50
49
2.2V
48
47
46
1
2
3
4
5
6
7
8
9
45
0
10
1
2
3
4
5
6
7
8
9
10
OUTPUT SINK CURRENT (mA)
Figure 16.
Figure 17.
Supply Current
vs.
Output Sink Current
Bias Current
vs.
Input Voltage
60
5
TA = 125°C
-40°C
+IN, -IN
58
0
BIAS CURRENT (nA)
SUPPLY CURRENT (PA)
9
52
OUTPUT SINK CURRENT (mA)
5.5V
56
3.3V
55
54
53
2.2V
52
85°C
+IN, -IN
-5
-10
25°C
+IN, -IN
-15
25°C
+IN, -IN
51
1
2
3
4
5
6
7
8
9
-20
-0.3
10
OUTPUT SINK CURRENT (mA)
-0.2
-0.1
INPUT VOLTAGE (V)
Figure 18.
8
8
TA = 85°C
54
33
50
0
7
55
TA = -40°C
34
57
6
Supply Current
vs.
Output Sink Current
35
59
5
Supply Current
vs.
Output Sink Current
36
30
0
4
Figure 15.
38
37
3
Figure 14.
40
39
2
OUTPUT SINK CURRENT (mA)
Figure 19.
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Typical Performance Characteristics (continued)
+
V = 3.3V and TA =25°C unless otherwise noted.
Bias Current
vs.
Input Voltage
Bias Current
vs.
Input Voltage
0.4
2.0
125°C -IN
BIAS CURRENT (nA)
BIAS CURRENT (nA)
1.6
0.3
25°C -IN
0.2
-40°C -IN
0.1
25°C +IN
125°C +IN
1.2
0.8
85°C -IN
0.4
-40°C +IN
0.0
0.0
0.6
1.2
1.8
2.4
3.0
0.0
0.0
3.6
85°C +IN
0.6
1.2
INPUT VOLTAGE (V)
Figure 21.
Output Voltage Low
vs.
Output Sink Current
Output Voltage Low
vs.
Output Sink Current
OUTPUT VOLTAGE LOW (mV)
OUTPUT VOLTAGE LOW (mV)
TA = 85°C
300
250
V+ = 3.3V
200
150
100
V+ = 5.5V
50
2
4
6
V+ = 2.2V
500
400
V+ = 3.3V
300
200
100
V+ = 5.5V
8
0
0
10
OUTPUT SINK CURRENT (mA)
2
4
6
8
10
OUTPUT SINK CURRENT (mA)
Figure 22.
Figure 23.
Output Voltage Low
vs.
Output Sink Current
Output Voltage Low
vs.
Output Sink Current
350
700
TA = 125°C
300
OUTPUT VOLTAGE LOW (mV)
TA = -40°C
OUTPUT VOLTAGE LOW (mV)
3.6
600
TA = 25°C
350
V+ = 2.2V
250
200
V+ = 3.3V
150
100
50
600
V+ = 2.2V
500
400
V+ = 3.3V
300
200
100
V+ = 5.5V
0
0
3.0
Figure 20.
V+ = 2.2V
0
0
2.4
INPUT VOLTAGE (V)
450
400
1.8
2
4
6
V+ = 5.5V
8
0
0
10
OUTPUT SINK CURRENT (mA)
2
4
6
8
10
OUTPUT SINK CURRENT (mA)
Figure 24.
Figure 25.
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Typical Performance Characteristics (continued)
+
V = 3.3V and TA =25°C unless otherwise noted.
Output Short Circuit Current
vs.
Output Voltage
TA = 25°C
80
V+ = 5.5V
60
40
V+ = 3.3V
20
V+ = 2.2V
0
0
1
2
4
5
70
OUTPUT SHORT CIRCUIT CURRENT (mA)
OUTPUT SHORT CIRCUIT CURRENT (mA)
100
Output Short Circuit Current
vs.
Output Voltage
V+ = 3.3V
60
25°C
50
40
30
85°C
20
125°C
10
0
0
6
1
1
OUTPUT VOLTAGE (V)
3
Figure 26.
Figure 27.
Propagation Delay
vs.
Input Overdrive
Rise and Fall Times
vs.
Output Pull-Up Resistor
1e2
V+ = 3.3V
CL = 10 pF
LH +IN
20
HL -IN
10
HL +IN
LH -IN
RISE
TA = 25°C
1e1
RISE AND FALL TIME (PA)
PROPAGATION DELAY (és)
2
OUTPUT VOLTAGE (V)
40
30
-40°C
1
1e-1
FALL
1e-2
0
0
1e-3
1e-1
10 20 30 40 50 60 70 80 90 100
INPUT OVERDRIVE (mV)
VOUT when
+IN = V+
-IN = VIN
2V/DIV
DC
1e2
1e3
Figure 29.
Propagation Delay
Output Leakage Current
vs.
Output Voltage
tPDHL1
tPDLH1
tPDLH2
tPDHL2
VIN
10 mV/DIV
AC
RL = 10 k:
CL = 10 pF
10 mV OF OVERDRIVE
V+ = 3.3V
10
25°C
1
-40°C
0.1
0.01
0
4 Ps/DIV
1
2
4
5
6
OUTPUT VOLTAGE (V)
Figure 30.
10
1e1
Figure 28.
OUTPUT LEAKAGE CURRENT (pA)
VOUT when
+IN = VIN
-IN = GND
2V/DIV
DC
1
OUTPUT PULL-UP RESISTOR (k:)
Figure 31.
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Typical Performance Characteristics (continued)
+
V = 3.3V and TA =25°C unless otherwise noted.
OITPUT LEAKAGE CURRENT (nA)
Output Leakage Current
vs.
Output Voltage
125°C
V+ = 3.3V
10
1
85°C
0.1
0.01
0
1
2
4
5
6
OUTPUT VOLTAGE (V)
Figure 32.
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APPLICATION INFORMATION
3 RESISTOR VOLTAGE DIVIDER SELECTION
The LMV7231 trip points can be set by external resistor dividers as shown in Figure 33
V+
VIN
0.1 PF
COPOL
R1
Ch. 1
+
-
+IN1
*
*
R2
10k
CO1
VOUT
+
-
-IN1
R3
REF
COPOL
OV1 UV1
Ch. 6
+IN6
CO6
-IN6
REF
REF
REF
LMV7231
OV6 UV6
AOSEL
OV1
OV2
OV3
OV4
OV5
OV6
AO
*
UV1
UV2
UV3
UV4
UV5
UV6
GND
10k
* Open
Drain
RESERVED
Figure 33. External Resistor Dividers
Each trip point, over-voltage, VOV, and under-voltage, VUV, can be optimized for a falling supply, VTHF, or a rising
supply, VTHR. Therefore there are 22 = 4 different optimization cases. Exiting the voltage detection window
(Figure 34), rising into and out of the window (Figure 35), entering the window (Figure 36), falling into and out of
the window (Figure 37). Note that for each case each trip point can be optimized for either a rising or falling
signal, not both. The governing equations make it such that if the same resistor, R3, and over/under-voltage
ratio, VOV/VUV, is used across the channels the same nominal current will travel through the resistor ladder. As a
result R2 will also be the same across channels and only R1 needs to change to set voltage detection window
maximizing reuse of resistor values and minimizing design complexity. Select the R3 resistor value to be below
100kΩ so the current through the divider ladder is much greater than the LMV7231 bias current. If the current
traveling through the resistor divider is on the same magnitude of the LMV7231 IBIAS, the IBIAS current will create
error in your circuit and cause trip voltage shifts. Keep in mind the greatest error due to IBIAS will be caused when
that current passes through the greatest equivalent resistance, REQ = R1‖(R2+R3), which will be seen by the
positive input of the window comparator, +IN.
12
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VUV
VOV
VUV
VOUT
VOV
VOUT
VIN
VIN
R3 set
R3 set
R2 = R3((VTHF/VTHR)VOV/VUV ± 1)
R2 = R3(VOV/VUV ± 1)
R1 = R3((1/VTHR)VOV - (VTHF/VTHR)VOV/VUV)
R1 = R3((1/VTHR)VOV - VOV/VUV)
Ex. VOV = 3.465V, VUV = 3.135V, i.e. VRANGE = 3.3V +/- 5%
Ex. VOV = 3.465V, VUV = 3.135V, i.e. VRANGE = 3.3V +/- 5%
R3 set to 10 k5
R3 set to 10 k5
R2 = 10k((0.394/0.4)3.465/3.135 ± 1)
8875
R1 = 10k((1/0.4)3.465 - (0.394/0.4)3.465/3.135)
R2 = 10k((3.465/3.135) ± 1)
75 k5
R1 = 10k((1/0.4)3.465 ± 3.465/3.135)
Figure 34. Exiting the Voltage Detection Window
VUV
1.05 k5
Figure 35. Rising Into and Out Of the Voltage
Detection Window
VOV
VUV
VOUT
75 k5
VOV
VOUT
VIN
VIN
R3 set
R3 set
R2 = R3((VTHR/VTHF)VOV/VUV ± 1)
R2 = R3(VOV/VUV ± 1)
R1 = R3((1/VTHF)VOV - (VTHR/VTHF)VOV/VUV)
R1 = R3((1/VTHF)VOV - VOV/VUV)
Ex. VOV = 3.465V, VUV = 3.135V, i.e. VRANGE = 3.3V +/- 5%
Ex. VOV = 3.465V, VUV = 3.135V, i.e. VRANGE = 3.3V +/- 5%
R3 set to 10 k5
R3 set to 10 k5
R2 = 10k((0.4/0.394)3.465/3.135 ± 1)
1.21 k5
R1 = 10k((1/0.394)3.465 - (0.4/0.394)3.465/3.135)
R2 = 10k((3.465/3.135) ± 1)
76.8 k5
1.05 k5
R1 = 10k((1/0.394)3.465 ± 3.465/3.135)
Figure 36. Entering the Voltage Detection Window
76.8 k5
Figure 37. Falling Into and Out Of the Voltage
Detection Window
INPUT/OUTPUT VOLTAGE RANGE ABOVE V+
The LMV7231 Hex Window Comparator with 1.5% precision can accurately monitor up to 6 power rails or
batteries at one time. The input and output voltages of the device can exceed the supply voltage, V+, of the
comparator, and can be up to the absolute maximum ratings without causing damage or performance
degradation. The typical µC input pin with crowbar diode ESD protection circuitry will not allow the input to go
above V+, and thus its usefulness is limited in power supply supervision applications.
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The supply independent inputs of the window comparator blocks allow the LMV7231 to be tolerant of system
faults. For example if the power is suddenly removed from the LMV7231 due to a system malfunction yet there
still exists a voltage on the input, this will not be an issue as long as the monitored input voltage does not exceed
absolute maximum ratings. Another example where this feature comes in handy is a battery sense application
such as the one in Figure 38. The boards may be sitting on the shelf unbiased with V+ grounded, and yet have a
fully charged battery on board. If the comparator measuring the battery had crowbar diodes, the diode from –IN
to V+ would turn on, sourcing current from the battery eventually draining the battery. However, when using the
LMV7231 no current, except the low input bias current of the device, will flow into the chip, and the battery
charge will be preserved.
V+ = 3.3V
R1
499k
R2
1M
+
-
VBATT
VOUT
R3
3.01k
Figure 38. Battery Sense Application
The output pin voltages of the device can also exceed the supply voltage, V+, of the comparator. This provides
extra flexibility and enables designs which pull up the outputs to higher voltage levels to meet system
requirements. For example it’s possible to run the LMV7231 at its minimum operating voltage, V+ = +2.2V, but
pull up the output up to the absolute maximum ratings to bias a blue LED, with a forward voltage of VF = +4V.
In a power supply supervision application the hardwired LMV7231 is a sound solution compared to the uC with
software alternative for several reasons. First, startup is faster. During startup you don’t need to account for code
loading time, oscillator ramp time, and reset time. Second, operation is quick. The LMV7231 has a maximum
propagation delay in the µs and isn’t affected by sampling and conversion delays related to reading data,
calculating data, and setting flags. Third, less overhead. The LMV7231 doesn’t require an expensive power
consuming microcontroller nor is it dependent on controller code which could get damaged or crash.
POWER SUPPLY BYPASSING
Bypass the supply pin, V+, with a 0.1 μF ceramic capacitor placed close to the V+ pin. If transients with rise/fall
times of 100’s μs and magnitudes of 100’s mV are expected on the power supply line a RC low pass filter
network as shown in Figure 39 is recommended for additional bypassing. If no such bypass network is used
power supply transients can cause the internal voltage reference of the comparator to temporarily shift potentially
resulting in a brief incorrect comparator output. For example if an RC network with 100Ω resistance and 10μF
capacitance (1.1ms rise time) is used the voltage reference will shift temporarily the amount, VTH Power Supply
Sensitivity (VTHPSS), specified in the Electrical Characteristics table.
R1
VSUPPLY 100
C1
10 PF
C2
0.1 PF
V+
LMV7231
Figure 39. Power Supply Bypassing
POWER SUPPLY SUPERVISION
Figure 40 shows a power supply supervision circuit utilizing the LMV7231. This application uses the efficient,
easy to use LM25007 step-down switching regulator. This switching regulator can handle a 9V – 42V input
voltage range and it’s regulated output voltage is set to 5V with R2 = R3 = 3kΩ.
VOUT = 2.5 x (R2 + R3)/R3
= 2.5 x (3k + 3k)/3k = 5V
14
(1)
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Resistor R6 and capacitors C6, C7 are utilized to minimize output ripple voltage per the LM25007 evaluation
board application note.
The comparator voltage window is set to 5V +/- 5% by R7=1.15kΩ , R8=10Ω, R9=95.3Ω. See 3 RESISTOR
VOLTAGE DIVIDER SELECTION section in the Application Information section of the datasheet for details on
how to set the comparator voltage window.
With components selected the output ripple voltage seen on the LM25007 is approximately 30 - 35mV and is
reduced to about 4mV at the comparator input, +IN1, by the resistor divider. This ripple voltage can be reduced
multiple ways. First, user can operate the device in continuous conduction mode rather than discontinuous
conduction mode. To do this increase the load current of the device (see LM25007 datasheet for more details).
However, make sure not to exceed the power rating of the resistors in the resistor ladder. Second, ripple can be
reduced further with a bypass cap, C9, at the resistor divider. If desired a user can select a 1uF capacitor to
achieve less than 3mV ripple at +IN1. However, there is a tradeoff and adding capacitance at this node will lower
the system response time.
Input = 9V - 42V
VIN
C1
R1
115k
VCC
BST
1.0 PF
0.1 PF
0.01 PF L1 100 PH
C5
LM25007
ON/OFF
C4
0.1PF
C3
R6
C6
121k
2200
pF
SW
RON/SD
D1
RCL
R5
200k
VOUT = 5V
R2
3k
C7
0.01 PF
FB
C2
22 PF
RTN
R3
3k
V+ = 3.3V
C8
COPOL
V+
Controller
(FPGA)
0.1 PF
+
-
*
*
CO1
+IN1
R8
10
+
V+
R11
10k
R7
1.15k
Ch. 1
R10
10k
COPOL
UV1 OV1
C9
*optional
-IN1
R9
95.3
REF
CO6
Ch. 6
+IN6
-IN6
UV6 OV6
AOSEL
OV1
OV2
OV3
OV4
OV5
OV6
V+ R12
10k
AO
*
UV1
UV2
UV3
UV4
UV5
UV6
* Open
Drain
RESERVED
REF
REF
REF
LMV7231
GND
Figure 40. Power Supply Supervision
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SNOSB45E – FEBRUARY 2010 – REVISED MARCH 2013
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REVISION HISTORY
Changes from Revision D (March 2013) to Revision E
•
16
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 15
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PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
LMV7231SQ/NOPB
ACTIVE
WQFN
RTW
24
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
L7231SQ
LMV7231SQE/NOPB
ACTIVE
WQFN
RTW
24
250
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
L7231SQ
LMV7231SQX/NOPB
ACTIVE
WQFN
RTW
24
4500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
L7231SQ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Feb-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
LMV7231SQ/NOPB
WQFN
RTW
24
LMV7231SQE/NOPB
WQFN
RTW
LMV7231SQX/NOPB
WQFN
RTW
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
1000
178.0
12.4
4.3
4.3
1.3
8.0
12.0
Q1
24
250
178.0
12.4
4.3
4.3
1.3
8.0
12.0
Q1
24
4500
330.0
12.4
4.3
4.3
1.3
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Feb-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LMV7231SQ/NOPB
WQFN
RTW
24
1000
210.0
185.0
35.0
LMV7231SQE/NOPB
WQFN
RTW
24
250
210.0
185.0
35.0
LMV7231SQX/NOPB
WQFN
RTW
24
4500
367.0
367.0
35.0
Pack Materials-Page 2
MECHANICAL DATA
RTW0024A
SQA24A (Rev B)
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