AD AD8251 Devices connected Datasheet

Circuit Note
CN-0385
Devices Connected/Referenced
Circuits from the Lab® reference designs are engineered and
tested for quick and easy system integration to help solve today’s
analog, mixed-signal, and RF design challenges. For more
information and/or support, visit www.analog.com/CN0385.
AD4003
18-Bit, 2 MSPS, PulSAR®, 7.0 mW ADC in
MSOP/QFN
AD8251
10 MHz, 20 V/μs, G = 1, 2, 4, 8, iCMOS
Programmable Gain Instrumentation
Amplifier
ADuM141E
Robust, Quad Channel Isolator with
Output Enable and 1 Reverse Channel
ADG5207
High Voltage, Latch-Up Proof, 8-Channel
Differential Multiplexer
AD8475
Precision, Selectable Gain, Fully
Differential Amplifier
ADA4807-2
3.1 nV/√Hz, 1 mA, 180 MHz, Rail-to-Rail
Input/Output Dual Op Amp
Isolated, Multichannel Data Acquisition System with PGIA for Single-Ended and
Differential Industrial Level Signals
EVALUATION AND DESIGN SUPPORT
Circuit Evaluation Boards
CN-0385 Circuit Evaluation Board (EVAL-CN0385-FMCZ)
System Demonstration Platform (EVAL-SDP-CH1Z)
Design and Integration Files
Schematics, Layout Files, Bill of Materials
CIRCUIT FUNCTION AND BENEFITS
The circuit shown in Figure 1 is a cost effective, isolated, multichannel data acquisition system that is compatible with standard
industrial signal levels. The components are specifically selected
to optimize settling time between samples, providing 18-bit
performance at channel switching rates up to approximately
750 kHz.
The circuit can process eight gain-independent channels and is
compatible with both single-ended and differential input signals.
The analog front end includes a multiplexer, programmable
gain instrumentation amplifier (PGIA); precision analog-todigital converter (ADC) driver for performing the single-ended
to differential conversion; and an 18-bit, 2.0 MSPS precision
PulSAR® ADC for sampling the signal on the active channel.
Gain configurations of 0.4, 0.8, 1.6, and 3.2 are available.
The maximum sample rate of the system is 2 MSPS in turbo mode,
and 1.5 MSPS in normal mode. The channel switching logic is
synchronous to the ADC conversions, and the maximum channel
switching rate is 1.5 MHz. A single channel can be sampled at
up to 2 MSPS with 18-bit resolution in turbo mode. Channel
switching rates up to 750 kHz also provide 18-bit performance.
Rev. 0
Circuits from the Lab® reference designs from Analog Devices have been designed and built by Analog
Devices engineers. Standard engineering practices have been employed in the design and construction
of each circuit, and their function and performance have been tested and verified in a lab environment
at room temperature. However, you are solely responsible for testing the circuit and determining its
suitability and applicability for your use and application. Accordingly, in no event shall Analog Devices
be liable for direct, indirect, special, incidental, consequential or punitive damages due to any cause
whatsoeverconnectedtotheuseofanyCircuitsfromtheLabcircuits. (Continuedonlastpage)
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2016 Analog Devices, Inc. All rights reserved.
CN-0385
Circuit Note
5V
2.2µF
+15V
ADR4540
NC1
VIN
NC3
GND
TP
NC7
VOUT
NC5
+5V
5V
C0+
C0–
–IN +
–
+
100Ω
DB
OUT
REF
–
+IN +
LOGIC
100pF
1.8V
3.3V 5.5V
–V S DGND WR A1 A0
1-OF-8
DECODER
–15V
1kΩ
–
+
1kΩ
CS
OUT+
120pF
200Ω
OUT–
200Ω
120pF
REF VDD VIO SDI
+IN
AD4003 SCK
–IN
SDO
GND CNV
FMC
SDI
SCK
SDO
CNV
ADuM141E
+16V
+15V
–5V
5.5V
ADP7118
ADP5070
SDI
SCK
SDO
CS
CPLD
–15V
ADP2441
10µF
+VS
–IN_0.4 1.25kΩ
1.25kΩ
–IN_0.8
VCOM
+IN_0.8
+IN_0.4
1.25kΩ
1.25kΩ
–V S
12V
3.3V
ADuM3470
0.1µF
AD8475
100pF
100pF
100Ω
4.99kΩ
AD8251
+VS
–
VSS
C7–
DA
100pF
100Ω
+
–
+5V
100Ω
A0
A1
A2
EN
GND
C7+
1/2
ADA4807-2
4.99kΩ
2.2µF
1/2
ADA4807-2
+15V
VDD ADG5207
–
+
ADP7182
–15V
–16V
3.3V
5.5V
ADP7118
ADP7118
5.5V
ADP7118
15142-001
5V
1.8V
Figure 1. Isolated Multichannel Data Acquisition Simplified Circuit (All Connections and Decoupling Not Shown)
CIRCUIT DESCRIPTION
The circuit shown in Figure 1 is an isolated multichannel data
acquisition signal chain consisting of a multiplexer, programmable
gain stage, ADC driver, and a fully differential, precision, successive
approximation register (SAR) ADC. The channel switching and
gain switching is synchronized to the conversion period of the
ADC.
The system can monitor up to eight channels using a single ADC,
reducing component count and cost compared to systems with
one ADC per channel. Each channel can be configured with
a different gain, allowing for flexibility of input ranges. It is
manipulated by the complex programmable logic device (CPLD)
which can be configured in the Labview graphical user interface
(GUI). The effective sample rate for each channel is equal to the
sample rate of the ADC divided by the total number of channels
being sampled.
The maximum sample rate of the system is limited by the settling
time of the components (such as the programmable gain amplifier
(PGA) bandwidth and RC filter bandwidth) in the analog front
end and the isolated digital interface clock rate which runs at
75 MHz. Multiplexed signals are discontinuous in nature, resulting
in potentially large voltage steps between sampling intervals.
The components in the signal chain must be given adequate time
to settle to these steps before the ADC performs a conversion.
To maximize the time given for the signal to settle, the multiplexer
channels are switched immediately after the ADC begins a new
conversion.
The board power supply can take a dc input from 5 V to 12 V
at the dc jack or 12 V from the SDP-H1 controller board. The
ADP2441 dc-to-dc converter generates 3.3 V for the digital
interface and the ADuM3470 primary supply input. The
ADP5070, ADP7118, and ADP7182 are used to generate
positive and negative ±15 V supplies. The ADP7118 is used to
generate 5 V, 3.3 V, and 1.8 V for the analog and digital power
supplies. The ADuM141E is selected for isolated high speed SPI
communication. It has 150 Mbps maximum data rate, low
propagation delay, and low dynamic power consumption.
Component Selection
The ADG5207 is a high voltage, latch-up proof, 8-channel
differential multiplexer. The ultralow capacitance and charge
injection of these switches make them ideal solutions for data
acquisition and sample-and-hold applications, where low glitch
and fast settling are required. A switching network at the inputs
of the ADG5207 adds compatibility with both single-ended and
differential input signals. The active channel is selected via the
address pins of the device, which are controlled by the CPLD,
and which can be configured in the GUI.
The AD8251 is a programmable gain instrumentation amplifier
that provides selectable gain settings of 1, 2, 4, and 8. The higher
gain settings boost smaller input signals to the full-scale input
range of the AD4003. Each gain setting has its own suitable
input range, which is shown in Table 1.
Table 1. Input Range for Each of the Four Gain Configurations
Gain
0.4
0.8
1.6
3.2
Rev. 0 | Page 2 of 13
Full-Scale Input Range
±10.24 V
±5.12 V
±2.56 V
±1.28 V
Circuit Note
CN-0385
The AD8475 funnel amplifier provides high precision attenuation
(0.4×), accurate common-mode level shifting, and single-ended
to differential conversion. Its low output noise spectral density
(10 nV/√Hz) and fast settling time (50 ns to 0.001% for a 2 V
output step) make it well suited to drive the AD4003.
The AD4003 is a fully-differential, 2 MSPS, 18-bit precision SAR
ADC that features a typical signal-to-noise ratio (SNR) of 98 dB
when using a 4.096 V reference. The AD4003 is also low power,
and only consumes approximately 17 mW at full throughput. Its
power consumption scales with throughput, and can operate at
lower sample rates to cut its power use (for example, 0.17 mW
at 100 kSPS).
System DC Accuracy Errors
7
∆εb, MAX = (max(εb,i −
∑ εb , j
j =0
8
) | i = 0, 1, ..., 7)
where εb,i and εb,j are the offset errors for the i and j channels,
respectively.
This offset error match can be found for each of the gain
configurations. Note that offset error can be expressed either in
codes or volts.
Gain Error Measurement
011...111
011...110
011...101
Error in the gain of the system also contributes to overall system
inaccuracy. The ideal transfer function of the AD4003 is shown in
Figure 2, where the −217 and 217 − 1 output codes correspond to
a negative full-scale input voltage (−FS) and a positive full-scale
input voltage (+FS), respectively; however, the combination of
offset error (εb) and gain error (εm) results in a deviation from
this relationship.
100...010
Gain error can be expressed as a percentage error between the
actual system gain and the ideal system gain. The more common
expression is in percent full-scale error (%FS), which is a measure
of the error between the ideal and actual input voltages that
produces the 217 − 1 code.
100...001
100...000
–FSR
–FSR + 1 LSB
–FSR + 0.5 LSB
+FSR – 1 LSB
+FSR – 1.5 LSB
ANALOG INPUT
15142-002
Figure 2 shows the ideal transfer function of the data acquisition
system.
ADC CODE (TWOS COMPLEMENT)
and the average offset error of all of the channels. Offset error
match is calculated using the following equation:
Figure 2. ADC Ideal Transfer Function
Each of the components in the data acquisition signal chain
adds its own offset error and gain error that cause the real
transfer function of the system to deviate from the ideal transfer
function shown in Figure 2. The cumulative effects of these
errors can be measured at a system level by comparing known
dc inputs near zero and full scale at the input to the ADG5207
(RC filter if it is present) and the resulting output codes from
the AD4003 to obtain a system calibration factor.
The ideal full-scale input voltage (VFS, IDEAL) is a function of the
resolution of the ADC (18-bits for the AD4003) and the
accuracy of the reference voltage (VREF). Errors in the voltage
reference translate to gain errors in the ADC. To decouple
reference errors from ADC gain error, VREF is measured using a
precision multimeter. The ideal full-scale input voltage can then
be calculated using
VFS , IDEAL =
217
218
=
2 × VREF , MEAS VREF , MEAS
The actual system gain can be found by calculating the slope of
the linear regression of a group of several input voltages (mLR)
and the resulting output codes:
Offset Error Measurement
YREAL = mLR × VIN
For ideal bipolar, differential ADCs, a 0 V differential input
results in an output code of 0. Real ADCs typically exhibit some
offset error (εb), which is defined as the deviation between the
ideal output code and the measured output code for a 0 V input.
The offset error for the data acquisition system can be found by
grounding its input and observing the resulting output code. This
error varies between each of the gain settings of the AD8251 and
between each of the channels of the ADG5207. Offset error is
therefore measured for each of the channels in all four gain
configurations.
Because the system monitors multiple channels, it is also important
to quantify the amount by which the offset error deviates between
channels. Offset error match (Δεb, MAX) is a measure of the maximum deviation between the offset error of each of the channels
The real full-scale input voltage (VFS, REAL) can then be calculated
using
VFS , REAL =
YREAL
217
=
mLR
mLR
The gain error (expressed in %FS error) can then be calculated
using
εm =
VFS , IDEAL − VFS , REAL
VFS , IDEAL
× 100%
The gain error of the system varies with the gain of the AD8251,
but is channel independent. Therefore, gain error is measured
for each of the four gain configurations, but only using one of
the ADG5207 channels in this system.
Rev. 0 | Page 3 of 13
CN-0385
Circuit Note
System Noise Analysis
Noise Due to the AD8475 Funnel Amplifier
One of the key design goals in precision data acquisition
systems is achieving a high SNR, which can be achieved by
increasing the full-scale signal amplitude and/or by decreasing
the noise power generated by the components in the system.
The rms noise contributed by the AD8475 (vn, AD8475) is a function
of its referred to output noise spectral density (NSD) (eAD8475) and
the RC filter bandwidth at the input to the AD4003 (BWRC):
The total noise power present in the system can be found by
taking the root sum square (rss) of the noise power contributed
by its individual components, referred to the input of the
AD4003:
v n, TOTAL = v n, ADG 5207 2 + v n, AD82512 + v n, AD8475 2 + v n, AD4003 2
The expected SNR of the system (SNREXPECTED) can then be
found using
 VREF 2 

SNREXPECTED = 20 log 
 vn, TOTAL 


where eAD8475 = 10 nV/√Hz.
Noise Due to the AD8251 Instrumentation Amplifier
The AD8251 functions as a gain stage that improves SNR for
small amplitude signals by boosting their amplitude to more
closely fill the ±VREF range at the input to the AD4003. Ideally, if
the system gain increases by a factor of G, the SNR (in dB) of
the input signal improves by
This level of improvement is not achievable in reality, however,
because wideband noise is also amplified by the noise gain of
the circuit. Fortunately, this degradation is not as large as the
improvement due to signal gain.
Noise Due to the AD4003 ADC
The noise of the AD4003 ADC is a function of both its inherent
quantization error and noise caused by internal components
(such as passive components producing thermal noise).
The rms input voltage noise of the AD4003 can be calculated
from its specified SNR using


VREF
× 10 
2
π
× BWRC
2
ΔSNR = log10(G)
The expected noise contributions for each component in the
system and the resulting expected SNR performance of the
whole system is shown in Table 2. The total system noise
calculation ignores thermal noise contributed by the passive
components in the system.
v n, AD4003 =
v n, AD8475 = e AD8475 ×
The rms noise contributed by the AD8251 is a function of its
referred to input NSD (eAD8251), its gain setting (GAD8251), the
attenuation factor of the AD8475 (GAD8475), and the noise filter
bandwidth at the input of the AD4003:
v n, AD 8251 = e AD8251 × G AD 8251 × G AD8475 ×
π
× BWRC
2
The value of eAD8251 is also dependent on the AD8251 gain; the
value of eAD8251 can be found in the AD8251 data sheet.
SNR AD 4003 

20

Noise Due to the ADG5207 Multiplexer
The SNR for the AD4003 (SNRAD4003) is specified as approximately
98 dB for a 4.096 V reference.
The single-pole RC filter at the input of the AD4003 limits the
wideband noise from the upstream components. A smaller filter
bandwidth improves SNR by further limiting noise power;
however, its time constant must also be sufficiently short to
settle voltage kickbacks due to charge injections that occur as
the AD4003 inputs reconnect to the front-end circuitry during
the acquisition phase. The appropriate bandwidth for the system
is at least 5 MHz (for more information, see the Analog
Dialogue article, Front-End Amplifier and RC Filter Design for a
Precision SAR Analog-to-Digital Converter).
The NSD and resulting rms noise contributed by the ADG5207
can be found by using the Johnson/Nyquist noise equation,
because the device acts like a series resistance between the
source and the rest of the analog front end:
en, ADG 5207 = 4 × kB × T × RON
and
vn, ADG 5207 = en, ADG 5207 × GAD8251 × GAD8475 ×
π
× BWRC
2
The resistance of each channel (RON) can be found in the
ADG5207 data sheet.
A summary of the calculated noise performance of the system is
shown in Table 2. The largest contributors to the total noise are
the AD8251 in-amp and the AD4003 ADC.
Rev. 0 | Page 4 of 13
Circuit Note
CN-0385
Table 2. Noise Performance for the Multichannel Data Acquisition System
AD8251
en, AD8251
vn, AD8251
(nV/√Hz)
(µV rms)
40
44.7
27
60.4
22
98.4
18
161
Settling Time Analysis
When the circuit shown in Figure 1 is sampling multiple
channels, each of the different inputs are merged into a timedivision multiplexed signal by the ADG5207. Multiplexed
signals are discontinuous in nature, and typically have large
voltage steps occurring in short time intervals. For the system
in Figure 1, the voltage differential between two consecutive
channels may be as large as 20 V at the inputs of the ADG5207,
and the time allotted for settling is only as long as the sampling
period.
Figure 3 shows the settling time model of the circuit in Figure 1.
Each of the components in the system has its own settling
characteristics (see the following sections).
PART 2
PART 3
PART 4
RC + MUX
PGIA
ADC DRIVER
RC + ADC
ADG5207
AD8251
AD8475
AD4003
tS_ADG5207
tS_AD8251
tS_AD8475
tS_AD4003
Measuring high precision settling is also difficult without a
specialized characterization platform, because of the effects of
oscilloscope overdrive and sensitivity, and the difficulty of
generating an input pulse with sufficient rise time and settling
time.
t S _ TOTAL = t S_ADG5207 2 + t S_AD82512 + t S_AD84752 + t S_AD40032
Settling time is defined as the time required for the analog frontend circuitry to settle an input step to a certain precision. This
precision is usually specified in percent error (for example, 0.1%
or 0.01%); however, in conversion systems, it is also helpful to
relate it to resolution. For example, settling to a 16-bit resolution
is roughly equivalent to settling to 0.001%. Table 3 shows the
relationship between settling to percent error and to resolution
for a single-pole system.
Table 3. Percent Error and Effective Resolution
LSB (%FS)
1.563
0.391
0.0977
0.0244
0.0061
0.00153
0.00038
0.000095
0.000024
Total
vn, total SNR
(µV rms) (dB)
63.6
93.2
75.5
91.7
108.6
88.5
168.2
84.7
Settling time can be estimated provided certain bounds and
assumptions are used in analyzing the circuit. The total settling
time can be calculated by taking the rss of the settling times of
the individual components:
Figure 3. Settling Time Model of CN-0385 Circuit
Resolution,
No. of Bits
6
8
10
12
14
16
18
20
22
AD4003
vn, AD4003
(µV rms)
35.4
35.4
35.4
35.4
many devices do not specify settling characteristics to very high
precision. Settling time for an active device is also not linearly
related to settling precision, and it may take up to 30 times as
long to settle to 0.01% as to 0.1%. The settling time can be due
to long-term thermal effects inside the amplifier. Settling time
is also dependent on the load that the device is driving, and
settling time is generally not characterized for multiple load
conditions.
15142-003
PART 1
AD8475
en, AD8475
vn, AD8475
(nV/√Hz)
(µV rms)
10
28
10
28
10
28
10
28
The maximum throughput of the system is inversely proportional
to the total settling time:
f SR <
1
t S _ TOTAL
Settling Time of the ADG5207
The equivalent circuit for a CMOS switch can be approximated as
an ideal switch in series with a resistor (RON) and in parallel with
two capacitors (CS, CD). The multiplexer stage and associated
filters can therefore be modeled as shown in Figure 4.
No. of Time Constants =
−ln (% Error/100)
4.16
5.55
6.93
8.32
9.70
11.09
12.48
13.86
15.25
ADG5207
AD8251
RON
S1A
CS
DA
RS
CD
CIN
RON
S8A
CS
RON
S1B
CS
DB
RS
CD
CIN
RON
S8B
Estimating the settling time of an analog front end with
multiple components is not trivial for a variety of reasons. First,
Rev. 0 | Page 5 of 13
CS
Figure 4. Settling Time Model of the ADG5207
15142-004
Gain
0.4
0.8
1.6
3.2
ADG5207
en, ADG5207
vn, ADG5207
(nV/√Hz)
(µV rms)
2.04
2.29
2.04
4.57
2.04
9.15
2.04
18.3
CN-0385
Circuit Note
Each channel functions similarly to an RC circuit having an
associated time constant that dominates settling time.
Dynamically switching channels complicates signal settling;
at the time channels are switched, the difference between the
previous output and the current input produces a kickback
transient. This kickback is similar to the one that occurs at the
input to the AD4003 as it enters the acquisition phase. For a
more detailed description, see the Analog Dialogue article,
Front-End Amplifier and RC Filter Design for a Precision SAR
Analog-to-Digital Converter.
Settling Time of the AD8251 and AD8475
The AD8251 data sheet specifies its settling time for a variety of
input voltage step sizes down to a 0.001% error for each gain
configuration. Given a load of 10 kΩ and gain setting of 1, the
AD8251 can settle a 20 V step at its output to 0.001% in
approximately 1 μs. The gain of 1 setting requires the most
settling time; therefore, the settling time analysis uses 1 μs.
However, the 1 μs number may not be accurate when the
AD8251 is driving one of the inputs of the AD8475, which has
an input impedance of 2.92 kΩ instead of 10 kΩ. It is also not
possible to ascertain settling time of the AD8251 to 18-bit
resolution, because of the nonlinear relationship between
settling time and precision. Therefore, the best settling time
estimation is 0.001% error (or 16-bit resolution).
The circuit in Figure 4 was simulated using NI Multisim™, as
shown in Figure 5, with the following component values from
the respective device data sheets:
RON = 250 Ω
CS = 3.5 pF
CD = 36 pF
RIN||CIN = 1.25 GΩ||2 pF
The AD8475 has a settling time specification of 50 ns to 0.001%
for a 2 V differential output step. The maximum voltage step size
expected on the outputs of the AD8475 is twice the reference
voltage (VREF), or approximately 8 V. Assuming that the settling
time is proportional to the output voltage step, the settling time to
0.001% (16 bits) for an 8 V step is approximately 200 ns (4 × 50 ns).
The input resistance of the AD8251 (RIN) is sufficiently large
(1.25 GΩ) to be omitted from simulation.
XSC1
The settling time of each amplifier is, therefore,
G
A B C
100Ω
RON1
250Ω
V1
+10V
CS1OFF
3.5pF
56pF
S1
1
2
RON2
250Ω
56pF
2
+ –
CS2OFF
3.5pF
15142-005
V2
–10V
C1
2pF
CD1
36pF
MUX CONTROL
Figure 5. Multisim Settling Time Model of the ADG5207
The simulation results are shown in Figure 6. The time required
for the output of the ADG5207 to settle to 0.001% of 10 V is
tS_ADG5207 = 188 ns.
Figure 7 shows the equivalent circuit of the inputs of the AD4003.
REXT and CEXT are the components in the RC wideband noise
filter in front of the ADC. RIN and CIN are the input resistance
and capacitance of the AD4003, respectively. CIN is mainly the
internal capacitive digital-to-analog converter (DAC). CPIN is
primarily the pin capacitance, and is ignored. The values for
these components are as follows:




REXT = 200 Ω
CEXT = 120 pF
RIN = 400 Ω
CIN = 40 pF
REF
MUX CTR (V)
4
REXT
3
2
188ns, +10V
0
GND
OUTPUT (V)
10
5
0
–5
0ns, –10V
CPIN
50
100
150
TIME (ns)
200
250
300
15142-006
0
GND
AD4003
D1
RIN
C IN
D2
GND
Figure 7. Settling Time Model of the AD4003 and RC Noise Filter
–10
–50
IN+ OR IN–
EXT
1
VOLTS (V)
VOLTS (V)
tS_AD8251 = 1 μs
tS_AD8475 = 200 ns
Settling Time of the RC Noise Filter and AD4003
OUTPUT
1
100Ω


T
D
15142-007




Figure 6. Settling Time Waveforms for the ADG5207 Simulation Model
The AD4003 employs an internal capacitive DAC and a charge
redistribution algorithm to determine its output code. The
conversion process contains two phases, acquisition and
conversion. During acquisition, the capacitive DAC is
connected to the input terminals of the AD4003. During
conversion, it is disconnected from the input terminals, and
internal logic performs the charge-redistribution algorithm.
Compared to other PulSAR ADCs, the AD4003 has a much
Rev. 0 | Page 6 of 13
Circuit Note
CN-0385
shorter conversion time, and it allows the user to return to
acquisition phase before the end of conversion. Therefore, if the
user runs the ADC at slower throughput, there is have more
time to settle the kickback.
The simulation results are shown in Figure 9. The time taken
for the output to settle to 0.001% of 4 V is tS_AD4003= 711 ns.
The signal must be settled by the end of the acquisition phase
for an accurate conversion. To maximize the time given for the
signal to settle, the multiplexer switches channels immediately
after the AD4003 begins its conversion phase.
4.0V
V1
4.0V
RC_EXT
In addition to settling from the multiplexed signal from the
output of the AD8475, the RC noise filter and AD4003 inputs
also need to settle to the voltage kickback that occurs at the
beginning of the acquisition phase. For more information, see
the Analog Dialogue article, Front-End Amplifier and RC Filter
Design for a Precision SAR Analog-to-Digital Converter.
3.3V
CNV
4.0V
TIME (µs)
Figure 9. Settling Time Waveforms for the AD4003 and RC Noise Filter
Simulation Model
Total System Settling Time
The total settling time of the entire circuit shown in Figure 1
can now be estimated by calculating the rss of the settling times
for each component:
The settling time for this portion of the system is equal to the
time between V1 switching to 4 V (at TIME = 0, see Figure 9) to
ADC_IN settling to 0.001% of 4 V.
XSC1
G
V1
R1
200Ω
V1
0V 4V
5µs 10µs
S1
RC_EXT
C1
120pF
tS_ADG5207 = 188 ns
tS_AD8251 = 1000 ns
tS_AD8475 = 200 ns
tS_AD4003 = 711 ns
•
t S_TOTAL = 188 ns 2 + 1 μs 2 + 200 ns 2 + 711 ns 2 ≈ 1257 ns
The expected maximum channel switching sample rate of the
system is then
ADC_IN
1
≈ 795 kSPS
1257 ns
Offset and Gain Error Results
+ –
C2
40pF
U1
Table 4 shows the offset error measured (in LSBs) for each of the
channels in each gain configuration for the circuit in Figure 1.
Table 4 also shows the average offset error of all of the channels
for each gain configuration.
CNV
NOT
15142-008
CNV PHASE
0V 3.3V
300ns 10µs
T
D
•
•
•
•
f SR <
R2
400Ω
15142-009
The settling time for the circuit in Figure 7 was simulated in NI
Multisim, as shown in Figure 8. V1 represents the maximum
voltage step expected at either input of the AD4003 (from a
single-ended output of the AD8475). CNV and S1 simulate the
AD4003 switching from the conversion phase (occurring when
V1 changes value) to the acquisition phase (300 ns after start of
conversion). CNV keeps S1 open until 300 ns after V1 steps
from 0 V to 4 V to represent the transition from the conversion
phase to the acquisition phase. ADC_IN is the voltage that is
sampled by the AD4003 on a CNV rising edge.
A B C
711ns, 4V
ADC_IN
Figure 8. Multisim™ Settling Time Model of the AD4003 and RC Noise Filter
The offset errors were measured by grounding all of the channel
inputs and collecting and averaging 32,768 samples taken on
each of the channels in each gain configuration.
Table 4. Offset Error Measurements for all Channels and Gain Configurations (Error in LSBs)
Gain
0.4
0.8
1.6
3.2
Channel 1
1.34
1.98
3.25
5.57
Channel 2
1.33
1.99
3.19
5.66
Channel 3
1.31
2.02
3.22
5.67
Channel 4
1.36
2.06
3.19
5.55
Channel 5
1.44
2.00
3.17
5.57
Rev. 0 | Page 7 of 13
Channel 6
1.45
1.98
3.08
5.50
Channel 7
1.46
1.99
3.13
5.54
Channel 8
1.48
1.97
3.14
5.52
Channel Average
1.40
2.00
3.17
5.57
CN-0385
Circuit Note
Table 5. Gain Error Measurements for all Gain Configurations
Gain Error (%FS)
0.02
0.02
0.03
0.02
fS = 1.5MSPS
fIN = 10kHz
SNR = 91.48dB
THD = –94.35dB
SINAD = 89.67dB
–40
–60
–80
–100
–120
–140
–160
–200
0
Performance Results Without Channel Switching
FREQUENCY (kHz)
Figure 10, Figure 11, Figure 12, and Figure 13 show the fast
Fourier transform (FFT) plots for a 10 kHz, full-scale, sine wave
input on a single channel for gain configurations of 0.4, 0.8, 1.6,
and 3.2, respectively. Table 6 shows the SNR and rms noise
measured for each of the gain configurations.
RMS Noise (µV rms)
55.2
62.6
80.7
108.9
0
THD (dB)
−99.2
−98.5
−97.0
−94.6
–40
SNR = 92.52dB
THD = –93.96dB
–40
SNR = 90.25dB
THD = –94.12dB
SINAD = 88.76dB
–60
–80
–100
–120
–140
–180
–200
Figure 12. FFT for 10 kHz, 5 V p-p Input for Gain = 1.6 on Single,
Static Channel
AMPLITUDE (dBFS)
–120
–140
–60
–80
–100
–120
–140
–160
–160
–180
–180
FREQUENCY (kHz)
SNR = 87.77dB
THD = –93.27dB
SINAD = 86.69dB
–40
–80
50 100 150 200 250 300 350 400 450 500 550 600 650 700 750
fS = 1.5MSPS
fIN = 10kHz
–20
–100
0
50 100 150 200 250 300 350 400 450 500 550 600 650 700 750
0
–60
–200
0
FREQUENCY (kHz)
15142-010
AMPLITUDE (dBFS)
–20
fS = 1.5MSPS
fIN = 10kHz
fS = 1.5MSPS
fIN = 10kHz
–160
The input signal was supplied by an Audio Precision SYS-2700
series signal generator, with the board set in differential input
mode. Figure 14 shows total harmonic distortion (THD)
measurements vs. the frequency of the input signal for each
gain configuration.
0
–20
15142-012
SNR (dB)
93.9
92.8
90.6
88.0
Figure 11. FFT for 10 kHz, 10 V p-p Input for Gain = 0.8 on Single,
Static Channel
AMPLITUDE (dBFS)
Table 6. SNR, Noise, and THD vs. Gain for 10 kHz Input
Gain
0.4
0.8
1.6
3.2
50 100 150 200 250 300 350 400 450 500 550 600 650 700 750
15142-011
–180
Figure 10. FFT for 10 kHz, 20 V p-p Input for Gain = 0.4 on Single,
Static Channel
–200
0
50 100 150 200 250 300 350 400 450 500 550 600 650 700 750
FREQUENCY (kHz)
Figure 13. FFT for 10 kHz, 2.5 V p-p Input for Gain = 3.2 on Single,
Static Channel
Rev. 0 | Page 8 of 13
15142-013
Gain
0.4
0.8
1.6
3.2
0
–20
AMPLITUDE (dBFS)
Table 5 shows the gain error measured for each of the gain
configurations for the circuit in Figure 1. The %FS error was
found using the analysis methods described previously, and the
actual gain in V/V was calculated by subtracting this error from
the ideal gain.
Circuit Note
The dc tests involved varying the voltage step size between the
two channels and the channel switching rate. The channel
switching rate was varied from 50 kHz to 1 MHz in 50 kHz
increments. The voltage step size was varied over different
ranges for each of the gain configurations. A mean code result
was measured for each channel for each voltage step size and
channel switching rate by averaging 8,192 samples taken on
each channel. A mean code result was also measured for each
channel in the static case (no switching between channels). The
mean code errors discussed below were found by taking the
difference between the mean codes measured for the static case
and for the switching channels.
GAIN = 0.4dB
GAIN = 0.8dB
GAIN = 1.6dB
GAIN = 3.2dB
–60
–80
–120
1
10
100
INPUT FREQUENCY (kHz)
15142-014
–100
Figure 14. THD Measured for Various Input Frequencies on a Single,
Static Channel
System Performance with Channel Switching
Several tests were performed to evaluate the performance of the
system when scanning multiple channels. Experiments using
precision dc sources measured the error in output code with
respect to sample rate (see the Circuit Note CN-0269 for similar
tests) and voltage step size between channels. AC performance was
also measured for switching between two out of phase, full-scale
inputs from a precision ac source (Audio Precision AP SYS-2712).
Figure 15 and Figure 16 show the test setup for dc and ac
performance tests, respectively. The channel switching rate is
the rate at which the ADG5207 switches from one channel to
another, and is equivalent to the sample rate of the AD4003.
DVC
DVC
–
+
+
Figure 17, Figure 18, Figure 19, and Figure 20 show the mean
code error for various voltage step sizes at several switching rates
in each of the four gain configurations. Figure 21, Figure 22,
Figure 23, and Figure 24 show the mean code error for full-scale
voltage steps at various switching rates in each of the four gain
configurations.
300
100kSPS,
100kSPS,
500kSPS,
500kSPS,
800kSPS,
800kSPS,
250
200
150
CHANNEL
CHANNEL
CHANNEL
CHANNEL
CHANNEL
CHANNEL
100
50
0
–50
–100
–150
EVAL-CN0385-FMCZ
–200
–
–250
0
5
10
C2–
300
GND
250
15142-015
350
+ G
EVAL-CN0385-FMCZ
–
A
B
A
B
A
B
150
100
50
0
–50
–150
EVAL-SDP-CH1Z
C7–
–200
C7+
–250
GND
15142-016
ADA4627
BUFFERS
CHANNEL
CHANNEL
CHANNEL
CHANNEL
CHANNEL
CHANNEL
–100
C5–
C5+
100kSPS,
100kSPS,
500kSPS,
500kSPS,
800kSPS,
800kSPS,
200
MEAN CODE ERROR
+ G –
20
Figure 17. Mean Code Error vs. Voltage Step Size, Gain = 0.4
EVAL-SDP-CH1Z
C2+
Figure 15. Settling Time Evaluation Setup Using DC Calibrators
AP SYS-2712
15
STEP SIZE (V)
C1–
C1+
A
B
A
B
A
B
15142-017
THD (dB)
–40
Figure 16. Settling Time Evaluation Setup Using AC Signal Generator
Rev. 0 | Page 9 of 13
0
5
10
15
20
STEP SIZE (V)
Figure 18. Mean Code Error vs. Voltage Step Size, Gain = 0.8
15142-018
–20
MEAN CODE ERROR
0
CN-0385
CN-0385
Circuit Note
500
350
100kSPS,
100kSPS,
500kSPS,
500kSPS,
800kSPS,
800kSPS,
300
A
B
A
B
A
B
+FS
–FS
400
300
MEAN CODE ERROR
MEAN CODE ERROR
250
200
CHANNEL
CHANNEL
CHANNEL
CHANNEL
CHANNEL
CHANNEL
150
100
50
0
200
100
0
–100
–50
–200
–100
5
10
15
20
STEP SIZE (V)
100kSPS,
100kSPS,
500kSPS,
500kSPS,
800kSPS,
800kSPS,
250
A
B
A
B
A
B
100
50
0
–50
–200
15
20
–300
15142-020
10
STEP SIZE (V)
0
200
400
600
800
CHANNEL SWITCHING RATE (kHz)
Figure 23. Mean Code Error vs. Channel Switching Rate for Full-Scale
Input Step, Gain = 1.6
Figure 20. Mean Code Error vs. Voltage Step Size, Gain = 3.2
400
+FS
–FS
250
+FS
–FS
100
–100
300
800
200
0
5
600
300
150
0
400
400
MEAN CODE ERROR
200
CHANNEL
CHANNEL
CHANNEL
CHANNEL
CHANNEL
CHANNEL
200
CHANNEL SWITCHING RATE (kHz)
500
300
–100
0
Figure 22. Mean Code Error vs. Channel Switching Rate for Full-Scale
Input Step, Gain = 0.8
Figure 19. Mean Code Error vs. Voltage Step Size, Gain = 1.6
MEAN CODE ERROR
–400
15142-023
0
15142-019
–200
15142-022
–300
–150
+FS
–FS
300
200
150
MEAN CODE ERROR
MEAN CODE ERROR
200
100
50
0
–50
–100
100
0
–100
–200
–150
0
200
400
600
CHANNEL SWITCHING RATE (kHz)
800
–400
15142-021
–250
Figure 21. Mean Code Error vs. Channel Switching Rate for Full-Scale
Input Step, Gain = 0.4
0
200
400
600
CHANNEL SWITCHING RATE (kHz)
800
15142-024
–300
–200
Figure 24. Mean Code Error vs. Channel Switching Rate for Full-Scale
Input Step, Gain = 3.2
Rev. 0 | Page 10 of 13
Circuit Note
CN-0385
The mean code error increases as the voltage step size and
channel switching rate increase. This increase is caused by the
combined slew and settling time limitations of the components
in the signal chain. Increasing the step size forces the system to
settle larger changes in voltage and increasing the channel
switching rate decreases the amount of time the system is given
to settle these changes. At sufficiently high step sizes and
switching rates, the mean code error becomes unpredictably
large, as in the gain of 0.4 configuration (see Figure 17 and
Figure 21). This code error is caused by the slew rate limitations
of the input buffer amplifiers in the AD8251 in-amp.
The performance of the system when using the ac source was
evaluated by comparing its THD with respect to the channel
switching rate. The AP SYS-2712 provided a full-scale sine wave
input on one channel and an inverted version of the sine wave
on another channel. THD was measured for various sample
rates, ranging from 25 kSPS to 1.5 MSPS in 25 kSPS increments.
Figure 25 shows the THD measured for each of the channels in
each of the gain configurations.
–40
GAIN = 0.4dB
GAIN = 0.8dB
GAIN = 1.6dB
GAIN = 3.2dB
–50
This circuit uses the EVAL-CN0385-FMCZ circuit board and
the EVAL-SDP-CH1Z SDP-H1 system demonstration platform
controller board. The two boards have 160-pin mating connectors,
allowing quick setup and evaluation of the performance of the
circuit. The circuit board contains the circuit to be evaluated, as
described in this circuit note, and the SDP-H1 controller board
is used with the CN-0385 Evaluation Software to capture the data
from the circuit board.
Equipment Needed
The following equipment is needed:







–60
THD (dB)
CIRCUIT EVALUATION AND TEST

–70
PC with a USB port and Windows® XP or Windows Vista®
(32-bit), or Windows 7 (32-bit)
EVAL-CN0385-FMCZ circuit evaluation board
EVAL-SDP-CH1Z SDP-H1 controller board
CN-0385 Evaluation Software (download from
ftp://ftp.analog.com/pub/cftl/CN0385/)
5 V to 12 V dc power supply or wall wart
(9 V wall wart included with EVAL-CN0385-FMCZ board)
USB to micro-USB cable
Low distortion, low output impedance signal generator to
provide ±10 V output
Low noise, high precision dc supply to provide ±10 V output
Getting Started
Download the evaluation software from ftp://ftp.analog.com/
pub/cftl/CN0385/, and then install the software on the PC.
–80
–90
Functional Block Diagram
–110
0
200
400
600
800
CHANNEL SWITCHING RATE (kHz)
15142-025
–100
Figure 25. THD vs. ADG5207 Channel Switching Rate for Full-Scale
1 kHz Input
See Figure 1 for the circuit block diagram and the EVAL-CN0385FMCZ-SCH.pdf file for the complete circuit schematic. This file
is contained in the CN-0385 Design Support Package (available
at www.analog.com/CN0385-DesignSupport). A functional block
diagram of the test setup is shown in Figure 26.
5V TO 12V
POWER
The THD performance of the system begins to degrade at
roughly 700 kSPS (depending on the gain configuration). The
whole signal chain SNR and THD performance is mainly
limited by the PGA AD8251. A smaller RC filter at the front of
AD4003 also gives better THD at higher channel switching
sampling rate.
PC
J1/P3
AC/DC
SOURCE(S)
COMMON VARIATIONS
EVAL-CN0385-CH1Z
P1
USB
P2/
P8
15142-026
EVAL-SDP-CH1Z
The AD4003 ADC is pin-for-pin compatible with various
other 14-bit, 16-bit, and 18-bit, 10-lead precision SAR ADCs
that can be used in the CN-0385 system. The ADG1207, with
wider bandwidth, can be an alternative to the ADG5207. The
ADG5248F, with fault protection and detection function, can
be used for single-ended inputs. The AD8475 provides a
differential output signal for other differential ADCs, such as
the AD7690. The ADA4805-1 op amp is an alternative for the
AD8475 when driving pseudo differential or single-ended
ADCs, such as the AD4000. Other Analog Devices, Inc., LDOs,
such as the ADP7102 and ADP7142, can replace the ADP7118.
Figure 26. Test Setup Functional Block Diagram
Hardware Setup
Figure 27 shows the EVAL-CN0385-FMCZ evaluation hardware.
Information and details regarding the SDP-H1 board can be
found in the SDP-H1 User Guide.
Connect the 160-pin connector on the circuit board to the J4
connector on the SDP-H1 controller board.
Rev. 0 | Page 11 of 13
CN-0385
Circuit Note
First, connect a 5 V to 12 V dc wall wart to the P3 dc jack or to
Terminal Block J1 and Jumper J2 on position V_EXT. Or, place
J2 in position V_FMC to use the 12 V supply from the SDP-H1
board. Then connect the SDP-H1 board to the PC via the USB
to micro-USB cable.
Test
Information and details regarding test setup and calibration,
and how to use the evaluation software for data capture can be
found in the CN-0385 Software User Guide (available at
www.analog.com/CN0385-UserGuide).
15142-027
With the power supply or dc wall wart and USB cable connected,
launch the evaluation software. When USB communications are
established, the SDP-H1 board can be used to send, receive, and
capture data from the EVAL-CN0385-FMCZ board and perform
data analysis in the time and frequency domains.
Figure 27. EVAL-CN0385-FMCZ Evaluation Hardware
Rev. 0 | Page 12 of 13
Circuit Note
CN-0385
LEARN MORE
Data Sheets and Evaluation Boards
CN-0385 Design Support Package:
www.analog.com/CN0385-DesignSupport
CN-0385 Circuit Evaluation Board (EVAL-CN0385-FMCZ)
UG-502. SDP-H1 User Guide. Analog Devices.
AD4003 Data Sheet
Ardizzoni, John. “A Practical Guide to High-Speed Printed-CircuitBoard Layout,” Analog Dialogue 39-09, September 2005.
AD8251 Data Sheet
Kester, Walt. “Multichannel Data Acquisition Systems” in Data
Conversion Handbook, Chapter 8, Section 8.2. Elsevier.
ADA4807-2 Data Sheet
System Demonstration Platform (EVAL-SDP-CH1Z)
Pachchigar, Maithil. “Complete Sensor-to-Bits Solution Simplifies
Industrial Data-Acquisition System Design,” Analog Dialogue
47-04, April 2013.
Pachchigar, Maithil. “Demystifying High-Performance Multiplexed
Data-Acquisition Systems,” Analog Dialogue 48-07, July 2014.
Walsh, Alan. “Front-End Amplifier and RC Filter Design for a
Precision SAR Analog-to-Digital Converter,” Analog
Dialogue 46-12, December 2012.
ADG5207 Data Sheet
AD8475 Data Sheet
ADR4540 Data Sheet
ADuM141E Data Sheet
ADP7118 Data Sheet
ADP7182 Data Sheet
ADP5070 Data Sheet
ADuM3470 Data Sheet
AN-359 Application Note. Settling time of Operational
Amplifiers. Analog Devices.
ADP2441 Data Sheet
AN-931 Application Note. Understanding PulSAR ADC Support
Circuitry. Analog Devices.
10/2016—Revision 0: Initial Version
REVISION HISTORY
AN-1024 Application Note. How to Calculate the Settling Time
and Sampling Rate of a Multiplexer. Analog Devices.
AN-1264 Application Note. Precision Signal Conditioning for
High Resolution Industrial Applications. Analog Devices.
MT-004 Tutorial. The Good, the Bad and the Ugly Aspects of
ADC Input Noise – Is No Noise Good Noise? Analog Devices.
MT-046 Tutorial. Op Amp Settling Time. Analog Devices.
MT-048 Tutorial. Op Amp Noise Relationships: 1/f Noise, RMS
Noise and Equivalent Noise Bandwidth. Analog Devices.
(Continued from first page) Circuits from the Lab reference designs are intended only for use with Analog Devices products and are the intellectual property of Analog Devices or its licensors.
While you may use the Circuits from the Lab reference designs in the design of your product, no other license is granted by implication or otherwise under any patents or other intellectual
property by application or use of the Circuits from the Lab reference designs. Information furnished by Analog Devices is believed to be accurate and reliable. However, Circuits from the
Lab reference designs are supplied "as is" and without warranties of any kind, express, implied, or statutory including, but not limited to, any implied warranty of merchantability,
noninfringement or fitness for a particular purpose and no responsibility is assumed by Analog Devices for their use, nor for any infringements of patents or other rights of third parties
that may result from their use. Analog Devices reserves the right to change any Circuits from the Lab reference designs at any time without notice but is under no obligation to do so.
©2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
CN15142-0-10/16(0)
Rev. 0 | Page 13 of 13