Differential Input, Dual, Simultaneous Sampling, 5 MSPS, 12-Bit, SAR ADC AD7356 FEATURES Dual 12-bit SAR ADC Simultaneous sampling Throughput rate: 5 MSPS per channel Specified for VDD at 2.5 V No conversion latency Power dissipation: 36 mW at 5 MSPS On-chip reference: 2.048 V ± 0.25%, 6 ppm/°C Dual conversion with read High speed serial interface: SPI-/QSPI™-/MICROWIRE™-/DSPcompatible −40°C to +125°C operation Available in a 16-lead TSSOP FUNCTIONAL BLOCK DIAGRAM VDD VDRIVE AD7356 VINA+ 12-BIT SUCCESSIVE APPROXIMATION ADC T/H VINA– REFA SDATAA BUF SCLK CONTROL LOGIC REF CS BUF REFB VINB+ 12-BIT SUCCESSIVE APPROXIMATION ADC T/H SDATAB 06505-001 VINB– AGND AGND REFGND DGND Figure 1. GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD73561 is a dual, 12-bit, high speed, low power, successive approximation ADC that operates from a single 2.5 V power supply and features throughput rates up to 5 MSPS. The part contains two ADCs, each preceded by a low noise, wide bandwidth track-and-hold circuit that can handle input frequencies in excess of 110 MHz. 1. The conversion process and data acquisition use standard control inputs allowing for easy interfacing to microprocessors or DSPs. The input signal is sampled on the falling edge of CS; a conversion is also initiated at this point. The conversion time is determined by the SCLK frequency. 2. The AD7356 uses advanced design techniques to achieve very low power dissipation at high throughput rates. With a 2.5 V supply and a 5 MSPS throughput rate, the part consumes typically 14 mA. The part also offers a flexible power/throughput rate management option. The analog input range for the part is the differential common mode ±VREF/2. The AD7356 has an on-chip 2.048 V reference that can be overdriven when an external reference is preferred. The AD7356 is available in a 16-lead thin shrink small outline package (TSSOP). 1 3. Two Complete ADC Functions. These functions allow simultaneous sampling and conversion of two channels. The conversion result of both channels is simultaneously available on separate data lines or in succession on one data line if only one serial port is available. High Throughput with Low Power Consumption. The AD7356 offers a 5 MSPS throughput rate with 36 mW power consumption. No Conversion Latency. The AD7356 features two standard successive approximation ADCs with accurate control of the sampling instant via a CS input and, once off, conversion control. Table 1. Related Devices Generic AD7352 AD7266 AD7866 AD7366 AD7367 Resolution 12-bit 12-bit 12-bit 12-bit 14-bit Throughput 3 MSPS 2 MSPS 1 MSPS 1 MSPS 1 MSPS Analog Input Differential Differential/single ended Single-ended Single-ended bipolar Single-ended bipolar Protected by U.S. Patent No. 6,681,332. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2008 Analog Devices, Inc. All rights reserved. AD7356 TABLE OF CONTENTS Features .............................................................................................. 1 Analog Inputs ............................................................................. 13 Functional Block Diagram .............................................................. 1 Driving Differential Inputs ....................................................... 14 General Description ......................................................................... 1 ADC Transfer Function ............................................................. 14 Product Highlights ........................................................................... 1 Modes of Operation ....................................................................... 15 Revision History ............................................................................... 2 Normal Mode.............................................................................. 15 Specifications..................................................................................... 3 Partial Power-Down Mode ....................................................... 15 Timing Specifications .................................................................. 5 Full Power-Down Mode ............................................................ 16 Absolute Maximum Ratings............................................................ 6 Power-Up Times ......................................................................... 17 ESD Caution .................................................................................. 6 Power vs. Throughput Rate ....................................................... 17 Pin Configuration and Function Descriptions ............................. 7 Serial Interface ................................................................................ 18 Typical Performance Characteristics ............................................. 8 Application Hints ........................................................................... 19 Terminology .................................................................................... 10 Grounding and Layout .............................................................. 19 Theory of Operation ...................................................................... 12 Evaluating the AD7356 Performance ...................................... 19 Circuit Information .................................................................... 12 Outline Dimensions ....................................................................... 20 Converter Operation .................................................................. 12 Ordering Guide .......................................................................... 20 Analog Input Structure .............................................................. 12 REVISION HISTORY 10/08—Revision 0: Initial Version Rev. 0 | Page 2 of 20 AD7356 SPECIFICATIONS VDD = 2.5 V ± 10%, VDRIVE = 2.25 V to 3.6 V, internal reference = 2.048 V, fSCLK = 80 MHz, fSAMPLE = 5 MSPS, TA = TMIN to TMAX 1 , unless otherwise noted. Table 2. Parameter DYNAMIC PERFORMANCE Signal-to-Noise Ratio (SNR) 2 Signal-to-(Noise and Distortion) (SINAD)2 Total Harmonic Distortion (THD)2 Spurious Free Dynamic Range (SFDR)2 Intermodulation Distortion (IMD)2 Second-Order Terms Third-Order Terms ADC-to-ADC Isolation2 CMRR2 SAMPLE AND HOLD Aperture Delay Aperture Delay Match Aperture Jitter Full Power Bandwidth @ 3 dB @ 0.1 dB DC ACCURACY Resolution Integral Nonlinearity (INL)2 Differential Nonlinearity (DNL)2 Positive Full-Scale Error2 Positive Full-Scale Error Match2 Midscale Error2 Midscale Error Match2 Negative Full-Scale Error2 Negative Full-Scale Error Match2 ANALOG INPUT Fully Differential Input Range (VIN+ and VIN−) Common-Mode Voltage Range Min Typ 70 69.5 71.5 71 −84 −85 VREF Temperature Coefficient VREF Long Term Stability VREF Thermal Hysteresis2 VREF Noise VREF Output Impedance Unit −77.5 −78.5 dB dB dB dB Test Conditions/Comments fIN = 1 MHz sine wave fa = 1 MHz + 50 kHz, fb = 1 MHz − 50 KHz −84 −76 −100 −100 dB dB dB dB 3.5 40 16 ns ps ps 110 77 MHz MHz 12 ±0.5 ±0.5 ±1 ±2 +5 ±2 ±1 ±2 0.5 DC Leakage Current Input Capacitance REFERENCE INPUT/OUTPUT VREF Input Voltage Range VREF Input Current VREF Output Voltage Max ±0.5 32 8 2.048 + 0.1 0.3 2.038 2.043 6 100 50 60 1 ±1 ±0.99 ±6 ±8 0/+11 ±8 ±6 ±8 Bits LSB LSB LSB LSB LSB LSB LSB LSB VCM ± VREF/2 V 1.9 V ±5 μA pF pF VDD 0.45 2.058 2.053 20 Rev. 0 | Page 3 of 20 V mA V V ppm/°C ppm ppm μV rms Ω fIN = 1 MHz, fNOISE = 100 kHz to 2.5 MHz fNOISE = 100 kHz to 2.5 MHz Guaranteed no missed codes to 12 bits VCM = common-mode voltage, VIN+ and VIN− must remain within GND and VDD The voltage around which VIN+ and VIN− are centered When in track mode When in hold mode When in reference overdrive mode 2.048 V ± 0.5% max @ VDD = 2.5 V ± 5% 2.048 V ± 0.25% max @ VDD = 2.5 V ± 5% and 25°C For 1000 hours AD7356 Parameter LOGIC INPUTS Input High Voltage (VINH) Input Low Voltage (VINL) Input Current (IIN)) Input Capacitance (CIN) LOGIC OUTPUTS Output High Voltage (VOH) Output Low Voltage (VOL) Floating-State Leakage Current Floating-State Output Capacitance Output Coding CONVERSION RATE Conversion Time Track-and-Hold Acquisition Time2 Throughput Rate POWER REQUIREMENTS 3 VDD VDRIVE ITOTAL 4 Normal Mode (Operational) Normal Mode (Static) Partial Power-Down Mode Full Power-Down Mode Power Dissipation Normal Mode (Operational) Normal Mode (Static) Partial Power-Down Mode Full Power-Down Mode Min Typ Max Unit 0.3 × VDRIVE ±1 V V μA pF 0.2 ±1 V V μA pF 0.6 × VDRIVE 3 VDRIVE − 0.2 5.5 Straight binary t2 + 13 × tSCLK Test Conditions/Comments VIN = 0 V or VDRIVE 30 5 ns ns MSPS 2.75 3.6 V V 14 6 3.5 5 20 7.8 4.5 40 90 mA mA mA μA μA SCLK on or off SCLK on or off SCLK on or off, −40°C to +85°C SCLK on or off, 85°C to 125°C 36 16 9.5 16 59 21.5 11.5 110 250 mW mW mW μW μW SCLK on or off SCLK on or off SCLK on or off, −40°C to +85°C SCLK on or off, 85°C to 125°C 2.25 2.25 Full-scale step input, settling to 0.5 LSBs Nominal VDD = 2.5 V Digital inputs = 0 V or VDRIVE 1 Temperature ranges are as follows: Y Grade: −40°C to +125°C; B Grade: −40°C to +85°C. See the Terminology section. 3 Current and power typical specifications are based on results with VDD = 2.5 V and VDRIVE = 3.0 V. 4 ITOTAL is the total current flowing in VDD and VDRIVE. 2 Rev. 0 | Page 4 of 20 AD7356 TIMING SPECIFICATIONS VDD = 2.5 V ± 10%, VDRIVE = 2.25 V to 3.6 V, internal reference = 2.048 V, TA = TMAX to TMIN 1 , unless otherwise noted. Table 3. Parameter fSCLK tCONVERT tQUIET t2 t3 2 t42, 3 t5 t6 t72 t82 t9 t102 Limit at TMIN , TMAX 50 80 t2 + 13 × tSCLK 5 5 6 Unit kHz min MHz max ns max ns min ns min ns max 12.5 11 9.5 9 5 5 3.5 9.5 5 4.5 9.5 ns max ns max ns max ns max ns min ns min ns min ns max ns min ns min ns max Description tSCLK = 1/fSCLK Minimum time between end of serial read and next falling edge of CS CS to SCLK setup time Delay from CS until SDATAA and SDATAB are three-state disabled Data access time after SCLK falling edge 1.8 V ≤ VDRIVE < 2.25 V 2.25 V ≤ VDRIVE < 2.75 V 2.75 V ≤ VDRIVE < 3.3 V 3.3 V ≤ VDRIVE ≤ 3.6 V SCLK low pulse width SCLK high pulse width SCLK to data valid hold time CS rising edge to SDATAA, SDATAB high impedance CS rising edge to falling edge pulse width SCLK falling edge to SDATAA, SDATAB high impedance SCLK falling edge to SDATAA, SDATAB high impedance 1 Temperature ranges are as follows: Y Grade: −40°C to +125°C; B Grade: −40°C to +85°C. Specified with a load capacitance of 10 pF on SDATAA and SDATAB. 3 The time required for the output to cross 0.4 V or 2.4 V. 2 Rev. 0 | Page 5 of 20 AD7356 ABSOLUTE MAXIMUM RATINGS Table 4. Parameter VDD to AGND, DGND, REFGND VDRIVE to AGND, DGND, REFGND VDD to VDRIVE AGND to DGND to REFGND Analog Input Voltages1 to AGND Digital Input Voltages2 to DGND Digital Output Voltages3 to DGND Input Current to Any Pin Except Supply Pins4 Operating Temperature Range Y Grade B Grade Storage Temperature Range Junction Temperature TSSOP θJA Thermal Impedance θJC Thermal Impedance Lead Temperature, Soldering Reflow Temperature (10 sec to 30 sec) ESD Rating −0.3 V to +3 V −0.3 V to +5 V −5 V to +3 V −0.3 V to +0.3 V −0.3 V to VDD + 0.3 V −0.3 V to VDRIVE + 0.3 V −0.3 V to VDRIVE + 0.3 V ±10 mA Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION −40°C to +125°C −40°C to +85°C −65°C to +150°C 150°C 143°C/W 45°C/W 255°C 1.5 kV 1 Analog input voltages are VINA+, VINA−, VINB+, VINB−, REFA, and REFB. Digital input voltages are CS and SCLK. 3 Digital output voltages are SDATAA and SDATAB. 4 Transient currents of up to 100 mA do not cause SCR latch-up. 2 Rev. 0 | Page 6 of 20 AD7356 VINA+ 1 16 VDRIVE VINA– 2 15 SCLK REFA 3 AD7356 14 SDATAA TOP VIEW (Not to Scale) 13 SDATAB AGND 5 12 DGND REFB 6 11 AGND VINB– 7 10 CS VINB+ 8 9 VDD REFGND 4 06505-002 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 2. Pin Configuration Table 5. Pin Function Descriptions Pin No. 1, 2 3, 6 Mnemonic VINA+, VINA− REFA, REFB 4 REFGND 5, 11 AGND 7, 8 9 VINB−, VINB+ VDD 10 CS 12 DGND 13, 14 SDATAB, SDATAA 15 SCLK 16 VDRIVE Description Analog Inputs of ADC A. These analog inputs form a fully differential pair. Reference Decoupling Capacitor Pins. Decoupling capacitors are connected between these pins and the REFGND pin to decouple the reference buffer for each respective ADC. It is recommended to decouple each reference pin with a 10 μF capacitor. Provided the output is buffered, the on-chip reference can be taken from these pins and applied externally to the rest of the system. The nominal internal reference voltage is 2.048 V and appears at these pins. These pins can also be overdriven by an external reference. The input voltage range for the external reference is 2.048 V + 100 mV to VDD. Reference Ground. This is the ground reference point for the reference circuitry on the AD7356. Refer any external reference signal to this REFGND voltage. Decoupling capacitors must be placed between this pin and the REFA and REFB pins. Connect the REFGND pin to the AGND plane of a system. Analog Ground. This is the ground reference point for all analog circuitry on the AD7356. All analog input signals should be referred to this AGND voltage. The AGND and DGND voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis. Analog Inputs of ADC B. These analog inputs form a fully differential pair. Power Supply Input. The VDD range for the AD7356 is 2.5 V ± 10%. Decouple the supply to AGND with a 0.1 μF capacitor in parallel with a 10 μF tantalum capacitor. Chip Select. Active low logic input. This input provides the dual functions of initiating conversions on the AD7356 and framing the serial data transfer. Digital Ground. This is the ground reference point for all digital circuitry on the AD7356. Connect this pin to the DGND plane of a system. The DGND and AGND voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis. Serial Data Outputs. The data output is supplied to each pin as a serial data stream. The bits are clocked out on the falling edge of the SCLK input. To access the 12 bits of data from the AD7356, 14 SCLK falling edges are required. The data simultaneously appears on both data output pins from the simultaneous conversions of both ADCs. The data stream consists of two leading zeros followed by the 12 bits of conversion data. The data is provided MSB first. If CS is held low for 16 SCLK cycles rather than 14 on the AD7356, then two trailing zeros appear after the 12 bits of data. If CS is held low for a further 16 SCLK cycles on either SDATAA or SDATAB, the data from the other ADC follows on the SDATA pins. This allows data from a simultaneous conversion on both ADCs to be gathered in serial format on either SDATAA or SDATAB. Serial Clock. Logic input. A serial clock input provides the serial clock for accessing the data from the AD7356. This clock is also used as the clock source for the conversion process. Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface operates. The voltage at this pin may be different than the voltage at VDD. The VDRIVE supply should be decoupled to DGND with a 0.1 μF capacitor in parallel with a 10 μF tantalum capacitor. Rev. 0 | Page 7 of 20 AD7356 TYPICAL PERFORMANCE CHARACTERISTICS 0 16,384 POINT FFT fSAMPLE = 5MSPS fIN = 1MHz SNR = 71.8dB SINAD = 71.6dB THD = –83.5dB –60 –80 –100 0 250 500 750 40,000 30,000 20,000 10,000 06505-003 –120 50,000 93 HITS 0 2044 1000 1250 1500 1750 2000 2249 2499 2045 2046 06505-005 dB –40 60,000 NUMBER OF OCCURRENCES –20 20 HITS 2047 2048 2049 2050 CODE FREQUENCY (kHz) Figure 6. Histogram of Codes for 65,000 Samples Figure 3. Typical FFT 1.0 73 0.8 72 0.6 70 0.2 SNR (dB) DNL ERROR (LSB) 71 0.4 0 –0.2 69 68 –0.4 67 –0.6 0 500 1000 1500 2000 2500 3000 3500 06505-037 –1.0 66 06505-027 –0.8 65 0 4000 1000 2000 3000 4000 5000 ANALOG INPUT FREQUENCY (kHz) CODE Figure 7. SNR vs. Analog Input Frequency Figure 4. Typical DNL Error –60 1.0 0.8 –65 0.6 –70 PSRR (dB) 0.2 0 –0.2 –0.6 0 500 1000 1500 2000 2500 3000 3500 –90 4000 0 5 10 15 20 25 SUPPLY RIPPLE FREQUENCY (MHz) CODE Figure 5. Typical INL Error 06505-035 –85 –0.8 –1.0 –75 –80 –0.4 06505-028 INL ERROR (LSB) 0.4 Figure 8. PSRR vs. Supply Ripple Frequency with No Supply Decoupling Rev. 0 | Page 8 of 20 AD7356 11 2.0482 2.0480 ACCESS TIME (ns) 2.0476 2.0474 2.0472 2.0470 2.0468 9 8 7 2.0466 2.0464 2.0460 0 500 1000 1500 2000 2500 5 1.8 3000 2.0 2.2 2.4 Figure 9. VREF vs. Reference Output Current Drive 2.8 3.0 3.2 3.4 3.6 3.2 3.4 3.6 Figure 12. Access Time vs. VDRIVE 9 1.0 +125°C +85°C +25°C –40°C 0.8 8 0.6 INL MAX 0.4 0.2 HOLD TIME (ns) DNL MAX 0 INL MIN –0.2 7 6 –0.4 DNL MIN 5 06505-010 –0.6 –0.8 –1.0 0 10 20 30 40 50 60 70 4 1.8 80 Figure 10. Linearity Error vs. SCLK Frequency 0.6 DNL MAX 0.2 INL MAX INL MIN DNL MIN –1.0 2.10 06505-011 –0.6 2.15 2.20 2.25 2.30 2.35 2.40 2.2 2.4 2.6 2.8 3.0 Figure 13. Hold Time vs. VDRIVE 1.0 –0.2 2.0 VDRIVE (V) SCLK FREQUENCY (MHz) 2.45 2.50 EXTERNAL VREF (V) Figure 11. Linearity Error vs. External VREF Rev. 0 | Page 9 of 20 06505-040 LINEARITY ERROR (LSB) 2.6 VDRIVE (V) CURRENT LOAD (µA) 06505-039 06505-038 6 2.0462 LINEARITY ERROR (LSB) VREF (V) +125°C +85°C +25°C –40°C 10 2.0478 AD7356 TERMINOLOGY Integral Nonlinearity (INL) INL is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale (1 LSB below the first code transition) and full scale (1 LSB above the last code transition). Power Supply Rejection Ratio (PSRR) PSRR is defined as the ratio of the power in the ADC output at full-scale frequency, f, to the power of a 100 mV p-p sine wave applied to the ADC VDD supply of frequency, fS. The frequency of the input varies from 5 kHz to 25 MHz. Differential Nonlinearity (DNL) DNL is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. where: Pf is the power at frequency, f, in the ADC output. PfS is the power at frequency, fS, in the ADC output. Negative Full-Scale Error Negative full-scale error is the deviation of the first code transition (00 … 000) to (00 … 001) from the ideal (that is, −VREF + 0.5 LSB) after the midscale error has been adjusted out. Common-Mode Rejection Ratio (CMRR) CMRR is defined as the ratio of the power in the ADC output at full-scale frequency, f, to the power of a 100 mV p-p sine wave applied to the common-mode voltage of VIN+ and VIN− of frequency, fS. Negative Full-Scale Error Match Negative full-scale error match is the difference in negative fullscale error between the two ADCs. Midscale Error Midscale error is the deviation of the midscale code transition (011 … 111) to (100 … 000) from the ideal (that is, 0 V). Midscale Error Match Midscale error match is the difference in midscale error between the two ADCs. Positive Full-Scale Error Positive full-scale error is the deviation of the last code transition (111 … 110) to (111 … 111) from the ideal (that is, VREF − 1.5 LSB) after the midscale error has been adjusted out. Positive Full-Scale Error Match Positive full-scale error match is the difference in positive fullscale error between the two ADCs. ADC-to-ADC Isolation ADC-to-ADC isolation is a measure of the level of crosstalk between ADC A and ADC B. It is measured by applying a fullscale 1 MHz sine wave signal to one of the two ADCs and applying a full-scale signal of variable frequency to the other ADC. The ADC-to-ADC isolation is defined as the ratio of the power of the 1 MHz signal on the converted ADC to the power of the noise signal on the other ADC that appears in the FFT. The noise frequency on the unselected channel varies from 100 kHz to 2.5 MHz. PSRR (dB) = 10 log(Pf/PfS) CMRR (dB) = 10 log(Pf/PfS) where: Pf is the power at frequency (f) in the ADC output. PfS is the power at frequency (fS) in the ADC output. Track-and-Hold Acquisition Time The track-and-hold amplifier returns to track mode at the end of a conversion. The track-and-hold acquisition time is the time required for the output of the track-and-hold amplifier to reach its final value, within ±0.5 LSB, after the end of a conversion. Signal-to-(Noise and Distortion) Ratio (SINAD) SINAD is the measured ratio of signal-to-(noise and distortion) at the output of the ADC. The signal is the rms amplitude of the fundamental. Noise is the sum of all nonfundamental signals up to half the sampling frequency (fS/2), excluding dc. The ratio is dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. The theoretical SINAD for an ideal N-bit converter with a sine wave input is given by SINAD = (6.02 N + 1.76) dB Thus, for a 12-bit converter, SINAD is 74 dB and for a 14-bit converter, SINAD is 86 dB. Rev. 0 | Page 10 of 20 AD7356 The AD7356 is tested using the CCIF standard where two input frequencies near the top end of the input bandwidth are used. In this case, the second-order terms are usually distanced in frequency from the original sine waves and the third-order terms are usually at a frequency close to the input frequencies. As a result, the second- and third-order terms are specified separately. The calculation of the intermodulation distortion is as per the THD specification, where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in decibels. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of harmonics to the fundamental. For the AD7356, it is defined as THD (dB ) = −20 log V2 2 + V3 2 + V4 2 + V5 2 + V6 2 V1 where: V1 is the rms amplitude of the fundamental. V2, V3, V4, V5, and V6 are the rms amplitudes of the second through the sixth harmonics. Spurious Free Dynamic Range (SFDR) SFDR is the ratio of the rms value of the next largest component in the ADC output spectrum (up to fS/2 and excluding dc) to the rms value of the fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for ADCs where the harmonics are buried in the noise floor, it is a noise peak. Intermodulation Distortion (IMD) With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities creates distortion products at sum and difference frequencies of mfa ± nfb where m, n = 0, 1, 2, 3, and so on. Intermodulation distortion terms are those for which neither m nor n is equal to zero. For example, the second-order terms include (fa + fb) and (fa − fb), while the third-order terms include (2fa + fb), (2fa − fb), (fa + 2fb), and (fa − 2fb). Thermal Hysteresis Thermal hysteresis is defined as the absolute maximum change of reference output voltage after the device is cycled through temperature from either T_HYS+ = +25°C to TMAX to +25°C T_HYS– = +25°C to TMIN to +25°C Thermal hysteresis is expressed in ppm using the following equation: VHYS (ppm) = V REF (25°C ) − VREF (T _ HYS) × 10 6 VREF (25°C ) where: VREF(25°C) is VREF at 25°C. VREF(T_HYS) is the maximum change of VREF at T_HYS+ or T_HYS–. Rev. 0 | Page 11 of 20 AD7356 THEORY OF OPERATION The AD7356 is a high speed, dual, 12-bit, single-supply, successive approximation analog-to-digital converter (ADC). The part operates from a 2.5 V power supply and features throughput rates of up to 5 MSPS. The AD7356 contains two on-chip differential track-and-hold amplifiers, two successive approximation ADCs, and a serial interface with two separate data output pins. The part is housed in a 16-lead TSSOP, offering the user considerable space-saving advantages over alternative solutions. The serial clock input accesses data from the part but also provides the clock source for each successive approximation ADC. The AD7356 has an on-chip 2.048 V reference. If an external reference is desired the internal reference can be overdriven with a reference value ranging from (2.048 V + 100 mV) to VDD. If the internal reference is to be used elsewhere in the system, then the reference output needs to be buffered first. The differential analog input range for the AD7356 is VCM ± VREF/2. The AD7356 features power-down options to allow power saving between conversions. The power-down feature is implemented via the standard serial interface, as described in the Modes of Operation section. CS B A SW2 CS A SW2 VREF CAPACITIVE DAC Figure 16 shows the equivalent circuit of the analog input structure of the AD7356. The four diodes provide ESD protection for the analog inputs. Care must be taken to ensure that the analog input signals never exceed the supply rails by more than 300 mV. This causes these diodes to become forward biased and start conducting into the substrate. These diodes can conduct up to 10 mA without causing irreversible damage to the part. The C1 capacitors in Figure 16 are typically 8 pF and can primarily be attributed to pin capacitance. The R1 resistors are lumped components made up of the on resistance of the switches. The value of these resistors is typically about 30 Ω. The C2 capacitors are the sampling capacitors of the ADC with a capacitance of 32 pF typically. VDD CONTROL LOGIC SW3 D VIN+ CAPACITIVE DAC CONTROL LOGIC SW3 CS B B C1 Figure 14. ADC Acquisition Phase R1 C2 D VDD D VIN– C1 R1 C2 D 06505-015 VREF A SW1 06505-012 VIN– A SW1 COMPARATOR VIN– COMPARATOR CS B VIN+ ANALOG INPUT STRUCTURE The AD7356 has two successive approximation ADCs, each based around two capacitive DACs. Figure 14 and Figure 15 show simplified schematics of one of these ADCs in acquisition and conversion phase. The ADC comprises a control logic, a SAR, and two capacitive DACs. In Figure 14 (the acquisition phase), SW3 is closed, SW1 and SW2 are in Position A, the comparator is held in a balanced condition, and the sampling capacitor arrays acquire the differential signal on the input. VIN+ CAPACITIVE DAC Figure 15. ADC Conversion Phase CONVERTER OPERATION CAPACITIVE DAC When the ADC starts a conversion (see Figure 15), SW3 opens and SW1 and SW2 move to Position B, causing the comparator to become unbalanced. Both inputs are disconnected once the conversion begins. The control logic and charge redistribution DACs are used to add and subtract fixed amounts of charge from the sampling capacitor arrays to bring the comparator back into a balanced condition. When the comparator is rebalanced, the conversion is complete. The control logic generates the ADC output code. The output impedances of the sources driving the VIN+ and VIN− pins must be matched; otherwise, the two inputs may have different settling times, resulting in errors. 06505-013 CIRCUIT INFORMATION Figure 16. Equivalent Analog Input Circuit, Conversion Phase–Switches Open, Track Phase—Switches Closed Rev. 0 | Page 12 of 20 AD7356 When no amplifier is used to drive the analog input, limit the source impedance to low values. The maximum source impedance depends on the amount of THD that can be tolerated. THD increases as the source impedance increases and performance degrades. Figure 17 shows a graph of the THD vs. the analog input signal frequency for different source impedances. –65 –67 –69 –71 THD (dB) –73 100Ω –75 ANALOG INPUTS Differential signals have some benefits over single-ended signals, including noise immunity based on the devices common-mode rejection and improvements in distortion performance. Figure 19 defines the fully differential input of the AD7356. VREF p-p COMMON-MODE VOLTAGE The amplitude of the differential signal is the difference between the signals applied to the VIN+ and VIN− pins in each differential pair (VIN+ − VIN−). VIN+ and VIN− should be simultaneously driven by two signals each of amplitude (VREF) that are 180° out of phase. This amplitude of the differential signal is, therefore, –VREF to +VREF peak-to -peak regardless of the common mode (CM). CM = (VIN+ + VIN−)/2 10Ω –85 1000 1500 2000 06505-026 –83 2500 FREQUENCY (kHz) Figure 17. THD vs. Analog Input Signal Frequency for Various Source Impedances This results in the span of each input being CM ± VREF/2. This voltage has to be set up externally. When setting up the CM, ensure that VIN+ and VIN− remain within GND/VDD. When a conversion takes place, CM is rejected, resulting in a virtually noise-free signal of amplitude, –VREF to +VREF, corresponding to the digital codes of 0 to 4095 for the AD7356. Figure 18 shows a graph of the THD vs. the analog input frequency while sampling at 5 MSPS. In this case, the source impedance is 33 Ω. –66 –70 –78 –82 –86 07044-029 THD (dB) –74 0 VIN– Figure 19. Differential Input Definition 33Ω –81 –90 VREF p-p *ADDITIONAL PINS OMITTED FOR CLARITY. 50Ω –79 200 AD7356* CM is the average of the two signals and is, therefore, the voltage on which the two inputs are centered. –77 –87 100 VIN+ 06505-034 For ac applications, removing high frequency components from the analog input signal is recommended by the use of an RC low-pass filter on the analog input pins. In applications where harmonic distortion and signal-to-noise ratio are critical, the analog input should be driven from a low impedance source. Large source impedances significantly affect the ac performance of the ADC and may necessitate the use of an input buffer amplifier. The choice of the op amp is a function of the particular application. 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000 ANALOG INPUT FREQUENCY (kHz) Figure 18. THD vs. Analog Input Frequency Rev. 0 | Page 13 of 20 AD7356 The voltage applied to Point A sets up the common-mode voltage. In both diagrams, it is connected in some way to the reference. The AD8022 is a suitable dual op amp that could be used in this configuration to provide differential drive to the AD7356. Differential operation requires VIN+ and VIN− to be driven simultaneously with two equal signals that are 180° out of phase. Because not all applications have a signal preconditioned for differential operation, there is often a need to perform a singleended-to-differential conversion. 2 × VREF p-p Differential Amplifier VREF An ideal method of applying differential drive to the AD7356 is to use a differential amplifier such as the AD8138. This part can be used as a single-ended-to-differential amplifier or as a differential-to-differential amplifier. The AD8138 also provides common-mode level shifting. Figure 20 shows how the AD8138 can be used as a single-ended-to-differential amplifier. The positive and negative outputs of the AD8138 are connected to the respective inputs on the ADC via a pair of series resistors to minimize the effects of switched capacitance on the front end of the ADC. The architecture of the AD8138 results in outputs that are very highly balanced over a wide frequency range without requiring tightly matched external components. GND 2.048V 1.024V 0V RS* 51Ω RG 2 A VIN– C F2 V– AD7356* 27Ω REFA/REFB VIN– 10kΩ 10µF *ADDITIONAL PINS OMITTED FOR CLARITY. Figure 21. Dual Op Amp Circuit to Convert a Single-Ended Unipolar Signal into a Differential Signal 2.048V 1.024V 0V 220Ω 440Ω GND V+ 27Ω VIN+ V– 220Ω 220Ω 220Ω 2.048V 1.024V 0V V+ REFA/REFB 2.048V 1.024V 0V RF2 2.048V 1.024V 0V V+ AD7356 RS* VIN+ 220Ω 220Ω VIN+ AD8138 27Ω A 10kΩ 27Ω V– AD7356* VIN– REFA/REFB 10kΩ 10µF 20kΩ 10µF 06505-033 +2.048V GND –2.048V V+ 2 × VREF p-p RG 1 VOCM 440Ω V– C F1 R F1 2.048V 1.024V 0V 220Ω 06505-032 DRIVING DIFFERENTIAL INPUTS 10kΩ *ADDITIONAL PINS OMITTED FOR CLARITY. If the analog inputs source being used has zero impedance, all four resistors (RG1, RG2, RF1, and RF2) should be the same value as each other. If the source has a 50 Ω impedance and a 50 Ω termination, for example, increase the value of RG2 by 25 Ω to balance this parallel impedance on the input and thus ensure that both the positive and negative analog inputs have the same gain. The outputs of the amplifier are perfectly matched balanced differential outputs of identical amplitude, and are exactly 180° out of phase. Op Amp Pair An op amp pair can be used to directly couple a differential signal to one of the analog input pairs of the AD7356. The circuit configurations shown in Figure 21 and Figure 22 show how an op amp pair can be used to convert a single-ended signal into a differential signal for a bipolar and unipolar input signal, respectively. ADC TRANSFER FUNCTION The output coding for the AD7356 is straight binary. The designed code transitions occur at successive LSB values (1 LSB, 2 LSBs, and so on). The LSB size is (2 × VREF)/4096. The ideal transfer characteristic of the AD7356 is shown in Figure 23. 111 ... 111 111 ... 110 111 ... 101 000 ... 010 000 ... 001 000 ... 000 –VREF + 1 LSB –VREF + 0.5 LSB +VREF – 1 LSB +VREF – 1.5 LSB ANALOG INPUT Figure 23. AD7356 Ideal Transfer Characteristic Rev. 0 | Page 14 of 20 06505-014 Figure 20. Using the AD8138 as a Single-Ended-to-Differential Amplifier Figure 22. Dual Op Amp Circuit to Convert a Single-Ended Bipolar Signal into a Differential Unipolar Signal ADC CODE 06505-031 *MOUNT AS CLOSE TO THE AD7356 AS POSSIBLE AND ENSURE THAT HIGH PRECISION RS RESISTORS ARE USED. RS – 33Ω; RG1 = RF1 = RF2 = 499Ω; C F1 = CF2 = 39pF; RG2 = 523Ω AD7356 MODES OF OPERATION These modes of operation are designed to provide flexible power management options. These options can be chosen to optimize the power dissipation/throughput rate ratio for the differing application requirements. NORMAL MODE Normal mode is intended for applications needing the fastest throughput rates because the user does not have to worry about any power-up times because the AD7356 remains fully powered at all times. Figure 24 shows the general diagram of the operation of the AD7356 in normal mode. CS 1 10 14 SDATAA SDATAB LEADING ZEROS + CONVERSION RESULT 06505-018 SCLK Figure 24. Normal Mode Operation The conversion is initiated on the falling edge of CS, as described in the Serial Interface section. To ensure that the part remains fully powered up at all times, CS must remain low until at least 10 SCLK falling edges have elapsed after the falling edge of CS. If CS is brought high any time after the 10th SCLK falling edge but before the 14th SCLK falling edge, the part remains powered up; however, the conversion is terminated and SDATAA and SDATAB go back into three-state. To complete the conversion and access the conversion result for the AD7356, 14 serial clock cycles are required. The SDATA lines do not return to threestate after 14 SCLK cycles have elapsed but instead do so when CS is brought high again. If CS is left low for another two SCLK cycles, two trailing zeros are clocked out after the data. If CS is left low for a further 14 SCLK cycles, the result for the other ADC on board is also accessed on the same SDATA line (see Figure 31 and the Serial Interface section). Once 32 SCLK cycles have elapsed, the SDATA line returns to three-state on the 32nd SCLK falling edge. If CS is brought high prior to this, the SDATA line returns to three-state at that point. Thus, CS may idle low after 32 SCLK cycles until it is brought high again sometime prior to the next conversion. The bus still returns to three-state upon completion of the dual result read. When a data transfer is complete and SDATAA and SDATAB have returned to three-state, another conversion can be initiated after the quiet time, tQUIET, has elapsed by bringing CS low again (assuming the required acquisition time has been allowed). PARTIAL POWER-DOWN MODE Partial power-down mode is intended for use in applications in which slower throughput rates are required. Either the ADC is powered down between each conversion or a series of conversions can be performed at a high throughput rate and the ADC is then powered down between these bursts of several conversions. It is recommended that the AD7356 not remain in partial power-down mode for longer than 100 μs. When the AD7356 is in partial power-down, all analog circuitry is powered down except for the on-chip reference and reference buffers. To enter partial power-down mode, the conversion process must be interrupted by bringing CS high any time after the second falling edge of SCLK and before the 10th falling edge of SCLK, as shown in Figure 25. When CS has been brought high in this window of SCLKs, the part enters partial power-down, the conversion that was initiated by the falling edge of CS is terminated, and SDATAA and SDATAB go back into three-state. If CS is brought high before the second SCLK falling edge, the part remains in normal mode and does not power down. This avoids accidental power-down due to glitches on the CS line. CS 1 2 10 14 SCLK SDATAA SDATAB THREE-STATE 06505-019 The mode of operation of the AD7356 is selected by controlling the logic state of the CS signal during a conversion. There are three possible modes of operation: normal mode, partial powerdown mode, and full power-down mode. After a conversion has is initiated, the point at which CS is pulled high determines which power-down mode, if any, the device enters. Similarly, if already in a power-down mode, CS can control whether the device returns to normal operation or remains in a power-down mode. Figure 25. Entering Partial Power-Down Mode To exit this mode of operation and power up the AD7356 again, perform a dummy conversion. On the falling edge of CS, the device begins to power up, and continues to power up as long as CS is held low until after the falling edge of the 10th SCLK. The device is fully powered up after approximately 200 ns have elapsed (or one full conversion) and valid data results from the next conversion, as shown in Figure 26. If CS is brought high before the second falling edge of SCLK, the AD7356 again goes into partial power-down. This avoids accidental power-up due to glitches on the CS line. Although the device may begin to power up on the falling edge of CS, it powers down again on the rising edge of CS. If the AD7356 is already in partial power-down mode and CS is brought high between the second and 10th falling edges of SCLK, the device enters full power-down mode. Rev. 0 | Page 15 of 20 AD7356 To reach full power-down, the next conversion cycle must be interrupted in the same way, as shown in Figure 27. When CS is brought high in this window of SCLKs, the part fully powers down. FULL POWER-DOWN MODE Full power-down mode is intended for use in applications where throughput rates slower than those in partial powerdown mode are required because power-up from a full powerdown takes substantially longer than that from a partial powerdown. This mode is more suited to applications in which a series of conversions performed at a relatively high throughput rate are followed by a long period of inactivity and, thus, powerdown. When the AD7356 is in full power-down mode, all analog circuitry is powered down including the on-chip reference and reference buffers. Full power-down mode is entered in a similar way as partial power-down mode, except that the timing sequence shown in Figure 25 must be executed twice. The conversion process must be interrupted in a similar fashion by bringing CS high anywhere after the second falling edge of SCLK and before the 10th falling edge of SCLK. The device enters partial power-down mode at this point. Note that it is not necessary to complete the 14 or 16 SCLKs once CS has been brought high to enter a power-down mode. To exit full power-down mode and power-up the AD7356, perform a dummy conversion, similar to powering up from partial power-down. On the falling edge of CS, the device begins to power up as long as CS is held low until after the falling edge of the 10th SCLK. The required power-up time must elapse before a conversion can be initiated, as shown in Figure 28. THE PART IS FULLY POWERED UP; SEE THE POWER-UP TIMES SECTION. THE PART BEGINS TO POWER UP. tPOWER-UP1 CS 1 10 SDATAA SDATAB 14 1 INVALID DATA 14 06505-020 SCLK VALID DATA Figure 26. Exiting Partial Power-Down Mode THE PART ENTERS PARTIAL POWER-DOWN MODE. THE PART BEGINS TO POWER UP. THE PART ENTERS FULL POWER-DOWN MODE. CS 1 2 SDATAA SDATAB 10 14 1 THREE-STATE INVALID DATA 2 10 INVALID DATA 14 THREE-STATE 06505-021 SCLK Figure 27. Entering Full Power-Down Mode THE PART BEGINS TO POWER UP. THE PART IS FULLY POWERED UP; SEE THE POWER-UP TIMES SECTION. tPOWER-UP2 CS SDATAA SDATAB 10 1 14 INVALID DATA 1 14 VALID DATA Figure 28. Exiting Full Power-Down Mode Rev. 0 | Page 16 of 20 06505-022 SCLK AD7356 The AD7356 has two power-down modes: partial power-down and full power-down, which are described in detail in the Normal Mode, Partial Power-Down Mode, and Full Power-Down Mode sections. This section deals with the power-up time required when coming out of any of these modes. Note that the recommended decoupling capacitors must be in place on the REFA and REFB pins for the power-up times to apply. To power up from partial power-down mode, one dummy cycle is required. The device is fully powered up after approximately 200 ns have elapsed from the falling edge of CS. When the partial power-up time has elapsed, the ADC is fully powered up, and the input signal is acquired properly. The quiet time, tQUIET, must still be allowed from the point where the bus goes back into three-state after the dummy conversion to the next falling edge of CS. To power up from full power-down mode, approximately 6 ms should be allowed from the falling edge of CS, shown in Figure 28 as tPOWER-UP2. Alternatively, if the part is to be placed into full power-down mode when the supplies are applied, three dummy cycles must be initiated. The first dummy cycle must hold CS low until after the 10th SCLK falling edge; the second and third dummy cycles place the part into full power-down mode (see Figure 27 and the Modes of Operation section). POWER vs. THROUGHPUT RATE The power consumption of the AD7356 varies with the throughput rate. When using very slow throughput rates and as fast an SCLK frequency as possible, the various powerdown options can be used to make significant power savings. However, the AD7356 quiescent current is low enough that even without using the power-down options, there is a noticeable variation in power consumption with sampling rate. This is true whether a fixed SCLK value is used or it is scaled with the sampling rate. Figure 29 shows a plot of power vs. throughput rate when operating in normal mode for a fixed maximum SCLK frequency and a SCLK frequency that scales with the sampling rate. The internal reference was used for Figure 29. Note that during power-up from partial power-down mode, the track-and-hold, which is in hold mode while the part is powered down, returns to track mode after the first SCLK edge that the part receives after the falling edge of CS. Rev. 0 | Page 17 of 20 34 30 POWER (mW) When power supplies are first applied to the AD7356, the ADC can power up in either of the power-down modes or in normal mode. Because of this, it is best to allow a dummy cycle to elapse to ensure that the part is fully powered up before attempting a valid conversion. Likewise, if the part is to be kept in partial power-down mode immediately after the supplies are applied, then two dummy cycles must be initiated. The first dummy cycle must hold CS low until after the 10th SCLK falling edge; in the second cycle, CS must be brought high between the second and 10th SCLK falling edges (see Figure 25). 38 26 80MHz SCLK 22 VARIABLE SCLK 18 14 10 06505-030 POWER-UP TIMES 0 1000 2000 3000 4000 THROUGHPUT (kSPS) Figure 29. Power vs. Throughput Rate 5000 AD7356 SERIAL INTERFACE SDATA line in use goes back into three-state on the 32nd SCLK falling edge or the rising edge of CS, whichever occurs first. Figure 30 shows the detailed timing diagram for serial interfacing to the AD7356. The serial clock provides the conversion clock and controls the transfer of information from the AD7356 during conversion. A minimum of 14 serial clock cycles is required to perform the conversion process and to access data from one conversion on either data line of the AD7356. CS falling low provides the leading zero to be read in by the microcontroller or DSP. The remaining data is then clocked out by subsequent SCLK falling edges, beginning with a second leading zero. Thus, the first falling clock edge on the serial clock has the leading zero provided and also clocks out the second leading zero. The 12-bit result then follows with the final bit in the data transfer and is valid on the 14th falling edge (having been clocked out on the previous (13th) falling edge). In applications with a slower SCLK, it may be possible to read in data on each SCLK rising edge depending on the SCLK frequency. With a slower SCLK, the first rising edge, of SCLK after the CS falling edge has the second leading zero provided, and the 13th rising SCLK edge has DB0 provided. The CS signal initiates the data transfer and conversion process. The falling edge of CS puts the track and hold into hold mode, at which point the analog input is sampled and the bus is taken out of three-state. The conversion is also initiated at this point and requires a minimum of 14 SCLKs to complete. Once 13 SCLK falling edges have elapsed, the track and hold goes back into track on the next SCLK rising edge, as shown in Figure 30 at Point B. If a 16-bit data transfer is used on the AD7356, then two trailing zeros appear after the final LSB. On the rising edge of CS, the conversion is terminated and SDATAA and SDATAB go back into three-state. If CS is not brought high, but is instead held low for an additional 14 SCLK cycles, the data from the conversion on ADC B is output on SDATAA (see Figure 31). Likewise, the data from the conversion on ADC A is output on SDATAB. In this case, the tACQUISITION CS t9 tCONVERT t6 1 3 2 4 t3 SDATAA DB11 0 0 SDATAB THREESTATE 2 LEADING ZEROS t4 DB10 B 5 13 t5 t7 DB9 DB2 DB8 tQUIET t8 DB0 DB1 THREE-STATE 06505-024 t2 SCLK Figure 30. Serial Interface Timing Diagram CS t6 1 2 3 t3 SDATAA DB11 A 0 0 THREESTATE 2 LEADING ZEROS 5 4 t4 DB10 A DB9 A t5 15 14 16 17 32 t10 t7 ZERO ZERO ZERO ZERO DB11 B 2 TRAILING ZEROS 2 LEADING ZEROS Figure 31. Reading Data from Both ADCs on One SDATA Line with 32 SCLKs Rev. 0 | Page 18 of 20 ZERO ZERO 2 TRAILING ZEROS THREESTATE 06505-025 t2 SCLK AD7356 APPLICATION HINTS GROUNDING AND LAYOUT The analog and digital supplies to the AD7356 are independent and separately pinned out to minimize coupling between the analog and digital sections of the device. The printed circuit board (PCB) that houses the AD7356 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. This design facilitates the use of ground planes that can be easily separated. To provide optimum shielding for ground planes, a minimum etch technique is generally best. The two AGND pins of the AD7356 should be sunk in the AGND plane. The REFGND pin should also be sunk in the AGND plane. Digital and analog ground planes should be joined in only one place. If the AD7356 is in a system in which multiple devices require an AGND and DGND connection, the connection should still be made at one point only, a star ground point that should be established as close as possible to the ground pins on the AD7356. Avoid running digital lines under the device because this couples noise onto the die. Allow the analog ground planes to run under the AD7356 to avoid noise coupling. The power supply lines to the AD7356 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. To avoid radiating noise to other sections of the board, shield fast switching signals such as clocks, with digital ground; and never run clock signals near the analog inputs. Avoid crossover of digital and analog signals. To reduce the effects of feedthrough within the board, traces on opposite sides of the board should run at right angles to each other. A microstrip technique is the best method but is not always possible with a double sided board. In this technique, the component side of the board is dedicated to ground planes and signals are placed on the solder side. Good decoupling is important; decouple all supplies with 10 μF tantalum capacitors in parallel with 0.1 μF capacitors to GND. To achieve the best results from these decoupling components, they must be placed as close as possible to the device, ideally right up against the device. The 0.1 μF capacitor, (including the common ceramic types or surface-mount types) should have low effective series resistance (ESR) and effective series inductance (ESI). These low ESR and ESI capacitors provide a low impedance path to ground at high frequencies to handle transient currents due to logic switching. EVALUATING THE AD7356 PERFORMANCE The recommended layout for the AD7356 is outlined in the evaluation board documentation. The evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from the PC via the converter evaluation and development board (CED). The CED can be used in conjunction with the AD7356 evaluation board (as well as many other evaluation boards ending in the ED designator from Analog Devices, Inc.) to demonstrate/ evaluate the ac and dc performance of the AD7356. The software allows the user to perform ac (fast Fourier transform) and dc (linearity) tests on the AD7356. The software and documentation are on a CD shipped with the evaluation board. Rev. 0 | Page 19 of 20 AD7356 OUTLINE DIMENSIONS 5.10 5.00 4.90 16 9 4.50 4.40 4.30 6.40 BSC 1 8 PIN 1 1.20 MAX 0.15 0.05 0.20 0.09 0.30 0.19 0.65 BSC COPLANARITY 0.10 SEATING PLANE 8° 0° 0.75 0.60 0.45 COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 32. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters ORDERING GUIDE Model AD7356BRUZ1 AD7356BRUZ-500RL71 AD7356BRUZ-RL1 AD7356YRUZ1 AD7356YRUZ-500RL71 AD7356YRUZ-RL1 EVAL-AD7356EDZ1, 2 EVAL-CED1Z1, 3 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +125°C −40°C to +125°C −40°C to +125°C Package Description 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP Evaluation Board Converter Evaluation and Development Board 1 Package Option RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 Z = RoHS Compliant Part. This evaluation board can be used as a standalone evaluation board or in conjunction with the EVAL-CED1Z board for evaluation/demonstration purposes. 3 This evaluation board is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the ED designator. 2 ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06505-0-10/08(0) Rev. 0 | Page 20 of 20