OKI MSM7524GS-K Dtmf transceiver Datasheet

E2A0024-16-X1
¡ Semiconductor
MSM7524
¡ Semiconductor
This version: Jan.
1998
MSM7524
Previous version: Nov. 1996
DTMF Transceiver
GENERAL DESCRIPTION
The MSM7524 is the single chip DTMF transceiver –generator/receiver– with the call progress
tone generator/detector and the special tone –1300 Hz in the first version, possible to be
modified– detector.
Each function block can be controlled by an external MCU via 4-bit processor interface.
The chip operates with +5 V single supply with low power consumption, and is suitable for
the telephone terminal equipment.
FEATURES
• Power supply voltage : +5 V ±10%
• Low power consumption
Operating mode : 8 mA Typ.
Power down mode : 10 mA Typ.
• 4-bit processor interface
• Dynamic range of DTMF receiver : 40 dB
• Low signal distortion output from DTMF generator
• Call progress tone detector : 330 to 640 Hz
• Call progress tone generator : 350/400/440/480 Hz
• Special tone detector: 1300 Hz ±20 Hz (for FAX)
• 3.58 MHz crystal oscillator circuit on chip
• Package :
32-pin plastic SSOP
(SSOP32-P-430-1.00–K) (Product name : MSM7524GS-K)
1/21
¡ Semiconductor
MSM7524
BLOCK DIAGRAM
FXI– (28)
–
+
OPA-IV
PRE
LPF
FX
Detector
FX (27)
PRE
LPF
C.P.T*
Detector
CP (22)
PRE
LPF
DTMF
Receiver
LPF
DTMF
Generator
GS3 (29)
CPI+ (30)
+
–
CPI– (31)
OPA-V
GS2 (32)
PBI+ (3)
+
–
PBI– (2)
OPA-I
Control
Register
A&B
GS1 (1)
PBTO (24)
PBA– (25)
–
+
OPA-III
PBAO (26)
CPTO (7)
CPA– (6)
C. P. T*
Generator
–
+
Processor
Interface
OPA-II
D1 (21)
D2 (20)
D3 (19)
D4 (18)
SCLK (14)
R/W (17)
AD0 (16)
CS (15)
CPAO (5)
SG (4)
SG
Generator
Status
Register
X1 (11)
X2 (12)
PON (10)
V DD (9)
AG (8)
DG (23)
CLKO (13)
*C. P. T : Call Progress Tone
2/21
¡ Semiconductor
MSM7524
PIN CONFIGURATION (TOP VIEW)
GS1
1
32
GS2
PBI–
2
31
CPI–
PBI+
3
30
CPI+
SG
4
29
GS3
CPAO
5
28
FXI–
CPA–
6
27
FX
CPTO
7
26
PBAO
AG
8
25
PBA–
VDD
9
24
PBTO
PON
10
23
DG
X1
11
22
CP
X2
12
21
D1
CLKO
13
20
D2
SCLK
14
19
D3
CS
15
18
D4
AD0
16
17
R/W
32-Pin Plastic SSOP
3/21
¡ Semiconductor
MSM7524
PIN DESCRIPTION
Pin No.
Name
I/O
Description
1
GS1
O
Output and two input pins of the on-chip operational amplifier (1).
2
PBI–
I
These pins are used to implement the pre-amplifier for DTMF tone
3
PBI+
I
receiving. Refer to Fig. 1.
C1
IN
PBI+/CPI+
R2
R1
R3
R2
+
PBI-/CPI-
C1
–
GS1/GS2-
IN
GS1/GS2
PBI-/CPIR3 PBI+/CPI+
SG
–
SG
(A)
+
(B)
• R1, R2, R3 ≥ 50 kW, C1 = 2.2 µF
• Voltage Gain; 1 + R2/R3.........(A)
R2/R3...............(B)
Figure 1 Receive Gain Adjustment
Voltage gain should be less than 10(20 dB).
DTMF receiver's detect and non-detect amplitude are specified as
the receive signal level at GS1.
4
SG
O
5
CPAO
O
6
CPA–
I
On-chip signal ground.
The potential is approximately half of VDD.
Output and inverting input pins of the on-chip operational amplifier
(II). The non-inverting input is internally connected to SG. When
not using this amplifier, these pins should be wired to each other.
Call progress tone (CPT) output. Tone amplitude is approximately
0 dBm on CPTO, but the transmit signal level can be adjusted by
using the on-chip operational amplifier (II). Refer to Fig. 2.
Make/Break of CPT transmitting is controlled through the
processor interface.
PBTO/CPTO
7
CPTO
GENERATOR
R4
O
PBA/CPA
–
+
R5
OUT
PBAO/CPAO
SG
• R4, R5, ≥ 20 kW
• Voltage Gain; R5/R4 £ 10(20 dB)
Figure 2 Transmit Gain Adjustment
4/21
¡ Semiconductor
MSM7524
Pin No.
Name
I/O
8
AG
—
9
VDD
—
Description
Analog ground, 0 V.
This pin should be common with DG (pin 23) at the system ground point.
Power supply, +5 V.
Power down control.
10
PON
I
When digital "1" is applied to PON, the whole circuitry on chip falls
into the power down mode.
This pin is pulled-up to digit "1" internaly.
X1 and X2 are connected to a 3.579545 MHz crystal to generate a
11
X1
I
crystal clock for the chip.
If required to use an external clock, X1 should be left open and X2
12
X2
O
should be connected to the external clock source via a capacitor
of 100 pF.
13
CLKO
O
3.579545 MHz clock output.
External processor interface clock input.
During "WRITE" mode, the data on D4 to D1 pins are written into the
internal register at the falling edge of SCLK. During "READ" mode,
14
SCLK
I
the output data from the internal register appears on D4 to D1 pins
at the rising edge of SCLK.
SCLK is not required to be a periodic clock pulse stream. SCLK is
internally pulled-down to digital "0".
Chip select.
15
CS
I
When CS is on digital "0", "READ" and "WRITE" operations become
possible. CS is internally pulled-down.
Address data input.
When digital "1" is applied to AD0, data writing into the control
16
ADO
I
register and data reading out from the status register become possible.
When digital "0" is applied to, data writing into the DTMF tone transmit
register and data reading out from the DTMF tone receive register
become possible. AD0 is internally pulled-down.
"READ" and "WRITE" control signal input.
"READ" or "WRITE" operation becomes possible during digital "1" or "0",
17
R/W
I
18
D4
I/O
19
D3
I/O
4-bit micro-processor interface bus.
20
D2
I/O
All pins are internally pulled-down.
21
D1
I/O
respectively.
R/W is internally pulled-down to digital "0".
5/21
¡ Semiconductor
Pin No.
Name
MSM7524
I/O
Description
Call progress tone detect.
When the tone is detected, CP shows digital "1" state. Detected call progress
22
CP
O
tone frequency and amplitude range are specified as follows.
Frequency; 330 to 640 Hz
Amplitude; 0 to –40 dBm (at GS2)
23
DG
—
Digital ground, 0 V.
This pin should be common with AG (pin 8) at the system ground point.
DTMF tone output.
The signal amplitude of the low-group and the high-group tones are
–6.5 dBm and –5.5 dBm at PBTO, respectively, but, the transmit signal
24
PBTO
O
amplitude can be adjusted by applying the on-chip operational amplifier
(III). Refer to Fig. 2.
Make/Break of DTMF tone transmitting is controlled through the
processor interface.
25
PBA–
I
26
PBAO
O
Inverting input and output pins of the on-chip operational amplifier
(III).
The non-inverting input is internally connected to SG. When not
using this amplifier, these pins should be wired to each other.
Special tone detect.
The MSM7524 first version provides this function for 1300 Hz tone
which is well-known for FAX auto-receipt.
When the tone is detected, FX shows digital "1" state.
27
FX
O
Detected tone frequency and amplitude range are specified as
follows.
Frequency: 1280 to 1320 Hz
Amplitude: 0 to –34 dBm (at GS3)
When CP is on digital "1" (call progress tone is detected), FX is
forced to be on digital "0" state regardless of the special tone existence.
6/21
¡ Semiconductor
Pin No.
Name
MSM7524
I/O
Description
Special tone input and gain adjustment.
FXI- and GS3 are connected to the inverting input and the output of
the on-chip operational amplifiers (IV). The inverting input of the
28
FXI–
I
amplifier (IV) is internally connected to SG.
When not using the special tone detect function, FXI- and GS3
should be wired to each other.
Regarding the gain adjustment, refer to Fig. 3.
C1
R2
IN
FXI-
–
+
R3
GS3
29
GS3
SG
O
• R2, R3, ≥ 50 kW, C1 = 2.2 µF
• Voltage Gain; R3/R2 £ 10 (20 dB)
Figure 3 Receive Gain Adjustment for FX
Two input and output pins of the on-chip operational amplifier (V).
30
CPI+
I
These pins are useful to implement the pre-amplifier for Call
Progress Tone receiving.
31
CPI–
I
Refer to Fig. 1.
Voltage gain should be less than 10 (20 dB).
32
GS2
O
Detect and non-detect amplitude are specified as the receive signal
level at GS2.
7/21
¡ Semiconductor
MSM7524
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Condition
Ta = 25°C
Rating
Unit
–0.3 to +7
V
Power Supply Voltage
VDD
Input Voltage
VIN
AG or DG
0.3 to VDD + 0.3
V
Storage Temperature
TSTG
—
–55 to +150
°C
With respect to
RECOMMENDED OPERATING CONDITIONS
Parameter
Power Supply Voltage
Symbol
Condition
Min.
Typ.
Max.
Unit
VDD
—
+4.5
+5.0
+5.5
V
Operating Temperature
Top
—
–25
—
+85
°C
Input Clock Frequency
fCLK
External Clock
–0.1
—
+0.1
%
VDD
CVA
Between VDD and AG
0.1 + 10
—
—
mF
SG
CSA
Between SG and AG
1
—
—
mF
tlr
CS, AD0, R/W,
—
—
50
ns
Bypass Capacitor
Digital Input Rise Time
tlf
D4 to D1, PON, SCLK
—
—
50
ns
Frequency Deviation
—
+25°C ±5°C
–100
—
+100
ppm
Temperature Characteristics
—
At –25°C to 85°C
–50
—
+50
ppm
—
—
—
—
50
W
—
—
—
16
—
pF
Crystal
Digital Input Fall Time
Equivalent Series
Resistance
Load Capacitance
8/21
¡ Semiconductor
MSM7524
ELECTRICAL CHARACTERISTICS
DC and Digital Inerface Characteristics
(VDD = +5 V ±10%, Ta = –25°C to 85°C)
Parameter
Power Supply Voltage
Input Voltage
Symbol
Condition
Min.
Typ.
Max.
Unit
IDD1
Operating Mode
—
8.0
11.0
mA
IDD2
Power Down Mode
VIH
Output Voltage
Analog Output Offset Voltage
VOH
VOL
VOFF
100
mA
VDD
V
0.0
—
0.8
V
–10
—
+80
–10
—
+10
–10
—
+10
PON
–80
—
+10
IOH = –0.4 mA
2.4
—
VDD
V
IOL = 1.6 mA
0.0
0.2
0.4
V
–100
—
+100
mV
—
10
—
MW
20
—
—
MW
SCLK, CS, AD0,
VI =
5V
Input Leakage Current
IIL
10
—
—
VIL
IIH
—
2.2
PON
SCLK, CS, AD0,
VI =
0V
—
R/W, D1 to D4
R/W, D1 to D4
CPAO, PBAO
mA
mA
CPI+, CPI-, PBI+,
Analog Input Resistance
RIN
PBI-, FXI-, PBA-,
CPAPBTO, PBAO,
Analog Output Resistance
ROUT
CPTO, CPAO, GS1,
GS2, GS3
9/21
¡ Semiconductor
MSM7524
ANALOG INTERFACE CHARACTERISTICS
DTMF Generator
Parameter
DTMF Tone Transmit Amplitude
Tone Transmit Amplitude Ratio
(VDD = +5 V ±10%, Ta = –25°C to 85°C)
Symbol
Condition
Min.
Typ.
Max.
Unit
Low Group Tone
–8.5
–6.5
–4.5
dBm
VPBTH
High Group Tone
–7.5
–5.5
–3.5
dBm
VPBDF
VPBTH-VPBTL
0.0
1.0
2.0
dB
—
—
±1.5
%
—
—
–23
dB
4 to 8 kHz
—
—
P-20
dB
8 to 12 kHz
—
—
P-60
dB
12 kHz to
—
—
P-60
dB
VPBTL
Tone Frequency Accuracy
fDPB
Total Harmonic Distortion
THDPB
at
PBTO
Out-of-Band Spurious *
To Nominal
Rrequency
Total Harmonics
- Fundamental
VSPS
*P: Inband energy
Call Progress Tone (CPT) Generator
(VDD = +5 V ±10%, Ta = –25°C to 85°C)
Parameter
Tone Amplitude
Tone Transmit Amplitude Ratio
Symbol
Condition
Typ.
Max.
Unit
VCPT
—
–2.0
0
2.0
dBm
fCPT0
CPT2 = 0, CPT1 = 0
380
400
420
Hz
CPT2 = 0, CPT1 = 1
330
350
370
Hz
CPT2 = 1, CPT1 = 0
420
440
460
Hz
CPT2 = 1, CPT1 = 1
460
480
500
Hz
—
—
–23
dB
fCPT1
fCPT2
at
CPTO
fCPT3
Tone Harmonic Distortion
Min.
THDCPT
—
Total Harmonics
– Fundamental
10/21
¡ Semiconductor
MSM7524
Call Progress Tone (CPT) Detector
(VDD = +5 V ±10%, Ta = –25°C to 85°C)
Parameter
Symbol
Condition
Min.
Typ.
Detect Amplitude
VDETCP
fIN: 330 to 640 Hz,
–40
Non-detect Amplitude
VREJCP
at GS2
—
Hysteresis of Detect Amplitude
VHYSCP
—
—
Detect Frequency
fDETCP
—
330
Time to Detect
tDETCP
Detect
Time to Reject
tREJCP
Non-detect
Detect Delay Time
tDELCP
Detect Hold Time
tHOLCP
Non-detect Frequency
Refer to Fig. 4.
fREJCP
—
Max.
Unit
—
0
dBm
—
–60
dBm
4.0
—
dB
—
640
Hz
70
—
—
ms
—
—
35
ms
35
50
70
ms
ms
—
50
—
700
—
—
—
—
270
Hz
tDETCP
tREJCP
CPI
tDELCP
tHOLCP
CP
Figure 4 CPT Detect Timing
11/21
¡ Semiconductor
MSM7524
Special Tone (ex. F-tone for FAX auto-receipt) Detector
(VDD = +5 V ±10%, Ta = –25°C to 85°C)
Parameter
Symbol
Condition
Min.
Typ.
Detect Amplitude
VDETFX
fIN : 1,300 Hz ±20 Hz,
–34
Non-detect Amplitude
VREJFX
at GS3
—
Hysteresis of Detect Amplitude
VHYSFX
—
Detect Frequency
fDETFX
—
Time to Detect
tDETFX
Detect
Non-detect
Time to Reject
tREJFX
Detect Delay Time
tDELFX
Detect Hold Time
tHOLFX
Non-detect Frequency
Max.
Unit
—
0
dBm
—
–60
dBm
—
4.0
—
dB
1,280
—
1,320
Hz
70
—
—
ms
Refer to Fig. 5.
fREJFX
—
—
—
35
ms
35
50
70
ms
ms
—
50
—
1360
—
—
—
—
1240
Hz
tDETFX
tREJFX
FXI
tDELFX
tHOLFX
FX
Figure 5 Special Tone Detect Timing
12/21
¡ Semiconductor
MSM7524
DTMF Receiver
(VDD = +5 V ±10%, Ta = –25°C to 85°C)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
Detect Amplitude
VDETDT
fIN : Nominal
–40
—
0
dBm
Non-detect Amplitude
VREJDT
Frequency ±1.5%, at GS1
—
—
–60
dBm
—
—
±1.5
%
±3.8
—
—
%
Detect Frequency
fDETDT
Non-detect Frequency
fREJDT
Level Twist
To Nominal Frequency
VTWIST
VHigh Group–VLow Group
–6.0
—
+6.0
dB
Noise to Signal Ratio (N/S)
VN/S
N : 0.3 to 3.4 kHz
—
–12
—
dB
Dial Tone Rejection Ratio
VREJ
350 to 480 Hz
22
—
—
dB
Signal Repetition Time
tCYCDT
120
—
—
Time to Detect
tDETDT
Detect
49
—
—
Time to Reject
tREJFDT
Non-detect
—
—
24
Interdigit Pause
tPAUDT
30
—
—
Acceptable Drop Out
tBRKDT
Detect Delay Time
tDELDT
Detect Hold Time
tHOLDT
Refer to Fig. 6.
tCYCDT
tDETDT
tPAUDT
tREJDT
—
—
2
24
41
49
21
28
35
ms
tBRKDT
PBI
tDELDT
tHOLDT
D4 to D1
SP
Figure 6 DTMF Receiver Timing
13/21
¡ Semiconductor
MSM7524
Processor Interface Characteristics
(VDD = +5 V ±10%, Ta = –25°C to 85°C)
Parameter
SCLK Period
CS
R/W
Condition
Min.
Typ.
Max.
tCYC
Refer to Fig. 7.
1
—
—
tHI
Digital "1"
400
—
—
tLO
Digital "0"
400
—
—
Setup Time
tAS
AD0 Æ SCLK
80
—
—
Hold Time
tAH
SCLK Æ AD0
10
—
—
Setup Time
tCS
CS Æ SCLK
80
—
—
SCLK Pulse Width
AD0
Symbol
Hold Time
tCH
SCLK Æ CS
10
—
—
Setup Time
tRWS
R/W Æ SCLK
80
—
—
Hold Time
tRWH
SCLK Æ R/W
10
—
—
Setup Time
tDWS
D4 to D1 Æ SCLK
80
—
—
(Write)
Hold Time
tDWH
SCLK Æ D4 to D1
10
—
—
D4 to D1
Delay Time
tDRD
SCLK Æ D4 to D1
—
—
150
(Read)
Hold Time
tDRH
D4 to D1 Æ SCLK
10
—
—
D4 to D1
Unit
ns
tCYC
tHI
tLO
SCLK
tAS
tAH
tAS
tAH
tCS
tCH
tCS
tCH
tRWS
tRWH
tRWS
tRWH
ADO
CS
R/W
tDWH
tDWS
D4 to D1
tDRD
tDRH
DATA
DATA
"WRITE"
"READ"
Figure 7 Processor Interface READ/WRITE Timing
14/21
¡ Semiconductor
MSM7524
PROCESSOR INTERFACE
Internal Register Address and Function
Table-1
AD0
R/W
READ/WRITE
Registers
0
0
WRITE
DTMF Tone Transmit Data
0
1
READ
DTMF Tone Receive Data
1
0
WRITE
Control Data
1
1
READ
Status Data
DTMF Tone Transmit/Receive Data Registers
Table-2
Low-Group Tone
High-Group Tone
(Hz)
(Hz)
D4
D3
D2
D1
Digit
0
0
0
1
1
0
0
1
0
2
0
0
1
1
3
1477
0
1
0
0
4
1209
0
1
0
1
5
0
1
1
0
6
0
1
1
1
7
1
0
0
0
8
1
0
0
1
9
1477
1
0
1
0
0
1336
1
0
1
1
*
1209
697
770
1336
1336
1477
1209
852
941
1
1
0
0
#
1
1
0
1
A
697
1
1
1
0
B
770
1
1
1
1
C
852
0
0
0
0
D
941
1336
1209
1477
1633
15/21
¡ Semiconductor
MSM7524
Control Data Register A
Table-3-1
D4
D3
D2
D1
RSEL
—
CPEN
MFC
Table-3-2
Bit
Name
Function
Control data register select.
"0" : Register A is selected.
D4
RSEL
"1" : Register B is selected on the next Write cycle to the Control Register address.
Subsequent Write cycles to the Control Register are directed back to Control
Register A.
D3
—
Not used. Set to digital "0" or "1".
Call Progress Tone (CP)/Special tone (FX) detect control.
D2
CPEN
"0" : Disable CP and FX. Both CP and FX are held on digital "0".
"1" : Enable CP and FX.
DTMF Tone Transmit Make/Break control.
D1
MFC
"0" : Disable. PBTO outputs only DC potential at SG.
"1" : Enable. DTMF tone is generated via PBTO.
16/21
¡ Semiconductor
MSM7524
Control Data Register B
Table-4-1
D4
D3
D2
D1
CPT2
CPT1
CPTC
—
Table-4-2
Bit
Name
Function
Call Progress tone frequency select.
D4
D3
CPT2
CPT1
Frequency (Hz)
CPT2
0
0
400
CPT1
0
1
350
1
0
440
1
1
480
Call Progress tone Transmit/Make/Break control.
D2
CPTC
D1
MFC
"0" : Disable. CPTO outputs only DC potential at SG.
"1" : Enable. Call Progress tone is generated via CPTO.
Not used. Set to digital "0" or "1".
Note) All control data on Registers A and B should be cleared by software and/or PON control.
Power-down control by PON makes all logic status and control data to be cleared.
17/21
¡ Semiconductor
MSM7524
Status Data Register
Table-5-1
D4
D3
D2
D1
SP
SPFLG
CPFLG
AFLG
Table-5-2
Bit
Name
Function
Signal Present for DTMF tone receive.
D4
SP
"0" : Valid data is in the receive data register.
"1" : Data is invalid.
D3
SPFLG
D2
CPFLG
D1
AFLG
Flag for valid DTMF tone receive.
SPFLG is reset to digital "0" after an external processor reads out the status register data.
Flag for valid Call Progress tone detect.
CPFLG is reset to digital "0" after an external processor reads out the status register data.
AFLG is set to digital "1" when SPFLG and/or CPFLG is set to digital "1".
After an external processor reads out the status register data, AFLG is reset to digital "0".
18/21
¡ Semiconductor
MSM7524
PROCESSOR CONTROL
Table-6
An example of the micro-processor control for each mode is shown in Table-6.
Mode
q
Power
w
ON
CS AD0 R/W D4
Processor Control
Clear CRA.
(CRB is selected next.)
Clear CRB.
(CRA is selected next.)
e Next mode is selected.
q
w
DTMF
Tone Receive
e
Observe STR.
(Non detect state)
Observe STR.
(Detect state)
Observe STR.
(Detect state or After read STR)
r Read RR.
t
Observe STR.
(For next tone)
q CPT detect enable.
w
CPT
Detect
e
r
Observe STR.
(Non detect state)
Observe STR.
(Detect state)
Observe STR*.
(Detect state or After read STR)
q DTMF tone data.
DTMF
w
Tone Transmit
e
DTMF tone
transmit "Make".
DTMF tone
transmit "Break".
q Select CRB.
w
CPT
Transmit
CPT
transmit ON.
e Select CRB.
r
CPT
transmit OFF.
Transmit
"Make"
Transmit
"Break"
D3
D2
D1
Valid
Register
0
1
0
1
0
0
0
CRA
0
1
0
0
0
0
0
CRB
0
1
0
X
X
X
X
CRA
0
1
1
1
0
0
0
STR
0
1
1
0
1
0
1
STR
0
1
1
0
0
0
0
STR
0
0
1
X
X
X
X
RR
0
1
1
1
0
0
0
STR
0
1
0
0
—
1
0
CRA
0
1
1
1
0
0
0
STR
0
1
1
1
0
1
1
STR
0
1
1
1
0
0
0
STR
0
0
0
X
X
X
X
TR
0
1
0
0
—
0
1
CRA
0
1
0
0
—
0
0
CRA
0
1
0
1
—
0
0
CRA
0
1
0
X
X
1
—
CRB
0
1
0
1
—
0
0
CRA
0
1
0
X
X
0
—
CRB
* CP is still held on digital "1" while CPT is detected.
Note) CPT :
CRA :
CRB :
STR :
Call Progress Tone
Control Resister A
Control Register B
Status Register
TR
RR
X
—
:
:
:
:
DTMF Tone Transmit Register
DTMF Tone Receive Register
Expected Data
Digital " 0" or "1"
19/21
¡ Semiconductor
MSM7524
APPLICATION CIRCUIT
MSM7524
R1
DTMF Tone
Analog
Input
C1
R2
32 R3
1
GS1
GS2
PBI-
CPI-
PBI+
CPI+
SG
GS3
CPA0
FXI-
CPA-
FX
CPT0
PBA0
AG
PBA-
VDD
PBT0
31
2
4
5
0V
C6
+5 V
R6
23
PON
DG
X1
CP
C3
Special Tone
Analog
Input
X2
D1
CLK0
D2
SCLK
D3
CS
D4
DTMF Tone
(Load ≥ 50 kW)
22
11
21
12
20
19
14
15
28
24
9
Crystal
13
3.579545 MHZ
SG
25
8
10
29 R5
26
7
–
+ C5
CPT
Analog
Input
27
6
CPT Output
(Load ≥ 50 kW)
C2
30
3
C4
R4
18
To MPU
17
16
AD0
R/W
R1 to R6 ≥ 50 kW, C1, C2, C3 = 0.22 µF, C4, C5 = 1 µF, C6 = 10 µF
DTMF Tone :
Receive Gain
R1/R2
*R1 = R2 = 50 kW, Receive Range : –40 to 0 dBm
CPT Detect :
Gain
R3/R4
*R3 = R4 = 50 kW, Detect Range : –40 to 0 dBm
Special Tone :
Detect Gain
R5/R6
*R5 = 100 kW, Detect Range : –40 to 6 dBm
R6 = 50 kW
Note) The decoupling capacitors (C4, C5, C6) should be connected close to the
device.
20/21
¡ Semiconductor
MSM7524
PACKAGE DIMENSIONS
(Unit : mm)
SSOP32-P-430-1.00-K
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
0.60 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
21/21
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