IDT72105 IDT72115 IDT72125 CMOS PARALLEL-TO-SERIAL FIFO 256 x 16, 512 x 16, 1024 x 16 Integrated Device Technology, Inc. FEATURES: DESCRIPTION: • • • • • The IDT72105/72115/72125s are very high-speed, lowpower,dedicated, parallel-to-serial FIFOs. These FIFOs possess a 16-bit parallel input port and a serial output port with 256, 512 and 1K word depths, respectively. The ability to buffer wide word widths (x16) make these FIFOs ideal for laser printers, FAX machines, local area networks (LANs), video storage and disk/tape controller applications. Expansion in width and depth can be achieved using multiple chips. IDT’s unique serial expansion logic makes this possible using a minimum of pins. The unique serial output port is driven by one data pin (SO) and one clock pin (SOCP). The Least Significant or Most Significant Bit can be read first by programming the DIR pin after a reset. Monitoring the FIFO is eased by the availability of four status flags: Empty, Full, Half-Full and Almost-Empty/AlmostFull. The Full and Empty flags prevent any FIFO data overflow or underflow conditions. The Half-Full Flag is available in both single and expansion mode configurations. The Almost-Empty/ Almost-Full Flag is available only in a single device mode. The IDT72105/15/25 are fabricated using IDT’s leading edge, submicron CMOS technology. Military grade product is manufactured in compliance with the latest revision of MilSTD-883, Class B. • • • • 25ns parallel port access time, 35ns cycle time 45MHz serial output shift rate Wide x16 organization offering easy expansion Low power consumption (50mA typical) Least/Most Significant Bit first read selected by asserting the FL/DIR pin Four memory status flags: Empty, Full, Half-Full, and Almost-Empty/Almost-Full Dual-Port zero fall-through architecture Available in 28-pin 300 mil plastic DIP and 28-pin SOIC Industrial temperature range (-40oC to +85oC) is available, tested to military electrical specifications FUNCTIONAL BLOCK DIAGRAM D 0–15 W RS 16 RESET LOGIC WRITE POINTER RAM ARRAY 256 x 16 512 x 16 1024 x 16 READ POINTER RSIX RSOX EXPANSION LOGIC FLAG LOGIC FL/DIR FF EF HF AEF SERIAL OUTPUT LOGIC The IDT logo is a registered trademark of Integrated Device Technology, Inc. FAST is a trademark of National Semiconductor Co. SOCP SO COMMERCIAL TEMPERATURE RANGE 1996 Integrated Device Technology, Inc. 2665 drw 01 DECEMBER 1996 For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391. 5.35 DSC-2665/6 1 IDT72105, IDT72115, IDT72125, 256 x 16, 512 x 16, 1024 x 16 PARALLEL-TO-SERIAL CMOS FIFO COMMERCIAL TEMPERATURE RANGES PIN CONFIGURATION W D0 D1 D2 D3 D4 D5 D6 D7 EF FF HF RSIX GND 1 28 2 27 3 26 4 25 5 24 6 7 P28-2 SO28-3 23 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 Vcc D 15 D 14 D 13 D 12 D 11 D 10 D9 D8 RS SO SOCP RSOX/AEF FL/DIR 2665 drw 02a DIP/SOIC TOP VIEW PIN DESCRIPTIONS Symbol Name I/O Description D0–D15 Inputs I RS Reset I W Write I SOCP Serial Output Clock I First Load/ Direction I This is a dual purpose input used in the width and depth expansion configurations. The First Load ( FL) function is programmed only during Reset (RS ) and a LOW on FL indicates the first device to be loaded with a byte of data. All other devices should be programmed HIGH. The Direction (DIR) pin controls shift direction after Reset and tells the device whether to read out the Least Significant or Most Significant bit first. RSIX Read Serial In Expansion I In the single device configuration, RSIX is set HIGH. In depth expansion or daisy chain expansion, RSIX is connected to RSOX (expansion out) of the previous device. SO Serial Output O Serial data is output on the Serial Output (SO) pin. Data is clocked out LSB or MSB depending on the Direction pin programming. During Expansion the SO pins are tied together. FF Full Flag O When FF goes LOW, the device is full and further WRITE operations are inhibited. When HIGH, the device is not full. FF is EF Empty Flag O When EF goes LOW, the device is empty and further READ operations are inhibited. When HIGH, the device is not empty. EF is HF Half-Full Flag O When HF is LOW, the device is more than half-full. When HF is HIGH, the device is empty to half-full. FL/DIR RSOX/AEF Read Serial Out Expansion Almost-Empty, Almost-Full Flag O Data inputs for 16-bit wide data. When RS is set low, internal READ and WRITE pointers are set to the first location of the RAM array. FF and HF go HIGH. EF and AEF go LOW. A reset is required before an initial WRITE after power-up. W must be high during the RS cycle. Also the First Load pin (FL) is programmed only during Reset. A write cycle is initiated on the falling edge of WRITE if the Full Flag (FF) is not set. Data set-up and hold times must be adhered to with respect to the rising edge of WRITE. Data is stored in the RAM array sequentially and independently of any ongoing read operation. A serial bit read cycle is initiated on the rising edge of SOCP if the Empty Flag (EF) is not set. In both Depth and Serial Word Width Expansion modes, all of the SOCP pins are tied together. This is a dual purpose output. In the single device configuration (RSIX HIGH), this is an AEF output pin. When AEF is LOW, the device is empty-to-(1/8 full -1) or (7/8 full +1)-to-full. When AEF is HIGH, the device is 1/8-full up to 7/8-full. In the Expansion configuration (RSOX connected to RSIX of the next device) a pulse is sent from RSOX to RSIX to coordinate the width, depth or daisy chain expansion. VCC Power Supply Single power supply of 5V. GND Ground Single ground of 0V. 2665 tbl 01 5.35 2 IDT72105, IDT72115, IDT72125, 256 x 16, 512 x 16, 1024 x 16 PARALLEL-TO-SERIAL CMOS FIFO COMMERCIAL TEMPERATURE RANGE STATUS FLAGS Number of Words in FIFO IDT72105 IDT72115 IDT72125 FF AEF HF EF 0 0 0 H L H L 1–31 1–63 1–127 H L H H 32–128 64–256 128–512 H H H H 129–224 257–448 513–896 H H L H 225–255 449–511 897–1023 H L L H 256 512 1024 L L L H 2665 tbl 02 RECOMMENDED DC OPERATING CONDITIONS (1) ABSOLUTE MAXIMUM RATINGS Symbol VTERM TA TBIAS TSTG IOUT Rating Terminal Voltage with Respect to GND Operating Temperature Temperature Under Bias Storage Temperature DC Output Current Commercial –0.5 to + 7.0 Unit V 0 to +70 °C –55 to +125 °C –55 to + 125 °C 50 mA Symbol Parameter Min. Typ. Max. Unit VCC Supply Voltage 4.5 5.0 5.5 V GND Supply Voltage 0 0 0 V VIH Input High Voltage 2.0 — — V VIL(1) Input Low Voltage — — 0.8 V NOTE: 1. 1.5V undershoots are allowed for 10ns once per cycle. 2665 tbl 04 NOTE: 2665 tbl 03 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DC ELECTRICAL CHARACTERISTICS (Commercial VCC = 5.0V ± 10%, TA = 0°C to +70°C) IDT72105/IDT72115/ IDT72125 Commercial Symbol I IL (1) Parameter Input Leakage Current (Any Input) Min. Typ. –1 — Max. Unit 1 µA IOL(2) Output Leakage Current –10 — 10 µA VOH Output Logic "1" Voltage I OUT = –2mA(5) 2.4 — — V — — 0.4 V 8mA(6) VOL Output Logic "0" Voltage IOUT = ICC1 (3) Power Supply Current — 50 100 mA ICC2 (3) Average Standby Current — 4 8 mA — 1 6 mA (W = RS = FL/DIR = VIH)(SOCP = VIL ) ICC3 (3,4,7) Power Down Current NOTES: 1. Measurements with 0.4V ≤ VIN ≤ VCC. 2. SOCP = VIL, 0.4 ≤ VOUT ≤ VCC. 3. ICC measurements are made with outputs open. 4. RS = FL/DIR = W = VCC - 0.2V; SOCP = 0.2V; all other inputs ≥ VCC - 0.2 or ≤ 0.2V. 5. For SO, IOUT = -4mA. 6. For SO, IOUT = 16mA. 7. Measurements are made after reset. 5.35 2665 tbl 05 3 IDT72105, IDT72115, IDT72125, 256 x 16, 512 x 16, 1024 x 16 PARALLEL-TO-SERIAL CMOS FIFO COMMERCIAL TEMPERATURE RANGES AC ELECTRICAL CHARACTERISTICS (Commercial: VCC = 5V±10%, TA = 0°C to +70°C) COM'L 72105L25 72115L25 72125L25 Symbol Parameter 72105L50 72115L50 72125L50 Figure Min. Max. Min. Max. Unit tS Parallel Shift Frequency — — 28.5 — 15 MHz tSOCP Serial Shift Frequency — — 50 — 40 MHz PARALLEL INPUT TIMINGS tWC Write Cycle Time 2 35 — 65 — ns tWPW Write Pulse Width 2 25 — 50 — ns tWR Write Recovery Time 2 10 — 15 — ns tDS Data Set-up Time 2 12 — 15 — ns tDH Data Hold Time 2 0 — 2 — ns tWEF Write High to EF HIGH 5, 6 — 35 — 45 ns tWFF tWF tWPF Write Low to FF LOW Write Low to Transitioning HF, AEF Write Pulse Width After FF HIGH 4, 7 — 35 — 45 ns 8 — 35 — 45 ns 7 25 — 50 — ns 20 — 25 — ns SERIAL OUTPUT TIMINGS tSOCP Serial Clock Cycle Time 3 tSOCW Serial Clock Width HIGH/LOW 3 8 — 10 — ns tSOPD SOCP Rising Edge to SO Valid Data 3 — 14 — 15 ns 3 3 14 3 15 ns SOCP Rising Edge to SO at High-Z (1) tSOLZ SOCP Rising Edge to SO at Low-Z (1) tSOCEF SOCP Rising Edge to EF LOW tSOHZ tSOCFF tSOCF tREFSO SOCP Rising Edge to FF HIGH SOCP Rising Edge to Transitioning HF, AEF SOCP Delay After EF HIGH 3 3 14 3 15 ns 5, 6 — 35 — 45 ns 4, 7 — 35 — 45 ns 8 — 35 — 45 ns 6 35 — 65 — ns RESET TIMINGS tRSC Reset Cycle Time 1 35 — 65 — ns tRS Reset Pulse Width 1 25 — 50 — ns tRSS Reset Set-up Time 1 25 — 50 — ns tRSR Reset Recovery Time 1 10 — 15 — ns 9 7 — 8 — ns EXPANSION MODE TIMINGS tFLS tFLH FL Set-up Time to RS Rising Edge FL Hold Time to RS Rising Edge 9 0 — 2 — ns tDIRS DIR Set-up Time to SOCP Rising Edge 9 10 — 12 — ns tDIRH DIR Hold Time from SOCP Rising Edge 9 5 — 5 — ns tSOXD1 SOCP Rising Edge to RSOX Rising Edge 9 — 15 — 17 ns tSOXD2 SOCP Rising Edge to RSOX Falling Edge 9 — 15 — 17 ns tSIXS RSIX Set-up Time to SOCP Rising Edge 9 5 — 8 — ns tSIXPW RSIX Pulse Width 9 10 — 15 — ns NOTE: 1. Values guaranteed by design. 2665 tbl 06 5.35 4 IDT72105, IDT72115, IDT72125, 256 x 16, 512 x 16, 1024 x 16 PARALLEL-TO-SERIAL CMOS FIFO COMMERCIAL TEMPERATURE RANGE AC TEST CONDITIONS Input Pulse Levels 5V GND to 3.0V Input Rise/Fall Times 5ns Input Timing Reference Levels 1.5V Output Reference Levels 1.5V Output Load 1.1KΩ TO OUTPUT PIN See Figure A 2665 tbl 07 30pF * 680Ω CAPACITANCE (TA = +25°C, f = 1.0MHz) 2665 drw 03 Parameter(1) Conditions Max. Unit CIN Input Capacitance VIN = 0V 10 pF COUT Output Capacitance VOUT = 0V 12 pF Symbol NOTE: or equivalent circuit Figure A. Output Load 2665 tbl 08 *Includes jig and scope capacitances. 1. This parameter is sampled and not 100% tested. FUNCTIONAL DESCRIPTION Parallel Data Input The device must be reset before beginning operation so that all flags are set to their initial state. In width or depth expansion the First Load pin (FL) must be programmed to indicate the first device. The data is written into the FIFO in parallel through the D0– 15 input data lines. A write cycle is initiated on the falling edge of the Write (W) signal provided the Full Flag (FF) is not asserted. If the W signal changes from HIGH-to-LOW and the Full Flag (FF) is already set, the write line is internally inhibited internally from incrementing the write pointer and no write operation occurs. Data set-up and hold times must be met with respect to the rising edge of Write. On the rising edge of W, the write pointer is incremented. Write operations can occur simultaneously or asynchronously with read operations. Serial Data Output The serial data is output on the SO pin. The data is clocked out on the rising edge of SOCP providing the Empty Flag (EF) is not asserted. If the Empty Flag is asserted then the next data word is inhibited from moving to the output register and being clocked out by SOCP. The serial word is shifted out Least Significant Bit or Most Significant Bit first, depending on the FL/DIR level during operation. A LOW on DIR will cause the Least Significant Bit to be read out first. A HIGH on DIR will cause the Most Significant Bit to be read out first. tRSC tRS RS tRSS tRSR W tRSC FLAG STABLE AEF, EF tRSC FLAG STABLE HF, FF tRSS SOCP tRSR NOTE 2 tFLS tFLH FL/DIR 2665 drw 04 NOTES: 1. EF, FF, HF and AEF may change status during Reset, but flags will be valid at tRSC. 2. SOCP should be in the steady LOW or HIGH during tRSS. The first LOW-HIGH (or HIGH-LOW) transition can begin after tRSR. Figure 1. Reset 5.35 5 IDT72105, IDT72115, IDT72125, 256 x 16, 512 x 16, 1024 x 16 PARALLEL-TO-SERIAL CMOS FIFO COMMERCIAL TEMPERATURE RANGES t WC t WPW t WR W D 0–15 t DS 2665 drw 05 t DH Figure 2. Write Operation 1/t SOCP 0 1 n–1 SOCP t SOCW t SOCW SO (First Device in Width Expansion Mode) t SOHZ SO (Single Device Mode or Second Device in Width Expansion Mode) t SOLZ t SOPD NOTE: 1. In Single Device Mode, SO will not tri-state except after reset. Figure 3. Read Operation LAST WRITE IGNORED WRITE FIRST READ 0 1 n–1 2665 drw 06 ADDITIONAL READS 0 1 n–1 FIRST WRITE SOCP W t SOCFF t WFF FF 2665 drw 07 Figure 4. Full Flag from Last Write to First Read LAST READ NO READ FIRST WRITE ADDITIONAL WRITES FIRST READ W 0 1 n–1 0 1 n–1 NOTE 1 SOCP t SOCEF t SOCFF EF t SOPD SO VALID VALID VALID 2665 drw 08 NOTE: 1. SOCP should not be clocked until EF goes HIGH. Figure 5. Empty Flag from Last Read to First Write 5.35 6 IDT72105, IDT72115, IDT72125, 256 x 16, 512 x 16, 1024 x 16 PARALLEL-TO-SERIAL CMOS FIFO COMMERCIAL TEMPERATURE RANGE DATA IN W t WEF t SOCEF EF t 0 REFSO 1 n–1 NOTE 1 SOCP NOTE 2 t SOLZ SO t SOPD NOTE: 1. Once EF has gone LOW and the last bit of the final word has been shifted out, SOCP should not be clocked until EF goes HIGH. 2. In Single Device Mode, SO will not tri-state except after Reset. It will retain the last valid data. 2665 drw 09 Figure 6. Empty Boundary Condition Timing 0 1 n–1 SOCP t SOCFF t WFF FF t WPF W t DS DATA IN t DH DATA IN VALID t SOPD NOTE 1 SO NOTE 1 DATA OUT VALID 2665 drw 10 NOTE: 1. Single Device Mode will not tri-state but will retain the last valid data. Figure 7. Full Boundary Condition Timing W HALF-FULL (1/2) HALF-FULL HF HALF-FULL + 1 t WF t SOCF t WF t SOCF SOCP AEF 7/8 FULL AEF ALMOST-EMPTY (1/8 FULL – 1) ALMOST-FULL (7/8 FULL + 1) 1/8 FULL 7/8 FULL ALMOST-EMPTY (1/8 FULL – 1) 2665 drw 11 Figure 8. Half-Full, Almost-Full and Almost-Empty Timings 5.35 7 IDT72105, IDT72115, IDT72125, 256 x 16, 512 x 16, 1024 x 16 PARALLEL-TO-SERIAL CMOS FIFO COMMERCIAL TEMPERATURE RANGES RS 15 0 SOCP t FLS t FLH t DIRS t DIRH FL/DIR t SOXD1 t SOXD2 RSOX t SIXS RSIX t RSIXPW 2665 drw 12 Figure 9. Serial Read Expansion OPERATING CONFIGURATIONS Single Device Mode The device must be reset before beginning operation so that all flags are set to location zero. In the standalone case, the RSIX line is tied HIGH and indicates single device operation to the device. The RSOX/AEF pin defaults to AEF and outputs the Almost-Empty and Almost-Full Flag. Width Expansion Mode In the cascaded case, word widths of more than 16 bits can be achieved by using more than one device. By tying the RSOX and RSIX pins together, as shown in Figure 11, and programming which is the Least Significant Device, a cascaded serial word is achieved. The Least Significant Device is programmed by a LOW on the FL/DIR pin during reset. All other devices should be programmed HIGH on the FL/DIR pin at reset. PARALLEL DATA IN D 0–15 Vcc SERIAL OUTPUT CLOCK RSIX RSOX/AEF SOCP SO ALMOST-EMPTY/FULL FLAG SERIAL DATA OUT 2665 drw 13 Figure 10. Single Device Configuration 5.35 8 IDT72105, IDT72115, IDT72125, 256 x 16, 512 x 16, 1024 x 16 PARALLEL-TO-SERIAL CMOS FIFO COMMERCIAL TEMPERATURE RANGE Inputs Mode Reset Read/Write Internal Status Outputs RS FL DIR Read Pointer Write Pointer AEF, EF FF HF 0 X X Location Zero Location Zero 0 1 1 0,1 Increment(1) Increment(1) X X X 1 X NOTE: 1. Pointer will increment if appropriate flag is HIGH. 2665 tbl 09 Table 1. Reset and First Load Truth Table–Single Device Configuration The Serial Data Output (SO) of each device in the serial word must be tied together. Since the SO pin is three stated, only the device which is currently shifting out is enabled and driving the 1-bit bus. NOTE: After reset, the level on the FL/DIR pin decides if the Least Significant or Most Significant Bit is read first out of each device. The three flag outputs, Empty (EF), Half-Full (HF) and Full (FF), should be taken from the Most Significant Device (in the example, FIFO #2). The Almost-Empty/Almost-Full flag is not available. The RSOX pin is used for expansion. SERIAL OUTPUT CLOCK PARALLEL DATA IN LOW AT RESET D 0–15 W RSIX SOCP FL/DIR FIFO #1 RSOX SO HIGH AT RESET EF D 16–31 HF W FF RSIX SOCP FL/DIR FIFO #2 RSOX SO EF EMPTY FLAG HF HALF-FULL FLAG FF FULL FLAG SERIAL DATA OUT 2665 drw 14 Figure 11. Width Expansion for 32-bit Parallel Data In Depth Expansion (Daisy Chain) Mode The IDT72105/15/25 can easily be adapted to applications requiring greater than 1024 words. Figure 12 demonstrates Depth Expansion using three IDT72105/15/25s and an IDT74FCT138 Address Decoder. Any depth can be attained by adding additional devices. The Address Decoder is necessary to determine which FIFO is being written. A word of data must be written sequentially into each FIFO so that the data will be read in the correct sequence. The IDT72105/15/25 operates in the Depth Expansion Mode when the following conditions are met: 1. The first device must be programmed by holding FL LOW at Reset. All other devices must be programmed by holding FL HIGH at reset. 2. The Read Serial Out Expansion pin (RSOX) of each device must be tied to the Read Serial In Expansion pin (RSIX) of the next device (see Figure 12). 5.35 3. External logic is needed to generate composite Empty, Half-Full and Full Flags. This requires the OR-ing of all EF, HF and FF Flags. 4. The Almost-Empty and Almost-Full Flag is not available due to using the RSOX pin for expansion. Compound Expansion (Daisy Chain) Mode The IDT72105/15/25 can be expanded in both depth and width as Figure 13 indicates: 1. The RSOX-to-RSIX expansion signals are wrapped around sequentially. 2. The write (W) signal is expanded in width. 3. Flag signals are only taken from the Most Significant Devices. 4. The Least Significant Device in the array must be programmed with a LOW on FL/DIR during reset. 9 IDT72105, IDT72115, IDT72125, 256 x 16, 512 x 16, 1024 x 16 PARALLEL-TO-SERIAL CMOS FIFO COMMERCIAL TEMPERATURE RANGES LOW AT RESET PARALLEL DATA IN D 0–15 W FL/DIR RSIX RSOX ADDRESS 00 DECODER 01 74FCT138 10 EMPTY FLAG HF FIFO #1 SOCP EF SO FF HIGH AT RESET D 0–15 W SERIAL OUTPUT CLOCK FL/DIR RSIX HALF-FULL FLAG HF FIFO #2 SOCP EF RSOX SO FF HIGH AT RESET D 0–15 W FL/DIR RSIX HF FIFO #3 SOCP RSOX EF SO FULL FLAG FF SERIAL DATA OUT 2665 drw 15 Figure 12. A 3K x 16 Parallel-to-Serial FIFO using the IDT72125 Inputs Internal Status RS FL DIR Read Pointer Reset-First Device 0 0 X Location Zero Reset All Other Devices 0 1 X Read/Write 1 X 0,1 Mode Outputs Write Pointer EF HF, FF Location Zero 0 1 Location Zero Location Zero 0 1 X X X X NOTE: 1. RS = Reset Input, FL/FIR = First Load/Direction, EF = Empty Flag Output, HF = Half- Full Flag Output, FF = Full Flag Output. 2665 tbl 10 Table 2. Reset and First Load Truth Table–Width/Depth Compound Expansion Mode 5.35 10 IDT72105, IDT72115, IDT72125, 256 x 16, 512 x 16, 1024 x 16 PARALLEL-TO-SERIAL CMOS FIFO COMMERCIAL TEMPERATURE RANGE ADDRESS DECODER 74FCT138 PARALLEL DATAIN 00 01 10 SERIAL OUTPUT CLOCK LOW ON RESET HIGH ON RESET SOCP D 0–15 FL/DIR EF FIFO #1 W RSIX RSOX SOCP D 0–15 SO FL/DIR FIFO #3 W RSIX RSOX SOCP D 0–15 SO FL/DIR RSIX RSOX SO W RSOX RSIX D 16–31 FF W HF FF FL/DIR FIFO #2 EF HF EF FIFO #5 W HF FF SOCP D 16–31 SOCP SO FL/DIR FIFO #4 RSOX RSIX SOCP D 16–31 SO FL/DIR FIFO #6 W RSIX RSOX SO EF HF FF EF HF FF EF HF FF EMPTY FLAG HALF-FULL FLAG FULL FLAG SERIAL DATA OUT 2665 drw 16 Figure 13. A 3K x 32 Parallel-to-Serial FIFO using the IDT72125 5.35 11 IDT72105, IDT72115, IDT72125, 256 x 16, 512 x 16, 1024 x 16 PARALLEL-TO-SERIAL CMOS FIFO COMMERCIAL TEMPERATURE RANGES ORDERING INFORMATION IDT XXXXX Device Type X Power X Speed X Package X Process/ Temperature Range 5.35 BLANK Commercial (0°C to +70°C) TP SO Plastic THINDIP (300mil) Small Outline (Gull Wing) 25 50 (50 MHz serial shift rate) (40MHz serial shift rate) L Low Power 72105 72115 72125 256 x 16-Bit Parallel-to-Serial FIFO 512 x 16-Bit Parallel-to-Serial FIFO 1024 x 16-Bit Parallel-to-Serial FIFO Commercial only Parallel Access Time (tA) in ns 2665 drw 17 12