ICS843004 Integrated Circuit Systems, Inc. FEMTOCLOCKS™LVCMOS/CRYSTAL-TO3.3V LVPECL FREQUENCY SYNTHESIZER GENERAL DESCRIPTION FEATURES The ICS843004 is a 4 output LVPECL synthesizer optimized to generate Fibre Channel reference HiPerClockS™ clock frequencies and is a member of the HiPerClocksTM family of high performance clock solutions from ICS. Using a 26.5625MHz 18pF parallel resonant crystal, the following frequencies can be generated based on the 2 frequency select pins (F_SEL[1:0]): 212.5MHz, 187.5MHz, 159.375MHz, 156.25, 106.25MHz, and 53.125MHz. The ICS843004 uses ICS’ 3rd generation low phase noise VCO technology and can achieve 1ps or lower typical rms phase jitter, easily meeting Fibre Channel jitter requirements. The ICS843004 is packaged in a small 24-pin TSSOP package. • Four 3.3V LVPECL outputs ICS • Selectable crystal oscillator interface or LVCMOS/LVTTL single-ended input • Supports the following output frequencies: 212.5MHz, 187.5MHz, 159.375MHz, 156.25, 106.25MHz, 53.125MHz • VCO range: 560MHz - 680MHz • RMS phase jitter @ 212.5MHz, using a 26.5625MHz crystal (637KHz - 10MHz): 0.72ps (typical) • RMS phase noise at 212.5MHz (typical) Phase noise: Offset Noise Power 100Hz ............... -95.0 dBc/Hz 1KHz .............. -114.3 dBc/Hz 10KHz .............. -123.8 dBc/Hz 100KHz .............. -124.6 dBc/Hz • Full 3.3V supply mode • -30°C to 85°C ambient operating temperature PIN ASSIGNMENT FREQUENCY SELECT FUNCTION TABLE Input Frequency 26.5625 Inputs M Divider F_SEL1 F_SEL0 Value 0 0 24 N Divider Value 3 M/N Divider Value 8 4 6 Output Frequency (MHz) 212.5 26.5625 0 1 24 159.375 26.5625 1 0 24 6 4 106.25 26.5625 1 1 24 12 2 53.125 26.04166 0 1 24 4 6 156.25 23.4375 0 0 24 3 8 187.5 nQ1 Q1 VCC o Q0 nQ0 MR nPLL_SEL nc VCCA F_SEL0 VCC F_SEL1 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 nQ2 Q2 VCCO Q3 nQ3 VEE nc nXTAL_SEL TEST_CLK VEE XTAL_IN XTAL_OUT ICS843004 BLOCK DIAGRAM 2 F_SEL[1:0] Pulldown nPLL_SEL 24-Lead TSSOP 4.40mm x 7.8mm x 0.92mm package body G Package Top View Q0 Pulldown TEST_CLK Pulldown 1 1 26.5625MHz XTAL_IN OSC XTAL_OUT nXTAL_SEL 0 Phase Detector F_SEL[1:0] 0 0 ÷3 0 1 ÷4 10 11 VCO 637.5MHz ÷6 ÷12 0 (w/26.5625MHz Reference) nQO Q1 nQ1 Q2 Pulldown nQ2 M = 24 (fixed) MR 843004AG Q3 nQ3 Pulldown www.icst.com/products/hiperclocks.html 1 REV. A NOVEMBER 18, 2004 ICS843004 Integrated Circuit Systems, Inc. FEMTOCLOCKS™LVCMOS/CRYSTAL-TO3.3V LVPECL FREQUENCY SYNTHESIZER TABLE 1. PIN DESCRIPTIONS Number Name 1, 2 nQ1, Q1 Output Differential output pair. LVPECL interface levels. 3, 22 VCCO Power Output supply pins. 4, 5 Q0, nQ0 Ouput 6 MR Input 7 nPLL_SEL Input 8, 18 nc Unused 9 Power 15, 19 VCCA F_SEL0, F_SEL1 VCC XTAL_OUT, XTAL_IN VEE 16 TEST_CLK Input 17 nXTAL_SEL Input 20, 21 nQ3, Q3 Output 23, 24 Q2, nQ2 Output 10, 12 11 13, 14 Type Input Power Input Power Description Differential output pair. LVPECL interface levels. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs Qx to go low and the inver ted outputs nQx Pulldown to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. Selects between the PLL and TEST_CLK as input to the dividers. When Pulldown LOW, selects PLL (PLL Enable). When HIGH, deselects the reference clock (PLL Bypass). LVCMOS/LVTTL interface levels. No connect. Analog supply pin. Pulldown Frequency select pins. LVCMOS/LVTTL interface levels. Core supply pin. Parallel resonant cr ystal interface. XTAL_OUT is the output, XTAL_IN is the input. Negative supply pins. Pulldown LVCMOS/LVTTL clock input. Selects between cr ystal or TEST_CLK inputs as the the PLL Reference Pulldown source. Selects XTAL inputs when LOW. Selects TEST_CLK when HIGH. LVCMOS/LVTTL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance 4 pF RPULLDOWN Input Pulldown Resistor 51 KΩ 843004AG Test Conditions Minimum www.icst.com/products/hiperclocks.html 2 Typical Maximum Units REV. A NOVEMBER 18, 2004 ICS843004 Integrated Circuit Systems, Inc. FEMTOCLOCKS™LVCMOS/CRYSTAL-TO3.3V LVPECL FREQUENCY SYNTHESIZER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, θJA 70°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = -30°C TO 85°C Symbol Parameter Minimum Typical Maximum Units VCC Core Supply Voltage Test Conditions 3.135 3.3 3.465 V VCCA Analog Supply Voltage 3.135 3.3 3.465 V VCCO Output Supply Voltage 3.135 3.3 3.465 V I EE Power Supply Current 135 mA ICCA Analog Supply Current 15 mA Included in IEE TABLE 3B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = -30°C TO 85°C Symbol Parameter VIH Input High Voltage nPLL_SEL, nXTAL_SEL, Input F_SEL0, F_SEL1, MR Low Voltage TEST_CLK TEST_CLK, MR, Input F_SEL0, F_SEL1, High Current nPLL_SEL, nXTAL_SEL, TEST_CLK, MR, Input F_SEL0, F_SEL1, Low Current nPLL_SEL, nXTAL_SEL, VIL IIH IIL Test Conditions Minimum Typical Maximum Units 2 VCC + 0.3 V -0.3 0.8 V -0.3 1.3 V 150 µA VCC = VIN = 3.465V VCC = 3.465V, VIN = 0V -150 µA TABLE 3C. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = -30°C TO 85°C Symbol Parameter Maximum Units VOH Output High Voltage; NOTE 1 Test Conditions Minimum VCCO - 1.4 Typical VCCO - 0.9 V VOL Output Low Voltage; NOTE 1 VCCO - 2.0 VCCO - 1.7 V VSWING Peak-to-Peak Output Voltage Swing 0.6 1.0 V NOTE 1: Outputs terminated with 50Ω to VCCO - 2V. 843004AG www.icst.com/products/hiperclocks.html 3 REV. A NOVEMBER 18, 2004 ICS843004 Integrated Circuit Systems, Inc. FEMTOCLOCKS™LVCMOS/CRYSTAL-TO3.3V LVPECL FREQUENCY SYNTHESIZER TABLE 4. CRYSTAL CHARACTERISTICS Parameter Test Conditions Minimum Mode of Oscillation Typical Maximum Units Fundamental 28.33 MHz Equivalent Series Resistance (ESR) Frequency 23.33 26.5625 50 Ω Shunt Capacitance 7 pF Maximum Units 226.66 MHz MHz NOTE: Characterized using an 18pF parallel resonant crystal. TABLE 5. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = -30°C TO 85°C Symbol fOUT tPD tsk(o) tjit(Ø) tR / tF Parameter Output Frequency Propagation Delay, NOTE 1 Test Conditions Minimum F_SEL[1:0] = 00 186.67 Typical F_SEL[1:0] = 01 140 170 F_SEL[1:0] = 10 93.33 113.33 MHz F_SEL[1:0] = 11 46.67 56.66 MHz nPLL_SEL = 1 3.0 3.8 ns 30 ps Output Skew; NOTE 2, 4 RMS Phase Jitter (Random); NOTE 3 Output Rise/Fall Time 212.5MHz, (637KHz - 10MHz) 0.70 ps 159.375MHz, (637KHz - 10MHz) 0.75 ps 156.25MHz, (1.875MHz - 20MHz) 0.58 ps 106.25MHz, (637KHz - 10MHz) 0.81 ps 53.125MHz, (637KHz - 10MHz) 0.98 ps 20% to 80% 300 F_SEL[1:0] ≠ 00 49 odc Output Duty Cycle F_SEL[1:0] = 00 45 NOTE 1: Measured from the differential input crossing point to the output at VCCO/2. NOTE 2: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at VCCO/2. NOTE 3: Please refer to the Phase Noise Plot. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. 843004AG www.icst.com/products/hiperclocks.html 4 600 ps 51 55 % % REV. A NOVEMBER 18, 2004 ICS843004 Integrated Circuit Systems, Inc. FEMTOCLOCKS™LVCMOS/CRYSTAL-TO3.3V LVPECL FREQUENCY SYNTHESIZER TYPICAL PHASE NOISE AT 53.125MHZ 0 -10 -20 -30 53.125MHz -40 RMS Phase Jitter (Random) 637Khz to 10MHz = 0.98ps (typical) ➤ -50 Fibre Channel Jitter Filter -70 -80 -90 Raw Phase Noise Data -100 -110 ➤ NOISE POWER dBc Hz -60 -120 -130 -140 -150 -160 ➤ -170 -180 -190 10 100 1k 10k Phase Noise Result by adding Fibre Channel Filter to raw data 100k 1M 10M 100M OFFSET FREQUENCY (HZ) TYPICAL PHASE NOISE AT 106.25MHZ 0 -10 -20 -30 106.25MHz -40 RMS Phase Jitter (Random) 637Khz to 10MHz = 0.81ps (typical) ➤ -50 -70 Fibre Channel Jitter Filter -80 -90 Raw Phase Noise Data -100 ➤ NOISE POWER dBc Hz -60 -110 -120 -130 -140 -150 ➤ -160 -170 -180 -190 10 100 1k 10k Phase Noise Result by adding Fibre Channel Filter to raw data 100k 1M 10M 100M OFFSET FREQUENCY (HZ) 843004AG www.icst.com/products/hiperclocks.html 5 REV. A NOVEMBER 18, 2004 ICS843004 Integrated Circuit Systems, Inc. FEMTOCLOCKS™LVCMOS/CRYSTAL-TO3.3V LVPECL FREQUENCY SYNTHESIZER TYPICAL PHASE NOISE AT 156.25MHZ 0 -10 -20 -30 156.25MHz -40 RMS Phase Jitter (Random) 637Khz to 10MHz = 0.58ps (typical) ➤ -50 -70 10Gb Ethernet Jitter Filter -80 -90 Raw Phase Noise Data -100 ➤ NOISE POWER dBc Hz -60 -110 -120 -130 -140 -150 ➤ -160 -170 -180 Phase Noise Result by adding 10Gb Ethernet Filter to raw data -190 10 100 1k 10k 100k 1M 10M 100M OFFSET FREQUENCY (HZ) TYPICAL PHASE NOISE AT 159.375MHZ 0 -10 -20 -30 159.375MHz -40 RMS Phase Jitter (Random) 637Khz to 10MHz = 0.75ps (typical) ➤ -50 -70 Fibre Channel Jitter Filter -80 -90 Raw Phase Noise Data -100 ➤ NOISE POWER dBc Hz -60 -110 -120 -130 -140 -150 ➤ -160 -170 -180 Phase Noise Result by adding Fibre Channel Filter to raw data -190 10 100 1k 10k 100k 1M 10M 100M OFFSET FREQUENCY (HZ) 843004AG www.icst.com/products/hiperclocks.html 6 REV. A NOVEMBER 18, 2004 ICS843004 Integrated Circuit Systems, Inc. FEMTOCLOCKS™LVCMOS/CRYSTAL-TO3.3V LVPECL FREQUENCY SYNTHESIZER TYPICAL PHASE NOISE AT 212.5MHZ 0 -10 -20 -30 212.5MHz -40 RMS Phase Jitter (Random) 637Khz to 10MHz = 0.70ps (typical) ➤ -50 Fibre Channel Jitter Filter -70 -80 Raw Phase Noise Data -90 -100 ➤ NOISE POWER dBc Hz -60 -110 -120 -130 -140 ➤ -150 -160 -170 -180 Phase Noise Result by adding Fibre Channel Filter to raw data -190 10 100 1k 10k 100k 1M 10M 100M OFFSET FREQUENCY (HZ) 843004AG www.icst.com/products/hiperclocks.html 7 REV. A NOVEMBER 18, 2004 ICS843004 Integrated Circuit Systems, Inc. FEMTOCLOCKS™LVCMOS/CRYSTAL-TO3.3V LVPECL FREQUENCY SYNTHESIZER PARAMETER MEASUREMENT INFORMATION 2V Qx V CC, VCCA, VCCO nQx SCOPE Qx nQy LVPECL Qy nQx VEE t sk(o) -1.3V±0.165V 3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT OUTPUT SKEW Noise Power Phase Noise Plot TEST_CLK nQ0:nQ3 Phase Noise Mask Q0:Q3 tPD Offset Frequency f1 f2 RMS Jitter = Area Under the Masked Phase Noise Plot RMS PHASE JITTER PROPAGATION DELAY nQ0:nQ3 80% Q0:Q3 80% VSW I N G Pulse Width t odc = Clock Outputs PERIOD 20% 20% t PW tR tF t PERIOD OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD 843004AG OUTPUT RISE/FALL TIME www.icst.com/products/hiperclocks.html 8 REV. A NOVEMBER 18, 2004 ICS843004 Integrated Circuit Systems, Inc. FEMTOCLOCKS™LVCMOS/CRYSTAL-TO3.3V LVPECL FREQUENCY SYNTHESIZER APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS843004 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, VCCA, and VCCO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10Ω resistor along with a 10µF and a .01µF bypass capacitor should be connected to each VCCA. 3.3V VCC .01µF 10Ω VCCA .01µF 10µF FIGURE 1. POWER SUPPLY FILTERING TERMINATION FOR 3.3V LVPECL OUTPUT The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. designed to drive 50Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 2A and 2B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are 3.3V Zo = 50Ω 125Ω FOUT FIN Zo = 50Ω Zo = 50Ω FOUT 50Ω RTT = 1 Z ((VOH + VOL) / (VCC – 2)) – 2 o FIN 50Ω Zo = 50Ω VCC - 2V RTT 84Ω FIGURE 2A. LVPECL OUTPUT TERMINATION 843004AG 125Ω 84Ω FIGURE 2B. LVPECL OUTPUT TERMINATION www.icst.com/products/hiperclocks.html 9 REV. A NOVEMBER 18, 2004 ICS843004 Integrated Circuit Systems, Inc. FEMTOCLOCKS™LVCMOS/CRYSTAL-TO3.3V LVPECL FREQUENCY SYNTHESIZER CRYSTAL INPUT INTERFACE The ICS843004 has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 3 below were determined using a 26.5625MHz 18pF parallel resonant crystal and were chosen to minimize the ppm error. XTAL_OUT C1 33p X1 18pF Parallel Crystal XTAL_IN C2 27p ICS843004 Figure 3. CRYSTAL INPUt INTERFACE LAYOUT GUIDELINE Figure 4 shows a schematic example of the ICS843004. An example of LVEPCL termination is shown in this schematic. Additional LVPECL termination approaches are shown in the LVPECL Termination Application Note. In this example, an 18pF parallel resonant 26.5625MHz crystal is used. The C1=27pF and C2=33pF are recommended for frequency accuracy. For different board layout, the C1 and C2 may be slightly adjusted for optimizing frequency accuracy. 3.3V VCCA VCC R2 10 R3 133 R5 133 Zo = 50 Ohm C3 10uF C4 0.01u + VCC VCCO C6 0.1u To Logic Input pins RD1 Not Install To Logic Input pins RD2 1K U1 ICS843004 XTAL_OUT XTAL_IN VEE TEST_CLK nXTAL_SEL VCC VEE nQ3 Q3 VCCO Q2 nQ2 RU2 Not Install RU1 1K - R6 82.5 R4 82.5 F_SEL1 VCC F_SEL0 VCCA NC nPLL_SEL MR nQ0 Q0 VCCO Q1 nQ1 Set Logic Input to '0' VDD VCC=3.3V 3.3V VCCO=3.3V R7 133 13 14 15 16 17 18 19 20 21 22 23 24 Set Logic Input to '1' VDD Zo = 50 Ohm C7 0.1u 12 11 10 9 8 7 6 5 4 3 2 1 Logic Control Input Examples R9 133 Zo = 50 Ohm X1 25MHz 18pF Zo = 50 Ohm C9 0.1u C1 27pF VCCO C2 33pF VCC + R8 82.5 - R10 82.5 C8 0.1u FIGURE 4. ICS843004 SCHEMATIC EXAMPLE 843004AG www.icst.com/products/hiperclocks.html 10 REV. A NOVEMBER 18, 2004 ICS843004 Integrated Circuit Systems, Inc. FEMTOCLOCKS™LVCMOS/CRYSTAL-TO3.3V LVPECL FREQUENCY SYNTHESIZER POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS843004. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS843004 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 135mA = 467.8mW Power (outputs)MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 4 * 30mW = 120mW Total Power_MAX (3.465V, with all outputs switching) = 467.8mW + 120mW = 587.8mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 65°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.588W * 65°C/W = 123.2°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 6. THERMAL RESISTANCE θJA FOR 24-PIN TSSOP, FORCED CONVECTION θJA by Velocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards 843004AG 0 1 2.5 70°C/W 65°C/W 62°C/W www.icst.com/products/hiperclocks.html 11 REV. A NOVEMBER 18, 2004 ICS843004 Integrated Circuit Systems, Inc. FEMTOCLOCKS™LVCMOS/CRYSTAL-TO3.3V LVPECL FREQUENCY SYNTHESIZER 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 5. VCC Q1 VOUT RL 50 VCC - 2V FIGURE 5. LVPECL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of V - 2V. CC • For logic high, VOUT = V OH_MAX (V CCO_MAX • -V OH_MAX OL_MAX CCO_MAX -V OL_MAX CC_MAX – 0.9V ) = 0.9V For logic low, VOUT = V (V =V =V CC_MAX – 1.7V ) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. ))/R ] * (V – (V - 2V))/R ] * (V -V ) = [(2V - (V -V -V )= Pd_H = [(V OH_MAX CC_MAX CC_MAX OH_MAX OH_MAX CC_MAX OH_MAX L CC_MAX L [(2V - 0.9V)/50Ω] * 0.9V = 19.8mW Pd_L = [(V OL_MAX – (V CC_MAX - 2V))/R ] * (V L CC_MAX -V OL_MAX ) = [(2V - (V CC_MAX -V OL_MAX ))/R ] * (V L CC_MAX -V OL_MAX )= [(2V - 1.7V)/50Ω] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW 843004AG www.icst.com/products/hiperclocks.html 12 REV. A NOVEMBER 18, 2004 ICS843004 Integrated Circuit Systems, Inc. FEMTOCLOCKS™LVCMOS/CRYSTAL-TO3.3V LVPECL FREQUENCY SYNTHESIZER RELIABILITY INFORMATION TABLE 7. θJAVS. AIR FLOW TABLE FOR 24 LEAD TSSOP θJA by Velocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 70°C/W 65°C/W 62°C/W TRANSISTOR COUNT The transistor count for ICS843004 is: 2578 843004AG www.icst.com/products/hiperclocks.html 13 REV. A NOVEMBER 18, 2004 ICS843004 Integrated Circuit Systems, Inc. PACKAGE OUTLINE - G SUFFIX FOR FEMTOCLOCKS™LVCMOS/CRYSTAL-TO3.3V LVPECL FREQUENCY SYNTHESIZER 24 LEAD TSSOP TABLE 8. PACKAGE DIMENSIONS SYMBOL Millimeters Minimum N A Maximum 24 -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 7.70 7.90 E E1 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 0.75 α 0° 8° aaa -- 0.10 Reference Document: JEDEC Publication 95, MO-153 843004AG www.icst.com/products/hiperclocks.html 14 REV. A NOVEMBER 18, 2004 ICS843004 Integrated Circuit Systems, Inc. FEMTOCLOCKS™LVCMOS/CRYSTAL-TO3.3V LVPECL FREQUENCY SYNTHESIZER TABLE 9. ORDERING INFORMATION Part/Order Number Marking Package Count Temperature ICS843004AG ICS843004AG 24 Lead TSSOP 60 per tube -30°C to 85°C ICS843004AGT ICS843004AG 24 Lead TSSOP on Tape and Reel 2500 -30°C to 85°C The aforementioned trademark, HiPerClockS™ and FEMTOCLOCKS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 843004AG www.icst.com/products/hiperclocks.html 15 REV. A NOVEMBER 18, 2004 ICS843004 Integrated Circuit Systems, Inc. FEMTOCLOCKS™LVCMOS/CRYSTAL-TO3.3V LVPECL FREQUENCY SYNTHESIZER REVISION HISTORY SHEET Rev Table Page A 1 A 10 843004AG Description of Change Date Added 187.5MHz to the Frequency Selection Function Table. 8/26/04 Added Schematic Layout. 11/18/04 www.icst.com/products/hiperclocks.html 16 REV. A NOVEMBER 18, 2004