® L6221AS L6221AD L6221N QUAD DARLINGTON SWITCH . .. .. . FOUR NON INVERTING INPUTS WITH ENABLE OUTPUT VOLTAGE UP TO 50 V OUTPUT CURRENT UP TO 1.8 A VERY LOW SATURATION VOLTAGE TTL COMPATIBLE INPUTS INTEGRAL FAST RECIRCULATION DIODES Powerdip 12 + 2 + 2 Multiwatt 15 DESCRIPTION The L6221 monolithic quad darlington switch is designed for high current, high voltage switching applications. Each of the four switches is controlled by a logic input and all four are controlled by a common enable input. All inputs are TTL-compatible for direct connection to logic circuits. Each switch consists of an open-collector darlington transistor plus a fast diode for switching applications with inductive device loads. The emitters of the four switches are commoned. Any number of inputs and outputs of the same device may be paralleled. SO16+2+2 ORDERING NUMBERS: L6221AS (Powerdip) L6221N (Multiwatt15) L6221AD (SO16+2+2) BLOCK DIAGRAM June 2003 1/15 L6221AS - L6221AD - L6221N THERMAL DATA Symbol Rth j-pins Rth j-case Rth j-amb Parameter Thermal Resistance Junction-pins Thermal Resistance Junction-case Thermal Resistance Junction-ambient SO20 Max. Max. Max. Powerdip Multiwatt15 17 – 80 14 – 80 Unit °C/W °C/W °C/W – 3 35 PIN CONNECTIONS (top views) L6221AS (Powerdip) L6221AD (SO16+2+2) OUT4 1 20 IN4 CLAMPB 2 19 IN3 N.C. 3 18 N.C. OUT3 4 17 ENABLE GND 5 16 GND GND 6 15 GND OUT2 7 14 VS N.C. 8 13 N.C. CLAMPA 9 12 IN2 10 11 IN1 OUT1 D95IN231 L6221N (Multiwatt-15) 2/15 L6221AS - L6221AD - L6221N ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit 50 V Logic Supply Voltage 7 V Input Voltage, Enable Voltage Vs IC Continuous Collector Current (for each channel) 1.8 A IC Collector Peak Current (repetitive, duty cycle = 10 % ton = 5 ms) 2.5 A IC Collector Peak Current (non repetitive, t = 10 µs) 3.2 A Vo Output Voltage Vs VIN, VEN Top Operating Temperature Range (junction) – 40 to + 150 °C Tstg Storage Temperature Range – 55 to + 150 °C Isub Output Substrate Current 350 mA Ptot Total Power Dissipation 4.3 20 3.5 1 2.3 1 W W W W W W at at at at at at Tpins Tcase Tcase Tamb Tamb Tamb = = = = = = 90 90 90 70 70 70 °C °C °C °C °C °C (powerdip) (multiwatt) (SO20) (powerdip) (multiwatt) (SO20) TRUTH TABLE Enable Input Power Out H H L H L X ON OFF OFF For each input : H = High level L = Low level PIN FUNCTIONS (see block diagram) Name Function IN 1 Input to Driver 1 IN 2 Input to Driver 2 OUT 1 Output of Driver 1 OUT 2 Output of Driver 2 CLAMP A IN 3 IN 4 Diode Clamp to Driver 1 and Driver 2 Input to Driver 3 Input to Driver 4 OUT 3 Output of Driver 3 OUT 4 Output of Driver 4 CLAMP B ENABLE VS GND Diode Clamp to Driver 3 and Driver 4 Enable Input to All Drivers Logic Supply Voltage Common Ground 3/15 L6221AS - L6221AD - L6221N ELECTRICAL CHARACTERISTICS Refer to the test circuit to Fig. 1 to Fig. 9 (VS = 5V, Tamb = 25oC unless otherwise specified) Symbol Parameter Test Conditions Min . Typ . Max . Unit VS Logic Supply Voltage Is Logic Supply Current All Outputs ON, IC = 0.7A All Outputs OFF Output Sustaining Voltage VIN = VINL, VEN = VENH IC = 100 mA Output Leakage Current VCE = 50V VIN = VINL, VEN = VENH Collector Emitter Saturation Voltage (one input on ; all others inputs off.) Vs = 4.5V VIN = VINH, VEN = VENH IC = 0.6A IC = 1A IC = 1.8A 1 1.2 1.6 0.8 V VIN = VINL, VEN = VENL – 100 µA VCE(sus) ICEX VCE(sat) 4.5 5.5 V 20 20 mA mA 46 V 1 mA V VINL, VENL Input Low Voltage IINL, IENL Input Low Current VINL, VENH Input High Voltage IINH , IENH Input High Current VIN = VINH, VEN = VENH ± 10 µA IR Clamp Diode Leakage Current VR = 50 V, VEN = VENH VIN = VINL 100 µA VF Clamp Diode Forward Voltage IF = 1A IF = 1.8A 1.6 2.0 V V td (on) Turn on Delay Time Vp = 5V, RL = 10Ω 2 µs td (off) Turn off Delay Time Vp = 5V, RL = 10Ω 5 µs Logic Supply Current Variation VIN = 5V, VEN = 5V Iout = – 300 mA for Each Channel 120 mA ∆Is 4/15 2.0 V L6221AS - L6221AD - L6221N TEST CIRCUITS (X) = Referred to Multiwatt package X = Referred to Powerdip package Figure 1 : Logic supply current. Set V IN = 4.5V, V EN = 0.8V, or V IN = 0.8V, V EN = 4.5V, for I S (all outputs off) Set V IN = 2V, V EN = 2V, for I S (all outputs on) Figure 2 : Output Sustaining Voltage. Figure 3 : Output Leakage Current. 5/15 L6221AS - L6221AD - L6221N Figure 4 : Collector-emitter Saturation Voltage Figure 5 : Set Set Set Set Figure 6 : Clamp Diode Leakage Current. 6/15 Logic Input Characteristics S1, S2 open, VIN, VEN = 0.8V for IIN L, IEN L S1, S2 open, VIN, VEN = 2V for IIN H, IEN H S1, S2 close, VIN, VEN = 0.8V for VIN L, VEN L S1, S2 close, VIN, VEN = 2V for VIN H, VEN H Figure 7 : Clamp Diode Forward Voltage. L6221AS - L6221AD - L6221N Figure 8 : Switching Times Test Circuit. Figure 9 : Switching TImes Waveforms. Figure 10 : Allowed Peak Collector Current versus Duty Cycle for 1, 2, 3 or 4 Contemporary Working Outputs (L6221AS) Figure 11 : Allowed Peak Collector Current versus Duty Cycle for 1, 2, 3 or 4 Contemporary Working Outputs (L6221N) 7/15 L6221AS - L6221AD - L6221N Figure 12 : Collector Saturation Voltage versus Collector Current Figure 13 : Free-wheeling Diode Forward Voltage versus Diode Current Figure 14 : Collector Saturation Voltage versus Junction Temperature at IC = 1A Figure 15 : Free-wheeling Diode Forward Voltage versus Junction Temperature at IF = 1A Figure 16 : Saturation Voltage vs. Junc- Figure 17 : Free-wheeling Diode Forward 8/15 L6221AS - L6221AD - L6221N APPLICATION INFORMATION When inductive loads are driven by L6221A/N, a zener diode in series with the integral free-wheeling diodes increases the voltage across which energy stored in the load is discharged and therefore speeds the current decay (fig. 18). For reliability it is suggested that the zener is chosen so that Vp + Vz < 35 V. The reasons for this are two fold : 1) The zener voltage changes in temperature and current. 2) The instantaneous power must be limited to avoid the reverse second breakdown. Figure 18. Figure 19 : Driver for Solenoids up to 3A. Some care must be taken to ensure that the collectors are placed close together to avoid different current partitioning at turn-off. We suggest to put in parallel channel 1 and 4 and channel 2 and 3 as shown in figure 19 for the similar electrical characteristics of the logic section (turn-on and turn-off delay time) and the power stages (collector saturation voltage, free-wheeling diode forward voltage). 9/15 L6221AS - L6221AD - L6221N Figure 20 : Saturation Voltage versus Collector Current Figure 22 : Peak Collector Current versus Duty Cycle for 1 or 2 Paralleled Outputs Driven (L6221N) 10/15 Figure 21 : Peak Collector Current versus Duty Cycle for 1 or 2 Paralleled Outputs Driven (L6221AS) L6221AS - L6221AD - L6221N MOUNTING INSTRUCTION The Rth j-amb of the L6221AS can be reduced by soldering the GND pins to a suitable copper area of the printed circuit board (Fig. 23) or to an external heatsink (Fig. 24). The diagram of figure 25 shows the maximum dissipable power Ptot and the Rth j-amb as a function of the side " α" of two equal square copper areas hav- ing a thickness of 35µ (1.4 mils). During soldering the pins temperature must not exceed 260 °C and the soldering time must not be longer than 12 seconds. The external heatsink or printed circuit copper area must be connected to electrical ground. Figure 23 : Example of P.C. Board Copper Area Which is Used as Heatsink Figure 24 : External Heatsink Mounting Example Figure 25 : Maximum Dissipable Power and Junction to Ambient Thermal Resistance versus Side " α" Figure 26 : Maximum Allowable Power Dissipation versus Ambient Temperature 11/15 L6221AS - L6221AD - L6221N mm DIM. MIN. a1 0.51 B 0.85 b b1 TYP. inch MAX. MIN. TYP. MAX. 0.020 1.40 0.033 0.50 0.38 0.055 0.020 0.50 D 0.015 0.020 20.0 0.787 E 8.80 0.346 e 2.54 0.100 e3 17.78 0.700 F 7.10 0.280 I 5.10 0.201 L OUTLINE AND MECHANICAL DATA 3.30 0.130 Powerdip 16 Z 12/15 1.27 0.050 L6221AS - L6221AD - L6221N mm DIM. MIN. TYP. inch MAX. MIN. TYP. MAX. A 5 0.197 B 2.65 0.104 C 1.6 D OUTLINE AND MECHANICAL DATA 0.063 1 0.039 E 0.49 0.55 0.019 0.022 F 0.66 0.75 0.026 0.030 G 1.02 1.27 1.52 0.040 0.050 0.060 G1 17.53 17.78 18.03 0.690 0.700 0.710 H1 19.6 0.772 H2 20.2 0.795 L 21.9 22.2 22.5 0.862 0.874 0.886 L1 21.7 22.1 22.5 0.854 0.870 0.886 L2 17.65 18.1 0.695 L3 17.25 17.5 17.75 0.679 0.689 0.699 L4 10.3 10.7 10.9 0.406 0.421 0.429 0.713 L7 2.65 2.9 0.104 M 4.25 4.55 4.85 0.167 0.179 0.191 0.114 M1 4.63 5.08 5.53 0.182 0.200 0.218 S 1.9 2.6 0.075 S1 1.9 2.6 0.075 0.102 Dia1 3.65 3.85 0.144 0.152 0.102 Multiwatt15 V 13/15 L6221AS - L6221AD - L6221N mm inch OUTLINE AND MECHANICAL DATA DIM. MIN. TYP. MAX. MIN. TYP. MAX. A 2.35 2.65 0.093 0.104 A1 0.1 0.3 0.004 0.012 B 0.33 0.51 0.013 0.020 C 0.23 0.32 0.009 0.013 D 12.6 13 0.496 0.512 E 7.4 7.6 0.291 0.299 e 1.27 0.050 H 10 10.65 0.394 0.419 h 0.25 0.75 0.010 0.030 L 0.4 1.27 0.016 0.050 SO20 K 0˚ (min.)8˚ (max.) L h x 45˚ A B e A1 K H D 20 11 E 1 0 1 SO20MEC 14/15 C L6221AS - L6221AD - L6221N Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. 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