MP3422 The Future of Analog IC Technology 6.5A, 600kHz High Efficiency, Synchronous Step-Up Converter with Output Disconnect in 2x2mm QFN Package DESCRIPTION FEATURES The MP3422 is a high-efficiency, synchronous, current–mode, step-up converter with output disconnect. • • • • • • • • • • • • The MP3422 starts up from an input voltage as low as 1.9V, while providing inrush current limiting and output short-circuit protection. The integrated P-channel synchronous rectifier improves efficiency and eliminates the need for an external Schottky diode. This P-channel disconnects the output from the input during shutdown. The 600kHz switching frequency allows small external components, while the internal compensation and soft-start minimize external component count. The MP3422 provides a compact solution for a 5V output, 2.5A load requirement, using a supply voltage down to 2.8V. The MP3422 is available in 14-pin QFN 2mmx2mm package. Up to 98% Efficiency 1.9V to 5.5V Input Range 2.5V to 5.5V Output Range Internal Synchronous Rectifier 600kHz Fixed Switching Frequency >6.5A Switch Current Limit Capability 43uA Quiescent Current High Efficiency over Full Load Range Internal Soft-start and Compensation True Output Load Disconnect from Input OCP, SCP, OVP and OTP Protection Small 2x2mm QFN14 Package APPLICATIONS • • • • • Battery-Powered Products Power Banks, Juice Packs, Battery Back-up Units USB Power Supply Consumer Electronic Accessories Tablets All MPS parts are lead-free and adhere to the RoHS directive. For MPS green status, please visit MPS website under Products, Quality Assurance page. “MPS” and “The Future of Analog IC Technology” are Registered Trademarks of Monolithic Power Systems, Inc. TYPICAL APPLICATION Efficiency vs. Load Current 100 VOUT=5V VIN=4.2V 98 96 94 VIN=3.3V VIN=2.8V 92 90 88 86 84 0 0.5 1 1.5 2 2.5 LOAD CURRENT (A) MP3422 Rev.1.01 8/6/2014 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. 1 MP3422—6.5A, 600KHZ HIGH EFFICIENCY, SYNCHRONOUS, STEP-UP CONVERTER WITH OUTPUT DISCONNECT IN 2X2MM QFN PACKAGE ORDERING INFORMATION Part Number* MP3422GG Package QFN-14 (2mmX2mm) Top Marking See Below * For Tape & Reel, add suffix –Z (e.g. MP3422GG–Z) TOP MARKING CN: product code of MP3422GG; Y: year code; LLL: lot number; PACKAGE REFERENCE TOP VIEW MP3422 Rev.1.01 8/6/2014 PGND 1 PGND 2 SW 3 OUT 4 FB AGND 12 11 10 INA 13 PGND 9 IN 14 SW 8 EN 7 NC 5 6 OUT OUT www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. 2 MP3422—6.5A, 600KHZ HIGH EFFICIENCY, SYNCHRONOUS, STEP-UP CONVERTER WITH OUTPUT DISCONNECT IN 2X2MM QFN PACKAGE ABSOLUTE MAXIMUM RATINGS (1) Thermal Resistance SW Pin ................. -0.3V to +6.5V (9V for <5ns) All other Pins .............................. -0.3V to +6.5V Continuous Power Dissipation (TA = +25°C) (2) .......................................................... 1.56W Junction Temperature .............................. 150°C Lead Temperature ................................... 260°C Storage Temperature ............... -65°C to +150°C QFN-14 (2mmx2mm) ............ 80 ....... 16 °C/W Recommended Operating Conditions (3) Supply Voltage VIN ......................... 1.9V to 5.5V VOUT ............................................... 2.5V to 5.5V Operating Junction Temp. (TJ). -40°C to +125°C MP3422 Rev.1.01 8/6/2014 (4) θJA θJC Notes: 1) Exceeding these ratings may damage the device. 2) The maximum allowable power dissipation is a function of the maximum junction temperature TJ (MAX), the junction-toambient thermal resistance θJA, and the ambient temperature TA. The maximum allowable continuous power dissipation at any ambient temperature is calculated by PD (MAX) = (TJ (MAX)-TA)/θJA. Exceeding the maximum allowable power dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown. Internal thermal shutdown circuitry protects the device from permanent damage. 3) The device is not guaranteed to function outside of its operating conditions. 4) Measured on JESD51-7, 4-layer PCB. www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. 3 MP3422—6.5A, 600KHZ HIGH EFFICIENCY, SYNCHRONOUS, STEP-UP CONVERTER WITH OUTPUT DISCONNECT IN 2X2MM QFN PACKAGE ELECTRICAL CHARACTERISTICS VIN = VEN = 3.3V, VOUT = 5V, TJ= -40°C to125°C, typical values are tested at TJ =25°C, unless otherwise noted. Parameters Voltage Range Symbol Start Operating Input Voltage Condition VIN Quiescent Current Typ 1.9 IQ_NS Shutdown Current Min ISD VEN=VIN=3.3V, VOUT=5V, no load Measured on OUT pin, TJ=25°C VEN=VIN=3.3V, VOUT=5V, no load Measured on IN pin VEN=VOUT=0V, Measured on IN pin, TJ=25°C VIN Rising TJ=25°C VIN Falling, VOUT=5V IN UVLO Rising Threshold IN UVLO Falling Threshold VUVLO VUVLO VOUT Start Switching Rising Threshold VUVLO_OUT_R TJ=25°C IN-R IN-F 43 Max Units 5.5 V 57 µA 0.3 1 µA 0.1 1 µA 1.3 650 1.6 V mV 1.7 1.79 V Step-up Converter Operation Frequency FSW Feedback Voltage VFB Feedback Input Current IFB NMOS On-Resistance NMOS Leakage Current PMOS On-Resistance PMOS Leakage Current Maximum Duty Cycle RNDS ON IN LK RPDS ON IP LK DMAX (5) Linear Charge Current Limit (5) NMOS Current Limit TJ=25°C 500 600 700 -40°C≤TJ≤125°C 440 600 760 TJ=25°C 795 807 819 -40°C≤TJ≤125°C 791 807 823 mV 1 50 nA VFB=850mV VSW =5V VSW =5V, VOUT=0V 90 ICH_LIMIT VOUT=1.7V VOUT=0V ISW ISW VIN=5V, VOUT=3.3V Duty=44%, VIN=2.8V, VOUT=5V LIMIT1 LIMIT2 kHz 13 100 18 0.1 95 0.7 0.2 mΩ nA mΩ µA % A A 4 A A 6.5 Logic Interface EN High-Level Voltage EN Low-Level Voltage VEN VEN EN Input Current 1.2 H 0.4 L IEN Connect to VIN V V 10 nA 150 °C 20 °C Protection Thermal Shutdown (5) Over Temperature Hysteresis (5) Notes: 5) Guaranteed by characterization, not production tested. MP3422 Rev.1.01 8/6/2014 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. 4 MP3422—6.5A, 600KHZ HIGH EFFICIENCY, SYNCHRONOUS, STEP-UP CONVERTER WITH OUTPUT DISCONNECT IN 2X2MM QFN PACKAGE TYPICAL CHARACTERISTICS VIN = VEN = 3.3V, VOUT = 5V, L = 1.5µH, TA = 25°C, unless otherwise noted. Quiescent Current vs. Input Voltage VIN>VOUT 60 60 VIN<VOUT 2 EN=LOW 50 1.6 40 40 1.2 30 30 0.8 20 20 0.4 10 1.5 2 2.5 3 3.5 4 4.5 5 5.5 INPUT VOLTAGE(V) 10 1.5 2 2.5 3 3.5 4 4.5 5 5.5 OUTPUT VOLTAGE(V) Input UVLO Threshold vs. Temperature 1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 INPUT VOLTAGE(V) EN Threshold vs. Temperature VOUT Rising Threshold for switching vs. Temperature 2.5 0.4 Falling Threshold 0.5 Rising Threshold Falling Threshold 0.25 820 750 Frequency vs. Temperature 815 700 FREQUENCY(kHz) 805 800 795 790 650 600 550 785 780 -40 -20 0 20 40 60 80 100120140 MP3422 Rev.1.01 8/6/2014 500 -40 -20 0 20 40 60 80 100120140 2 1.75 1.5 1.25 1 -40 -20 0 20 40 60 80 100120140 0 -40 -20 0 20 40 60 80 100120140 Feedback Voltage vs. Temperature 810 VOUT THRESHOLD(V) Rising Threshold 0.8 0.75 1 LINEAR CHARGING LIMIT(A) 1.2 EN THRESHOLD(V) 2.25 1.6 0 -40 -20 0 20 40 60 80 100120140 FB REGULATION VOLTAGE(mV) Shutdown Current vs. Input Voltage 50 2 VIN UVLO THRESHOLD(V) Quiescent Current vs. Output Voltage Linear-Charging Current Limit vs. Output Voltage 0.75 VIN=4.2V 0.5 0.25 VIN=2.8V 0 0 0.4 0.8 1.2 1.6 OUTPUT VOLTAGE(V) www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. 2 5 MP3422—6.5A, 600KHZ HIGH EFFICIENCY, SYNCHRONOUS, STEP-UP CONVERTER WITH OUTPUT DISCONNECT IN 2X2MM QFN PACKAGE TYPICAL CHARACTERISTICS (continued) VIN = VEN = 3.3V, VOUT = 5V, L = 1.5µH, TA = 25°C, unless otherwise noted. Linear-Charging Current Limit vs. Temperature MP3422 Rev.1.01 8/6/2014 600 VIN=1.9V 800 VOUT=1.6V 400 200 VOUT=0V 0 -40 -20 0 20 40 60 80 100120140 LINEAR CHARGING LIMIT(mA) LINEAR CHARGING LIMIT(mA) 800 Linear-Charging Current Limit vs. Temperature VIN=3.3V 600 400 VOUT=1.6V 200 VOUT=0V 0 -40 -20 0 20 40 60 80 100120140 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. 6 MP3422—6.5A, 600KHZ HIGH EFFICIENCY, SYNCHRONOUS, STEP-UP CONVERTER WITH OUTPUT DISCONNECT IN 2X2MM QFN PACKAGE TYPICAL PERFORMANCE CHARACTERISTICS VIN = 3.3V, VOUT = 5V, L=1.5uH, TA = 25°C, tested on standard EVB, unless otherwise noted. MP3422 Rev.1.01 8/6/2014 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. 7 MP3422—6.5A, 600KHZ HIGH EFFICIENCY, SYNCHRONOUS, STEP-UP CONVERTER WITH OUTPUT DISCONNECT IN 2X2MM QFN PACKAGE TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 3.3V, VOUT = 5V, L=1.5uH, TA = 25°C, tested on standard EVB, unless otherwise noted. MP3422 Rev.1.01 8/6/2014 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. 8 MP3422—6.5A, 600KHZ HIGH EFFICIENCY, SYNCHRONOUS, STEP-UP CONVERTER WITH OUTPUT DISCONNECT IN 2X2MM QFN PACKAGE PIN FUNCTIONS Pin # Name Pin Function 1, 2, 13 PGND Power Ground. 3, 14 SW Power Switch Output. SW is the connection node of the internal NMOS switch and synchronous switch. Connect the power inductor between SW and input power. Keep these PCB trace lengths as short and wide as possible to reduce EMI and voltage spikes. Output Pin. OUT is the drain of the Internal Synchronous Rectifier MOSFET. Bias is derived from OUT when VOUT is higher than VIN. PCB trace length from OUT to the output filter capacitor(s) should be as short and wide as possible. OUT is completely disconnected from IN when EN is low due to the output disconnect feature. No Connect. Reserved for factory use only. Float or connect this pin to GND in the application. 4, 5, 6 OUT 7 NC 8 EN Chip Enable Control Input. 9 IN Power Supply Input. The startup bias is derived from IN. Must be locally bypassed. Once OUT exceeds IN, bias comes from OUT. Thus, once started, operation is completely independent from IN. 10 INA 11 AGND 12 FB MP3422 Rev.1.01 8/6/2014 Power supply input for factory use only, must be connected to IN pin in the application. Analog Signal Ground. Feedback Input to Error Amplifier. Connect resistor divider tap to this pin. The output voltage can be adjusted from 2.5V to 5.5V www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. 9 MP3422—6.5A, 600KHZ HIGH EFFICIENCY, SYNCHRONOUS, STEP-UP CONVERTER WITH OUTPUT DISCONNECT IN 2X2MM QFN PACKAGE FUNCTION DIAGRAM L1 Cin IN INA SCP/OVP SW VoutGood Startup PWM Control AGND 1.7V Body Vin Control A B C OUT Current Limit SYNC Drive Control R1 OSC 600KHz Slope Comp ∑ PGND Cp Rc Cout Cc RT PWM Comparator Vref EN Enable Control Undervoltage Lockout FB EA 0.8V REF Enable R2 Figure 1: Functional Block Diagram MP3422 Rev.1.01 8/6/2014 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. 10 MP3422—6.5A, 600KHZ HIGH EFFICIENCY, SYNCHRONOUS, STEP-UP CONVERTER WITH OUTPUT DISCONNECT IN 2X2MM QFN PACKAGE OPERATION The MP3422 is a 600kHz, synchronous step-up converter with true output disconnect. It is packaged in a QFN 2X2-14 lead package. The device features fixed-frequency current mode PWM controls for excellent line and load regulation. Internal soft-start and loop compensation simplifies the design process and minimizes external components. The internal low RDSon MOSFETs, combined with frequency stretching operation, enables the device to maintain high efficiency over a wide load current range. Start-Up When the IC is enabled and the voltage on the IN pin exceeds Vuvlo_in-R, the MP3422 starts up in the linear charge period. During this linear charge period, the PMOS rectifier turns on until the output capacitor is charged to 1.7V. The PMOS current is limited to 0.2A when Vout is 0V to avoid inrush current. While the output ramps up, the PMOS current limit also increases and ramps to 0.7A at 1.7V output. This circuit also helps to limit the output current under short circuit conditions. Once the output is charged to 1.7V, the linear charge period elapses and the MP3422 starts switching in normal closed loop operation. In normal operation, with Vo lower than Vin+0.3V the MP3422 operates in step down mode with 4A typical peak current limit, and works in boost mode when Vo is higher than Vin+0.3V with more than 6.5A current limit. Table 1: Work Mode during Startup VOUT<1.7V VOUT ≥1.7V & VOUT < VIN + 0.3V VOUT ≥1.7V & VOUT ≥ VIN + 0.3V Linear Charge Mode Down Mode Boost Mode In down mode, gate of HS-FET is pulled to VIN, and it works with high impedance when HSFET is on, the power-loss is high and regulation is bad in down mode. Down mode is designed for work in startup and SCP condition, it is not suggested to set MP3422 in down mode in normal work, unless the thermal and regulation will not affect the system performance. MP3422 Rev.1.01 8/6/2014 Once the output voltage exceeds the input voltage, the MP3422 powers its internal circuits from Vout instead of Vin. Soft-Start The MP3422 provides soft-start by charging an internal capacitor with a current source. This soft start voltage continues to rise, following the FB voltage, during the linear charge period. Once the linear charge period elapses, and the voltage on this capacitor is charged, the reference voltage is slowly ramped up. The reference soft start time is typically 2ms from 0V to 0.807V. The soft start capacitor is discharged completely in the event of a commanded shutdown, thermal shutdown or short circuit at the output. Device Enable Operation is enabled when the EN pin is switched high and placed into shutdown mode when low. In shutdown mode, the regulator stops switching and all internal control circuitry is off. The load is isolated from the input. Power Save Mode The MP3422 will automatically enter power save mode (PSM) when the load decreases and resume PWM mode when the load increases. When the device goes into PSM, it lowers the switching frequency saving switching and driver losses, and switches to pulse skip mode if the load continues to decrease. Error Amplifier The error amplifier (EA) is an internallycompensated amplifier. The EA compares the internal 0.807V reference voltage against VFB to generate an error signal. The output voltage of the MP3422 is adjusted by an external resistor divider. A voltage divider from VOUT to ground programs the output voltage via the FB pin from 2.5V to 5.5V using the equation: VOUT=0.807V x (1+R1/R2) Set the value of R1 and R2 to achieve low quiescent current. R1 values larger than 600k are recommended for good stability and transient balance. www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. 11 MP3422—6.5A, 600KHZ HIGH EFFICIENCY, SYNCHRONOUS, STEP-UP CONVERTER WITH OUTPUT DISCONNECT IN 2X2MM QFN PACKAGE Current Sensing Lossless current sensing converts the NMOS switch current signal to a voltage which is summed with the internal slope compensation. The summed signal is compared to the error amplifier output to provide a peak current control command for the PWM. Minimum peak switch current limit is 6.5A. The switch current signal is blanked for about 60ns internally to enhance noise rejection. Output Disconnect The MP3422 is designed to allow true output disconnect by eliminating body diode conduction of the internal PMOS rectifier. This allows VOUT to go to zero volts during shutdown, or isolate and maintain an external bias on VOUT. It also allows for inrush current limit at start-up, minimizing surge current seen by the input supply. To obtain the advantage of output disconnect, there must not be an external Schottky diode connected between the switch pin and VOUT. Over Load and Short Circuit Protection When an overload or a short circuit occurs, the output voltage will drop. If Vout drops below Vin+0.3V, the MP3422 will convert to step down mode. If Vout drops below 1.7V, the device will convert to linear charge mode. If Vout drops below about 70% of the nominal output voltage, the MP3422 will immediately shut down and restart after about 40μs as a new power-on cycle. Over Voltage Protection If Vout is higher than 7V, boost switching stops. This prevents overvoltage from damaging the internal power MOSFET. When the output drops below 7V, the device resumes switching automatically. Thermal Shutdown The device contains an internal temperature monitor. The switches turn off if the die temperature exceeds 150°C. The device will resume normal operation below 130°C. MP3422 Rev.1.01 8/6/2014 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. 12 MP3422—6.5A, 600KHZ HIGH EFFICIENCY, SYNCHRONOUS, STEP-UP CONVERTER WITH OUTPUT DISCONNECT IN 2X2MM QFN PACKAGE APPLICATION INFORMATION COMPONENT SELECTION Input Capacitor Selection Low ESR input capacitors reduce input switching noise and reduce the peak current drawn from the battery. Ceramic capacitors are a good choice for input decoupling and should be located as close as possible to the device. A ceramic capacitor larger than 22μF is recommended to restrain VIN ripple. Output Capacitor Selection The output capacitor requires a minimum capacitance value of 22μF at the programmed output voltage to ensure stability over the full operating range. A higher capacitance value may be required to lower the output ripple and also transient ripple. Low ESR capacitors such as X5R or X7R type ceramic capacitors are recommended. Supposing that ESR is zero, the minimum output capacitor to support the ripple in the PWM mode could be calculated by: CO ≥ IO × (VOUT(MAX) − VIN(MIN) ) fS × V OUT(MAX) ×ΔV Where, VOUT(MAX) = Maximum output voltage VIN(MIN) = Minimum Input voltage IO=Output current fS = Switching frequency ΔV= Acceptable output ripple A 1μF ceramic capacitor is recommended between the Out and PGnd pins. This reduces spikes on the SW node and improves EMI performance. Inductor Selection The MP3422 can utilize small surface mount chip inductors due to its 600kHz switching frequency. Inductor values between 1μH and 2.2μH are suitable for most applications. Larger values of inductance will allow slightly greater output current capability by reducing the inductor ripple current, but larger value inductance increases component size. The minimum inductance value is given by: L≥ VIN(MIN) × (VOUT(MAX) − VIN(MIN) ) VOUT(MAX) × ΔIL × fS The inductor current ripple is typically set for 30% to 40% of the maximum inductor current. The inductor should have low DCR (series resistance of the inductor current without saturating windings) to reduce the resistive power loss. The saturated current (ISAT) should be large enough to support the peak current. PCB Layout Considerations PCB layout for high frequency switching power supplies can be critical. Poor layout can result in reduced performance, excessive EMI, resistive loss and system instability. The steps below ensure good layout design. 1. The output capacitor must be placed as close as possible to the OUT pin, with minimal distance to PGND. A small decoupling capacitor should be paralleled with the bulk output capacitor and placed as close as possible to the OUT Pin. This is very important to reduce the spikes on the SW Pin and improve EMI performance. 2. The input capacitor and inductor should as close as possible to the IN and SW pins. The trace between the inductor and the SW pin should be wide and as short as possible. 3. The feedback loop should be far away from all noise sources such as the SW pin. The feedback divider resistors should be as close as possible to the FB and AGND pins. 4. The ground return of the input/output capacitors should be tied as close as possible to the PGND pin with a large copper GND area. Vias around the GND pin are recommended to lower the die temperature. 5. INA pin must be connected to IN. NC pin can either float or be connected to GND. (3) ΔIL=Acceptable inductor current ripple MP3422 Rev.1.01 8/6/2014 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. 13 MP3422—6.5A, 600KHZ HIGH EFFICIENCY, SYNCHRONOUS, STEP-UP CONVERTER WITH OUTPUT DISCONNECT IN 2X2MM QFN PACKAGE Figure 2 recommends components placement for MP3422. Top Layer SW L1 Bottom Layer Via VIN VOUT MP3422 OUT OUT OUT NC C1 SW SW IN PGND PGND PGND INA PGND C2A EN AGND R2 FB C2B PGND Vias for heat sink R1 Design Example Below is a design example following the application guidelines for the following specifications: Table 2: Design Example VIN 2.8V-4.2V VOUT 5V IOUT 0A-2.5A The typical application circuit for VOUT = 5V in Figure 3 shows the detailed application schematic, and is the basis for the typical performance waveforms. For more detailed device applications, please refer to the related Evaluation Board Datasheets. Figure 2, Layout Recommendation MP3422 Rev.1.01 8/6/2014 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. 14 MP3422—6.5A, 600KHZ HIGH EFFICIENCY, SYNCHRONOUS, STEP-UP CONVERTER WITH OUTPUT DISCONNECT IN 2X2MM QFN PACKAGE TYPICAL APPLICATION CIRCUITS L1 1.5uH VIN C1A 22uF C1B 22uF VOUT SW IN OUT INA R1 787kΩ MP3422 EN FB PGND C2A 1uF C2B 22uF C2C 5V 22uF R2 150kΩ AGND Figure 3, Typical Boost Application Circuit, VIN=2.8V to 4.2V, VOUT=5V, IOUT=0A-2.5A MP3422 Rev.1.01 8/6/2014 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. 15 MP3422—6.5A, 600KHZ HIGH EFFICIENCY, SYNCHRONOUS, STEP-UP CONVERTER WITH OUTPUT DISCONNECT IN 2X2MM QFN PACKAGE PACKAGE INFORMATION QFN-14 (2mmX2mm) NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. MP3422 Rev.1.01 8/6/2014 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. 16