FUJITSU SEMICONDUCTOR DATA SHEET DS05-20874-7E FLASH MEMORY CMOS 16M (2M × 8/1M × 16) BIT Dual Operation MBM29DL16XTD/BD -70/90 ■ FEATURES • 0.33 µm Process Technology • Simultaneous Read/Write operations (dual bank) Multiple devices available with different bank sizes (Refer to “MBM29DL16XTD/BD Device Bank Divisions Table” in ■GENERAL DESCRIPTION) Host system can program or erase in one bank, then immediately and simultaneously read from the other bank Zero latency between read and write operations Read-while-erase Read-while-program • Single 3.0 V read, program, and erase Minimizes system level power requirements (Continued) ■ PRODUCT LINE UP Part No. MBM29DL16XTD/MBM29DL16XBD VCC = 3.3 V +0.3 V –0.3 V 70 — VCC = 3.0 V +0.6 V –0.3 V — 90 Max Address Access Time (ns) 70 90 Max CE Access Time (ns) 70 90 Max OE Access Time (ns) 30 35 Ordering Part No. ■ PACKAGES 48-pin plastic TSOP (1) 48-pin plastic TSOP (1) 48-ball plastic FBGA Marking Side Marking Side (FPT-48P-M19) (FPT-48P-M20) (BGA-48P-M13) MBM29DL16XTD/BD-70/90 (Continued) • Compatible with JEDEC-standard commands Uses same software commands as E2PROMs • Compatible with JEDEC-standard world-wide pinouts 48-pin TSOP(1) (Package suffix: PFTN – Normal Bend Type, PFTR – Reversed Bend Type) 48-ball FBGA (Package suffix: PBT) • Minimum 100,000 program/erase cycles • High performance 70 ns maximum access time • Sector erase architecture Eight 4K word and thirty one 32K word sectors in word mode Eight 8K byte and thirty one 64K byte sectors in byte mode Any combination of sectors can be concurrently erased. Also supports full chip erase. • Boot Code Sector Architecture T = Top sector B = Bottom sector • HiddenROM region 64K byte of HiddenROM, accessible through a new “HiddenROM Enable” command sequence Factory serialized and protected to provide a secure electronic serial number (ESN) • WP/ACC input pin At VIL, allows protection of boot sectors, regardless of sector group protection/unprotection status At VACC, increases program performance • Embedded EraseTM* Algorithms Automatically pre-programs and erases the chip or any sector • Embedded ProgramTM* Algorithms Automatically writes and verifies data at specified address • Data Polling and Toggle Bit feature for detection of program or erase cycle completion • Ready/Busy output (RY/BY) Hardware method for detection of program or erase cycle completion • Automatic sleep mode When addresses remain stable, automatically switch themselves to low power mode. • Low VCC write inhibit ≤ 2.5 V • Erase Suspend/Resume Suspends the erase operation to allow a read data and/or program in another sector within the same device • Sector group protection Hardware method disables any combination of sector groups from program or erase operations • Sector Group Protection Set function by Extended sector group protection command • Fast Programming Function by Extended Command • Temporary sector group unprotection Temporary sector group unprotection via the RESET pin. • In accordance with CFI (Common Flash Memory Interface) * : Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc. 2 MBM29DL16XTD/BD-70/90 ■ GENERAL DESCRIPTION The MBM29DL16XTD/BD are a 16M-bit, 3.0 V-only Flash memory organized as 2M bytes of 8 bits each or 1M words of 16 bits each. The MBM29DL16XTD/BD are offered in a 48-pin TSOP(1) and 48-ball FBGA Package. These devices are designed to be programmed in-system with the standard system 3.0 V VCC supply. 12.0 V VPP and 5.0 V VCC are not required for write or erase operations. The devices can also be reprogrammed in standard EPROM programmers. MBM29DL16XTD/BD are organized into two banks, Bank 1 and Bank 2, which are considered to be two separate memory arrays for operations. It is the Fujitsu’s standard 3 V only Flash memories, with the additional capability of allowing a normal non-delayed read access from a non-busy bank of the array while an embedded write (either a program or an erase) operation is simultaneously taking place on the other bank. In the MBM29DL16XTD/BD, a new design concept is implemented, so called “Sliding Bank Architecture”. Under this concept, the MBM29DL16XTD/BD can be produced a series of devices with different Bank 1/Bank 2 size combinations; 0.5 Mb/15.5 Mb, 2 Mb/14 Mb, 4 Mb/12 Mb, 8 Mb/8 Mb. The standard MBM29DL16XTD/BD offer access times 70 ns and 90 ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention the devices have separate chip enable (CE), write enable (WE), and output enable (OE) controls. The MBM29DL16XTD/BD are pin and command set compatible with JEDEC standard E2PROMs. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the devices is similar to reading from 5.0 V and 12.0 V Flash or EPROM devices. The MBM29DL16XTD/BD are programmed by executing the program command sequence. This will invoke the Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. Typically, each sector can be programmed and verified in about 0.5 seconds. Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed before executing the erase operation. During erase, the devices automatically time the erase pulse widths and verify proper cell margin. A sector is typically erased and verified in 1.0 second. (If already completely preprogrammed.) The devices also feature a sector erase architecture. The sector mode allows each sector to be erased and reprogrammed without affecting other sectors. The MBM29DL16XTD/BD are erased when shipped from the factory. The devices feature single 3.0 V power supply operation for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. A low VCC detector automatically inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ7, by the Toggle Bit feature on DQ6, or the RY/BY output pin. Once the end of a program or erase cycle has been completed, the devices internally reset to the read mode. Fujitsu’s Flash technology combines years of EPROM and E2PROM experience to produce the highest levels of quality, reliability, and cost effectiveness. The MBM29DL16XTD/BD memories electrically erase the entire chip or all bits within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed one byte/word at a time using the EPROM programming mechanism of hot electron injection. 3 MBM29DL16XTD/BD-70/90 MBM29DL16XTD/BD Device Bank Divisions Table Device Part Number Organization Bank 1 Megabits Sector Sizes Megabits Sector Sizes MBM29DL161TD/BD 0.5 Mbit Eight 8K byte/4K word 15.5 Mbit Thirty-one 64K byte/32K word MBM29DL162TD/BD 2 Mbit Eight 8K byte/4K word, three 64K byte/32K word 14 Mbit Twenty-eight 64K byte/32K word MBM29DL163TD/BD 4 Mbit Eight 8K byte/4K word, seven 64K byte/32K word 12 Mbit Twenty-four 64K byte/32K word MBM29DL164TD/BD 8 Mbit Eight 8K byte/4K word, fifteen 64K byte/32K word 8 Mbit Sixteen 64K byte/32K word × 8/× 16 4 Bank 2 MBM29DL16XTD/BD-70/90 ■ PIN ASSIGNMENTS TSOP(1) A15 A14 A13 A12 A11 A10 A9 A8 A19 N.C. WE RESET N.C. WP/ACC RY/BY A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 (Marking Side) Normal Bend 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 BYTE VSS DQ 15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE VSS CE A0 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 A0 CE VSS OE DQ0 DQ8 DQ1 DQ9 DQ2 DQ10 DQ3 DQ11 VCC DQ4 DQ12 DQ5 DQ13 DQ6 DQ14 DQ7 DQ15/A-1 VSS BYTE A16 FPT-48P-M19 A1 A2 A3 A4 A5 A6 A7 A17 A18 RY/BY WP/ACC N.C. RESET WE N.C. A19 A8 A9 A10 A11 A12 A13 A14 A15 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 (Marking Side) Reverse Bend FPT-48P-M20 (Continued) 5 MBM29DL16XTD/BD-70/90 (Continued) FBGA (TOP VIEW) Marking side A1 A2 A3 A4 A5 A6 B1 B2 B3 B4 B5 B6 C1 C2 C3 C4 C5 C6 D1 D2 D3 D4 D5 D6 E1 E2 E3 E4 E5 E6 F1 F2 F3 F4 F5 F6 G1 G2 G3 G4 G5 G6 H1 H2 H3 H4 H5 H6 (BGA-48P-M13) A1 A3 A2 A7 A3 RY/BY B1 A4 B2 A17 B3 C1 A2 C2 A6 D1 A1 D2 E1 A0 F1 A4 WE A5 A9 A6 A13 WP/ACC B4 RESET B5 A8 B6 A12 C3 A18 C4 N.C. C5 A10 C6 A14 A5 D3 N.C. D4 A19 D5 A11 D6 A15 E2 DQ0 E3 DQ2 E4 DQ5 E5 DQ7 E6 A16 CE F2 DQ8 F3 DQ10 F4 DQ12 F5 DQ14 F6 BYTE G1 OE G2 DQ9 G3 DQ11 G4 VCC G5 DQ13 G6 DQ15/A-1 H1 VSS H2 DQ1 H3 DQ3 H4 DQ4 H5 DQ6 H6 VSS ■ PIN DESCRIPTIONS Pin A19 to A0, A-1 Address Inputs DQ15 to DQ0 Data Inputs/Outputs CE Chip Enable OE Output Enable WE Write Enable RY/BY Ready/Busy Output RESET Hardware Reset Pin/Temporary Sector Group Unprotection BYTE WP/ACC 6 Function Selects 8-bit or 16-bit mode Hardware Write Protection/Program Acceleration N.C. No Internal Connection VSS Device Ground VCC Device Power Supply MBM29DL16XTD/BD-70/90 ■ BLOCK DIAGRAM V CC Cell Matrix Bank 2 Address A19 to A0 (A-1) (Bank 2) Y-Gating & Data Latch V SS X-Decoder RY/BY State Control & Command Register Status DQ 15 to DQ 0 Control X-Decoder Bank 1 Address Cell Matrix (Bank 1) Y-Gating & Data Latch RESET WE CE OE BYTE WP/ACC DQ 15 to DQ0 ■ LOGIC SYMBOL A-1 20 A19 to A0 16 or 8 DQ 15 to DQ 0 CE OE WE RY/BY RESET BYTE WP/ACC 7 MBM29DL16XTD/BD-70/90 ■ DEVICE BUS OPERATION MBM29DL16XTD/BD User Bus Operations Table (BYTE = VIH) Operation CE OE WE A0 A1 A6 A9 DQ15 to DQ0 RESET WP/ACC L L H L L L VID Code H X L L H H L L VID Code H X Read* L L H A0 A1 A6 A9 DOUT H X Standby H X X X X X X High-Z H X Output Disable L H H X X X X High-Z H X L H L A0 A1 A6 A9 DIN H X L VID L H L VID X H X L L H L H L VID Code H X Temporary Sector Group Unprotection* X X X X X X X X VID X Reset (Hardware) / Standby X X X X X X X High-Z L X Boot Block Sector Write Protection X X X X X X X X X L Auto-Select Manufacturer Code*1 1 Auto-Select Device Code* 3 Write (Program/Erase) 2, 4 Enable Sector Group Protection* * 2, 4 Verify Sector Group Protection* * 5 = Pulse input. See “■DC CHARACTERISTICS” for voltage levels. Legend: L = VIL, H = VIH, X = VIL or VIH, *1 : Manufacturer and device codes are accessed via a command register write sequence. See “MBM29DL16XTD/ BD Command Definitions Table”. *2 : Refer to the section on Sector Group Protection. *3 : WE can be VIL if OE is VIL, OE at VIH initiates the write operations. *4 : VCC = 3.3 V ± 10% *5 : Also used for the extended sector group protection. MBM29DL16XTD/BD User Bus Operations Table (BYTE = VIL) 15 CE OE WE DQ /A-1 Operation Auto-Select Manufacturer Code*1 1 Auto-Select Device Code* A0 A1 A6 A9 DQ7 to DQ0 RESET WP/ACC L L H L L L L VID Code H X L L H L H L L VID Code H X Read* L L H A-1 A0 A1 A6 A9 DOUT H X Standby H X X X X X X X High-Z H X Output Disable L H H X X X X X High-Z H X Write (Program/Erase) L H L A-1 A0 A1 A6 A9 DIN H X Enable Sector Group Protection*2,*4 L VID L L H L VID X H X Verify Sector Group Protection*2,*4 L L H L L H L VID Code H X Temporary Sector Group Unprotection*5 X X X X X X X X X VID X Reset (Hardware) / Standby X X X X X X X X High-Z L X 3 Boot Block Sector Write Protection X X X X X X X X X X L = Pulse input. See “■DC CHARACTERISTICS” for voltage levels. Legend: L = VIL, H = VIH, X = VIL or VIH, *1 : Manufacturer and device codes are accessed via a command register write sequence. See “MBM29DL16XTD/ BD Command Definitions Table”. *2 : Refer to the section on Sector Group Protection. *3 : WE can be VIL if OE is VIL, OE at VIH initiates the write operations. *4 : VCC = 3.3 V ± 10% *5 : Also used for the extended sector group protection. 8 MBM29DL16XTD/BD-70/90 MBM29DL16XTD/BD Command Definitions Table Command Sequence Read/Reset*1 Read/Reset*1 Word Byte Word Byte Bus Write Cycles Req’d 1 XXXh 3 555h 2AAh AAh AAAh 555h 3 Byte Program Suspend Program Resume Chip Erase Sector Erase Word Byte Word Byte Erase Suspend Erase Resume Set to Fast Mode Word Fast Program *2 Word Reset from Fast Mode *2 Word Extended Sector Group Protection *3 Byte Byte Byte Word Byte 4 1 1 6 6 1 1 3 2 2 3 Word 1 4 Query * Byte HiddenROM Entry Word HiddenROM Program *5 Word HiddenROM Erase *5 Word HiddenROM Exit *5 Byte Byte Byte 3 4 6 AAh 555h AAAh BA BA 555h AAAh 555h AAAh BA BA 555h AAAh XXXh XXXh BA BA XXXh Byte 2AAh 555h B0h — 30h — 2AAh AAh 555h 2AAh AAh 555h B0h — 30h — 2AAh AAh 555h AAh A0h PA 55h — — 55h 55h — — 55h PD 90h XXXh F0h*6 XXXh 60h SPA 555h AAAh (BA) 555h (BA) AAAh 555h AAAh — — 555h AAAh 555h AAAh — — 555h AAAh 55h — — — — — F0h RA*7 RD*7 — — — — 90h IA*7 ID*7 — — — — A0h PA PD — — — — — — — — 555h AAAh — — — — 80h 80h — — — — — — — — 555h 2AAh AAh AAAh 555h 555h 2AAh AAh AAAh 555h — — — — — — 55h 10h 55h SA 30h — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — 55h — — — 55h — 20h SPA 555h AAAh 555h AAAh 555h AAAh 40h SPA*7 SD*7 — — — — — — — 88h — — — — — — A0h PA (HRA) PD — — — — 80h 555h 2AAh AAh AAAh 555h 55h HRA 30h 90h XXXh — — — (HRBA) 55h 555h — 60h 2AAh AAh AAAh 55h 55h (BA) 55h 98h — (BA) AAh 555h 2AAh AAh AAAh 555h 555h 2AAh AAh AAAh 555h 555h 2AAh AAh AAAh 555h 4 — 555h 555h Word — 2AAh AAAh Byte Word F0h 555h Word Autoselect Program First Bus Second Bus Third Bus Fourth Bus Fifth Bus Sixth Bus Write Cycle Write Cycle Write Cycle Read/Write Write Cycle Write Cycle Cycle Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data 555h (HRBA) 00h — AAAh *1 : Both of these reset commands are equivalent. *2 : This command is valid during Fast Mode. *3 : This command is valid while RESET = VID (except during HiddenROM MODE) . 9 MBM29DL16XTD/BD-70/90 *4 : The valid addresses are A6 to A0. *5 : This command is valid during HiddenROM mode. *6 : The data “00h” is also acceptable. *7 : The fourth bus cycle is only for read. Notes: • Address bits A19 to A11 = X = “H” or “L” for all address commands except or Program Address (PA), Sector Address (SA), and Bank Address (BA). • • Bus operations are defined in “MBM29DL16XTD/BD User Bus Operations Tables (BYTE = VIH and BYTE = VIL)”. • • • • • • • 10 RA = IA = Address of the memory location to be read Autoselect read address that sets both the bank address specified at (A19, A18, A17, A16, A15) and all the other A6, A1, A0, (A-1) . PA = Address of the memory location to be programmed Addresses are latched on the falling edge of the write pulse. SA = Address of the sector to be erased. The combination of A19, A18, A17, A16, A15, A14, A13, and A12 will uniquely select any sector. BA = Bank Address (A15 to A19) RD = Data read from location RA during read operation. ID = Device code/manufacture code for the address located by IA. PD = Data to be programmed at location PA. Data is latched on the rising edge of write pulse. SPA = Sector group address to be protected. Set sector group address (SGA) and (A6, A1, A0) = (0, 1, 0). SD = Sector group protection verify data. Output 01h at protected sector group addresses and output 00h at unprotected sector group addresses. HRA = Address of the HiddenROM area 29DL16XTD (Top Boot Type) Word Mode: 0F8000h to 0FFFFFh Byte Mode: 1F0000h to 1FFFFFh 29DL16XBD (Bottom Boot Type) Word Mode: 000000h to 007FFFh Byte Mode: 000000h to 00FFFFh HRBA =Bank Address of the HiddenROM area 29DL16XTD (Top Boot Type) :A19 = A18 = A17 = A16 = A15 = VIH 29DL16XBD (Bottom Boot Type) :A19 = A18 = A17 = A16 = A15 = VIL The system should generate the following address patterns: Word Mode: 555h or 2AAh to addresses A10 to A0 Byte Mode: AAAh or 555h to addresses A10 to A0 and A–1 Both Read/Reset commands are functionally equivalent, resetting the device to the read mode. Command combinations not described in “MBM29DL16XTD/BD Command Definitions Table” are illegal. MBM29DL16XTD/BD-70/90 MBM29DL161TD/BD Sector Group Protection Verify Autoselect Codes Table Type A19 to A12 A6 A1 A0 A-1*1 Code (HEX) BA*3 VIL VIL VIL VIL 04h VIL 36h BA*3 VIL VIL VIH X 2236h VIL 39h X 2239h VIL 01h*2 Manufacture’s Code Byte MBM29DL161TD Word Device Code Byte MBM29DL161BD VIL BA*3 VIL VIH Word Sector Group Addresses Sector Group Protection VIH VIL VIL *1 : A−1 is for Byte mode. At Byte mode, DQ8 to DQ14 are High-Z and DQ15 is A−1, the lowest address. *2 : Outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses. *3 : When VID is applied to A9, both Bank 1 and Bank 2 are put into Autoselect mode, which makes simultaneous operation unable to be executed. Consequently, specifying the bank address is not required. However, the bank address needs to be indicated when Autoselect mode is read out at command mode, because then it enables to activate simultaneous operation. Extended Autoselect Code Table Type Code Manufacturer’s Code 04h (B)* DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 0 0 0 0 0 1 0 0 36h A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 39h A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z 0 0 1 1 1 0 0 1 A-1/0 0 0 0 0 0 0 0 MBM29DL161TD (W) 2236h 0 Device Code (B)* 0 1 0 0 0 1 0 MBM29DL161BD (W) 2239h 0 Sector Group Protection 01h A-1/0 0 1 0 0 0 1 0 0 0 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 * : At Byte mode, DQ8 to DQ14 are High-Z and DQ15 is A−1, the lowest address. (B) : Byte mode (W) : Word mode HI-Z : High-Z 11 MBM29DL16XTD/BD-70/90 MBM29DL162TD/BD Sector Group Protection Verify Autoselect Codes Table Type A19 to A12 A6 A1 A0 A-1*1 Code (HEX) BA*3 VIL VIL VIL VIL 04h VIL 2Dh BA*3 VIL VIL VIH X 222Dh VIL 2Eh X 222Eh VIL 01h*2 Manufacture’s Code Byte MBM29DL162TD Word Device Code Byte MBM29DL162BD VIL BA*3 VIL VIH Word Sector Group Addresses Sector Group Protection VIH VIL VIL *1 : A−1 is for Byte mode. At Byte mode, DQ8 to DQ14 are High-Z and DQ15 is A−1, the lowest address. *2 : Outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses. *3 : When VID is applied to A9, both Bank 1 and Bank 2 are put into Autoselect mode, which makes simultaneous operation unable to be executed. Consequently, specifying the bank address is not required. However, the bank address needs to be indicated when Autoselect mode is read out at command mode, because then it enables to activate simultaneous operation. Extended Autoselect Code Table Type Code Manufacturer’s Code 04h (B)* DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 0 0 0 0 0 1 0 0 2Dh A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z 0 0 1 0 1 1 0 1 0 0 1 0 1 1 0 1 2Eh A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z 0 0 1 0 1 1 1 0 A-1/0 0 0 0 0 0 0 0 MBM29DL162TD (W) 222Dh 0 Device Code (B)* 0 1 0 0 0 1 0 MBM29DL162BD (W) 222Eh 0 Sector Group Protection 01h A-1/0 0 1 0 0 0 1 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 * : At Byte mode, DQ8 to DQ14 are High-Z and DQ15 is A−1, the lowest address. (B) : Byte mode (W) : Word mode HI-Z : High-Z 12 MBM29DL16XTD/BD-70/90 MBM29DL163TD/BD Sector Group Protection Verify Autoselect Codes Table Type A19 to A12 A6 A1 A0 A-1*1 Code (HEX) BA*3 VIL VIL VIL VIL 04h VIL 28h BA*3 VIL VIL VIH X 2228h VIL 2Bh X 222Bh VIL 01h*2 Manufacture’s Code Byte MBM29DL163TD Word Device Code Byte MBM29DL163BD VIL BA*3 VIL VIH Word Sector Group Addresses Sector Group Protection VIH VIL VIL *1 : A−1 is for Byte mode. At Byte mode, DQ8 to DQ14 are High-Z and DQ15 is A−1, the lowest address. *2 : Outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses. *3 : When VID is applied to A9, both Bank 1 and Bank 2 are put into Autoselect mode, which makes simultaneous operation unable to be executed. Consequently, specifying the bank address is not required. However, the bank address needs to be indicated when Autoselect mode is read out at command mode, because then it enables to activate simultaneous operation. Extended Autoselect Code Table Type Code Manufacturer’s Code 04h (B)* DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 0 0 0 0 0 1 0 0 28h A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z 0 0 1 0 1 0 0 0 0 0 1 0 1 0 0 0 2Bh A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z 0 0 1 0 1 0 1 1 A-1/0 0 0 0 0 0 0 0 MBM29DL163TD (W) 2228h 0 Device Code (B)* 0 1 0 0 0 1 0 MBM29DL163BD (W) 222Bh 0 Sector Group Protection 01h A-1/0 0 1 0 0 0 1 0 0 0 1 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 * : At Byte mode, DQ8 to DQ14 are High-Z and DQ15 is A−1, the lowest address. (B) : Byte mode (W) : Word mode HI-Z : High-Z 13 MBM29DL16XTD/BD-70/90 MBM29DL164TD/BD Sector Group Protection Verify Autoselect Codes Table Type A19 to A12 A6 A1 A0 A-1*1 Code (HEX) BA*3 VIL VIL VIL VIL 04h VIL 33h BA*3 VIL VIL VIH X 2233h VIL 35h X 2235h VIL 01h*2 Manufacture’s Code Byte MBM29DL164TD Word Device Code Byte MBM29DL164BD VIL BA*3 VIL VIH Word Sector Group Addresses Sector Group Protection VIH VIL VIL *1 : A−1 is for Byte mode. At Byte mode, DQ8 to DQ14 are High-Z and DQ15 is A−1, the lowest address. *2 : Outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses. *3 : When VID is applied to A9, both Bank 1 and Bank 2 are put into Autoselect mode, which makes simultaneous operation unable to be executed. Consequently, specifying the bank address is not required. However, the bank address needs to be indicated when Autoselect mode is read out at command mode, because then it enables to activate simultaneous operation. Extended Autoselect Code Table Type Code Manufacturer’s Code 04h (B)* DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 0 0 0 0 0 1 0 0 33h A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 35h A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z 0 0 1 1 0 1 0 1 A-1/0 0 0 0 0 0 0 0 MBM29DL164TD (W) 2233h 0 Device Code (B)* 0 1 0 0 0 1 0 MBM29DL164BD (W) 2235h 0 Sector Group Protection 01h A-1/0 0 1 0 0 0 1 0 0 0 1 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 * : At Byte mode, DQ8 to DQ14 are High-Z and DQ15 is A−1, the lowest address. (B) : Byte mode (W) : Word mode HI-Z : High-Z 14 MBM29DL16XTD/BD-70/90 ■ FLEXIBLE SECTOR-ERASE ARCHITECTURE Sector Address Table (MBM29DL161TD) Bank Sector Bank 2 Bank 1 SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38 Sector Address Sector Size (×8) (×16) Bank Address (Kbytes/ Address Range Address Range A19 A18 A17 A16 A15 A14 A13 A12 Kwords) 0 0 0 0 0 X X X 64/32 000000h to 00FFFFh 000000h to 007FFFh 0 0 0 0 1 X X X 64/32 010000h to 01FFFFh 008000h to 00FFFFh 0 0 0 1 0 X X X 64/32 020000h to 02FFFFh 010000h to 017FFFh 0 0 0 1 1 X X X 64/32 030000h to 03FFFFh 018000h to 01FFFFh 0 0 1 0 0 X X X 64/32 040000h to 04FFFFh 020000h to 027FFFh 0 0 1 0 1 X X X 64/32 050000h to 05FFFFh 028000h to 02FFFFh 0 0 1 1 0 X X X 64/32 060000h to 06FFFFh 030000h to 037FFFh 0 0 1 1 1 X X X 64/32 070000h to 07FFFFh 038000h to 03FFFFh 0 1 0 0 0 X X X 64/32 080000h to 08FFFFh 040000h to 047FFFh 0 1 0 0 1 X X X 64/32 090000h to 09FFFFh 048000h to 04FFFFh 0 1 0 1 0 X X X 64/32 0A0000h to 0AFFFFh 050000h to 057FFFh 0 1 0 1 1 X X X 64/32 0B0000h to 0BFFFFh 058000h to 05FFFFh 0 1 1 0 0 X X X 64/32 0C0000h to 0CFFFFh 060000h to 067FFFh 0 1 1 0 1 X X X 64/32 0D0000h to 0DFFFFh 068000h to 06FFFFh 0 1 1 1 0 X X X 64/32 0E0000h to 0EFFFFh 070000h to 077FFFh 0 1 1 1 1 X X X 64/32 0F0000h to 0FFFFFh 078000h to 07FFFFh 1 0 0 0 0 X X X 64/32 100000h to 10FFFFh 080000h to 087FFFh 1 0 0 0 1 X X X 64/32 110000h to 11FFFFh 088000h to 08FFFFh 1 0 0 1 0 X X X 64/32 120000h to 12FFFFh 090000h to 097FFFh 1 0 0 1 1 X X X 64/32 130000h to 13FFFFh 098000h to 09FFFFh 1 0 1 0 0 X X X 64/32 140000h to 14FFFFh 0A0000h to 0A7FFFh 1 0 1 0 1 X X X 64/32 150000h to 15FFFFh 0A8000h to 0AFFFFh 1 0 1 1 0 X X X 64/32 160000h to 16FFFFh 0B0000h to 0B7FFFh 1 0 1 1 1 X X X 64/32 170000h to 17FFFFh 0B8000h to 0BFFFFh 1 1 0 0 0 X X X 64/32 180000h to 18FFFFh 0C0000h to 0C7FFFh 1 1 0 0 1 X X X 64/32 190000h to 19FFFFh 0C8000h to 0CFFFFh 1 1 0 1 0 X X X 64/32 1A0000h to 1AFFFFh 0D0000h to 0D7FFFh 1 1 0 1 1 X X X 64/32 1B0000h to 1BFFFFh 0D8000h to 0DFFFFh 1 1 1 0 0 X X X 64/32 1C0000h to 1CFFFFh 0E0000h to 0E7FFFh 1 1 1 0 1 X X X 64/32 1D0000h to 1DFFFFh 0E8000h to 0EFFFFh 1 1 1 1 0 X X X 64/32 1E0000h to 1EFFFFh 0F0000h to 0F7FFFh 1 1 1 1 1 0 0 0 8/4 1F0000h to 1F1FFFh 0F8000h to 0F8FFFh 1 1 1 1 1 0 0 1 8/4 1F2000h to 1F3FFFh 0F9000h to 0F9FFFh 1 1 1 1 1 0 1 0 8/4 1F4000h to 1F5FFFh 0FA000h to 0FAFFFh 1 1 1 1 1 0 1 1 8/4 1F6000h to 1F7FFFh 0FB000h to 0FBFFFh 1 1 1 1 1 1 0 0 8/4 1F8000h to 1F9FFFh 0FC000h to 0FCFFFh 1 1 1 1 1 1 0 1 8/4 1FA000h to 1FBFFFh 0FD000h to 0FDFFFh 1 1 1 1 1 1 1 0 8/4 1FC000h to 1FDFFFh 0FE000h to 0FEFFFh 1 1 1 1 1 1 1 1 8/4 1FE000h to 1FFFFFh 0FF000h to 0FFFFFh Note: The address range is A19: A-1 if in byte mode (BYTE = VIL). The address range is A19: A0 if in word mode (BYTE = VIH) 15 MBM29DL16XTD/BD-70/90 Sector Address Table (MBM29DL161BD) Bank Sector Bank 2 Bank 1 SA38 SA37 SA36 SA35 SA34 SA33 SA32 SA31 SA30 SA29 SA28 SA27 SA26 SA25 SA24 SA23 SA22 SA21 SA20 SA19 SA18 SA17 SA16 SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 Sector Address Sector Size Bank Address (Kbytes/ A19 A18 A17 A16 A15 A14 A13 A12 Kwords) 1 1 1 1 1 X X X 64/32 1 1 1 1 0 X X X 64/32 1 1 1 0 1 X X X 64/32 1 1 1 0 0 X X X 64/32 1 1 0 1 1 X X X 64/32 1 1 0 1 0 X X X 64/32 1 1 0 0 1 X X X 64/32 1 1 0 0 0 X X X 64/32 1 0 1 1 1 X X X 64/32 1 0 1 1 0 X X X 64/32 1 0 1 0 1 X X X 64/32 1 0 1 0 0 X X X 64/32 1 0 0 1 1 X X X 64/32 1 0 0 1 0 X X X 64/32 1 0 0 0 X X X X 64/32 1 0 0 0 0 X X X 64/32 0 1 1 1 1 X X X 64/32 0 1 1 1 0 X X X 64/32 0 1 1 0 1 X X X 64/32 0 1 1 0 0 X X X 64/32 0 1 0 1 1 X X X 64/32 0 1 0 1 0 X X X 64/32 0 1 0 0 1 X X X 64/32 0 1 0 0 0 X X X 64/32 0 0 1 1 1 X X X 64/32 0 0 1 1 0 X X X 64/32 0 0 1 0 1 X X X 64/32 0 0 1 0 0 X X X 64/32 0 0 0 1 1 X X X 64/32 0 0 0 1 0 X X X 64/32 0 0 0 0 1 X X X 64/32 0 0 0 0 0 1 1 1 8/4 0 0 0 0 0 1 1 0 8/4 0 0 0 0 0 1 0 1 8/4 0 0 0 0 0 1 0 0 8/4 0 0 0 0 0 0 1 1 8/4 0 0 0 0 0 0 1 0 8/4 0 0 0 0 0 0 0 1 8/4 0 0 0 0 0 0 0 0 8/4 Note: The address range is A19: A-1 if in byte mode (BYTE = VIL). The address range is A19: A0 if in word mode (BYTE = VIH). 16 (×8) Address Range (×16) Address Range 1F0000h to 1FFFFFh 1E0000h to 1EFFFFh 1D0000h to 1DFFFFh 1C0000h to 1CFFFFh 1B0000h to 1BFFFFh 1A0000h to 1AFFFFh 190000h to 19FFFFh 180000h to 18FFFFh 170000h to 17FFFFh 160000h to 16FFFFh 150000h to 15FFFFh 140000h to 14FFFFh 130000h to 13FFFFh 120000h to 12FFFFh 110000h to 11FFFFh 100000h to 10FFFFh 0F0000h to 0FFFFFh 0E0000h to 0EFFFFh 0D0000h to 0DFFFFh 0C0000h to 0CFFFFh 0B0000h to 0BFFFFh 0A0000h to 0AFFFFh 090000h to 09FFFFh 080000h to 08FFFFh 070000h to 07FFFFh 060000h to 06FFFFh 050000h to 05FFFFh 040000h to 04FFFFh 030000h to 03FFFFh 020000h to 02FFFFh 010000h to 01FFFFh 00E000h to 00FFFFh 00C000h to 00DFFFh 00A000h to 00BFFFh 008000h to 009FFFh 006000h to 007FFFh 004000h to 005FFFh 002000h to 003FFFh 000000h to 001FFFh 0F8000h to 0FFFFFh 0F0000h to 0F7FFFh 0E8000h to 0EFFFFh 0E0000h to 0E7FFFh 0D8000h to 0DFFFFh 0D0000h to 0D7FFFh 0C8000h to 0CFFFFh 0C0000h to 0C7FFFh 0B8000h to 0BFFFFh 0B0000h to 0B7FFFh 0A8000h to 0AFFFFh 0A0000h to 0A7FFFh 098000h to 09FFFFh 090000h to 097FFFh 088000h to 08FFFFh 080000h to 087FFFh 078000h to 07FFFFh 070000h to 077FFFh 068000h to 06FFFFh 060000h to 067FFFh 058000h to 05FFFFh 050000h to 057FFFh 048000h to 04FFFFh 040000h to 047FFFh 038000h to 03FFFFh 030000h to 037FFFh 028000h to 02FFFFh 020000h to 027FFFh 018000h to 01FFFFh 010000h to 017FFFh 008000h to 00FFFFh 007000h to 007FFFh 006000h to 006FFFh 005000h to 005FFFh 004000h to 004FFFh 003000h to 003FFFh 002000h to 002FFFh 001000h to 001FFFh 000000h to 000FFFh MBM29DL16XTD/BD-70/90 Sector Address Table (MBM29DL162TD) Bank Sector Bank 2 Bank 1 SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38 Sector Address Sector Size Bank (×8) (×16) (Kbytes/ Address Address Range Address Range Kwords) A19 A18 A17 A16 A15 A14 A13 A12 0 0 0 0 0 X X X 64/32 000000h to 00FFFFh 000000h to 007FFFh 0 0 0 0 1 X X X 64/32 010000h to 01FFFFh 008000h to 00FFFFh 0 0 0 1 0 X X X 64/32 020000h to 02FFFFh 010000h to 017FFFh 0 0 0 1 1 X X X 64/32 030000h to 03FFFFh 018000h to 01FFFFh 0 0 1 0 0 X X X 64/32 040000h to 04FFFFh 020000h to 027FFFh 0 0 1 0 1 X X X 64/32 050000h to 05FFFFh 028000h to 02FFFFh 0 0 1 1 0 X X X 64/32 060000h to 06FFFFh 030000h to 037FFFh 0 0 1 1 1 X X X 64/32 070000h to 07FFFFh 038000h to 03FFFFh 0 1 0 0 0 X X X 64/32 080000h to 08FFFFh 040000h to 047FFFh 0 1 0 0 1 X X X 64/32 090000h to 09FFFFh 048000h to 04FFFFh 0 1 0 1 0 X X X 64/32 0A0000h to 0AFFFFh 050000h to 057FFFh 0 1 0 1 1 X X X 64/32 0B0000h to 0BFFFFh 058000h to 05FFFFh 0 1 1 0 0 X X X 64/32 0C0000h to 0CFFFFh 060000h to 067FFFh 0 1 1 0 1 X X X 64/32 0D0000h to 0DFFFFh 068000h to 06FFFFh 0 1 1 1 0 X X X 64/32 0E0000h to 0EFFFFh 070000h to 077FFFh 0 1 1 1 1 X X X 64/32 0F0000h to 0FFFFFh 078000h to 07FFFFh 1 0 0 0 0 X X X 64/32 100000h to 10FFFFh 080000h to 087FFFh 1 0 0 0 1 X X X 64/32 110000h to 11FFFFh 088000h to 08FFFFh 1 0 0 1 0 X X X 64/32 120000h to 12FFFFh 090000h to 097FFFh 1 0 0 1 1 X X X 64/32 130000h to 13FFFFh 098000h to 09FFFFh 1 0 1 0 0 X X X 64/32 140000h to 14FFFFh 0A0000h to 0A7FFFh 1 0 1 0 1 X X X 64/32 150000h to 15FFFFh 0A8000h to 0AFFFFh 1 0 1 1 0 X X X 64/32 160000h to 16FFFFh 0B0000h to 0B7FFFh 1 0 1 1 1 X X X 64/32 170000h to 17FFFFh 0B8000h to 0BFFFFh 1 1 0 0 0 X X X 64/32 180000h to 18FFFFh 0C0000h to 0C7FFFh 1 1 0 0 1 X X X 64/32 190000h to 19FFFFh 0C8000h to 0CFFFFh 1 1 0 1 0 X X X 64/32 1A0000h to 1AFFFFh 0D0000h to 0D7FFFh 1 1 0 1 1 X X X 64/32 1B0000h to 1BFFFFh 0D8000h to 0DFFFFh 1 1 1 0 0 X X X 64/32 1C0000h to 1CFFFFh 0E0000h to 0E7FFFh 1 1 1 0 1 X X X 64/32 1D0000h to 1DFFFFh 0E8000h to 0EFFFFh 1 1 1 1 0 X X X 64/32 1E0000h to 1EFFFFh 0F0000h to 0F7FFFh 1 1 1 1 1 0 0 0 8/4 1F0000h to 1F1FFFh 0F8000h to 0F8FFFh 1 1 1 1 1 0 0 1 8/4 1F2000h to 1F3FFFh 0F9000h to 0F9FFFh 1 1 1 1 1 0 1 0 8/4 1F4000h to 1F5FFFh 0FA000h to 0FAFFFh 1 1 1 1 1 0 1 1 8/4 1F6000h to 1F7FFFh 0FB000h to 0FBFFFh 1 1 1 1 1 1 0 0 8/4 1F8000h to 1F9FFFh 0FC000h to 0FCFFFh 1 1 1 1 1 1 0 1 8/4 1FA000h to 1FBFFFh 0FD000h to 0FDFFFh 1 1 1 1 1 1 1 0 8/4 1FC000h to 1FDFFFh 0FE000h to 0FEFFFh 1 1 1 1 1 1 1 1 8/4 1FE000h to 1FFFFFh 0FF000h to 0FFFFFh Note: The address range is A19: A-1 if in byte mode (BYTE = VIL). The address range is A19: A0 if in word mode (BYTE = VIH) 17 MBM29DL16XTD/BD-70/90 Sector Address Table (MBM29DL162BD) Bank Sector Bank 2 Bank 1 SA38 SA37 SA36 SA35 SA34 SA33 SA32 SA31 SA30 SA29 SA28 SA27 SA26 SA25 SA24 SA23 SA22 SA21 SA20 SA19 SA18 SA17 SA16 SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 Sector Address Sector Bank Size (Kbytes/ Address Kwords) A19 A18 A17 A16 A15 A14 A13 A12 1 1 1 1 1 X X X 64/32 1 1 1 1 0 X X X 64/32 1 1 1 0 1 X X X 64/32 1 1 1 0 0 X X X 64/32 1 1 0 1 1 X X X 64/32 1 1 0 1 0 X X X 64/32 1 1 0 0 1 X X X 64/32 1 1 0 0 0 X X X 64/32 1 0 1 1 1 X X X 64/32 1 0 1 1 0 X X X 64/32 1 0 1 0 1 X X X 64/32 1 0 1 0 0 X X X 64/32 1 0 0 1 1 X X X 64/32 1 0 0 1 0 X X X 64/32 1 0 0 0 X X X X 64/32 1 0 0 0 0 X X X 64/32 0 1 1 1 1 X X X 64/32 0 1 1 1 0 X X X 64/32 0 1 1 0 1 X X X 64/32 0 1 1 0 0 X X X 64/32 0 1 0 1 1 X X X 64/32 0 1 0 1 0 X X X 64/32 0 1 0 0 1 X X X 64/32 0 1 0 0 0 X X X 64/32 0 0 1 1 1 X X X 64/32 0 0 1 1 0 X X X 64/32 0 0 1 0 1 X X X 64/32 0 0 1 0 0 X X X 64/32 0 0 0 1 1 X X X 64/32 0 0 0 1 0 X X X 64/32 0 0 0 0 1 X X X 64/32 0 0 0 0 0 1 1 1 8/4 0 0 0 0 0 1 1 0 8/4 0 0 0 0 0 1 0 1 8/4 0 0 0 0 0 1 0 0 8/4 0 0 0 0 0 0 1 1 8/4 0 0 0 0 0 0 1 0 8/4 0 0 0 0 0 0 0 1 8/4 0 0 0 0 0 0 0 0 8/4 Note: The address range is A19: A-1 if in byte mode (BYTE = VIL). The address range is A19: A0 if in word mode (BYTE = VIH). 18 (×8) Address Range (×16) Address Range 1F0000h to 1FFFFFh 1E0000h to 1EFFFFh 1D0000h to 1DFFFFh 1C0000h to 1CFFFFh 1B0000h to 1BFFFFh 1A0000h to 1AFFFFh 190000h to 19FFFFh 180000h to 18FFFFh 170000h to 17FFFFh 160000h to 16FFFFh 150000h to 15FFFFh 140000h to 14FFFFh 130000h to 13FFFFh 120000h to 12FFFFh 110000h to 11FFFFh 100000h to 10FFFFh 0F0000h to 0FFFFFh 0E0000h to 0EFFFFh 0D0000h to 0DFFFFh 0C0000h to 0CFFFFh 0B0000h to 0BFFFFh 0A0000h to 0AFFFFh 090000h to 09FFFFh 080000h to 08FFFFh 070000h to 07FFFFh 060000h to 06FFFFh 050000h to 05FFFFh 040000h to 04FFFFh 030000h to 03FFFFh 020000h to 02FFFFh 010000h to 01FFFFh 00E000h to 00FFFFh 00C000h to 00DFFFh 00A000h to 00BFFFh 008000h to 009FFFh 006000h to 007FFFh 004000h to 005FFFh 002000h to 003FFFh 000000h to 001FFFh 0F8000h to 0FFFFFh 0F0000h to 0F7FFFh 0E8000h to 0EFFFFh 0E0000h to 0E7FFFh 0D8000h to 0DFFFFh 0D0000h to 0D7FFFh 0C8000h to 0CFFFFh 0C0000h to 0C7FFFh 0B8000h to 0BFFFFh 0B0000h to 0B7FFFh 0A8000h to 0AFFFFh 0A0000h to 0A7FFFh 098000h to 09FFFFh 090000h to 097FFFh 088000h to 08FFFFh 080000h to 087FFFh 078000h to 07FFFFh 070000h to 077FFFh 068000h to 06FFFFh 060000h to 067FFFh 058000h to 05FFFFh 050000h to 057FFFh 048000h to 04FFFFh 040000h to 047FFFh 038000h to 03FFFFh 030000h to 037FFFh 028000h to 02FFFFh 020000h to 027FFFh 018000h to 01FFFFh 010000h to 017FFFh 008000h to 00FFFFh 007000h to 007FFFh 006000h to 006FFFh 005000h to 005FFFh 004000h to 004FFFh 003000h to 003FFFh 002000h to 002FFFh 001000h to 001FFFh 000000h to 000FFFh MBM29DL16XTD/BD-70/90 Sector Address Table (MBM29DL163TD) Sector Address Sector Size (×8) (×16) BA (Kbytes/ Address Range Address Range A19 A18 A17 A16 A15 A14 A13 A12 Kwords) SA0 0 0 0 0 0 X X X 64/32 000000h to 00FFFFh 000000h to 007FFFh SA1 0 0 0 0 1 X X X 64/32 010000h to 01FFFFh 008000h to 00FFFFh SA2 0 0 0 1 0 X X X 64/32 020000h to 02FFFFh 010000h to 017FFFh SA3 0 0 0 1 1 X X X 64/32 030000h to 03FFFFh 018000h to 01FFFFh SA4 0 0 1 0 0 X X X 64/32 040000h to 04FFFFh 020000h to 027FFFh SA5 0 0 1 0 1 X X X 64/32 050000h to 05FFFFh 028000h to 02FFFFh SA6 0 0 1 1 0 X X X 64/32 060000h to 06FFFFh 030000h to 037FFFh SA7 0 0 1 1 1 X X X 64/32 070000h to 07FFFFh 038000h to 03FFFFh SA8 0 1 0 0 0 X X X 64/32 080000h to 08FFFFh 040000h to 047FFFh SA9 0 1 0 0 1 X X X 64/32 090000h to 09FFFFh 048000h to 04FFFFh SA10 0 1 0 1 0 X X X 64/32 0A0000h to 0AFFFFh 050000h to 057FFFh SA11 0 1 0 1 1 X X X 64/32 0B0000h to 0BFFFFh 058000h to 05FFFFh Bank 2 SA12 0 1 1 0 0 X X X 64/32 0C0000h to 0CFFFFh 060000h to 067FFFh SA13 0 1 1 0 1 X X X 64/32 0D0000h to 0DFFFFh 068000h to 06FFFFh SA14 0 1 1 1 0 X X X 64/32 0E0000h to 0EFFFFh 070000h to 077FFFh SA15 0 1 1 1 1 X X X 64/32 0F0000h to 0FFFFFh 078000h to 07FFFFh SA16 1 0 0 0 0 X X X 64/32 100000h to 10FFFFh 080000h to 087FFFh SA17 1 0 0 0 1 X X X 64/32 110000h to 11FFFFh 088000h to 08FFFFh SA18 1 0 0 1 0 X X X 64/32 120000h to 12FFFFh 090000h to 097FFFh SA19 1 0 0 1 1 X X X 64/32 130000h to 13FFFFh 098000h to 09FFFFh SA20 1 0 1 0 0 X X X 64/32 140000h to 14FFFFh 0A0000h to 0A7FFFh SA21 1 0 1 0 1 X X X 64/32 150000h to 15FFFFh 0A8000h to 0AFFFFh SA22 1 0 1 1 0 X X X 64/32 160000h to 16FFFFh 0B0000h to 0B7FFFh SA23 1 0 1 1 1 X X X 64/32 170000h to 17FFFFh 0B8000h to 0BFFFFh SA24 1 1 0 0 0 X X X 64/32 180000h to 18FFFFh 0C0000h to 0C7FFFh SA25 1 1 0 0 1 X X X 64/32 190000h to 19FFFFh 0C8000h to 0CFFFFh SA26 1 1 0 1 0 X X X 64/32 1A0000h to 1AFFFFh 0D0000h to 0D7FFFh SA27 1 1 0 1 1 X X X 64/32 1B0000h to 1BFFFFh 0D8000h to 0DFFFFh SA28 1 1 1 0 0 X X X 64/32 1C0000h to 1CFFFFh 0E0000h to 0E7FFFh SA29 1 1 1 0 1 X X X 64/32 1D0000h to 1DFFFFh 0E8000h to 0EFFFFh SA30 1 1 1 1 0 X X X 64/32 1E0000h to 1EFFFFh 0F0000h to 0F7FFFh Bank 1 SA31 1 1 1 1 1 0 0 0 8/4 1F0000h to 1F1FFFh 0F8000h to 0F8FFFh SA32 1 1 1 1 1 0 0 1 8/4 1F2000h to 1F3FFFh 0F9000h to 0F9FFFh SA33 1 1 1 1 1 0 1 0 8/4 1F4000h to 1F5FFFh 0FA000h to 0FAFFFh SA34 1 1 1 1 1 0 1 1 8/4 1F6000h to 1F7FFFh 0FB000h to 0FBFFFh SA35 1 1 1 1 1 1 0 0 8/4 1F8000h to 1F9FFFh 0FC000h to 0FCFFFh SA36 1 1 1 1 1 1 0 1 8/4 1FA000h to 1FBFFFh 0FD000h to 0FDFFFh SA37 1 1 1 1 1 1 1 0 8/4 1FC000h to 1FDFFFh 0FE000h to 0FEFFFh SA38 1 1 1 1 1 1 1 1 8/4 1FE000h to 1FFFFFh 0FF000h to 0FFFFFh BA: Bank Address Bank Sector Note: The address range is A19: A-1 if in byte mode (BYTE = VIL). The address range is A19: A0 if in word mode (BYTE = VIH) 19 MBM29DL16XTD/BD-70/90 Sector Address Table (MBM29DL163BD) Sector Address Sector Size BA (Kbytes/ A19 A18 A17 A16 A15 A14 A13 A12 Kwords) SA38 1 1 1 1 1 X X X 64/32 SA37 1 1 1 1 0 X X X 64/32 SA36 1 1 1 0 1 X X X 64/32 SA35 1 1 1 0 0 X X X 64/32 SA34 1 1 0 1 1 X X X 64/32 SA33 1 1 0 1 0 X X X 64/32 SA32 1 1 0 0 1 X X X 64/32 SA31 1 1 0 0 0 X X X 64/32 SA30 1 0 1 1 1 X X X 64/32 SA29 1 0 1 1 0 X X X 64/32 SA28 1 0 1 0 1 X X X 64/32 SA27 1 0 1 0 0 X X X 64/32 Bank 2 SA26 1 0 0 1 1 X X X 64/32 SA25 1 0 0 1 0 X X X 64/32 SA24 1 0 0 0 X X X X 64/32 SA23 1 0 0 0 0 X X X 64/32 SA22 0 1 1 1 1 X X X 64/32 SA21 0 1 1 1 0 X X X 64/32 SA20 0 1 1 0 1 X X X 64/32 SA19 0 1 1 0 0 X X X 64/32 SA18 0 1 0 1 1 X X X 64/32 SA17 0 1 0 1 0 X X X 64/32 SA16 0 1 0 0 1 X X X 64/32 SA15 0 1 0 0 0 X X X 64/32 SA14 0 0 1 1 1 X X X 64/32 SA13 0 0 1 1 0 X X X 64/32 SA12 0 0 1 0 1 X X X 64/32 SA11 0 0 1 0 0 X X X 64/32 SA10 0 0 0 1 1 X X X 64/32 SA9 0 0 0 1 0 X X X 64/32 SA8 0 0 0 0 1 X X X 64/32 Bank 1 SA7 0 0 0 0 0 1 1 1 8/4 SA6 0 0 0 0 0 1 1 0 8/4 SA5 0 0 0 0 0 1 0 1 8/4 SA4 0 0 0 0 0 1 0 0 8/4 SA3 0 0 0 0 0 0 1 1 8/4 SA2 0 0 0 0 0 0 1 0 8/4 SA1 0 0 0 0 0 0 0 1 8/4 SA0 0 0 0 0 0 0 0 0 8/4 BA: Bank Address Bank Sector Note: The address range is A19: A-1 if in byte mode (BYTE = VIL). The address range is A19: A0 if in word mode (BYTE = VIH). 20 (×8) Address Range (×16) Address Range 1F0000h to 1FFFFFh 1E0000h to 1EFFFFh 1D0000h to 1DFFFFh 1C0000h to 1CFFFFh 1B0000h to 1BFFFFh 1A0000h to 1AFFFFh 190000h to 19FFFFh 180000h to 18FFFFh 170000h to 17FFFFh 160000h to 16FFFFh 150000h to 15FFFFh 140000h to 14FFFFh 130000h to 13FFFFh 120000h to 12FFFFh 110000h to 11FFFFh 100000h to 10FFFFh 0F0000h to 0FFFFFh 0E0000h to 0EFFFFh 0D0000h to 0DFFFFh 0C0000h to 0CFFFFh 0B0000h to 0BFFFFh 0A0000h to 0AFFFFh 090000h to 09FFFFh 080000h to 08FFFFh 070000h to 07FFFFh 060000h to 06FFFFh 050000h to 05FFFFh 040000h to 04FFFFh 030000h to 03FFFFh 020000h to 02FFFFh 010000h to 01FFFFh 00E000h to 00FFFFh 00C000h to 00DFFFh 00A000h to 00BFFFh 008000h to 009FFFh 006000h to 007FFFh 004000h to 005FFFh 002000h to 003FFFh 000000h to 001FFFh 0F8000h to 0FFFFFh 0F0000h to 0F7FFFh 0E8000h to 0EFFFFh 0E0000h to 0E7FFFh 0D8000h to 0DFFFFh 0D0000h to 0D7FFFh 0C8000h to 0CFFFFh 0C0000h to 0C7FFFh 0B8000h to 0BFFFFh 0B0000h to 0B7FFFh 0A8000h to 0AFFFFh 0A0000h to 0A7FFFh 098000h to 09FFFFh 090000h to 097FFFh 088000h to 08FFFFh 080000h to 087FFFh 078000h to 07FFFFh 070000h to 077FFFh 068000h to 06FFFFh 060000h to 067FFFh 058000h to 05FFFFh 050000h to 057FFFh 048000h to 04FFFFh 040000h to 047FFFh 038000h to 03FFFFh 030000h to 037FFFh 028000h to 02FFFFh 020000h to 027FFFh 018000h to 01FFFFh 010000h to 017FFFh 008000h to 00FFFFh 007000h to 007FFFh 006000h to 006FFFh 005000h to 005FFFh 004000h to 004FFFh 003000h to 003FFFh 002000h to 002FFFh 001000h to 001FFFh 000000h to 000FFFh MBM29DL16XTD/BD-70/90 Sector Address Table (MBM29DL164TD) Sector Address Sector Size (×8) (×16) Bank Sector BA (Kbytes/ Address Range Address Range A19 A18 A17 A16 A15 A14 A13 A12 Kwords) SA0 0 0 0 0 0 X X X 64/32 000000h to 00FFFFh 000000h to 007FFFh SA1 0 0 0 0 1 X X X 64/32 010000h to 01FFFFh 008000h to 00FFFFh SA2 0 0 0 1 0 X X X 64/32 020000h to 02FFFFh 010000h to 017FFFh SA3 0 0 0 1 1 X X X 64/32 030000h to 03FFFFh 018000h to 01FFFFh SA4 0 0 1 0 0 X X X 64/32 040000h to 04FFFFh 020000h to 027FFFh SA5 0 0 1 0 1 X X X 64/32 050000h to 05FFFFh 028000h to 02FFFFh SA6 0 0 1 1 0 X X X 64/32 060000h to 06FFFFh 030000h to 037FFFh SA7 0 0 1 1 1 X X X 64/32 070000h to 07FFFFh 038000h to 03FFFFh Bank 2 SA8 0 1 0 0 0 X X X 64/32 080000h to 08FFFFh 040000h to 047FFFh SA9 0 1 0 0 1 X X X 64/32 090000h to 09FFFFh 048000h to 04FFFFh SA10 0 1 0 1 0 X X X 64/32 0A0000h to 0AFFFFh 050000h to 057FFFh SA11 0 1 0 1 1 X X X 64/32 0B0000h to 0BFFFFh 058000h to 05FFFFh SA12 0 1 1 0 0 X X X 64/32 0C0000h to 0CFFFFh 060000h to 067FFFh SA13 0 1 1 0 1 X X X 64/32 0D0000h to 0DFFFFh 068000h to 06FFFFh SA14 0 1 1 1 0 X X X 64/32 0E0000h to 0EFFFFh 070000h to 077FFFh SA15 0 1 1 1 1 X X X 64/32 0F0000h to 0FFFFFh 078000h to 07FFFFh SA16 1 0 0 0 0 X X X 64/32 100000h to 10FFFFh 080000h to 087FFFh SA17 1 0 0 0 1 X X X 64/32 110000h to 11FFFFh 088000h to 08FFFFh SA18 1 0 0 1 0 X X X 64/32 120000h to 12FFFFh 090000h to 097FFFh SA19 1 0 0 1 1 X X X 64/32 130000h to 13FFFFh 098000h to 09FFFFh SA20 1 0 1 0 0 X X X 64/32 140000h to 14FFFFh 0A0000h to 0A7FFFh SA21 1 0 1 0 1 X X X 64/32 150000h to 15FFFFh 0A8000h to 0AFFFFh SA22 1 0 1 1 0 X X X 64/32 160000h to 16FFFFh 0B0000h to 0B7FFFh SA23 1 0 1 1 1 X X X 64/32 170000h to 17FFFFh 0B8000h to 0BFFFFh SA24 1 1 0 0 0 X X X 64/32 180000h to 18FFFFh 0C0000h to 0C7FFFh SA25 1 1 0 0 1 X X X 64/32 190000h to 19FFFFh 0C8000h to 0CFFFFh SA26 1 1 0 1 0 X X X 64/32 1A0000h to 1AFFFFh 0D0000h to 0D7FFFh Bank 1 SA27 1 1 0 1 1 X X X 64/32 1B0000h to 1BFFFFh 0D8000h to 0DFFFFh SA28 1 1 1 0 0 X X X 64/32 1C0000h to 1CFFFFh 0E0000h to 0E7FFFh SA29 1 1 1 0 1 X X X 64/32 1D0000h to 1DFFFFh 0E8000h to 0EFFFFh SA30 1 1 1 1 0 X X X 64/32 1E0000h to 1EFFFFh 0F0000h to 0F7FFFh SA31 1 1 1 1 1 0 0 0 8/4 1F0000h to 1F1FFFh 0F8000h to 0F8FFFh SA32 1 1 1 1 1 0 0 1 8/4 1F2000h to 1F3FFFh 0F9000h to 0F9FFFh SA33 1 1 1 1 1 0 1 0 8/4 1F4000h to 1F5FFFh 0FA000h to 0FAFFFh SA34 1 1 1 1 1 0 1 1 8/4 1F6000h to 1F7FFFh 0FB000h to 0FBFFFh SA35 1 1 1 1 1 1 0 0 8/4 1F8000h to 1F9FFFh 0FC000h to 0FCFFFh SA36 1 1 1 1 1 1 0 1 8/4 1FA000h to 1FBFFFh 0FD000h to 0FDFFFh SA37 1 1 1 1 1 1 1 0 8/4 1FC000h to 1FDFFFh 0FE000h to 0FEFFFh SA38 1 1 1 1 1 1 1 1 8/4 1FE000h to 1FFFFFh 0FF000h to 0FFFFFh BA: Bank Address Note: The address range is A19: A-1 if in byte mode (BYTE = VIL). The address range is A19: A0 if in word mode (BYTE = VIH) 21 MBM29DL16XTD/BD-70/90 Sector Address Table (MBM29DL164BD) Sector Address Sector Size Bank Sector BA (Kbytes/ A19 A18 A17 A16 A15 A14 A13 A12 Kwords) SA38 1 1 1 1 1 X X X 64/32 SA37 1 1 1 1 0 X X X 64/32 SA36 1 1 1 0 1 X X X 64/32 SA35 1 1 1 0 0 X X X 64/32 SA34 1 1 0 1 1 X X X 64/32 SA33 1 1 0 1 0 X X X 64/32 SA32 1 1 0 0 1 X X X 64/32 SA31 1 1 0 0 0 X X X 64/32 Bank 2 SA30 1 0 1 1 1 X X X 64/32 SA29 1 0 1 1 0 X X X 64/32 SA28 1 0 1 0 1 X X X 64/32 SA27 1 0 1 0 0 X X X 64/32 SA26 1 0 0 1 1 X X X 64/32 SA25 1 0 0 1 0 X X X 64/32 SA24 1 0 0 0 X X X X 64/32 SA23 1 0 0 0 0 X X X 64/32 SA22 0 1 1 1 1 X X X 64/32 SA21 0 1 1 1 0 X X X 64/32 SA20 0 1 1 0 1 X X X 64/32 SA19 0 1 1 0 0 X X X 64/32 SA18 0 1 0 1 1 X X X 64/32 SA17 0 1 0 1 0 X X X 64/32 SA16 0 1 0 0 1 X X X 64/32 SA15 0 1 0 0 0 X X X 64/32 SA14 0 0 1 1 1 X X X 64/32 SA13 0 0 1 1 0 X X X 64/32 SA12 0 0 1 0 1 X X X 64/32 Bank 1 SA11 0 0 1 0 0 X X X 64/32 SA10 0 0 0 1 1 X X X 64/32 SA9 0 0 0 1 0 X X X 64/32 SA8 0 0 0 0 1 X X X 64/32 SA7 0 0 0 0 0 1 1 1 8/4 SA6 0 0 0 0 0 1 1 0 8/4 SA5 0 0 0 0 0 1 0 1 8/4 SA4 0 0 0 0 0 1 0 0 8/4 SA3 0 0 0 0 0 0 1 1 8/4 SA2 0 0 0 0 0 0 1 0 8/4 SA1 0 0 0 0 0 0 0 1 8/4 SA0 0 0 0 0 0 0 0 0 8/4 BA: Bank Address Note: The address range is A19: A-1 if in byte mode (BYTE = VIL). The address range is A19: A0 if in word mode (BYTE = VIH). 22 (×8) Address Range (×16) Address Range 1F0000h to 1FFFFFh 1E0000h to 1EFFFFh 1D0000h to 1DFFFFh 1C0000h to 1CFFFFh 1B0000h to 1BFFFFh 1A0000h to 1AFFFFh 190000h to 19FFFFh 180000h to 18FFFFh 170000h to 17FFFFh 160000h to 16FFFFh 150000h to 15FFFFh 140000h to 14FFFFh 130000h to 13FFFFh 120000h to 12FFFFh 110000h to 11FFFFh 100000h to 10FFFFh 0F0000h to 0FFFFFh 0E0000h to 0EFFFFh 0D0000h to 0DFFFFh 0C0000h to 0CFFFFh 0B0000h to 0BFFFFh 0A0000h to 0AFFFFh 090000h to 09FFFFh 080000h to 08FFFFh 070000h to 07FFFFh 060000h to 06FFFFh 050000h to 05FFFFh 040000h to 04FFFFh 030000h to 03FFFFh 020000h to 02FFFFh 010000h to 01FFFFh 00E000h to 00FFFFh 00C000h to 00DFFFh 00A000h to 00BFFFh 008000h to 009FFFh 006000h to 007FFFh 004000h to 005FFFh 002000h to 003FFFh 000000h to 001FFFh 0F8000h to 0FFFFFh 0F0000h to 0F7FFFh 0E8000h to 0EFFFFh 0E0000h to 0E7FFFh 0D8000h to 0DFFFFh 0D0000h to 0D7FFFh 0C8000h to 0CFFFFh 0C0000h to 0C7FFFh 0B8000h to 0BFFFFh 0B0000h to 0B7FFFh 0A8000h to 0AFFFFh 0A0000h to 0A7FFFh 098000h to 09FFFFh 090000h to 097FFFh 088000h to 08FFFFh 080000h to 087FFFh 078000h to 07FFFFh 070000h to 077FFFh 068000h to 06FFFFh 060000h to 067FFFh 058000h to 05FFFFh 050000h to 057FFFh 048000h to 04FFFFh 040000h to 047FFFh 038000h to 03FFFFh 030000h to 037FFFh 028000h to 02FFFFh 020000h to 027FFFh 018000h to 01FFFFh 010000h to 017FFFh 008000h to 00FFFFh 007000h to 007FFFh 006000h to 006FFFh 005000h to 005FFFh 004000h to 004FFFh 003000h to 003FFFh 002000h to 002FFFh 001000h to 001FFFh 000000h to 000FFFh MBM29DL16XTD/BD-70/90 Sector Group Address Table (MBM29DL16XTD) (Top Boot Block) Sector Group A19 A18 A17 A16 A15 A14 A13 A12 Sectors SGA0 0 0 0 0 0 X X X SA0 0 0 0 0 1 X X X 0 0 0 1 0 X X X 0 0 0 1 1 X X X SGA2 0 0 1 X X X X X SA4 to SA7 SGA3 0 1 0 X X X X X SA8 to SA11 SGA4 0 1 1 X X X X X SA12 to SA15 SGA5 1 0 0 X X X X X SA16 to SA19 SGA6 1 0 1 X X X X X SA20 to SA23 SGA7 1 1 0 X X X X X SA24 to SA27 1 1 1 0 0 X X X 1 1 1 0 1 X X X 1 1 1 1 0 X X X SGA9 1 1 1 1 1 0 0 0 SA31 SGA10 1 1 1 1 1 0 0 1 SA32 SGA11 1 1 1 1 1 0 1 0 SA33 SGA12 1 1 1 1 1 0 1 1 SA34 SGA13 1 1 1 1 1 1 0 0 SA35 SGA14 1 1 1 1 1 1 0 1 SA36 SGA15 1 1 1 1 1 1 1 0 SA37 SGA16 1 1 1 1 1 1 1 1 SA38 SGA1 SGA8 SA1 to SA3 SA28 to SA30 23 MBM29DL16XTD/BD-70/90 Sector Group Address Table (MBM29DL16XBD) (Bottom Boot Block) Sector Group A19 A18 A17 A16 A15 A14 A13 A12 Sectors SGA0 0 0 0 0 0 0 0 0 SA0 SGA1 0 0 0 0 0 0 0 1 SA1 SGA2 0 0 0 0 0 0 1 0 SA2 SGA3 0 0 0 0 0 0 1 1 SA3 SGA4 0 0 0 0 0 1 0 0 SA4 SGA5 0 0 0 0 0 1 0 1 SA5 SGA6 0 0 0 0 0 1 1 0 SA6 SGA7 0 0 0 0 0 1 1 1 SA7 0 0 0 0 1 X X X 0 0 0 1 0 X X X 0 0 0 1 1 X X X SGA9 0 0 1 X X X X X SA11 to SA14 SGA10 0 1 0 X X X X X SA15 to SA18 SGA11 0 1 1 X X X X X SA19 to SA22 SGA12 1 0 0 X X X X X SA23 to SA26 SGA13 1 0 1 X X X X X SA27 to SA30 SGA14 1 1 0 X X X X X SA31 to SA34 1 1 1 0 0 X X X 1 1 1 0 1 X X X 1 1 1 1 0 X X X 1 1 1 1 1 X X X SGA8 SGA15 SGA16 24 SA8 to SA10 SA35 to SA37 SA38 MBM29DL16XTD/BD-70/90 Description Common Flash Memory Interface Code Table Description A0 to A6 DQ0 to DQ15 Query-unique ASCII string “QRY” 10h 11h 12h 0051h 0052h 0059h Primary OEM Command Set 02h: AMD/FJ standard type 13h 14h 0002h 0000h Address for Primary Extended Table 15h 16h 0040h 0000h Alternate OEM Command Set (00h = not applicable) 17h 18h Address for Alternate OEM Extended Table A0 to A6 DQ0 to DQ15 Erase Block Region 2 Information bit15 to bit0 : y = number of sectors bit31 to bit16 : Z = size (Z × 256 bytes) 31h 32h 33h 34h 001Eh 0000h 0000h 0001h Query-unique ASCII string “PRI” 40h 41h 42h 0050h 0052h 0049h 0000h 0000h Major version number, ASCII 43h 0031h Minor version number, ASCII 44h 0031h 19h 1Ah 0000h 0000h Address Sensitive Unlock 00h = Required 45h 0000h VCC Min (write/erase) DQ7 to DQ4: 1 V, DQ3 to DQ0: 100 mV 1Bh 0027h Erase Suspend 02h = To Read & Write 46h 0002h 0001h 1Ch 0036h Sector Protection 00h = Not Supported X = Number of sectors in per group 47h VCC Max (write/erase) DQ7 to DQ4: 1 V, DQ3 to DQ0: 100 mV VPP Min voltage 1Dh 0000h 48h 0001h VPP Max voltage 1Eh 0000h Sector Temporary Unprotection 01h = Supported Typical timeout per single byte/ word write 2N µs 1Fh 0004h Sector Protection Algorithm 49h 0004h 4Ah 00XXh Typical timeout for Min size buffer write 2N µs 20h 0000h Typical timeout per individual sector erase 2N ms 21h 000Ah Typical timeout for full chip erase 2N ms 22h 0000h Max timeout for byte/word write 2N times typical 23h 0005h Number of Sector for Bank 2 00h = Not Supported 1Fh = MBM29DL161TD 1Ch = MBM29DL162TD 18h = MBM29DL163TD 10h = MBM29DL164TD 1Fh = MBM29DL161BD 1Ch = MBM29DL162BD 18h = MBM29DL163BD 10h = MBM29DL164BD Max timeout for buffer write 2N times typical 24h 0000h Burst Mode Type 00h = Not Supported 4Bh 0000h Max timeout per individual sector erase 2N times typical 25h 0004h Page Mode Type 00h = Not Supported 4Ch 0000h Max timeout for full chip erase 2N times typical 26h 0000h 4Dh 0085h Device Size = 2N byte 27h 0015h ACC (Acceleration) Supply Minimum DQ7 to DQ4: 1 V, DQ3 to DQ0: 100 mV Flash Device Interface description 02h : × 8/ × 16 28h 29h 0002h 0000h 4Eh 0095h Max number of bytes in multi-byte write = 2N 2Ah 2Bh 0000h 0000h ACC (Acceleration) Supply Maximum DQ7 to DQ4: 1 V, DQ3 to DQ0: 100 mV 4Fh 00XXh Number of Erase Block Regions within device 2Ch 0002h Boot Type 02h = MBM29DL16XBD 03h = MBM29DL16XTD Erase Block Region 1 Information bit15 to bit0 : y = number of sectors bit31 to bit16 : Z = size (Z × 256 bytes) 2Dh 2Eh 2Fh 30h 0007h 0000h 0020h 0000h 25 MBM29DL16XTD/BD-70/90 ■ FUNCTIONAL DESCRIPTION • Simultaneous Operation MBM29DL16XTD/BD have feature, which is capability of reading data from one bank of memory while a program or erase operation is in progress in the other bank of memory (simultaneous operation), in addition to the conventional features (read, program, erase, erase-suspend read, and erase-suspend program). The bank selection can be selected by bank address (A15 to A19) with zero latency. The MBM29DL161TD/BD have two banks which contain Bank 1 (8KB × eight sectors) and Bank 2 (64KB × thirty-one sectors). The MBM29DL162TD/BD have two banks which contain Bank 1 (8KB × eight sectors, 64KB × three sectors) and Bank 2 (64KB × twenty eight sectors). The MBM29DL163TD/BD have two banks which contain Bank 1 (8KB × eight sectors, 64KB × seven sectors) and Bank 2 (64KB × twenty four sectors). The MBM29DL164TD/BD have two banks which contain Bank 1 (8KB × eight sectors, 64KB × fifteen sectors) and Bank 2 (64KB × sixteen sectors). The simultaneous operation can not execute multi-function mode in the same bank. “Simultaneous Operation Table” shows combination to be possible for simultaneous operation. (Refer to “(8) Bank-to-bank Read/Write Timing Diagram” in ■TIMING DIAGRAM.) Simultaneous Operation Table Case Bank 1 Status Bank 2 Status 1 Read mode Read mode 2 Read mode Autoselect mode 3 Read mode Program mode 4 Read mode Erase mode * 5 Autoselect mode Read mode 6 Program mode Read mode 7 Erase mode * Read mode *: An erase operation may also be supended to read from or program to a sector not being erased. • Read Mode The MBM29DL16XTD/BD have two control functions which must be satisfied in order to obtain data at the outputs. CE is the power control and should be used for a device selection. OE is the output control and should be used to gate data to the output pins if a device is selected. Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable access time (tCE) is the delay from stable addresses and stable CE to valid data at the output pins. The output enable access time is the delay from the falling edge of OE to valid data at the output pins. (Assuming the addresses have been stable for at least tACC-tOE time.) When reading out a data without changing addresses after power-up, it is necessary to input hardware reset or to change CE pin from “H” or “L” • Standby Mode There are two ways to implement the standby mode on the MBM29DL16XTD/BD devices, one using both the CE and RESET pins; the other via the RESET pin only. When using both pins, a CMOS standby mode is achieved with CE and RESET inputs both held at VCC ± 0.3 V. Under this condition the current consumed is less than 5 µA Max. During Embedded Algorithm operation, VCC active current (ICC2) is required even CE = “H”. The device can be read with standard access time (tCE) from either of these standby modes. 26 MBM29DL16XTD/BD-70/90 When using the RESET pin only, a CMOS standby mode is achieved with RESET input held at VSS ± 0.3 V (CE = “H” or “L”). Under this condition the current is consumed is less than 5 µA Max. Once the RESET pin is taken high, the device requires tRH of wake up time before outputs are valid for read access. In the standby mode the outputs are in the high impedance state, independent of the OE input. • Automatic Sleep Mode There is a function called automatic sleep mode to restrain power consumption during read-out of MBM29DL16XTD/BD data. This mode can be used effectively with an application requested low power consumption such as handy terminals. To activate this mode, MBM29DL16XTD/BD automatically switch themselves to low power mode when MBM29DL16XTD/BD addresses remain stably during access fine of 150 ns. It is not necessary to control CE, WE, and OE on the mode. Under the mode, the current consumed is typically 1 µA (CMOS Level). During simultaneous operation, VCC active current (ICC2) is required. Since the data are latched during this mode, the data are read-out continuously. If the addresses are changed, the mode is canceled automatically and MBM29DL16XTD/BD read-out the data for changed addresses. • Output Disable With the OE input at a logic high level (VIH), output from the devices are disabled. This will cause the output pins to be in a high impedance state. • Autoselect The autoselect mode allows the reading out of a binary code from the devices and will identify its manufacturer and type. This mode is intended for use by programming equipment for the purpose of automatically matching the devices to be programmed with its corresponding programming algorithm. This mode is functional over the entire temperature range of the devices. To activate this mode, the programming equipment must force VID (11.5 V to 12.5 V) on address pin A9. Two identifier bytes may then be sequenced from the devices outputs by toggling address A0 from VIL to VIH. All addresses are DON’T CARES except A0, A1, and A6 (A-1). (See “MBM29DL16XTD/BD User Bus Operations Tables (BYTE = VIH and BYTE = VIL)” in ■DEVICE BUS OPERATION.) The manufacturer and device codes may also be read via the command register, for instances when the MBM29DL16XTD/BD are erased or programmed in a system without access to high voltage on the A9 pin. The command sequence is illustrated in “MBM29DL16XTD/BD Command Definitions Table” (in ■DEVICE BUS OPERATION). (Refer to Autoselect Command section.) Byte 0 (A0 = VIL) represents the manufacturer’s code (Fujitsu = 04h) and word 1 (A0 = VIH) represents the device identifier code (MBM29DL161TD = 36h and MBM29DL161BD = 39h for ×8 mode; MBM29DL161TD = 2236h and MBM29DL161BD = 2239h for ×16 mode), (MBM29DL162TD = 2Dh and MBM29DL162BD = 2Eh for ×8 mode; MBM29DL162TD = 222Dh and MBM29DL162BD = 222Eh for ×16 mode), (MBM29DL163TD = 28h and MBM29DL163BD = 2Bh for ×8 mode; MBM29DL163TD = 2228h and MBM29DL163BD = 222Bh for ×16 mode), (MBM29DL164TD = 33h and MBM29DL164BD = 35h for ×8 mode; MBM29DL164TD = 2233h and MBM29DL164BD = 2235h for ×16 mode). These two bytes/words are given in “MBM29DL161TD/BD, MBM29DL162TD/BD, MBM29DL163TD/BD and MBM29DL164TD/BD Sector Group Protection Verify Autoselect Codes Tables” and these “Extended Autoselect Code Tables” in ■DEVICE BUS OPERATION. All identifiers for manufactures and device will exhibit odd parity with DQ7 defined as the parity bit. In order to read the proper device codes when executing the autoselect, A1 must be VIL. (See “MBM29DL161TD/BD, MBM29DL162TD/BD, MBM29DL163TD/BD and MBM29DL164TD/BD Sector Group Protection Verify Autoselect Codes Tables” and these “Extended Autoselect Code Tables” in ■DEVICE BUS OPERATION.) In case of applying VID on A9, since both Bank 1 and Bank 2 enters Autoselect mode, the simultenous operation can not be executed. 27 MBM29DL16XTD/BD-70/90 • Write Device erasure and programming are accomplished via the command register. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. The command register itself does not occupy any addressable memory location. The register is a latch used to store the commands, along with the address and data information needed to execute the command. The command register is written by bringing WE to VIL, while CE is at VIL and OE is at VIH. Addresses are latched on the falling edge of WE or CE, whichever happens later; while data is latched on the rising edge of WE or CE, whichever happens first. Standard microprocessor write timings are used. Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters. • Sector Group Protection The MBM29DL16XTD/BD feature hardware sector group protection. This feature will disable both program and erase operations in any combination of seventeen sector groups of memory. (See “Sector Group Addresses (MBM29DL16XTD/BD) Tables” in ■FLEXIBLE SECTOR-ERASE ARCHITECTURE). The sector group protection feature is enabled using programming equipment at the user’s site. The device is shipped with all sector groups unprotected. To activate this mode, the programming equipment must force VID on address pin A9 and control pin OE, (suggest VID = 11.5 V), CE = VIL and A0 = A6 = VIL, A1 = VIH. The sector group addresses (A19, A18, A17, A16, A15, A14, A13, and A12) should be set to the sector to be protected. “Sector Address Tables (MBM29DL161TD/BD, MBM29DL162TD/BD, MBM29DL163TD/BD, MBM29DL164TD/BD)” in ■FLEXIBLE SECTOR-ERASE ARCHITECTURE define the sector address for each of the thirty nine (39) individual sectors, and “Sector Group Addresses (MBM29DL16XTD/BD) Tables” in ■FLEXIBLE SECTOR-ERASE ARCHITECTURE define the sector group address for each of the seventeen (17) individual group sectors. Programming of the protection circuitry begins on the falling edge of the WE pulse and is terminated with the rising edge of the same. Sector group addresses must be held constant during the WE pulse. See “(15) AC Waveforms for Sector Group Protection” in ■TIMING DIAGRAM and “(5) Sector Group Protection Algorithm” in ■FLOW CHART for sector group protection waveforms and algorithm. To verify programming of the protection circuitry, the programming equipment must force VID on address pin A9 with CE and OE at VIL and WE at VIH. Scanning the sector group addresses (A19, A18, A17, A16, A15, A14, A13, and A12) while (A6, A1, A0) = (0, 1, 0) will produce a logical “1” code at device output DQ0 for a protected sector. Otherwise the device will produce “0” for unprotected sector. In this mode, the lower order addresses, except for A0, A1, and A6 are DON’T CARES. Address locations with A1 = VIL are reserved for Autoselect manufacturer and device codes. A-1 requires to apply to VIL on byte mode. It is also possible to determine if a sector group is protected in the system by writing an Autoselect command. Performing a read operation at the address location XX02h, where the higher order addresses (A19, A18, A17, A16, A15, A14, A13, and A12) are the desired sector group address will produce a logical “1” at DQ0 for a protected sector group. See “MBM29DL161TD/BD, MBM29DL162TD/BD, MBM29DL163TD/BD and MBM29DL164TD/BD Sector Group Protection Verify Autoselect Codes Tables” and these “Extended Autoselect Code Tables” in ■DEVICE BUS OPERATION for Autoselect codes. • Temporary Sector Group Unprotection This feature allows temporary unprotection of previously protected sector groups of the MBM29DL16XTD/BD devices in order to change data. The Sector Group Unprotection mode is activated by setting the RESET pin to high voltage (VID). During this mode, formerly protected sector groups can be programmed or erased by selecting the sector group addresses. Once the VID is taken away from the RESET pin, all the previously protected sector groups will be protected again. Refer to “(16) Temporary Sector Group Unprotection Timing Diagram” in ■TIMING DIAGRAM and “(6) Temporary Sector Group Unprotection Algorithm” in ■FLOW CHART. 28 MBM29DL16XTD/BD-70/90 • RESET Hardware Reset The MBM29DL16XTD/BD devices may be reset by driving the RESET pin to VIL. The RESET pin has a pulse requirement and has to be kept low (VIL) for at least “tRP” in order to properly reset the internal state machine. Any operation in the process of being executed will be terminated and the internal state machine will be reset to the read mode “tREADY” after the RESET pin is driven low. Furthermore, once the RESET pin goes high, the devices require an additional “tRH” before it will allow read access. When the RESET pin is low, the devices will be in the standby mode for the duration of the pulse and all the data output pins will be tri-stated. If a hardware reset occurs during a program or erase operation, the data at that particular location will be corrupted. Please note that the RY/BY output signal should be ignored during the RESET pulse. See “(11) RESET, RY/BY Timing Diagram” in ■TIMING DIAGRAM for the timing diagram. Refer to Temporary Sector Group Unprotection for additional functionality. • Boot Block Sector Protection The Write Protect function provides a hardware method of protecting certain boot sectors without using VID. This function is one of two provided by the WP/ACC pin. If the system asserts VIL on the WP/ACC pin, the device disables program and erase functions in the two “outermost” 8K byte boot sectors (MBM29DL16XTD: SA37 and SA38, MBM29DL16XBD: SA0 and SA1) independently of whether those sectors were protected or unprotected using the method described in “Sector Group Protection”. The two outermost 8K byte boot sectors are the two sectors containing the lowest addresses in a bottom-boot-configured device, or the two sectors containing the highest addresses in a top-boot-congfigured device. If the system asserts VIH on the WP/ACC pin, the device reverts to whether the two outermost 8K byte boot sectors were last set to be protected or unprotected. That is, sector group protection or unprotection for these two sectors depends on whether they were last protected or unprotected using the method described in “Sector Group Protection”. • Accelerated Program Operation MBM29DL16XTD/BD offers accelerated program operation which enables the programming in high speed. If the system asserts VACC to the WP/ACC pin, the device automatically enters the acceleration mode and the time required for program operation will reduce to about 60%. This function is primarily intended to allow high speed program, so caution is needed as the sector group will temporarily be unprotected. The system would use a fact program command sequence when programming during acceleration mode. Set command to fast mode and reset command from fast mode are not necessary. When the device enters the acceleration mode, the device automatically set to fast mode. Therefore, the pressent sequence could be used for programming and detection of completion during acceleration mode. Removing VACC from the WP/ACC pin returns the device to normal operation. Do not remove VACC from WP/ ACC pin while programming. See “(18) Accelerated Program Timing Diagram” in ■TIMING DIAGRAM. Erase operation at Acceleration mode is strictly prohibited. 29 MBM29DL16XTD/BD-70/90 ■ COMMAND DEFINITIONS Device operations are selected by writing specific address and data sequences into the command register. Writing incorrect address and data values or writing them in the improper sequence will reset the devices to the read mode. Some commands are required Bank Address (BA) input. When command sequences are inputed to bank being read, the commands have priority than reading. “MBM29DL16XTD/BD Command Definitions Table” in ■DEVICE BUS OPERATION defines the valid register command sequences. Note that the Erase Suspend (B0h) and Erase Resume (30h) commands are valid only while the Sector Erase operation is in progress. Also the Program Suspend (B0h) and Program Resume (30h) commands are valid only while the Program operation is in progress. Moreover both Read/Reset commands are functionally equivalent, resetting the device to the read mode. Please note that commands are always written at DQ0 to DQ7 and DQ8 to DQ15 bits are ignored. • Read/Reset Command In order to return from Autoselect mode or Exceeded Timing Limits (DQ5 = 1) to Read/Reset mode, the Read/ Reset operation is initiated by writing the Read/Reset command sequence into the command register. Microprocessor read cycles retrieve array data from the memory. The devices remain enabled for reads until the command register contents are altered. The devices will automatically power-up in the Read/Reset state. In this case, a command sequence is not required to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no spurious alteration of the memory content occurs during the power transition. Refer to the AC Read Characteristics and Waveforms for the specific timing parameters. • Autoselect Command Flash memories are intended for use in applications where the local CPU alters memory contents. As such, manufacture and device codes must be accessible while the devices reside in the target system. PROM programmers typically access the signature codes by raising A9 to a high voltage. However, multiplexing high voltage onto the address lines is not generally desired system design practice. The device contains an Autoselect command operation to supplement traditional PROM programming methodology. The operation is initiated by writing the Autoselect command sequence into the command register. The Autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle that contains the bank address (BA) and the Autoselect command. Then the manufacture and device codes can be read from the bank, and an actual data of memory cell can be read from the another bank. Following the command write, a read cycle from address (BA)00h retrieves the manufacture code of 04h. A read cycle from address (BA)01h for ×16((BA)02h for ×8) returns the device code (MBM29DL161TD = 36h and MBM29DL161BD = 39h for ×8 mode; MBM29DL161TD = 2236h and MBM29DL161BD = 2239h for ×16 mode), (MBM29DL162TD = 2Dh and MBM29DL162BD = 2Eh for ×8 mode; MBM29DL162TD = 222Dh and MBM29DL162BD = 222Eh for ×16 mode), (MBM29DL163TD = 28h and MBM29DL163BD = 2Bh for ×8 mode; MBM29DL163TD = 2228h and MBM29DL163BD = 222Bh for ×16 mode), (MBM29DL164TD = 33h and MBM29DL164BD = 35h for ×8 mode; MBM29DL164TD = 2233h and MBM29DL164BD = 2235h for ×16 mode). (See “MBM29DL161TD/BD, MBM29DL162TD/BD, MBM29DL163TD/BD and MBM29DL164TD/BD Sector Group Protection Verify Autoselect Codes Tables” and these “Extended Autoselect Code Tables” in ■DEVICE BUS OPERATION.) All manufacturer and device codes will exhibit odd parity with DQ7 defined as the parity bit. Sector state (protection or unprotection) will be informed by address (BA)02h for ×16 ((BA)04h for ×8). Scanning the sector group addresses (A19, A18, A17, A16, A15, A14, A13, and A12) while (A6, A1, A0) = (0, 1, 0) will produce a logical “1” at device output DQ0 for a protected sector group. The programming verification should be performed by verify sector group protection on the protected sector. (See “MBM29DL16XTD/BD User Bus Operations Tables (BYTE = VIH and BYTE = VIL)” in ■DEVICE BUS OPERATION.) The manufacture and device codes can be allowed reading from selected bank. To read the manufacture and device codes and sector group protection status from non-selected bank, it is necessary to write Read/Reset command sequence into the register and then Autoselect command should be written into the bank to be read. 30 MBM29DL16XTD/BD-70/90 If the software (program code) for Autoselect command is stored into the Flash memory, the device and manufacture codes should be read from the other bank where is not contain the software. To terminate the operation, it is necessary to write the Read/Reset command sequence into the register, and also to write the Autoselect command during the operation, execute it after writing Read/Reset command sequence. • Byte/Word Programming The devices are programmed on a byte-by-byte (or word-by-word) basis. Programming is a four bus cycle operation. There are two “unlock” write cycles. These are followed by the program set-up command and data write cycles. Addresses are latched on the falling edge of CE or WE, whichever happens later and the data is latched on the rising edge of CE or WE, whichever happens first. The rising edge of CE or WE (whichever happens first) begins programming. Upon executing the Embedded Program Algorithm command sequence, the system is not required to provide further controls or timings. The device will automatically provide adequate internally generated program pulses and verify the programmed cell margin. The system can determine the status of the program operation by using DQ7 (Data Polling), DQ6 (Toggle Bit), or RY/BY. The Data Polling and Toggle Bit must be performed at the memory location which is being programmed. The automatic programming operation is completed when the data on DQ7 is equivalent to data written to this bit at which time the devices return to the read mode and addresses are no longer latched. (See “Hardware Sequence Flags Table”.) Therefore, the devices require that a valid address to the devices be supplied by the system at this particular instance of time. Hence, Data Polling must be performed at the memory location which is being programmed. Any commands written to the chip during this period will be ignored. If hardware reset occurs during the programming operation, it is impossible to guarantee the data are being written. Programming is allowed in any sequence and across sector boundaries. Beware that a data “0” cannot be programmed back to a “1”. Attempting to do so may either hang up the device or result in an apparent success according to the data polling algorithm but a read from Read/Reset mode will show that the data is still “0”. Only erase operations can convert “0”s to “1”s. “(1) Embedded ProgramTM Algorithm” in ■FLOW CHART illustrates the Embedded ProgramTM Algorithm using typical command strings and bus operations. • Chip Erase Chip erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the “set-up” command. Two more “unlock” write cycles are then followed by the chip erase command. Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded Erase Algorithm command sequence the devices will automatically program and verify the entire memory for an all zero data pattern prior to electrical erase (Preprogram function). The system is not required to provide any controls or timings during these operations. The system can determine the status of the erase operation by using DQ7 (Data Polling), DQ6 (Toggle Bit), or RY/BY. The chip erase begins on the rising edge of the last CE or WE, whichever happens first in the command sequence and terminates when the data on DQ7 is “1” (See Write Operation Status section.) at which time the device returns to read the mode. Chip Erase Time; Sector Erase Time × All sectors + Chip Program Time (Preprogramming) “(2) Embedded EraseTM Algorithm” in ■FLOW CHART illustrates the Embedded EraseTM Algorithm using typical command strings and bus operations. 31 MBM29DL16XTD/BD-70/90 • Sector Erase Sector erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the “set-up” command. Two more “unlock” write cycles are then followed by the Sector Erase command. The sector address (any address location within the desired sector) is latched on the falling edge of CE or WE whichever happens later, while the command (Data = 30h) is latched on the rising edge of CE or WE which happens first. After time-out of “tTOW” from the rising edge of the last sector erase command, the sector erase operation will begin. Multiple sectors may be erased concurrently by writing the six bus cycle operations on “MBM29DL16XTD/BD Command Definitions Table” in ■DEVICE BUS OPERATION. This sequence is followed with writes of the Sector Erase command to addresses in other sectors desired to be concurrently erased. The time between writes must be less than “tTOW” otherwise that command will not be accepted and erasure will start. It is recommended that processor interrupts be disabled during this time to guarantee this condition. The interrupts can be re-enabled after the last Sector Erase command is written. A time-out of “tTOW” from the rising edge of last CE or WE whichever happens first will initiate the execution of the Sector Erase command(s). If another falling edge of CE or WE, whichever happens first occurs within the “tTOW” time-out window the timer is reset. (Monitor DQ3 to determine if the sector erase timer window is still open, see section DQ3, Sector Erase Timer.) Any command other than Sector Erase or Erase Suspend during this time-out period will reset the devices to the read mode, ignoring the previous command string. Resetting the devices once execution has begun will corrupt the data in the sector. In that case, restart the erase on those sectors and allow them to complete. (Refer to the Write Operation Status section for Sector Erase Timer operation.) Loading the sector erase buffer may be done in any sequence and with any number of sectors (0 to 38). Sector erase does not require the user to program the devices prior to erase. The devices automatically program all memory locations in the sector(s) to be erased prior to electrical erase (Preprogram function). When erasing a sector or sectors the remaining unselected sectors are not affected. The system is not required to provide any controls or timings during these operations. The system can determine the status of the erase operation by using DQ7 (Data Polling), DQ6 (Toggle Bit), or RY/BY. The sector erase begins after the “tTOW” time out from the rising edge of CE or WE whichever happens first for the last sector erase command pulse and terminates when the data on DQ7 is “1” (See Write Operation Status section.) at which time the devices return to the read mode. Data polling and Toggle Bit must be performed at an address within any of the sectors being erased. Multiple Sector Erase Time; [Sector Erase Time + Sector Program Time (Preprogramming)] × Number of Sector Erase In case of multiple sector erase across bank boundaries, a read from bank (read-while-erase) can not performe. “(2) Embedded EraseTM Algorithm” in ■FLOW CHART illustrates the Embedded EraseTM Algorithm using typical command strings and bus operations. • Erase Suspend/Resume The Erase Suspend command allows the user to interrupt a Sector Erase operation and then perform data reads from or programs to a sector not being erased. This command is applicable ONLY during the Sector Erase operation which includes the time-out period for sector erase. The Erase Suspend command will be ignored if written during the Chip Erase operation or Embedded Program Algorithm. Writting the Erase Suspend command (B0h) during the Sector Erase time-out results in immediate termination of the time-out period and suspension of the erase operation. Writing the Erase Resume command (30h) resumes the erase operation. The bank addresses of sector being erasing or suspending should be set when writting the Erase Suspend or Erase Resume command. When the Erase Suspend command is written during the Sector Erase operation, the device will take a maximum of “tSPD” to suspend the erase operation. When the devices have entered the erase-suspended mode, the RY/BY output pin will be at Hi-Z and the DQ7 bit will be at logic “1”, and DQ6 will stop toggling. The user must use the address of the erasing sector for reading DQ6 and DQ7 to determine if the erase operation has been suspended. Further writes of the Erase Suspend command are ignored. 32 MBM29DL16XTD/BD-70/90 When the erase operation has been suspended, the devices default to the erase-suspend-read mode. Reading data in this mode is the same as reading from the standard read mode except that the data must be read from sectors that have not been erase-suspended. Successively reading from the erase-suspended sector while the device is in the erase-suspend-read mode will cause DQ2 to toggle. (See the section on DQ2.) After entering the erase-suspend-read mode, the user can program the device by writing the appropriate command sequence for Program. This program mode is known as the erase-suspend-program mode. Again, programming in this mode is the same as programming in the regular Program mode except that the data must be programmed to sectors that are not erase-suspended. Successively reading from the erase-suspended sector while the devices are in the erase-suspend-program mode will cause DQ2 to toggle. The end of the erasesuspended Program operation is detected by the RY/BY output pin, Data polling of DQ7 or by the Toggle Bit I (DQ6) which is the same as the regular Program operation. Note that DQ7 must be read from the Program address while DQ6 can be read from any address within bank being erase-suspended. To resume the operation of Sector Erase, the Resume command (30h) should be written to the bank being erase suspended. Any further writes of the Resume command at this point will be ignored. Another Erase Suspend command can be written after the chip has resumed erasing. • Extended Command (1) Fast Mode MBM29DL16XTD/BD has Fast Mode function. This mode dispenses with the initial two unclock cycles required in the standard program command sequence by writing Fast Mode command into the command register. In this mode, the required bus cycle for programming is two cycles instead of four bus cycles in standard program command. (Do not write erase command in this mode.) The read operation is also executed after exiting this mode. To exit this mode, it is necessary to write Fast Mode Reset command into the command register. The first cycle must contain the bank address. (Refer to “(8) Embedded ProgramTM Algorithm for Fast Mode” in ■FLOW CHART.) The VCC active current is required even CE = VIH during Fast Mode. (2) Fast Programming During Fast Mode, the programming can be executed with two bus cycles operation. The Embedded Program Algorithm is executed by writing program set-up command (A0h) and data write cycles (PA/PD). (Refer to “(8) Embedded ProgramTM Algorithm for Fast Mode” in ■FLOW CHART.) (3) Extended Sector Group Protection In addition to normal sector group protection, the MBM29DL16XTD/BD has Extended Sector Group Protection as extended function. This function enable to protect sector group by forcing VID on RESET pin and write a command sequence. Unlike conventional procedure, it is not necessary to force VID and control timing for control pins. The extended sector group protection requires VID on RESET pin only. With this condition, the operation is initiated by writing the set-up command (60h) into the command register. Then, the sector group addresses pins (A19, A18, A17, A16, A15, A14, A13 and A12) and (A6, A1, A0) = (0, 1, 0) should be set to the sector group to be protected (recommend to set VIL for the other addresses pins), and write extended sector group protection command (60h). A sector group is typically protected in 250 µs. To verify programming of the protection circuitry, the sector group addresses pins (A19, A18, A17, A16, A15, A14, A13 and A12) and (A6, A1, A0) = (0, 1, 0) should be set and write a command (40h). Following the command write, a logical “1” at device output DQ0 will produce for protected sector in the read operation. If the output data is logical “0”, please repeat to write extended sector group protection command (60h) again. To terminate the operation, it is necessary to set RESET pin to VIH. (Refer to “(17) Extended Sector Group Protection Timing Diagram” in ■TIMING DIAGRAM and “(7) Extended Sector Group Protection Algorithm” in ■FLOW CHART.) (4) CFI (Common Flash Memory Interface) The CFI (Common Flash Memory Interface) specification outlines device and host system software interrogation handshake which allows specific vendor-specified software algorithms to be used for entire families of devices. This allows device-independent, JEDEC ID-independent, and forward-and backwardcompatible software support for the specified flash device families. Refer to CFI specification in detail. The operation is initiated by writing the query command (98h) into the command register. The bank address should be set when writing this command. Then the device information can be read from the bank, and an 33 MBM29DL16XTD/BD-70/90 actual data of memory cell be read from the another bank. Following the command write, a read cycle from specific address retrives device information. Please note that output data of upper byte (DQ8 to DQ15) is “0” in word mode (16 bit) read. Refer to the CFI code table. To terminate operation, it is necessary to write the read/reset command sequence into the register. (See “Common Flash Memory Interface Code Table” in ■FLEXIBLE SECTOR-ERASE ARCHITECTURE.) • HiddenROM Region The HiddenROM feature provides a Flash memory region that the system may access through a new command sequence. This is primarily intended for customers who wish to use an Electronic Serial Number (ESN) in the device with the ESN protected against modification. Once the HiddenROM region is protected, any further modification of that region is impossible. This ensures the security of the ESN once the product is shipped to the field. The HiddenROM region is 64K bytes in length and is stored at the same address of the 8KB ×8 sectors. The MBM29DL16XTD occupies the address of the byte mode 1F0000h to 1FFFFFh (word mode 0F8000h to 0FFFFFh) and the MBM29DL16XBD type occupies the address of the byte mode 000000h to 00FFFFh (word mode 000000h to 007FFFh). After the system has written the Enter HiddenROM command sequence, the system may read the HiddenROM region by using the addresses normally occupied by the boot sectors. That is, the device sends all commands that would normally be sent to the boot sectors to the HiddenROM region. This mode of operation continues until the system issues the Exit HiddenROM command sequence, or until power is removed from the device. On power-up, or following a hardware reset, the device reverts to sending commands to the boot sectors. • HiddenROM Entry Command MBM29DL16XTD/BD has a HiddenROM area with One Time Protect function. This area is to enter the security code and to unable the change of the code once set. Program/erase is possible in this area until it is protected. However, once it is protected, it is impossible to unprotect, so please use this with caution. HiddenROM area is 64K Byte and in the same address area of 8KB sector. The address of top boot is 1F0000h to 1FFFFFh at byte mode (0F8000h to 0FFFFFh at word mode) and the bottom boot is 000000h to 00FFFFh at byte mode (000000h to 007FFFh at word mode). These areas are normally the boot block area (8KB ×8 sector). Therefore, write the HiddenROM entry command sequence to enter the HiddenROM area. It is called as HiddenROM mode when the HiddenROM area appears. Sector other than the boot block area could be read during HiddenROM mode. Read/program/earse of the HiddenROM area is possible during HiddenROM mode. Write the HiddenROM reset command sequence to exit the HiddenROM mode. The bank address of the HiddenROM should be set on the third cycle of this reset command sequence. In case of MBM29DL161TD/BD, whose Bank 1 size is 0.5 Mbit, the simultaneous operation cannot execute multi-function mode between the HiddenROM area and Bank 2 Region. • HiddenROM Program Command To program the data to the HiddenROM area, write the HiddenROM program command sequence during HiddenROM mode. This command is same as the program command in the past except to write the command during HiddenROM mode. Therefore the detection of completion method is the same as in the past, using the DQ7 data poling, DQ6 toggle bit and RY/BY pin. Need to pay attention to the address to be programmed. If the address other than the HiddenROM area is selected to program, the data of the address will be changed. • HiddenROM Erase Command To erase the HiddenROM area, write the HiddenROM erase command sequence during HiddenROM mode. This command is same as the sector erase command in the past except to write the command during HiddenROM mode. Therefore the detection of completion method is the same as in the past, using the DQ7 data poling, DQ6 toggle bit and RY/BY pin. Need to pay attention to the sector address to be erased. If the sector address other than the HiddenROM area is selected, the data of the sector will be changed. 34 MBM29DL16XTD/BD-70/90 • HiddenROM Protect Command There are two methods to protect the HiddenROM area. One is to write the sector group protect setup command(60h), set the sector address in the HiddenROM area and (A6, A1, A0) = (0,1,0), and write the sector group protect command(60h) during the HiddenROM mode. The same command sequence could be used because except that it is in the HiddenROM mode and that it does not apply high voltage to RESET pin, it is the same as the extension sector group protect in the past. Please refer to “Function Explanation Extended Command (3) Extended Sector Group Protection” for details of extention sector group protect setting. The other is to apply high voltage (VID) to A9 and OE, set the sector address in the HiddenROM area and (A6, A1, A0) = (0,1,0), and apply the write pulse during the HiddenROM mode. To verify the protect circuit, apply high voltage (VID) to A9, specify (A6, A1, A0) = (0,1,0) and the sector address in the HiddenROM area, and read. When “1” appears to DQ0, the protect setting is completed. “0” will appear to DQ0 if it is not protected. Please apply write pulse agian. The same command sequence could be used for the above method because other than the HiddenROM mode, it is the same as the sector group protect in the past. Please refer to “Function Explanation Sector Group Protection” for details of sector group protect setting Other sector group will be effected if the address other than the HiddenROM area is selected for the sector group address, so please be carefull. Once it is protected, protection can not be cancelled, so please pay closest attention. • Write Operation Status Detailed in “Hardware Sequence Flags Table” are all the status flags that can determine the status of the bank for the current mode operation. The read operation from the bank where is not operate Embedded Algorithm returns a data of memory cell. These bits offer a method for determining whether a Embedded Algorithm is completed properly. The information on DQ2 is address sensitive. This means that if an address from an erasing sector is consectively read, then the DQ2 bit will toggle. However, DQ2 will not toggle if an address from a nonerasing sector is consectively read. This allows the user to determine which sectors are erasing and which are not. The status flag is not output from bank (non-busy bank) not executing Embedded Algorithm. For example, there is bank (busy bank) which is now executing Embedded Algorithm. When the read sequence is [1] <busy bank>, [2] <non-busy bank>, [3] <busy bank>, the DQ6 is toggling in the case of [1] and [3]. In case of [2], the data of memory cell is outputted. In the erase-suspend read mode with the same read sequence, DQ6 will not be toggled in the [1] and [3]. In the erase suspend read mode, DQ2 is toggled in the [1] and [3]. In case of [2], the data of memory cell is outputted. 35 MBM29DL16XTD/BD-70/90 Hardware Sequence Flags Table DQ7 DQ6 DQ5 DQ3 DQ2 DQ7 Toggle 0 0 1 0 Toggle 0 1 Toggle*1 1 1 0 0 Toggle Data Data Data Data Data DQ7 Toggle 0 0 1*2 Data Data Data Data Data Data Data Data Data Data Embedded Program Algorithm DQ7 Toggle 1 0 1 Embedded Erase Algorithm Exceeded Time Limits Erase Erase Suspend Program Suspended (Non-Erase Suspended Sector) Mode 0 Toggle 1 1 N/A DQ7 Toggle 1 0 N/A Status Embedded Program Algorithm Embedded Erase Algorithm Erase Suspend Read (Erase Suspended Sector) Erase Erase Suspend Read Suspended (Non-Erase Suspended Sector) In Progress Mode Erase Suspend Program (Non-Erase Suspended Sector) Program Suspend Read Program (Program Suspended Sector) Suspended Program Suspend Read Mode (Non-Program Suspended Sector) *1 : Successive reads from the erasing or erase-suspend sector cause DQ2 to toggle. *2 : Reading from non-erase suspend sector address will indicate logic “1” at the DQ2 bit. • DQ7 Data Polling The MBM29DL16XTD/BD devices feature Data Polling as a method to indicate to the host that the Embedded Algorithms are in progress or completed. During the Embedded Program Algorithm an attempt to read the devices will produce the complement of the data last written to DQ7. Upon completion of the Embedded Program Algorithm, an attempt to read the device will produce the true data last written to DQ7. During the Embedded Erase Algorithm, an attempt to read the device will produce a “0” at the DQ7 output. Upon completion of the Embedded Erase Algorithm an attempt to read the device will produce a “1” at the DQ7 output. The flowchart for Data Polling (DQ7) is shown in “(3) Data Polling Algorithm” (in ■FLOW CHART). For programming, the Data Polling is valid after the rising edge of fourth write pulse in the four write pulse sequence. For chip erase and sector erase, the Data Polling is valid after the rising edge of the sixth write pulse in the six write pulse sequence. Data Polling must be performed at sector address within any of the sectors being erased and not a protected sector. Otherwise, the status may not be valid. If a program address falls within a protected sector, Data Polling on DQ7 is active for approximately 1 µs, then that bank returns to the read mode. After an erase command sequence is written, if all sectors selected for erasing are protected, Data Polling on DQ7 is active for approximately 400 µs, then the bank returns to read mode. Once the Embedded Algorithm operation is close to being completed, the MBM29DL16XTD/BD data pins (DQ7) may change asynchronously while the output enable (OE) is asserted low. This means that the devices are driving status information on DQ7 at one instant of time and then that byte’s valid data at the next instant of time. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device has completed the Embedded Algorithm operation and DQ7 has a valid data, the data outputs on DQ0 to DQ6 may be still invalid. The valid data on DQ0 to DQ7 will be read on the successive read attempts. 36 MBM29DL16XTD/BD-70/90 The Data Polling feature is only active during the Embedded Programming Algorithm, Embedded Erase Algorithm or sector erase time-out. (See “Hardware Sequence Flags Table”.) See “(6) AC Waveforms for Data Polling during Embedded Algorithm Operations” in ■TIMING DIAGRAM for the Data Polling timing specifications and diagrams. • DQ6 Toggle Bit I The MBM29DL16XTD/BD also feature the “Toggle Bit I” as a method to indicate to the host system that the Embedded Algorithms are in progress or completed. During an Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data from the devices will result in DQ6 toggling between one and zero. Once the Embedded Program or Erase Algorithm cycle is completed, DQ6 will stop toggling and valid data will be read on the next successive attempts. During programming, the Toggle Bit I is valid after the rising edge of the fourth write pulse in the four write pulse sequence. For chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth write pulse in the six write pulse sequence. The Toggle Bit I is active during the sector time out. In programming, if the sector being written to is protected, the toggle bit will toggle for about 1 µs and then stop toggling without the data having changed. In erase, the devices will erase all the selected sectors except for the ones that are protected. If all selected sectors are protected, the chip will toggle the toggle bit for about 400 µs and then drop back into read mode, having changed none of the data. Either CE or OE toggling will cause the DQ6 to toggle. In addition, an Erase Suspend/Resume command will cause the DQ6 to toggle. The system can use DQ6 to determine whether a sector is actively erasing or is erase-suspended. When a bank is actively erasing (that is, the Embedded Erase Algorithm is in progress), DQ6 toggles. When a bank enters the Erase Suspend mode, DQ6 stops toggling. Successive read cycles during the erase-suspend-program cause DQ6 to toggle. To operate toggle bit function properly, CE or OE must be high when bank address is changed. See “(7) AC Waveforms for Toggle Bit I during Embedded Algorithm Operations” in ■TIMING DIAGRAM for the Toggle Bit I timing specifications and diagrams. • DQ5 Exceeded Timing Limits DQ5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under these conditions DQ5 will produce a “1”. This is a failure condition which indicates that the program or erase cycle was not successfully completed. Data Polling is the only operating function of the devices under this condition. The CE circuit will partially power down the device under these conditions (to approximately 2 mA). The OE and WE pins will control the output disable functions as described in “MBM29DL16XTD/BD User Bus Operations Tables (BYTE = VIH and BYTE = VIL)” (in ■DEVICE BUS OPERATION). The DQ5 failure condition may also appear if a user tries to program a non blank location without erasing. In this case the devices lock out and never complete the Embedded Algorithm operation. Hence, the system never reads a valid data on DQ7 bit and DQ6 never stops toggling. Once the devices have exceeded timing limits, the DQ5 bit will indicate a “1.” Please note that this is not a device failure condition since the devices were incorrectly used. If this occurs, reset the device with command sequence. 37 MBM29DL16XTD/BD-70/90 • DQ3 Sector Erase Timer After the completion of the initial sector erase command sequence the sector erase time-out will begin. DQ3 will remain low until the time-out is complete. Data Polling and Toggle Bit are valid after the initial sector erase command sequence. If Data Polling or the Toggle Bit I indicates the device has been written with a valid erase command, DQ3 may be used to determine if the sector erase timer window is still open. If DQ3 is high (“1”) the internally controlled erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase operation is completed as indicated by Data Polling or Toggle Bit I. If DQ3 is low (“0”), the device will accept additional sector erase commands. To insure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent Sector Erase command. If DQ3 were high on the second status check, the command may not have been accepted. See “Hardware Sequence Flags Table”. • DQ2 Toggle Bit II This toggle bit II, along with DQ6, can be used to determine whether the devices are in the Embedded Erase Algorithm or in Erase Suspend. Successive reads from the erasing sector will cause DQ2 to toggle during the Embedded Erase Algorithm. If the devices are in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause DQ2 to toggle. When the devices are in the erase-suspended-program mode, successive reads from the byte address of the non-erase suspended sector will indicate a logic “1” at the DQ2 bit. DQ6 is different from DQ2 in that DQ6 toggles only when the standard program or Erase, or Erase Suspend Program operation is in progress. The behavior of these two status bits, along with that of DQ7, is summarized as follows: For example, DQ2 and DQ6 can be used together to determine if the erase-suspend-read mode is in progress. (DQ2 toggles while DQ6 does not.) See also “Toggle Bit Status Table” and “(9) DQ2 vs. DQ6” in ■TIMING DIAGRAM. Furthermore, DQ2 can also be used to determine which sector is being erased. When the device is in the erase mode, DQ2 toggles if this bit is read from an erasing sector. To operate toggle bit function properly, CE or OE must be high when bank address is changed. • Reading Toggle Bits DQ6/DQ2 Whenever the system initially begins reading toggle bit status, it must read DQ7 to DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically a system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7 to DQ0 on the following read cycle. However, if, after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5) . If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system 38 MBM29DL16XTD/BD-70/90 tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation. (Refer to “(4) Toggle Bit Algorithm” in “■ FLOW CHART”.) Toggle Bit Status Table Mode Program DQ7 DQ6 DQ2 DQ7 Toggle 1 Erase 0 Toggle Toggle*1 Erase-Suspend Read (Erase-Suspended Sector) 1 1 Toggle DQ7 Toggle 1*2 Erase-Suspend Program *1 : Successive reads from the erasing or erase-suspend sector will cause DQ2 to toggle. *2 : Reading from the non-erase suspend sector address will indicate logic “1” at the DQ2 bit. • RY/BY Ready/Busy The MBM29DL16XTD/BD provide a RY/BY open-drain output pin as a way to indicate to the host system that the Embedded Algorithms are either in progress or has been completed. If the output is low, the devices are busy with either a program or erase operation. If the output is high, the devices are ready to accept any read/ write or erase operation. When the RY/BY pin is low, the devices will not accept any additional program or erase commands. If the MBM29DL16XTD/BD are placed in an Erase Suspend mode, the RY/BY output will be high. During programming, the RY/BY pin is driven low after the rising edge of the fourth write pulse. During an erase operation, the RY/BY pin is driven low after the rising edge of the sixth write pulse. The RY/BY pin will indicate a busy condition during the RESET pulse. Refer to “(10) RY/BY Timing Diagram during Program/Erase Operations” and “(11) RESET, RY/BY Timing Diagram” in ■TIMING DIAGRAM for a detailed timing diagram. The RY/BY pin is pulled high in standby mode. Since this is an open-drain output, the pull-up resistor needs to be connected to VCC; multiples of devices may be connected to the host system via more than one RY/BY pin in parallel. • Byte/Word Configuration The BYTE pin selects the byte (8-bit) mode or word (16-bit) mode for the MBM29DL16XTD/BD devices. When this pin is driven high, the devices operate in the word (16-bit) mode. The data is read and programmed at DQ0 to DQ15. When this pin is driven low, the devices operate in byte (8-bit) mode. Under this mode, the DQ15/A-1 pin becomes the lowest address bit and DQ8 to DQ14 bits are tri-stated. However, the command bus cycle is always an 8-bit operation and hence commands are written at DQ0 to DQ7 and the DQ8 to DQ15 bits are ignored. Refer to “(12) Timing Diagram for Word Mode Configuration” and “(13) Timing Diagram for Byte Mode Configuration” and “(14) BYTE Timing Diagram for Write Operations” in ■TIMING DIAGRAM for the timing diagram. • Data Protection The MBM29DL16XTD/BD are designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transitions. During power up the devices automatically reset the internal state machine in the Read mode. Also, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific multi-bus cycle command sequences. The devices also incorporate several features to prevent inadvertent write cycles resulting form VCC power-up and power-down transitions or system noise. 39 MBM29DL16XTD/BD-70/90 • Low VCC Write Inhibit To avoid initiation of a write cycle during VCC power-up and power-down, a write cycle is locked out for VCC less than VLKO. If VCC < VLKO, the command register is disabled and all internal program/erase circuits are disabled. Under this condition the device will reset to the read mode. Subsequent writes will be ignored until the VCC level is greater than VLKO. It is the users responsibility to ensure that the control pins are logically correct to prevent unintentional writes when VCC is above VLKO. If Embedded Erase Algorithm is interrupted, there is possibility that the erasing sector(s) cannot be used. • Write Pulse “Glitch” Protection Noise pulses of less than 3 ns (typical) on OE, CE, or WE will not initiate a write cycle. • Logical Inhibit Writing is inhibited by holding any one of OE = VIL, CE = VIH, or WE = VIH. To initiate a write cycle CE and WE must be a logical zero while OE is a logical one. • Power-Up Write Inhibit Power-up of the devices with WE = CE = VIL and OE = VIH will not accept commands on the rising edge of WE. The internal state machine is automatically reset to the read mode on power-up. • Sector Group Protection Device user is able to protect each sector group individually to store and protect data. Protection circuit voids both program and erase commands that are addressed to protected sectors. Any commands to program or erase addressed to protected sector are ignored (see “■ FUNCTIONAL DESCRIPTION Sector Group Protection”) 40 MBM29DL16XTD/BD-70/90 ■ ABSOLUTE MAXIMUM RATINGS (See WARNING) Parameter Symbol Rating Unit Min Max Tstg –55 +125 °C TA –40 +85 °C VIN, VOUT –0.5 VCC+0.5 V Power Supply Voltage*1 VCC –0.5 +4.0 V A9, OE, and RESET*1,*3 VIN –0.5 +13.0 V VACC –0.5 +10.5 V Storage Temperature Ambient Temperature with Power Applied Voltage with respect to Ground All pins except A9, OE, RESET *1,*2 1, 4 WP/ACC* * *1 : Voltage is defined on the basis of VSS = GND = 0 V. *2 : Minimum DC voltage on input or I/O pins is − 0.5 V. During voltage transitions, input or I/O pins may undershoot VSS to − 2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCC + 0.5 V. During voltage transitions, input or I/O pins may overshoot to VCC + 2.0 V for periods of up to 20 ns. *3 : Minimum DC input voltage on A9, OE and RESET pins is − 0.5 V. During voltage transitions, A9, OE and RESET pins may undershoot VSS to − 2.0 V for periods of up to 20 ns. Voltage difference between input and supply voltage (VIN − VCC) does not exceed + 9.0 V. Maximum DC input voltage on A9, OE and RESET pins is + 13.0 V which may overshoot to + 14.0 V for periods of up to 20 ns. *4 : Minimum DC input voltage on WP/ACC pin is − 0.5 V. During voltage transitions, WP/ACC pin may undershoot VSS to − 2.0 V for periods of up to 20 ns. Maximum DC input voltage on WP/ACC pin is + 10.5 V which may overshoot to + 12.0 V for periods of up to 20 ns when VCC is applied. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. ■ RECOMMENDED OPERATING CONDITIONS Parameter Symbol Ambient Temperature TA Power Supply Voltage* VCC Conditions Value Unit Min Max MBM29DL16XTD/BD-70 –20 +70 °C MBM29DL16XTD/BD-90 –40 +85 °C MBM29DL16XTD/BD-70 +3.0 +3.6 V MBM29DL16XTD/BD-90 +2.7 +3.6 V * : Voltage is defined on the basis of VSS = GND = 0 V. Note: Operating ranges define those limits between which the functionality of the devices are guaranteed. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 41 MBM29DL16XTD/BD-70/90 ■ MAXIMUM OVERSHOOT/MAXIMUM UNDERSOOT +0.6 V 20 ns 20 ns –0.5 V –2.0 V 20 ns Figure 1 Maximum Undershoot Waveform 20 ns V CC +2.0 V V CC +0.5 V +2.0 V 20 ns 20 ns Figure 2 Maximum Overshoot Waveform 1 20 ns +14.0 V +13.0 V V CC +0.5 V 20 ns 20 ns Note: This waveform is applied for A9, OE, and RESET. Figure 3 Maximum Overshoot Waveform 2 42 MBM29DL16XTD/BD-70/90 ■ DC CHARACTERISTICS Parameter Symbol Value Conditions Min Typ Max Unit Input Leakage Current ILI VIN = VSS to VCC, VCC = VCC Max –1.0 — +1.0 µA Output Leakage Current ILO VOUT = VSS to VCC, VCC = VCC Max –1.0 — +1.0 µA A9, OE, RESET Inputs Leakage Current ILIT VCC = VCC Max, A9, OE, RESET = 12.5 V — — 35 µA WP/ACC Accelerated Program Current ILIA VCC = VCC Max, WP/ACC = VACC Max — — 20 mA — — — — CE = VIL, OE = VIH, f = 5 MHz VCC Active Current*1 ICC1 CE = VIL, OE = VIH, f = 1 MHz Byte Word Byte Word 13 15 7 7 mA mA VCC Active Current*2 ICC2 CE = VIL, OE = VIH — — 35 mA VCC Current (Standby) ICC3 VCC = VCC Max, CE = VCC ± 0.3 V, RESET = VCC ± 0.3 V, WP/ACC = VCC ± 0.3 V — 1 5 µA VCC Current (Standby, Reset) ICC4 VCC = VCC Max, RESET = VSS ± 0.3 V — 1 5 µA VCC Current (Automatic Sleep Mode)*5 ICC5 VCC = VCC Max, CE = VSS ± 0.3 V, RESET = VCC ± 0.3 V, VIN = VCC ± 0.3 V or VSS ± 0.3 V — 1 5 µA VCC Active Current*6 (Read-While-Program) ICC6 CE = VIL, OE = VIH Byte — — 48 Word — — 50 VCC Active Current*6 (Read-While-Erase) ICC7 CE = VIL, OE = VIH Byte — — 48 Word — — 50 VCC Active Current (Erase-Suspend-Program) ICC8 CE = VIL, OE = VIH — — 35 mA Input Low Voltage VIL — –0.5 — +0.6 V Input High Voltage VIH — 2.0 — VCC+0.3 V Voltage for WP/ACC Sector Group Protection/Unprotection and Program Acceleration*4 VACC — 8.5 9.0 9.5 V Voltage for Autoselect and Sector Group Protection (A9, OE, RESET) *3,*4 VID — 11.5 12 12.5 V Output Low Voltage VOL IOL = 4.0 mA, VCC = VCC Min — — 0.45 V VOH1 IOH = –2.0 mA, VCC = VCC Min 2.4 — — V VOH2 IOH = –100 µA VCC–0.4 — — V 2.3 2.4 2.5 V Output High Voltage Low VCC Lock-Out Voltage VLKO — mA mA *1 : The ICC current listed includes both the DC operating current and the frequency dependent component. *2 : ICC active while Embedded Algorithm (program or erase) is in progress. *3 : This timing is only for Sector Group Protection operation and Autoselect mode. *4 : Applicable for only VCC. *5 : Automatic sleep mode enables the low power mode when address remain stable for 150 ns. *6 : Embedded Algorithm (program or erase) is in progress. (@5 MHz) 43 MBM29DL16XTD/BD-70/90 ■ AC CHARACTERISTICS • Read Only Operations Characteristics Symbol Parameter Value (Note) Test Setup JEDEC Standard 70 90 Min Max Min Max 70 90 ns Read Cycle Time tAVAV tRC Address to Output Delay tAVQV tACC CE = VIL OE = VIL 70 90 ns Chip Enable to Output Delay tELQV tCE OE = VIL 70 90 ns Output Enable to Output Delay tGLQV tOE — 30 35 ns Chip Enable to Output High-Z tEHQZ tDF — 25 30 ns Output Enable to Output High-Z tGHQZ tDF — 25 30 ns Output Hold Time From Addresses, CE or OE, Whichever Occurs First tAXQX tOH — 0 0 ns RESET Pin Low to Read Mode — tREADY — 20 20 µs CE to BYTE Switching Low or High — tELFL tELFH — 5 5 ns — Note: Test Conditions: Output Load: 1 TTL gate and 30 pF (MBM29DL16XTD/BD-70) 1 TTL gate and 100 pF (MBM29DL16XTD/BD-90) Input rise and fall times: 5 ns Input pulse levels: 0.0 V or 3.0 V Timing measurement reference level Input: 1.5 V Output:1.5 V 3.3 V IN3064 or Equivalent 2.7 kΩ Device Under Test 6.2 kΩ CL Diodes = IN3064 or Equivalent Notes : CL = 30 pF including jig capacitance (MBM29DL16XTD/BD-70) CL = 100 pF including jig capacitance (MBM29DL16XTD/BD-90) Figure 4 Test Conditions 44 Unit MBM29DL16XTD/BD-70/90 • Write/Erase/Program Operations Symbol Parameter 70 JEDEC Standard Min 90 Typ Max Min Typ Max Unit Write Cycle Time tAVAV tWC 70 90 ns Address Setup Time tAVWL tAS 0 0 ns — tASO 12 15 ns tWLAX tAH 45 45 ns — tAHT 0 0 ns Data Setup Time tDVWH tDS 30 35 ns Data Hold Time tWHDX tDH 0 0 ns — tOEH 0 0 ns 10 10 ns CE High During Toggle Bit Polling — tCEPH 20 20 ns OE High During Toggle Bit Polling — tOEPH 20 20 ns Read Recover Time Before Write tGHWL tGHWL 0 0 ns Read Recover Time Before Write tGHEL tGHEL 0 0 ns CE Setup Time tELWL tCS 0 0 ns WE Setup Time tWLEL tWS 0 0 ns CE Hold Time tWHEH tCH 0 0 ns WE Hold Time tEHWH tWH 0 0 ns Write Pulse Width tWLWH tWP 35 35 ns CE Pulse Width tELEH tCP 35 35 ns Write Pulse Width High tWHWL tWPH 25 30 ns CE Pulse Width High tEHEL tCPH 25 30 ns tWHWH1 tWHWH1 8 8 µs 16 16 µs tWHWH2 tWHWH2 1 1 s VCC Setup Time — tVCS 50 50 µs Rise Time to VID*2 — tVIDR 500 500 ns — tVACCR 500 500 ns — tVLHT 4 4 µs — tWPP 100 100 µs OE Setup Time to WE Active*2 — tOESP 4 4 µs 2 CE Setup Time to WE Active* — tCSP 4 4 µs Recover Time From RY/BY — tRB 0 0 ns RESET Pulse Width — tRP 500 500 Address Setup Time to OE Low During Toggle Bit Polling Address Hold Time Address Hold Time from CE or OE High During Toggle Bit Polling Output Enable Hold Time Programming Operation Read Toggle and Data Polling Byte Word Sector Erase Operation*1 Rise Time to VACC*3 Voltage Transition Time* 2 Write Pulse Width*2 ns (Continued) 45 MBM29DL16XTD/BD-70/90 (Continued) Parameter Symbol JEDEC Standard Min 90 Typ Max Min Typ Max Unit RESET High Level Period before Read — tRH 200 200 ns BYTE Switching Low to Output High-Z — tFLQZ 25 30 ns BYTE Switching High to Output Active — tFHQV 70 90 ns Program/Erase Valid to RY/BY Delay — tBUSY 90 90 ns Delay Time from Embedded Output Enable — tEOE 70 90 ns Erase Time-out Time — tTOW 50 50 µs Erase Suspend Transition Time — tSPD 20 20 µs *1 : This does not include preprogramming time. *2 : This timing is for Sector Group Protection operation. *3 : This timing is limited for Accelerated Program Operation only. 46 70 MBM29DL16XTD/BD-70/90 ■ ERASE AND PROGRAMMING PERFORMANCE Limits Parameter Unit Min Typ Max Sector Erase Time — 1 10 s Word Programming Time — 16 360 µs Byte Programming Time — 8 300 µs Chip Programming Time — — 50 s 100,000 — — cycle Program/Erase Cycle Comments Excludes programming time prior to erasure Excludes system-level overhead Excludes system-level overhead — ■ PIN CAPACITANCE Parameter Symbol Test Setup Typ Max Unit 6 7.5 pF 8.5 12 pF Input Capacitance CIN VIN = 0 Output Capacitance COUT VOUT = 0 Control Pin Capacitance CIN2 VIN = 0 8 10 pF WP/ACC Pin Capacitance CIN3 VIN = 0 17 18 pF Notes : • Test conditions TA = + 25 °C, f = 1.0 MHz • DQ15/A−1 pin capacitance is stipulated by output capacitance. 47 MBM29DL16XTD/BD-70/90 ■ TIMING DIAGRAM • Key to Switching Waveforms WAVEFORM INPUTS OUTPUTS Must Be Steady Will Be Steady May Change from H to L Will Be Changing from H to L May Change from L to H Will Be Changing from L to H “H” or “L” Any Change Permitted Changing State Unknown Does Not Apply Center Line is HighImpedance “Off” State (1) AC Waveforms for Read Operations tRC Address Address Stable tACC CE tOE tDF OE tOEH WE tCE Outputs 48 High-Z tOH Output Valid High-Z MBM29DL16XTD/BD-70/90 (2) AC Waveforms for Hardware Reset/Read Operations tRC Address Address Stable tACC CE tRH tRP tRH tCE RESET tOH Outputs High-Z Output Valid 49 MBM29DL16XTD/BD-70/90 (3) AC Waveforms for Alternate WE Controlled Program Operations Data Polling 3rd Bus Cycle Address 555h tWC PA tAS PA tRC tAH CE tCH tCS tCE OE tGHWL tWP tWPH tOE tWHWH1 WE tDF tOH tDS tDH Data Notes: • • • • • • 50 A0h PD DQ7 DOUT DOUT PA is address of the memory location to be programmed. PD is data to be programmed at byte address. DQ7 is the output of the complement of the data written to the device. DOUT is the output of the data written to the device. Figure indicates last two bus cycles out of four bus cycle sequence. These waveforms are for the ×16 mode. (The addresses differ from ×8 mode.) MBM29DL16XTD/BD-70/90 (4) AC Waveforms for Alternate CE Controlled Program Operations 3rd Bus Cycle Address Data Polling PA 555h tWC tAS PA tAH WE tWS tWH OE tGHEL tCP tCPH tWHWH1 CE tDS tDH Data Notes: • • • • • • A0h PD DQ7 DOUT PA is address of the memory location to be programmed. PD is data to be programmed at byte address. DQ7 is the output of the complement of the data written to the device. DOUT is the output of the data written to the device. Figure indicates last two bus cycles out of four bus cycle sequence. These waveforms are for the ×16 mode. (The addresses differ from ×8 mode.) 51 MBM29DL16XTD/BD-70/90 (5) AC Waveforms for Chip/Sector Erase Operations Address 2AAh 555h tWC tAS 555h 555h 2AAh SA* tAH CE tCS tCH OE tGHWL tWP tWPH WE tDS AAh Data 10h for Chip Erase tDH 55h 80h AAh 55h 10h/ 30h tVCS VCC *: SA is the sector address for Sector Erase. Addresses = 555h (Word) for Chip Erase. Note: These waveforms are for the ×16 mode. The addresses differ from ×8 mode. 52 MBM29DL16XTD/BD-70/90 (6) AC Waveforms for Data Polling during Embedded Algorithm Operations CE tCH tOE tDF OE tOEH WE tCE * DQ7 Data DQ7 = Valid Data DQ7 High-Z tWHWH1 or 2 DQ6 to DQ0 Data DQ0 to DQ6 = Output Flag tBUSY DQ0 to DQ6 Valid Data High-Z tEOE RY/BY * : DQ7 = Valid Data (The device has completed the Embedded operation). 53 MBM29DL16XTD/BD-70/90 (7) AC Waveforms for Toggle Bit I during Embedded Algorithm Operations Address tAHT tASO tAHT tAS CE tCEPH WE tOEPH tOEH tOEH OE tDH DQ 6/DQ2 tOE Toggle Data Data tCE Toggle Data Toggle Data * Stop Toggling tBUSY RY/BY * : DQ6 stops toggling (The device has completed the Embedded operation). 54 Output Valid MBM29DL16XTD/BD-70/90 (8) Bank-to-bank Read/Write Timing Diagram Address Read Command Read Command Read Read tRC tWC tRC tWC tRC tRC BA2 (PA) BA1 BA2 (PA) BA2 (555h) BA1 tAS BA1 tACC tAH tAS tAHT tCE CE tOE tCEPH OE tGHWL tDF tOEH tWP WE tDS Valid Output DQ tDH Valid Intput (A0h) tDF Valid Output Valid Intput (PD) Valid Output Status Note: This is example of Read for Bank 1 and Embedded Algorithm (program) for Bank 2. BA1: Address corresponding to Bank 1. BA2: Address corresponding to Bank 2. (9) DQ2 vs. DQ6 Enter Embedded Erasing WE Erase Suspend Erase Enter Erase Suspend Program Erase Suspend Read Erase Suspend Program Erase Resume Erase Suspend Read Erase Erase Complete DQ6 DQ2 Toggle DQ2 and DQ6 with OE or CE Note: DQ2 is read from the erase-suspended sector. 55 MBM29DL16XTD/BD-70/90 (10) RY/BY Timing Diagram during Program/Erase Operations CE Rising edge of the last write pulse WE Entire programming or erase operations RY/BY t BUSY (11) RESET, RY/BY Timing Diagram WE RESET tRP t RB RY/BY tREADY 56 MBM29DL16XTD/BD-70/90 (12) Timing Diagram for Word Mode Configuration CE tCE BYTE Data Output (DQ7 to DQ0) DQ14 to DQ0 tELFH DQ15/A-1 Data Output (DQ14 to DQ0) tFHQV DQ15 A-1 (13) Timing Diagram for Byte Mode Configuration CE BYTE DQ14 to DQ0 tELFL Data Output (DQ7 to DQ0) Data Output (DQ14 to DQ0) tACC DQ15/A-1 DQ15 A-1 tFLQZ (14) BYTE Timing Diagram for Write Operations Falling edge of the last write signal CE or WE Input Valid BYTE tAS tAH 57 MBM29DL16XTD/BD-70/90 (15) AC Waveforms for Sector Group Protection A19, A18, A17 A16, A15, A14 A13, A12 SPAX SPAY A0 A1 A6 VID VIH A9 tVLHT VID VIH OE tVLHT tVLHT tVLHT tWPP WE tOESP tCSP CE Data 01h tVCS VCC SPAX : Sector Group Address to be protected SPAY : Next Sector Group Address to be protected Note: A-1 is VIL on byte mode. 58 tOE MBM29DL16XTD/BD-70/90 (16) Temporary Sector Group Unprotection Timing Diagram VCC tVIDR tVCS tVLHT VID VIH RESET CE WE tVLHT Program or Erase Command Sequence tVLHT RY/BY Unprotection period 59 MBM29DL16XTD/BD-70/90 (17) Extended Sector Group Protection Timing Diagram VCC tVCS tVLHT RESET tVIDR tWC Add tWC SPAX SPAX SPAY A0 A1 A6 CE OE TIME-OUT tWP WE Data 60h 60h 40h 01h tOE SPAX : Sector Group Address to be protected SPAY : Next Sector Group Address to be protected TIME-OUT : Time-Out window = 250 µs (Min) 60 60h MBM29DL16XTD/BD-70/90 (18) Accelerated Program Timing Diagram VCC tVACCR tVCS tVLHT VACC VIH WP/ACC CE WE tVLHT Program Command Sequence tVLHT RY/BY Acceleration period 61 MBM29DL16XTD/BD-70/90 ■ FLOW CHART (1) Embedded ProgramTM Algorithm EMBEDDED ALGORITHM Start Write Program Command Sequence (See Below) Data Polling No Increment Address No Verify Data ? Yes Embedded Program Algorithm in program Last Address ? Yes Programming Completed Program Command Sequence (Address/Command): 555h/AAh 2AAh/55h 555h/A0h Program Address/Program Data Notes: • The sequence is applied for × 16 mode. • The addresses differ from × 8 mode. 62 MBM29DL16XTD/BD-70/90 (2) Embedded EraseTM Algorithm EMBEDDED ALGORITHM Start Write Erase Command Sequence (See Below) Data Polling No Data = FFh ? Yes Embedded Erase Algorithm in progress Erasure Completed Chip Erase Command Sequence (Address/Command): Individual Sector/Multiple Sector Erase Command Sequence (Address/Command): 555h/AAh 555h/AAh 2AAh/55h 2AAh/55h 555h/80h 555h/80h 555h/AAh 555h/AAh 2AAh/55h 2AAh/55h 555h/10h Sector Address /30h Sector Address /30h Sector Address /30h Additional sector erase commands are optional. Notes: • The sequence is applied for × 16 mode. • The addresses differ from × 8 mode. 63 MBM29DL16XTD/BD-70/90 (3) Data Polling Algorithm Start Read Byte (DQ7 to DQ0) Addr. = VA DQ7 = Data? VA = Address for programming = Any of the sector addresses within the sector being erased during sector erase or multiple sector erases operation. = Any of the sector addresses within the sector not being protected during chip erase operation. Yes No No DQ5 = 1? Yes Read Byte (DQ7 to DQ0) Addr. = VA DQ7 = Data? * No Fail Yes Pass * : DQ7 is rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5. 64 MBM29DL16XTD/BD-70/90 (4) Toggle Bit Algorithm Start Read DQ7 to DQ0 Addr. = VA *1 VA = Bank address being executed Embedded Algorithm. Read DQ7 to DQ0 Addr. = VA DQ6 = Toggle? No Yes No DQ5 = 1? Yes *1, 2 Read DQ7 to DQ0 Addr. = VA *1, 2 Read DQ7 to DQ0 Addr. = VA DQ6 = Toggle? No Yes Program/Erase Operation Not Complete.Write Reset Command Program/Erase Operation Complete *1: Read toggle bit twice to determine whether it is toggling. *2: Recheck toggle bit because it may stop toggling as DQ5 changes to “1”. 65 MBM29DL16XTD/BD-70/90 (5) Sector Group Protection Algorithm Start Setup Sector Group Addr. (A19, A18, A17, A16, A15, A14, A13, A12) PLSCNT = 1 OE = V ID, A 9 = V ID, CE = V IL, RESET = V IH A 6 = A 0 = V IL, A 1 = V IH Activate WE Pulse Time out 100 µs Increment PLSCNT WE = V IH, CE = OE = V IL (A 9 should remain V ID) Read from Sector Group (Addr. = SPA, A 1 = V IH, A 6 = A 0 = V IL)* No No PLSCNT = 25? Yes Data = 01H? Yes Yes Remove V ID from A 9 Write Reset Command Protect Another Sector Group ? No Device Failed Remove V ID from A 9 Write Reset Command Sector Group Protection Completed * : A-1 is V IL on byte mode. 66 MBM29DL16XTD/BD-70/90 (6) Temporary Sector Group Unprotection Algorithm Start RESET = VID *1 Perform Erase or Program Operations RESET = VIH Temporary Sector Group Unprotection Completed *2 *1: All protected sector groups are unprotected. *2: All previously protected sector groups are protected once again. 67 MBM29DL16XTD/BD-70/90 (7) Extended Sector Group Protection Algorithm Start RESET = VID Wait to 4 µs Device is Operating in Temporary Sector Group Unprotection Mode No Extended Sector Group Protection Entry? Yes To Setup Sector Group Protection Write XXXh/60h PLSCNT = 1 To Sector Group Protection Write SGA/60h (A0 = VIL, A1 = VIH, A6 = VIL) Time Out 250 µs Increment PLSCNT To Verify Sector Group Protection Write SGA/40h (A0 = VIL, A1 = VIH, A6 = VIL) Setup Next Sector Group Address Read from Sector Group Address (A0 = VIL, A1 = VIH, A6 = VIL) No No PLSCNT = 25? Yes Remove VID from RESET Write Reset Command Data = 01h? Yes Yes Protection Other Sector Group? No Device Failed Remove VID from RESET Write Reset Command Sector Group Protection Completed 68 MBM29DL16XTD/BD-70/90 (8) Embedded ProgramTM Algorithm for Fast Mode FAST MODE ALGORITHM Start 555h/AAh Set Fast Mode 2AAh/55h 555h/20h XXXh/A0h Program Address/Program Data Data Polling Verify Data? No In Fast Program Yes Increment Address No Last Address ? Yes Programming Completed (BA) XXXh/90h Reset Fast Mode XXXh/F0h Notes : • The sequence is applied for × 16 mode. • The addresses differ from × 8 mode. 69 MBM29DL16XTD/BD-70/90 ■ ORDERING INFORMATION Part No. MBM29DL161TD-70PFTN MBM29DL161TD-90PFTN MBM29DL162TD-70PFTN MBM29DL162TD-90PFTN MBM29DL163TD-70PFTN MBM29DL163TD-90PFTN MBM29DL164TD-70PFTN MBM29DL164TD-90PFTN MBM29DL161TD-70PFTR MBM29DL161TD-90PFTR MBM29DL162TD-70PFTR MBM29DL162TD-90PFTR MBM29DL163TD-70PFTR MBM29DL163TD-90PFTR MBM29DL164TD-70PFTR MBM29DL164TD-90PFTR MBM29DL161TD-70PBT MBM29DL161TD-90PBT MBM29DL162TD-70PBT MBM29DL162TD-90PBT MBM29DL163TD-70PBT MBM29DL163TD-90PBT MBM29DL164TD-70PBT MBM29DL164TD-90PBT MBM29DL161BD-70PFTN MBM29DL161BD-90PFTN MBM29DL162BD-70PFTN MBM29DL162BD-90PFTN MBM29DL163BD-70PFTN MBM29DL163BD-90PFTN MBM29DL164BD-70PFTN MBM29DL164BD-90PFTN MBM29DL161BD-70PFTR MBM29DL161BD-90PFTR MBM29DL162BD-70PFTR MBM29DL162BD-90PFTR MBM29DL163BD-70PFTR MBM29DL163BD-90PFTR MBM29DL164BD-70PFTR MBM29DL164BD-90PFTR MBM29DL161BD-70PBT MBM29DL161BD-90PBT MBM29DL162BD-70PBT MBM29DL162BD-90PBT MBM29DL163BD-70PBT MBM29DL163BD-90PBT MBM29DL164BD-70PBT MBM29DL164BD-90PBT Package 48-pin plastic TSOP (1) (FPT-48P-M19) Normal Bend 48-pin plastic TSOP (1) (FPT-48P-M20) Reverse Bend 48-pin plastic FBGA (BGA-48P-M13) 48-pin plastic TSOP (1) (FPT-48P-M19) Normal Bend 48-pin plastic TSOP (1) (FPT-48P-M20) Reverse Bend 48-pin plastic FBGA (BGA-48P-M13) Access Time 70 90 70 90 70 90 70 90 70 90 70 90 70 90 70 90 70 90 70 90 70 90 70 90 70 90 70 90 70 90 70 90 70 90 70 90 70 90 70 90 70 90 70 90 70 90 70 90 Sector Architecture Top Sector Bottom Sector (Continued) 70 MBM29DL16XTD/BD-70/90 (Continued) MBM29DL16X T E 70 PFTN PACKAGE TYPE PFTN = 48-Pin Thin Small Outline Package (TSOP) Normal Bend PFTR = 48-Pin Thin Small Outline Package (TSOP) Reverse Bend PBT = 48-Ball Fine pitch Ball Grid Array Package (FBGA) SPEED OPTION See Product Selector Guide DEVICE REVISION BOOT CODE SECTOR ARCHITECTURE T = Top sector B = Bottom sector DEVICE NUMBER/DESCRIPTION MBM29DL16X 16Mega-bit (2M × 8-Bit or 1M × 16-Bit) CMOS Flash Memory 3.0 V-only Read, Program, and Erase 71 MBM29DL16XTD/BD-70/90 ■ PACKAGE DIMENSIONS Note 1) * : Values do not include resin protrusion. Resin protrusion and gate protrusion are +0.15(.006)Max(each side). Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 48-pin plastic TSOP(1) (FPT-48P-M19) LEAD No. 1 48 INDEX Details of "A" part 0.25(.010) 0~8˚ 0.60±0.15 (.024±.006) 24 25 * 12.00±0.20 20.00±0.20 (.787±.008) * 18.40±0.20 (.724±.008) "A" (.472±.008) +0.10 1.10 –0.05 +.004 .043 –.002 (Mounting height) 0.10±0.05 (.004±.002) (Stand off height) 0.50(.020) 0.10(.004) +0.03 0.17 –0.08 0.22±0.05 (.009±.002) +.001 .007 –.003 C 0.10(.004) M Dimensions in mm (inches). Note: The values in parentheses are reference values 2003 FUJITSU LIMITED F48029S-c-6-7 Note 1) * : Values do not include resin protrusion. Resin protrusion and gate protrusion are +0.15(.006)Max(each side). Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 48-pin plastic TSOP(1) (FPT-48P-M20) LEAD No. 1 48 Details of "A" part INDEX 0.60±0.15 (.024±.006) 0~8˚ 0.25(.010) 24 25 +0.03 0.17 –0.08 +.001 0.10(.004) .007 –.003 0.50(.020) 0.22±0.05 (.009±.002) M 0.10±0.05 (.004±.002) (Stand off height) +0.10 "A" 1.10 –0.05 +.004 * 18.40±0.20 (.724±.008) 20.00±0.20 (.787±.008) C 0.10(.004) 2003 FUJITSU LIMITED F48030S-c-6-7 .043 –.002 (Mounting height) * 12.00±0.20(.472±.008) Dimensions in mm (inches). Note: The values in parentheses are reference values (Continued) 72 MBM29DL16XTD/BD-70/90 (Continued) 48-ball plastic FBGA (BGA-48P-M13) +0.15 9.00±0.20(.354±.008) +.006 1.05 –0.10 .041 –.004 (Mounting height) 0.38±0.10(.015±.004) (Stand off) 5.60(.220) 0.80(.031)TYP 6 5 8.00±0.20 (.315±.008) 4 4.00(.157) 3 INDEX 2 1 H C0.25(.010) G F E D 48-ø0.45±0.10 (48-ø.018±.004) C B A ø0.08(.003) M 0.10(.004) C 2001 FUJITSU LIMITED B48013S-c-3-2 Dimensions in mm (inches). Note: The values in parentheses are reference values 73 MBM29DL16XTD/BD-70/90 FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party’s intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. 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Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. F0303 FUJITSU LIMITED Printed in Japan