HV6506 32-Channel LCD Driver with Separate Backplane Output Ordering Information Package Options 44-J Lead Quad Plastic Chip Carrier Device HV6506 44 Lead Quad Plastic Gullwing HV6506PJ HV6506PG Dice in waffle pack HV6506X Features General Description ■ Processed with HVCMOS® technology The HV65 is a low-voltage serial to high-voltage parallel converter with push-pull outputs. This device has been designed for use as a driver circuit for LCD displays. It can also be used in any application requiring multiple output high-voltage current sourcing and sinking capabilities. The inputs are fully CMOS compatible. ■ 32 push-pull CMOS output up to 60V ■ Low power level shifting ■ Source/sink current minimum 5mA ■ Shift register speed 5MHz The device consists of a 32-bit shift register, 32 latches, and control logic to perform the polarity select of the outputs. HVout1 is connected to the first stage of the shift register through the polarity logic. Data is shifted through the shift register on the logic low to high transition of the clock. A DIR pin causes data shifting counterclockwise when grounded and clockwise when connected to VDD. A data output buffer is provided for cascading devices. This output reflects the current status of the last bit of the shift register. Operation of the shift register is not affected by the LE (latch enable) or the POL (polarity) inputs. Transfer of data from the shift register to the latch occurs when the LE (latch enable) input is high. The data in the latch is stored after LE transition from high to low. ■ Latched data outputs ■ Bidirectional shift register (DIR) ■ Backplane output Absolute Maximum Ratings1 Supply voltage, VDD2 -0.5V to +7.0V VPP2 -0.5V to +80V Output voltage, Logic input Ground levels2 -0.5V to VDD + 0.5V current3 Continuous total power 1.5A dissipation4 Operating temperature range Storage temperature range Lead temperature 1.6mm (1/16 inch) from case for 10 seconds 1200mW -40°C to +85°C -65°C to +125°C 260°C Notes: 1. Device will survive (but operation may not be specified or guaranteed) at these extremes. 2. All voltages are referenced to VSS. 3. Duty cycle is limited by the total power dissipated in the package. 4. For operation above 25°C ambient derate linearly to 85°C at 20mW/°C. 12-132 HV6506 Electrical Characteristics (over recommended operating conditions unless noted) DC Characteristics (VDD = 5V, VPP = 60V, VSS = GND) Symbol Parameter Min IDD VDD supply current 15 mA VDD = VDD max fCLK = 5MHz IPP High voltage supply current 0.5 mA Outputs high 0.5 mA Outputs low 0.5 mA All VIN = VSS or VDD IDDQ Quiescent VDD supply current VOH High-level output VOL Low-level output Max Units Conditions Q 50 V IO= 5mA, VPP = 60V Data out 4.6 V IO= -100µA 8 V IO= 5mA, VPP = 60V 0.4 V IO= 100µA Q Data out IIH High-level logic input current 1 µA VIH = VDD IIL Low-level logic input current -1 µA VIL = 0V VOLBP Low-level output voltage, backplane 8 V IO = 40mA VOHBP High-level output viltage, backplane V IO = -40mA 48 AC Characteristics (VDD = 5V, VPP = 60V, TC = 25°C) Symbol Parameter fCLK Clock frequency tW Clock width high or low tSU Min Max Units 5 MHz Conditions 100 ns Data set-up time before clock rises 25 ns tH Data hold time after clock rises 50 ns tON, tOFF Time from latch enable or POL to HVOUT 500 ns CL = 30pF tON, tOFF Time from POL to BP output 500 ns CL = 30pF tDHL Delay time clock to data high to low 200 ns CL = 15pF tDLH Delay time clock to data low to high 200 ns CL = 15pF tDLE Delay time clock to LE low to high tWLE Width of LE pulse tSLE LE set-up time before clock rises 50 ns 100 ns 50 ns 12 Recommended Operating Conditions Symbol Parameter VDD Logic supply voltage VPP Output off voltage VIH High-level input voltage VIL Low-level input voltage fCLK Clock frequency TA Operating free-air temperature IOD Allowable current through output diodes Min Max 4.5 5.5 V 0 60 V VDD V 0.8 V 3.5 0 5 -40 Notes: 1. Power-up sequence should be the following: 1. Connect ground. 2. Apply VDD. 3. Set all inputs (Data, CLK, Enable, etc.) to a known state. 4. Apply VPP. 2. Power-down sequence should be the reverse of the above. 3. The VPP should not drop below 0V during operation. 12-133 Units MHz +85 °C 200 mA HV6506 Switching Waveforms VIH Data Input 50% Data Valid 50% VIL tSU tH VIH Clock 50% 50% tWL 50% 50% VIL tWH VOH 50% VOL tDLH Data Out VOH 50% VOL tDHL VIH 50% 50% Latch Enable tDLE tWLE VOL tSLE VOH HVOUT w/ S/R LOW 50% tOFF VOL VOH HVOUT w/ S/R HIGH 50% VOL tON POL (ASYNCH w/ Clock) 50% 50% tOFF BPOUT tON VOHBP 50% 50% 12-134 VOLBP HV6506 Functional Block Diagram VPP Polarity Latch Enable VDD Data Input Clock Latch HVOUT1 Latch HVOUT2 32-Bit Shift Register DIR (Outputs 3 to 30 not shown) Latch HVOUT31 Latch HVOUT32 Data Out BPOUT GND Function Table Inputs Function Data CLK LE POL DIR Load S/R H or L ↑ L H X H or L *…* * X H or L L H X * *…* X H or L L L X * H ↑ H L X L ↑ H H H ↑ H L ↑ L Load latches All high All low Transparent Mode R/L Shift 12 Outputs Data Out 2…32 BPOUT * *…* * H * *…* * H *…* * *…* * L H *…* H *…* * L X L *…* H *…* * H H X H *…* L *…* * H H L X L *…* L *…* * L ↑ H H X L *…* H *…* * H H ↑ H H X H *…* L *…* * H L ↑ H L X L *…* L *…* * L H ↑ H L X H *…* H *…* * L X ↑ X X H Qn → Qn+1 * *…* Q32 X ↑ X X L Qn → Qn-1 * *…* Q1 Notes: H = high level, L = low level, X = irrelevant, ↑ = low-to-high transition. * = dependent on previous stage’s state before the last CLK or last LE high. 12-135 Shift Reg 1 2…32 HV Outputs 1 HV6506 Pin Configuration HV65 44 Pin J-Lead Package Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Function HV65 44 Pin Plastic Gullwing (QFP) Package Pin HVOUT 17/16 HVOUT 16/17 HVOUT 15/18 HVOUT 14/19 HVOUT 13/20 HVOUT 12/21 HVOUT 11/22 HVOUT 10/23 HVOUT 9/24 HVOUT 8/25 HVOUT 7/26 HVOUT 6/27 HVOUT 5/28 HVOUT 4/29 HVOUT 3/30 HVOUT 2/31 HVOUT 1/32 Data Out GND N/C N/C POL 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Function Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 LE VDD Clock DIR Data In VPP BP Out HVOUT 32/1 HVOUT 31/2 HVOUT 30/3 HVOUT 29/4 HVOUT 28/5 HVOUT 27/6 HVOUT 26/7 HVOUT 25/8 HVOUT 24/9 HVOUT 23/10 HVOUT 22/11 HVOUT 21/12 HVOUT 20/13 HVOUT 19/14 HVOUT 18/15 Note: 1. Pin designation for DIR = H/L Example: for DIR = H, Pin 1 = HVOUT 17 for DIR = L, Pin 1 = HVOUT 16 Function HVOUT 22/11 HVOUT 21/12 HVOUT 20/13 HVOUT 19/14 HVOUT 18/15 HVOUT 17/16 HVOUT 16/17 HVOUT 15/18 HVOUT 14/19 HVOUT 13/20 HVOUT 12/21 HVOUT 11/22 HVOUT 10/23 HVOUT 9/24 HVOUT 8/25 HVOUT 7/26 HVOUT 6/27 HVOUT 5/28 HVOUT 4/29 HVOUT 3/30 HVOUT 2/31 HVOUT 1/32 Pin 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Function Data Out GND N/C N/C POL LE VDD Clock DIR Data In VPP BP Out HVOUT 32/1 HVOUT 31/2 HVOUT 30/3 HVOUT 29/4 HVOUT 28/5 HVOUT 27/6 HVOUT 26/7 HVOUT 25/8 HVOUT 24/9 HVOUT 23/10 Note: 1. Pin designation for DIR = H/L Example: for DIR = H, Pin 1 is HVOUT 22 for DIR = L, Pin 1 is HVOUT 11 Package Outline 44 43 42 41 40 39 38 37 36 35 34 39 38 37 36 35 34 33 32 31 30 29 1 33 40 28 2 32 41 27 3 31 42 26 4 30 43 25 5 29 44 24 6 28 1 23 7 27 2 22 8 26 3 21 9 25 24 23 4 20 10 5 19 11 6 18 12 13 14 15 16 17 18 19 20 21 22 7 8 9 10 11 12 13 14 15 16 17 top view top view 44-pin PLCC 44-pin Quad Plastic Gullwing Package 12-136