SLOS433H − FEBRUARY 2004 − REVISED OCTOBER 2004 D D D D D D D D D D D 2.7-V and 5-V Performance −40°C to 125°C Specification at 5 V No Crossover Distortion Gain Bandwith of 152 kHz Low Supply Current − LPV321 . . . 9 µA − LPV358 . . . 15 µA − LPV324 . . . 28 µA Rail-to-Rail Output Swing at 100-kΩ Load − VCC+ − 3.5 mV − VCC− + 90 mV VICR . . . −0.2 V to VCC+ − 0.8 V Stable With Capacitive Load of 1000 pF Applications − Active Filters − General-Purpose, Low-Voltage Applications − Low-Power and/or Portable Applications Latch-Up Performance Exceeds 100 mA per JESD 78, Class II ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model (A114-A) − 200-V Machine Model (A115-A) − 1000-V Charged-Device Model (C101) LPV321 . . . DBV OR DCK PACKAGE (TOP VIEW) 1 IN+ VCC− IN− 5 VCC+ 4 OUTPUT 2 3 LPV358 . . . D, DDU, OR DGK PACKAGE (TOP VIEW) 1OUT 1IN− 1IN+ VCC− 1 8 2 7 3 6 4 5 VCC+ 2OUT 2IN− 2IN+ LPV324 . . . D OR PW PACKAGE (TOP VIEW) 1OUT 1IN− 1IN+ VCC+ 2IN+ 2IN− 2OUT 1 14 2 13 3 12 4 11 5 10 6 9 7 8 4OUT 4IN− 4IN+ VCC− 3IN+ 3IN− 3OUT description/ordering information The LPV321/358/324 devices are low-power (9 µA per channel at 5 V) versions of the LMV321/358/324 operational amplifiers. These are additions to the LMV321/358/324 family of commodity operational amplifiers. The LPV321/358/324 devices are the most cost-effective solutions for applications where low voltage, low-power operation, space saving, and low price are needed. These devices have rail-to-rail output-swing capability, and the input common-mode voltage range includes ground. They all exhibit excellent speed-power ratios, achieving 152 kHz of bandwidth, with a supply current of only 9 µA typical. The LPV321, LPV358, and LPV324 are characterized for operation from −40°C to 85°C. The LPV321I, LPV358I, and LPV324I are characterized for operation from −40°C to 125°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2004, Texas Instruments Incorporated !"#$ % &'!!($ #% )'*+&#$ ,#$(!,'&$% &!" $ %)(&&#$% )(! $.( $(!"% (/#% %$!'"($% %$#,#!, 0#!!#$1- !,'&$ )!&(%%2 ,(% $ (&(%%#!+1 &+',( $(%$2 #++ )#!#"($(!%- POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SLOS433H − FEBRUARY 2004 − REVISED OCTOBER 2004 description/ordering information (continued) ORDERING INFORMATION ORDERABLE PART NUMBER PACKAGE† TA SOT23-5 (DBV) Single SOT23-5 (DCK) SOIC-8 (D) −40°C −40 C to 85 85°C C Dual VSSOP-8 (DDU) VSSOP-8 (DGK) SOIC-14 (D) Quad TSSOP-14 (PW) SOT23-5 (DBV) Single SOT23-5 (DCK) SOIC-8 (D) −40°C −40 C to 125 125°C C Dual VSSOP-8 (DDU) VSSOP-8 (DGK) SOIC-14 (D) Quad TSSOP-14 (PW) Reel of 3000 LPV321DBVR Reel of 250 LPV321DBVT Reel of 3000 LPV321DCKR Reel of 250 LPV321DCKT Tube of 75 LPV358D Reel of 2500 LPV358DR Reel of 3000 LPV358DDUR Reel of 2500 LPV358DGKR Reel of 250 LPV358DGKT Tube of 50 LPV324D Reel of 2500 LPV324DR Tube of 90 LPV324PW Reel of 2000 LPV324PWR Reel of 3000 LPV321IDBVR Reel of 250 LPV321IDBVT Reel of 3000 LPV321IDCKR Reel of 250 LPV321IDCKT Tube of 75 LPV358ID Reel of 2500 LPV358IDR Reel of 3000 LPV358IDDUR Reel of 2500 LPV358IDGKR Reel of 250 LPV358IDGKT Tube of 50 LPV324ID Reel of 2500 LPV324IDR Tube of 90 LPV324IPW Reel of 2000 LPV324IPWR TOP-SIDE MARKING PREVIEW PREVIEW PREVIEW PREVIEW PREVIEW LPV324 PV324 PREVIEW PREVIEW PREVIEW PREVIEW PREVIEW LPV324I PV324I † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. symbol (each amplifier) − IN− OUT 2 + IN+ POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLOS433H − FEBRUARY 2004 − REVISED OCTOBER 2004 LPV324 simplified schematic VCC VBIAS1 + VCC − VBIAS2 + Output − VCC VCC VBIAS3 + IN− IN+ − VBIAS4 + − absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, VCC+ − VCC− (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Differential input voltage, VID (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±VCC Input voltage range, VI (either input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC− to VCC+ − 1 V Package thermal impedance, θJA (see Notes 3 and 4): 5-pin DBV package . . . . . . . . . . . . . . . . . . . 206°C/W 5-pin DCK package . . . . . . . . . . . . . . . . . . . 252°C/W 8-pin D package . . . . . . . . . . . . . . . . . . . . . . . 97°C/W 8-pin DDU package . . . . . . . . . . . . . . . . . . TBD°C/W 8-pin DGK package . . . . . . . . . . . . . . . . . . . 172°C/W 14-pin D package . . . . . . . . . . . . . . . . . . . . . . 86°C/W 14-pin PW package . . . . . . . . . . . . . . . . . . . 113°C/W Maximum junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values, except differential voltages and VCC specified for the measurement of IOS, are with respect to the network GND. 2. Differential voltages are at IN+ with respect to IN−. 3. Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = (TJ(max) − TA)/θJA. Selecting the maximum of 150°C can affect reliability. 4. The package thermal impedance is calculated in accordance with JESD 51-7. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SLOS433H − FEBRUARY 2004 − REVISED OCTOBER 2004 recommended operating conditions MIN VCC TA Supply voltage Operating free-air temperature MAX 2.7 5 LPV3xx −40 85 LPV3xxI −40 125 UNIT V °C ESD protection TEST CONDITIONS Human-Body Model Machine model Charged-Device Model 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TYP UNIT 2 kV 200 V 1 kV SLOS433H − FEBRUARY 2004 − REVISED OCTOBER 2004 2.7-V electrical characteristics TA = 25°C, VCC+ = 2.7 V, VCC− = 0 V, VIC = 1 V, VO = VCC+/2, and RL > 1 MΩ (unless otherwise noted) PARAMETER VIO Input offset voltage αVIO Average temperature coefficient of input offset voltage IIB IIO TEST CONDITIONS MIN TYP† MAX 1.2 7 UNIT mV mV/°C 4 Input bias current 1.7 50 nA Input offset current 0.6 40 nA CMRR Common-mode rejection ratio 0 ≤ VIC ≤ 1.7 V 50 70 dB kSVR Supply-voltage rejection ratio 2.7 V ≤ VCC+ ≤ 5 V, VIC = 1 V, VO = 1 V 50 65 dB VICR Common-mode input voltage range CMRR ≥ 50 dB 0 to 1.7 −0.2 to 1.9 V VO Output swing RL = 100 kΩ to 1.35 V VCC+ − 0.100 VCC+ − 0.003 0.080 High level Low level LPV321§ ICC Supply current 0.180 4 8 LPV358 (both amplifiers)§ 8 16 LPV324 (all four amplifiers) 16 24 V mA SR Slew rate‡ 0.1 V/ms GBW Gain bandwidth product CL = 22 pF (see Note 5) 205 kHz Fm Phase margin CL = 22 pF (see Note 5) 71 deg Gain margin CL = 22 pF (see Note 5) 11 dB Vn Equivalent input noise voltage f = 1 kHz 178 nV/√Hz In Equivalent input noise current f = 1 kHz 0.5 pA/√Hz † All typical values are at VCC = 2.7 V, TA = 25°C. ‡ Number specified is the slower of the positive and negative slew rates. § Product Preview NOTE 5: Closed-loop gain = 18 dB, VIC = VCC+/2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SLOS433H − FEBRUARY 2004 − REVISED OCTOBER 2004 5-V electrical characteristics TA = 25°C, VCC+ = 5 V, VCC− = 0 V, VIC = 2 V, VO = VCC+/2, and RL > 1 MΩ (unless otherwise noted) PARAMETER VIO TEST CONDITIONS Input offset voltage TA 25°C MIN TYP† MAX 1.5 7 −40°C to 85°C 10 −40°C to 125°C 11 UNIT mV αVIO Average temperature coefficient of input offset voltage IIB Input bias current CMRR Common-mode rejection ratio 0 ≤ VIC ≤ 4 V 25°C 50 71 dB kSVR Supply-voltage rejection ratio 2.7 V ≤ VCC+ ≤ 5 V, VIC = 1 V, VO = 1 V 25°C 50 65 dB VICR Common-mode input voltage range CMRR ≥ 50 dB 25°C 0 to 4 25°C 4 25°C 2 Input offset current 60 −40°C to 125°C 65 VO Output swing RL = 100 kΩ to 2.5 V 0.6 55 VCC+ − 0.100 VCC+ − 0.0035 VCC+ − 0.200 −40°C to 125°C VCC+ − 0.225 0.090 −40°C to 85°C IOS Output short-circuit current Sinking, VO = 5 V 25°C 17 20 72 9 −40°C to 85°C Supply current 15 AV§ Large-signal voltage gain RL = 100 kΩ 24 −40°C to 125°C 80 28 −40°C to 85°C 46 125 25°C 15 −40°C to 85°C 10 −40°C to 125°C 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 mA 42 −40°C to 125°C 100 SR¶ Slew rate 25°C 0.1 † All typical values are at VCC = 5 V, TA = 25°C. ‡ Product Preview § RL is connected to VCC−. The output voltage is 0.5 V ≤ VO ≤ 4.5 V. ¶ Number specified is the slower of the positive and negative slew rates. Connected as a voltage follower with 3-V step input. 6 20 −40°C to 85°C 25°C LPV324 (all four amplifiers) 12 40 25°C ICC mA 15 −40°C to 125°C LPV358 (both amplifiers)‡ V 0.240 2 25°C LPV321‡ 0.180 nA 0.220 −40°C to 125°C Sourcing, VO = 0 V 40 −40°C to 125°C −40°C to 85°C nA V 50 25°C Low level −0.2 to 4.2 −40°C to 85°C 25°C High level 50 −40°C to 85°C 25°C IIO mV/°C V/mV V/ms SLOS433H − FEBRUARY 2004 − REVISED OCTOBER 2004 5-V electrical characteristics TA = 25°C, VCC+ = 5 V, VCC− = 0 V, VIC = 2 V, VO = VCC+/2, and RL > 1 MΩ (unless otherwise noted) (continued) PARAMETER GBW Gain bandwidth product CL = 22 pF (see Note 5) Fm Phase margin CL = 22 pF (see Note 5) 25°C Gain margin CL = 22 pF (see Note 5) 25°C 12 dB Equivalent input noise voltage f = 1 kHz 25°C 146 nV/√Hz In Equivalent input noise current f = 1 kHz † All typical values are at VCC = 5 V, TA = 25°C. NOTE 5: Closed-loop gain = 18 dB, VIC = VCC+/2 25°C 0.3 pA/√Hz POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MIN TYP† TA 25°C Vn TEST CONDITIONS MAX UNIT 237 kHz 74 deg 7 SLOS433H − FEBRUARY 2004 − REVISED OCTOBER 2004 SUPPLY CURRENT vs SUPPLY VOLTAGE (LPV324 − All Channels) INPUT BIAS CURRENT vs TEMPERATURE 6 25 IB, IIB − Input Bias Current − nA ICC − Supply Current − A 30 TA = 85C TA = 40C TA = 25C 20 15 10 5 1 2 3 4 5 VCC+ = 5 V VIN = VCC+/2 4 3 2 1 0 −40 0 0 5 6 −20 0 VCC+ − Supply Voltage − V SOURCING CURRENT vs OUTPUT VOLTAGE 80 100 1K 100 IO − Source Current − mA IO − Source Current − mA 60 SOURCING CURRENT vs OUTPUT VOLTAGE 1K VCC+ = 2.7 V 10 1 0.1 0.01 0.01 0.1 1 10 100 VCC+ = 5 V 10 1 0.1 0.01 0.001 0.001 Output Voltage Referenced to V+ − V 0.01 0.1 Figure 4 POST OFFICE BOX 655303 1 Output Voltage Referenced to V+ − V Figure 3 8 40 Figure 2 Figure 1 0.001 0.001 20 TA − Temperature − C • DALLAS, TEXAS 75265 10 SLOS433H − FEBRUARY 2004 − REVISED OCTOBER 2004 SINKING CURRENT vs OUTPUT VOLTAGE SINKING CURRENT vs OUTPUT VOLTAGE 1K 1K 10 1 0.1 10 1 0.1 0.01 0.01 0.001 0.001 0.01 0.1 1 0.001 0.001 10 Figure 5 10 220 Rl Terminated to Opposing Supply Rail RL = 10 kΩ 200 180 Negative Swing RL = 100 kΩ 140 120 100 80 Positive Swing RL = 10 kΩ 40 20 Input Voltage Noise − nV/Hz Output Voltage From Supply Voltage − mV 1 INPUT VOLTAGE NOISE vs FREQUENCY 240 60 0.1 Figure 6 OUTPUT VOLTAGE SWING vs SUPPLY VOLTAGE 160 0.01 Output Voltage Referenced to GND − V Output Voltage Referenced to GND − V 220 VCC+ = 5 V 100 VCC+ = 2.7 V IO − Sink Current − mA IO − Sink Current − mA 100 200 VCC+ = 2.7 V 180 160 VCC+ = 5 V 140 120 RL = 100 kΩ 0 2.5 3 3.5 4 4.5 5 5.5 100 10 100 VCC+ − Supply Voltage − V Frequency − Hz Figure 7 Figure 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1K 9 SLOS433H − FEBRUARY 2004 − REVISED OCTOBER 2004 INPUT CURRENT NOISE vs FREQUENCY CROSSTALK REJECTION vs FREQUENCY 140 0.40 130 VCC+ = 2.7 V Crosstalk Rejection − dB 0.30 0.25 0.20 VCC+ = 5 V 0.15 0.10 0.05 120 110 100 90 80 70 60 50 0.00 10 100 1K 40 100 10K VCC+ = 5 V RL = 100 k AV = 1 VI = 3 VPP 1K Frequency − Hz 10K Figure 9 Figure 10 PSRR vs FREQUENCY FREQUENCY vs RL 85 180 40 VCC+ = 5 V, +PSRR 75 RL = 10 kΩ 65 VCC+ = 2.7 V RL = 10 kΩ RL = 100 kΩ Phase 30 VCC+ = 2.7 V, +PSRR 25 Gain 80 10 60 40 VCC+ = −2.7 V, −PSRR 0 20 −5 −15 100 0 1K 10K 100K 1M −10 1 Frequency − Hz 10 100 1K Frequency − kHz Figure 11 10 140 100 20 15 5 160 120 VCC+ = −5 V, −PSRR 45 Gain − dB PSRR − dB 55 35 100K Frequency − Hz Figure 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 −20 10K Phase Margin − Deg Input Current Noise − pA/Hz 0.35 SLOS433H − FEBRUARY 2004 − REVISED OCTOBER 2004 FREQUENCY RESPONSE vs CL 180 40 140 Gain VCC+ = 5 V RL = 10 kΩ RL = 100 kΩ 10 80 60 40 0 Gain − dB 100 20 100 20 10 CL = 22 pF CL = 200 pF CL = 1,000 pF 10 10K SLEW RATE vs SUPPLY VOLTAGE 0.13 100 0.12 80 0.11 60 Gain 40 20 20 0 10 −20 VCC+ = 5.0 V CL = 22 pF CL = 200 pF CL = 1,000 pF 100 Slew Rate − V/s 120 Phase Margin − Deg 30 Gain − dB 1K Figure 14 FREQUENCY RESPONSE vs CL 10 100 Frequency − kHz Phase −10 1 −40 −60 1 Figure 13 0 −20 −10 1K Frequency − kHz 40 80 40 Gain 0 −20 10 100 60 20 0 1 120 0 20 −10 CL = 22 pF CL = 200 pF CL = 1000 pF 30 Phase Margin − Deg 120 140 VCC+ = 2.7 V Phase 160 Phase 30 Gain − dB 40 Phase Margin − Deg FREQUENCY vs RL 0.1 0.09 0.08 Falling Edge 0.07 0.06 −40 0.05 −60 0.04 −80 1K Positive Edge Open Loop VID = 100 mV VCC+ = 5 V 0.03 2.5 3 3.5 4 4.5 5 5.5 VCC − Supply Voltage − V Frequency − kHz Figure 16 Figure 15 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 SLOS433H − FEBRUARY 2004 − REVISED OCTOBER 2004 NONINVERTING SMALL-SIGNAL PULSE RESPONSE NONINVERTING LARGE-SIGNAL PULSE RESPONSE 0.16 3 TA = 25°C RL = 10 kΩ VCC = 5 V/0 V AV = 1 2 1 0 Input − 20 mV/Div Input − 1 V/Div 4 0.12 0.08 0.04 VI = 100 mV/0 V 0 −1 100 s/Div −0.04 0.16 Output − 20 mV/Div Output − 1 V/Div 4 100 s/Div 3 2 TA = 25°C RL = 10 kΩ VCC = 5 V/0 V AV = 1 1 0 0.12 0.08 TA = 25°C VCC+ = 5 V/0 V RL = 10 kΩ AV = 1 0.04 0 −1 100 s/Div 100 s/Div Figure 18 Figure 17 INVERTING LARGE-SIGNAL PULSE RESPONSE INVERTING SMALL-SIGNAL PULSE RESPONSE Input − 20 mV/Div Input − 1 V/Div 6 4 2 0 −2 TA = 25°C 0.08 0.04 0 −0.04 −0.08 −4 100 s/Div TA = 25°C AV = −5 RL = 10 kΩ Rf = 10 kΩ VCC+ = 5 V Ri = 2 kΩ 0 −2 −4 Output − 20 mV/Div Output − 1 V/Div 2 0.16 0.12 0.08 0 100 s/Div TA = 25°C RL = 10 kΩ VCC+ = 5 V AV = −5 Rf = 10 kΩ Ri = 2 kΩ 0.04 100 s/Div Figure 20 Figure 19 12 100 s/Div 0.20 6 4 TA = 25 C POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. 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