PRELIMINARY TECHNICAL DATA a High Performance Multibit Σ∆ DAC with SACD Playback Preliminary Technical Data AD1955 FEATURES APPLICATIONS 5V Power Supply Stereo Audio DAC System. Accepts 16/18/20/24-Bit Data Supports 24-Bits, 192kHz Sample Rate PCM Audio Data Supports SACD bit-stream and External Digital Filter Interface Accepts a Wide Range of PCM Sample Rates Including: 32kHz, 44.1kHz. 48kHz, 88.2kHz, 96kHz, and 192kHz Multibit Sigma Delta Modulator with “Perfect Differential Linearity Restoration” for Reduced Idle Tones and Noise Floor Data Directed Scrambling DAC - Least Sensitive to Jitter Supports SACD playback with “Bit Expansion” filter Differential Current Output for Optimum Performance 8.64 mA p-p Output Current with +3dB headroom in SACD mode 120 dB SNR/DNR (not muted) at 48KHz Sample Rate (A-Weighted Stereo) 123 dB SNR/DNR (Mono) -110 dB THD+N 110 dB Stopband Attenuation with +/-0.0002dB Passband Ripple 8 Times Oversampling Digital Filter On-chip Clickless Volume Control Supports SACD-Mute pattern detection Supports 64fs/128fs DSD SACD with phase modulation Internal Digital Filter pass-through for External Filter Master clock: 256fs,384fs,512fs,768fs Hardware and Software Controllable Clickless Mute Serial (SPI) Control for: Serial Mode, Number of Bits, Sample Rate, Volume, Mute, De-emphasis, Mono Mode Digital De-emphasis for 32, 44.1, 48 KHz Sample Rates Flexible Serial Data Port with Right-Justified, Left-Justified, I2S-Compatible and DSP Serial Port 28 Lead SSOP Plastic Package High-End DVD-Audio, SACD, CD, Home Theatre Systems, Automotive Audio Systems, Sampling Musical Keyboards, Digital Mixing Consoles, Digital Audio Effects Processors PRODUCT OVERVIEW The AD1955 is a complete high performance single-chip stereo digital audio playback system. It is comprised of a multibit sigma-delta modulator, high performance digital interpolation filters, and continuoustime differential current output DAC section. Other features include an on-chip clickless stereo attenuator, mute capability, programmed through an SPI-compatible serial control port. The AD1955 is fully compatible with all known DVD audio formats including 192kHz as well as 96kHz sample frequencies and 24-bits. It also is backwards compatible by supporting 50/15µs digital de-emphasis intended for “redbook” Compact Discs, as well as de-emphasis at 32kHz and 48kHz sample rate. The AD1955 has a very flexible serial data input port that allows for glueless interconnection to a variety of ADCs, DSPs, SACD decoder, external digital filter, AES/EBU receivers and sample rate converters. The AD1955 can be configured in Left-justified, I2S, Right-Justified, or DSP serial port compatible modes. It can support MSB first, twoscompliment format, 16, 18, 20 and 24 bits in all standard PCM modes. Also the AD1955 has an interface for SACD playback and an external digital filter interface for use with an external digital interpolation filter or HDCD decoder. The AD1955 uses a +5 V power supply. It is fabricated on a single monolithic integrated circuit and is housed in a 28pin SSOP package for operation over the temperature range -400C to +1050C. FUNCTIONAL BLOCK DIAGRAM Master Clock Input DSD Bitstream Input 4 M U X Digital Supply Voltage Reference SPI Control Auto-Clock Divider 16/20/24Bit Audio Data / External Digital Filter Input 3/4 Control Data Input 3 Serial Data Interface Digital Filter Engine S/H Multibit Sigma-Delta Modulator NoiseShaped Scrambling External Filter I/F I-DAC L-ch Differential Current Output I-DAC R-ch DSD Filter RESET MUTE Analog Supply ZERO Flags Rev. PrF 3/18/2002 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 ©Analog Devices, Inc., 2002 PRELIMINARY TECHNICAL DATA AD1955 TEST CONDITIONS UNLESS OTHERWISE NOTED Analog Supply Voltages (AVDD) Digital Supply Voltages (DVDD) Reference Current (Iref) Ambient Temperature Input Clock Input Signal Input Sample Rate Measurement Bandwidth Word Width Load Capacitance Load Impedance Input Voltage HI Input Voltage LO +5.0V +5.0V .960 mA 25OC 12.288 MHz 996.11 Hz 0 dB Full Scale 48 kHz 20 Hz to 20KHz 24 Bits 100 pF 47 k ohms 2.4 V .8 V ANALOG PERFORMANCE (See Figures ) Iref = .960 mA Min Resolution Signal-to-noise Ratio (20 Hz to 20kHz) Differential Output (A-weighted, RMS) (Stereo) Differential Output (A-weighted, RMS) (Mono) Single-ended (Stereo) Dynamic Range (20 Hz to 20 kHz, -60 dB Input) Differential Output (A-weighted, RMS) (Stereo) Differential Output (A-weighted, RMS) (Mono) Single-ended (Stereo) Total Harmonic Distortion + Noise (Stereo) at 0 dBFS Analog Outputs Differential Output range (Full Scale) Output Capacitance at Each Output Pin Output bias current, Each Output Typ 24 Max Units Bits 120 123 119 dB dB dB 120 123 119 -108 dB dB dB dB 8.64 mA p-p pF mA 100 -3.24 Out-of-Band Energy (0.5XFs to 100 kHz) Reference Voltage DC Accuracy Gain Error Interchannel Gain Mismatch Gain Drift Interchannel Crosstalk (EIAJ method) Interchannel Phase Deviation Mute Attenuation De-emphasis Gain Error -90 dB V 2.39 +/-3 0.01 25 -125 +/- 0.1 -100 % dB ppm/OC dB Degrees dB dB +/- 0.1 NOTES: Performance of right and left channels are identical (exclusive of the Interchannel Gain Mismatch and Interchannel Phase Deviation specifications). Specifications subject to change without notice. DIGITAL I/O (-40oC to 105oC) Min Input Voltage HI (VIH) Input Voltage LO (VIL) Input Leakage (IIH@VIH=2.4 V) Input Leakage (IIL@VIL=0.8 V) High Level Output Voltage (VOH) IOH = 1 mA Low Level Output Voltage (VOL) IOL = 1 mA Input Capacitance Typ Max 2.0 0.8 10 10 2.4 0.4 20 Units V V uA uA V V pF Specifications subject to change without notice -2- Rev. PrF PRELIMINARY TECHNICAL DATA AD1955 TEMPERATURE RANGE Min Specifications Guaranteed Functionality Guaranteed Storage Typ Max Units O 25 -40 -55 C C O C O 105 125 Specifications subject to change without notice POWER Min Supplies Voltage, Digital Voltage, Analog Analog Current Analog Current - Reset Digital Current Digital Current - Reset Dissipation Operation - Both Supplies Operation - Analog Supply Operation - Digital Supply Power Supply Rejection Ratio 1kHz 300 mV p-p Signal at Analog Supply Pins 20kHz 300 mV p-p Signal at Analog Supply Pins Typ 4.50 4.50 Max 5 5 17 17 22 2 Units 5.50 5.50 V V mA mA mA mA 195 85 110 mW mW mW -77 -72 dB dB Specifications subject to change without notice DIGITAL FILTER CHARACTERISTICS Sample Rate (kHz) Passband (kHz) 44.1 DC-20 48 DC-21.8 96 DC-39.95 192 DC-87.2 Stopband (kHz) 24.1-328.7 26.23-358.28 56.9-327.65 117-327.65 Stopband Attenuation (dB) 110 110 115 95 Passband Ripple (dB) +/- 0.0002 +/- 0.0002 +/- 0.0005 +0/-0.04 (DC-21.8 kHz) +0/-0.5 (DC-65.4 kHz) +0/-1.5 (DC-87.2 kHz) Specifications subject to change without notice GROUP DELAY Chip Mode INT8x Mode INT4x Mode INT2x Mode Group Delay Calculation 5553/(128 × FS) 5601/(64 × FS) 5659/(32 × FS) Fs 48kHz 96kHz 192kHz Group Delay 903.8 911.6 921 Specifications subject to change without notice Units µs µs µs DIGITAL TIMING (Guaranteed over -40°C to 85°C, AVDD = DVDD = +5.0 V +/- 10%) tDMP tDML tDMH tDBH tDBL tDBP tDLS tDLH tDDS tDDH tDMP tDML tDMH tCLS tCLH tCDS tCDH tRSTL MCLK Period (FMCLK = 256*FLRCLK) MCLK LO Pulse Width (all modes) MCLK HI Pulse Width (all modes) BCLK HI Pulse Width BCLK LO Pulse Width BCLK Period LRCLK Setup LRCLK Hold (DSP Serial Port mode only) SDATA Setup SDATA Hold CCLK Period CCLK LO Pulse Width CCLK HI Pulse Width CLATCH Setup CLATCH Hold CDATA Setup CDATA Hold RST LO Pulse Width Specifications subject to change without notice. Rev. PrF -3- Min 54 0.4 X tDMP 0.4 X tDMP 20 20 60 20 5 5 10 50 15 15 10 10 10 10 15 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns PRELIMINARY TECHNICAL DATA AD1955 ABSOLUTE MAXIMUM RATINGS* Min Max PACKAGE CHARACTERISTICS DVDD to DGND -0.3 6 Units V AVDD to AGND -0.3 6 V Digital Inputs Analog Outputs AGND to DGND Reference Voltage Soldering DGND - 0.3 AGND - 0.3 -0.3 DVDD + 0.3 AVDD + 0.3 0.3 (AVDD + 0.3)/2 +300 10 V V V Min OJA (Thermal Resistance [Junction-to-Ambient]) OJC (Thermal Resistance [Junction-to-Case]) Typ 109.0 39.0 Max Units C/W O O C/W O C sec * Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ORDERING GUIDE Model Temperature AD1955YRS -40 OC to +105 OC Package Description 28-Lead SSOP AD1955YRSRL -40 OC to +105 OC 28-Lead SSOP Package Option* RS-28 RS-28 on 13” Reels *RS = Shrink Small Outline PIN CONFIGURATION DVDD 1 28 DGND EF_WCLK/LRCLK 2 27 MCLK EF_BCLK/BCLK 3 26 CCLK EF_LDATA/SDATA 4 25 CLATCH EF_RDATA 5 24 CDATA DSD_SCLK 6 23 PD/RST DSD_LDATA 7 22 MUTE DSD_RDATA 8 21 ZEROL DSD_PHASE 9 20 ZEROR AGND 10 19 AGND IOUTR+ 11 18 IOUTL+ IOUTR- 12 17 IOUTL- FILTR 13 16 FILTB IREF 14 15 AVDD CAUTION ESD (Electrostatic discharge) sensitive device. Electrostatic charges as high as 400 V readily accumulate on the human body and Test equipment and can discharge without detection. Although the AD1959 features proprietary ESD protection circuitry, permanent Damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. -4- Rev. PrF PRELIMINARY TECHNICAL DATA AD1955 PIN FUNCTION DESCRIPTIONS Pin 1 2 I/O Input Pin Name DVDD EF_WCLK/LRCLK 3 4 Input Input EF_BCLK/BCLK EF_LDATA/SDATA 5 Input EF_RDATA 6 I/O DSD_SCLK 7 8 9 Input Input I/O 10 11 12 13 Output Output Output DSD_LDATA DSD_RDATA DSD_PHASE AGND IOUTR+ IOUTRFILTR 14 15 16 17 18 19 20 Output IREF AVDD FILTB IOUTLIOUTL+ AGND ZEROR 21 Output ZEROL 22 Input MUTE 23 Input PD/RST 24 Input CDATA 25 26 Input Input CLATCH CCLK 27 28 Input MCLK DGND Rev. PrF Output Output Output Description Digital Power Supply Connected to Digital 5V supply. Word Clock in External Filter mode. Left/Right Clock input for input data in PCM mode. Bit Clock input in External Filter mode. Bit Clock input for input data in PCM mode. 8fs or 4fs L-ch Data input in External filter mode. Data should be MSB first two’s complement format. In the PCM mode, serial input, MSB first, containing two channels(left and right) of 16 to 24bit two’s complement 1fs data. 8fs or 4fs R-ch Data input in External filter mode. Data should be MSB first two’s complement format. Not used in PCM mode Shift clock input for DSD data. This clock should be 64x44.1kHz, 2.8224MHz or 128x44.1kHz, 5.6448MHz in normal mode or 128x44.1kHz, 5.6448MHz or 256x44.1kHz, 11.2896MHz in phase mode. DSD Left channel data input DSD Right channel data input DSD phase reference signal. This clock should be 64x44.1kHz, 2.8224MHz. If not used this pin should be connected Low. Analog Ground Right Channel Positive analog output. Right Channel Negative analog output. Voltage Reference Filter Capacitor Connection. Bypass and decouple the voltage reference with parallel 10uF and 0.1uF capacitors to AGND Connection point for external bias resistor. Analog power supply Connected to Analog 5V supply Filter Capacitor Connection with parallel 10uF and 0.1uF capacitors to AGND Left Channel Negative analog output. Left Channel Positive analog output. Analog Ground Right Channel Zero Flag Output. This pin goes high when the right channel has no signal input or the DSD mute pattern is detected. Left Channel Zero Flag Output. This pin goes high when the left channel has no signal input or the DSD mute pattern is detected. Mute. Assert HI to mute both stereo analog outputs. Deassert LO for normal operation. Power down/Reset. The AD1955 is placed in a reset state and the digital circuitry is powered down when this pin is held LO. The AD1955 is reset on the rising edge of this signal. The serial control port registers are reset to the default values. Connect HI for normal operation. Serial control input, MSB first, containing 16 bits of unsigned data. Used for specifying control information and channel-specific attenuation. Latch Input for control data. Control Clock input for control data. Control input data must be valid on the rising edge of CCLK. CCLK may be continuous or gated. Master Clock Input. Connect to an external clock source. Digital Ground -5- PRELIMINARY TECHNICAL DATA AD1955 OPERATING FEATURES Serial Data Input Port The AD1955’s flexible serial data input port accepts standard PCM audio data and external digital filter output data in twoscomplement, MSB-first format in PCM/External digital filter mode and a dedicated SACD serial port accepts DSD bit-stream data in SACD mode. If the PCM mode is selected by control register 0 bit12 and 13, the left channel data field always precedes the right channel data field. The serial data format and word length in PCM mode are set by the mode select bits (bits 4 and 5 and bits 2 and 3, respectively) in the SPI control register. In all data formats except for the right-justified mode, the serial port will accept an arbitrary number of bits up to a limit of 24 (extra bits will not cause an error, but they will be truncated internally). In Right-justified mode, control register 0, bits 2 and 3 are used to set the word length to 16, 18, 20, or 24 bits. The default on power up is 24-bit, I2S. In the external digital filter mode, selected by control register 0 bit 12 and 13, bits 2 and 3 are used to set the word length to 16, 18, 20 or 24 bits and the format is set with bits 4 and 5. For a burst-mode clock, the format should be set to Left-justified. DSP mode is not used. The LRCLK is always falling-edge active. The default on power-up is 24-bit mode in PCM and external digital filter mode. In SACD mode, selected by control register 0, bit 12 and 13, the SACD port will accept a DSD bit-stream. When the SPI Control Port is not being used, the SPI pins (24, 25 and 26) should be tied to DGND or DVDD. Serial Data Format in PCM mode The supported formats are shown in Figure 1. For detailed timing, see Figure 2. In Left-justified mode, LRCLK is HIGH for the left channel, and LOW for the right channel. Data should valid on the rising edge of BCLK. The MSB is left-justified to an LRCLK transition, with no MSB delay. In I2S mode, LRCLK is LOW for the left channel, and HIGH for the right channel. Data should be valid on the rising edge of BCLK. The MSB is left-justified to an LRCLK transition but with a single BCLK period delay. In DSP serial port mode, LRCLK must pulse HIGH for at least one bit clock period before the MSB of the left channel is valid, and LRCLK must pulse HI again for at least one bit clock period before the MSB of the right channel is valid. Data should be valid on the falling edge of BCLK. The DSP serial port mode can be used with any wordlength up to 24 bits. In this mode, it is the responsibility of the DSP to ensure that the left data is transmitted with the first LRCLK pulse after RESET, and that synchronism is maintained from that point forward. In Right-justified mode (16 bits shown), LRCLK is HIGH for the left channel, LOW for the right channel. Data is valid on the rising edge of BCLK. In normal operation, there are 64 bit clocks per frame (or 32 per half-frame). When the SPI wordlength control bits (bits 2 and 3 in control register 0) are set to 24 bits (0:0), the serial port will begin to accept data starting at the 8th bit clock pulse after the LRCLK transition. When the word length control bits are set to 20-bit mode, data is accepted starting at the 12th bit clock position. In 18-bit mode, data is accepted starting at the 14th bit clock position. In 16-bit mode, data is accepted starting at the 16th bit clock position. These delays are independent of the number of bit clocks per frame, and therefore other data formats are possible using the delay values described above. Note that the AD1955 is capable of a 32 X Fs BCLK frequency “packed mode” where the MSB is left-justified to an LRCLK transition, and the LSB is right-justified to the opposite LRCLK transition. LRCLK is HIGH for the left channel, and LOW for the right channel. Data is valid on the rising edge of BLCK. Packed mode can be used when the AD1955 is programmed in left or rightjustified mode. Serial Data Format in External Digital Filter mode In the external digital filter mode, the AD1955 will accept up to 24 bits serial, twos compliment, MSB first data from an external digital filter, an HDCD decoder or a general purpose DSP. If the external digital filter mode is selected by control register 0, bits 12 and 13, pins 2 to 5 are assigned as the word clock input (EF_WCLK, Pin 2) , bit clock input (EF_BCLK, Pin 3), left channel data input (EF_LDATA, Pin 4) and right channel data input (EF_RDATA, Pin 5) respectively to accept 8fs (48 kHz), 4fs (96kHz) or 2fs (196 kHz) over-sampled data. -6- Rev. PrF PRELIMINARY TECHNICAL DATA AD1955 Left and Right channel data are valid on rising edge of EF_BCLK. After LSB data is clocked in the AD1955, the falling edge of EF_WCLK signal loads all of data and starts conversion. The mode can be set to Left or Right-justified. A burst mode BCLK is also acceptable in Left-justified mode. LEF T C H A N N E L LR C LK R IG H T C H A N N E L B C LK SDATA MSB LSB MSB LSB I2 S M O D E - 1 6 T O 2 4 -B IT S P E R C H A N N E L LEF T C H A N N E L LR C LK R IG H T C H A N N E L B C LK SDATA MSB LSB MSB LSB R IG H T J U S T IF IE D M O D E - S E L E C T N U M B E R O F B IT S P E R C H A N N E L LR C LK B C LK SDATA MSB LSB MSB LSB D S P M O D E - 1 6 T O 2 4 -B IT S P E R C H A N N E L LEF T C H A N N E L LR C LK R IG H T C H A N N E L B C LK SDATA MSB LSB MSB L E F T J U S T IF IE D M O D E - 1 6 T O 2 4 -B IT S P E R C H A N N E L 1 /F s N O T E S : 1 . D S P M O D E D O E S N 'T I D E N T I F Y C H A N N E L 2 . L R C L K N O R M A L L Y O P E R A T E S A T F s E X C E P T F O R D S P M O D E W H IC H IS 2 x F s 3 . B C L K F R E Q U E N C Y IS N O R M A L L Y 6 4 x L R C L K B U T M A Y B E O P E R A T E D IN B U R S T M O D E Figure 1. Supported Serial Data Formats Figure 2. Serial Data Port Timing Rev. PrF -7- LSB PRELIMINARY TECHNICAL DATA AD1955 Serial Data Format in SACD mode In the SACD mode, the AD1955 supports both normal mode or phase modulation mode, which are selected by Control register 1, bit 6. If normal mode is selected, DSD_SCLK, DSD_LDATA and DSD_RDATA are used to interface with DSD decoder chip. In this mode, the DSD data is clocked in the AD1955 using rising edge of DSD_SCLK with 64fs rate, 2.8224MHz. DSD_PHASE pin should be connected LOW. If phase modulation mode is selected, DSD_PHASE pin is also used to interface with the DSD decoder. In this mode, a 64fs DSD_PHASE signal is used as a reference signal to receive the data from the decoder. The DSD data is clocked into the AD1955 with a 128fs DSD_SCLK. The AD1955 can operate as a master or slave device. In master mode, the AD1955 will output DSD_SCLK and DSD_PHASE (if in the phase modulation mode) to a DSD decoder and will support normal mode and Phase modulation mode 0. In slave mode, the AD1955 will accept DSD_SCLK and DSD_PHASE (if in the phase modulation mode) from a DSD decoder and supports all of the normal and phase modulation modes. When the SACD Port is not being used, the SACD pins (6, 7, 8 and 9) should be tied LOW. Master Clock The AD1955 must be set to the proper sample rate and master clock rate using Control Registers 0 and 1. The allowable master clock frequencies for each interpolation mode are as shown: Interpolation Mode 48kHz (INT8X) Mode 96kHz (INT4X) Mode 192kHz (INT2X) Mode Allowable master clock frequencies 256*Fs, 384*Fs, 512*Fs,768*Fs Nominal Input Sample Rate 32 kHz, 44.1 kHz, 48 KHz 128*Fs, 192*Fs, 256*Fs, 384*Fs 88.2 kHz, 96 KHz 64*Fs, 96*Fs, 128*Fs, 192*Fs 176.4 kHz, 192 KHz In the External Filter mode, the AD1955 accepts the following master clock frequenies depending on input sample rate: Input Data rate 8fs 4fs 2fs Allowable master clock frequencies 256*Fs, 384*fs, 512*Fs,768*Fs 128*Fs, 192*fs, 256*Fs, 384*Fs 64*Fs, 96*fs, 128*Fs, 192*Fs Nominal Input Sample Rate (to External Filter) 32 kHz, 44.1 kHz, 48 KHz 88.2 kHz, 96 KHz 176.4 kHz, 192 KHz In the SACD mode, the AD1955 accepts a 256fs, 512fs and 768fs Master Clock, where fs is nominally 44.1kHz. Zero Detection When the AD1955 detects that the audio input data is continuously zero during 1024 LRCLK periods in PCM mode or 8192 LRCLK periods in 8fs External Digital Filter mode, ZEROL (Pin 21 ) or ZEROR (Pin 20) is set to active. When the AD1955 is in SACD Mode, it will detect an SACD mute pattern. If the input bit-stream shows a mute pattern for about 22ms, the AD1955 will set ZEROL(Pin 21 ) or ZEROR(Pin 20) to active. The outputs can be set to active high or low using Control Register 1, bit 8. Reset/Power Down The AD1955 will be reset when the RESET pin is set low. The part may be powered down using bit 15, Control Register 0. -8- Rev. PrF PRELIMINARY TECHNICAL DATA AD1955 Audio Outputs The AD1955 audio outputs sink a current proportional to the input signal, superimposed on a steady state current. The current-tovoltage (I/V) converters used need to be able to supply this steady state current as well as the signal current or a resistor or current source can be used to a positive voltage to null this current to center the range of the I/V converters. Active I/V converters should be used, referenced to FILTR, and should hold the DAC outputs at this voltage level. Passive I/V conversion should not be used as the DAC performance will be seriously degraded. Serial Control Port The AD1955 has an SPI compatible control port to permit programming the internal control registers. The SPI control port is a three wire serial port. Its format is similar to the Motorola SPI format except that the input data word is 16-bits wide. The serial bit clock may be completely asynchronous to the sample rate of the DAC. The following figure shows the format of the SPI signal. Note that the CCLK may be continuous or a 16-clock burst. CLATCH CCLK CDATA D15 D14 D0 SPI REGISTER DEFINITIONS Table 1: DAC Control Register 0 Bit 13: 12 Bit 11: 10 Data format Output Format 00 : PCM 01 : Ext. DF 10 : SACD Slave 11 : SACD Master 00 : Stereo 01 : Not Allowed 10 : Mono Left 11 : Mono Right Bit 9:8 PCM Sample Rate 00 : 48kHz 01 : 96kHz 10 : 192kHz 11 : Rsvd Bit 7:6 De-Emphasis Curve Select 00 : None 01 : 44.1kHz 10 : 32kHz 11 : 48kHz Bit 5: 4 PCM/ EF Serial Data Format 00 : I2S 01 : Right-Just 10 : DSP 11 : LEFT-Just Bit 3: 2 PCM/ EF Serial Data Width 00 : 24Bits 01 : 20Bits 10 : 18Bits 11 : 16Bits Bit 1: 0 SPI Register Address 00 Bit 15 Bit 14 Power Down Mute 0 : Operation 0 : Not Muted 1 : Powered 1 : Muted Down Note: 0 = Default Setting Table 2: DAC Control Register 1 Bits 10:9 Bit 8 Bit 7 MCLK Zero Flag SACD Bit Rate Mode Polarity 0 : Active high 0 : 8fs / 64fs 00 : 256fs 1: Active low 1 : 4fs / 128fs 01 : 512fs 10 : 768fs 11 : 384fs Note: 0 = Default Setting Bit 6 SACD Mode 0 : Normal 1 : Phase Mode Table 3: DAC Volume Registers Bit 15: 2 Bit 1: 0 Volume SPI Register Address 14bit, Unsigned 10 = Left Volume 14bit, Unsigned 11 = Right Volume Note: Default = full volume Rev. PrF -9- Bit 5:4 SACD Phase Select 00 : Phase 0 01 : Phase 1 10 : Phase 2 11 : Phase 3 Bit 3 SACD Bit Inversion 0 : Normal 1 : Inverted Bit 2 SACD BCLK to MCLK Phase 0 : Rising edge 1 : Falling edge Bit 1: 0 SPI Register Address 01 PRELIMINARY TECHNICAL DATA AD1955 OUTLINE DIMENSIONS Dimensions shown in inches and (mm) 28-Lead Shrink Small Outline Package (SSOP) (RS-28) -10- Rev. PrF