MCNIX MX25R6435F Wide vcc range 64m-bit [x 1/x 2/x 4] cmos mxsmio Datasheet

PRELIMINARY
MX25R6435F
MX25R6435F
Wide Vcc Range, 64M-BIT [x 1/x 2/x 4]
CMOS MXSMIO® (SERIAL MULTI I/O)
FLASH MEMORY
Key Features
• Wide Range 1.7 to 3.6 volt for read, erase, and program operations
• Multi I/O Support - Single I/O, Dual I/O and Quad I/O
• Program Suspend/Resume & Erase Suspend/Resume
• Low Power Mode and High Performance Mode
P/N: PM2138
1
REV. 0.03, JAN. 30, 2015
PRELIMINARY
MX25R6435F
Contents
1. FEATURES............................................................................................................................................................... 4
2. GENERAL DESCRIPTION...................................................................................................................................... 6
Table 1. Additional Feature...........................................................................................................................7
3. PIN CONFIGURATIONS .......................................................................................................................................... 8
4. PIN DESCRIPTION................................................................................................................................................... 8
5. BLOCK DIAGRAM.................................................................................................................................................... 9
6. DATA PROTECTION............................................................................................................................................... 10
Table 2. Protected Area Sizes.................................................................................................................... 11
Table 3. 8K-bit Secured OTP Definition.....................................................................................................12
7. MEMORY ORGANIZATION.................................................................................................................................... 13
Table 4. Memory Organization...................................................................................................................13
8. DEVICE OPERATION............................................................................................................................................. 14
9. COMMAND DESCRIPTION.................................................................................................................................... 16
9-1.
9-2.
9-3.
9-4.
9-5.
9-6.
9-7.
9-8.
9-9.
9-10.
9-11.
9-12.
9-13.
9-14.
9-15.
9-16.
9-17.
9-18.
9-19.
9-20.
9-21.
9-22.
9-23.
9-24.
9-25.
9-26.
P/N: PM2138
Table 5. Command Set...............................................................................................................................16
Write Enable (WREN)............................................................................................................................... 19
Write Disable (WRDI)................................................................................................................................ 20
Read Identification (RDID)........................................................................................................................ 21
Read Electronic Signature (RES)............................................................................................................. 22
Read Electronic Manufacturer ID & Device ID (REMS)............................................................................ 23
ID Read..................................................................................................................................................... 24
Table 6. ID Definitions ...............................................................................................................................24
Read Status Register (RDSR).................................................................................................................. 25
Read Configuration Register (RDCR)....................................................................................................... 26
Write Status Register (WRSR).................................................................................................................. 31
Table 7. Protection Modes..........................................................................................................................32
Read Data Bytes (READ)......................................................................................................................... 35
Read Data Bytes at Higher Speed (FAST_READ)................................................................................... 36
Dual Read Mode (DREAD)....................................................................................................................... 37
2 x I/O Read Mode (2READ).................................................................................................................... 38
Quad Read Mode (QREAD)..................................................................................................................... 39
4 x I/O Read Mode (4READ).................................................................................................................... 40
Burst Read................................................................................................................................................ 42
Performance Enhance Mode.................................................................................................................... 43
Performance Enhance Mode Reset.......................................................................................................... 45
Sector Erase (SE)..................................................................................................................................... 46
Block Erase (BE32K)................................................................................................................................ 47
Block Erase (BE)...................................................................................................................................... 48
Chip Erase (CE)........................................................................................................................................ 49
Page Program (PP).................................................................................................................................. 50
4 x I/O Page Program (4PP)..................................................................................................................... 52
Deep Power-down (DP)............................................................................................................................ 53
Enter Secured OTP (ENSO)..................................................................................................................... 54
2
REV. 0.03, JAN. 30, 2015
PRELIMINARY
MX25R6435F
9-27. Exit Secured OTP (EXSO)........................................................................................................................ 54
9-28. Read Security Register (RDSCUR).......................................................................................................... 54
Table 8. Security Register Definition..........................................................................................................55
9-29. Write Security Register (WRSCUR).......................................................................................................... 55
9-30. Program Suspend and Erase Suspend.................................................................................................... 56
Table 9. Readable Area of Memory While a Program or Erase Operation is Suspended..........................56
Table 10. Acceptable Commands During Program/Erase Suspend after tPSL/tESL.................................56
Table 11. Acceptable Commands During Suspend (tPSL/tESL not required)............................................57
9-31. Program Resume and Erase Resume...................................................................................................... 58
9-32. No Operation (NOP)................................................................................................................................. 59
9-33. Software Reset (Reset-Enable (RSTEN) and Reset (RST)).................................................................... 59
9-34. High Voltage Operation............................................................................................................................. 60
9-35. Read SFDP Mode (RDSFDP)................................................................................................................... 61
Table 12. Signature and Parameter Identification Data Values .................................................................62
Table 13. Parameter Table (0): JEDEC Flash Parameter Tables...............................................................63
Table 14. Parameter Table (1): Macronix Flash Parameter Tables............................................................65
10. RESET.................................................................................................................................................................. 67
Table 15-1. Reset Timing-(Power On)........................................................................................................67
Table 15-2. Reset Timing-(Other Operation)..............................................................................................67
11. POWER-ON STATE.............................................................................................................................................. 68
12. ELECTRICAL SPECIFICATIONS......................................................................................................................... 69
Table 16. Absolute Maximum Ratings........................................................................................................69
Table 17. Capacitance................................................................................................................................69
Table 18. DC Characteristics......................................................................................................................71
Table 19. AC Characteristics .....................................................................................................................73
13. OPERATING CONDITIONS.................................................................................................................................. 77
Table 20. Power-Up Timing and VWI Threshold........................................................................................79
Table 21. Power-Up/Down Voltage and Timing..........................................................................................80
13-1. Initial Delivery State.................................................................................................................................. 80
14. ERASE AND PROGRAMMING PERFORMANCE............................................................................................... 81
15. LATCH-UP CHARACTERISTICS......................................................................................................................... 82
16. ORDERING INFORMATION................................................................................................................................. 83
17. PART NAME DESCRIPTION................................................................................................................................ 84
18. PACKAGE INFORMATION................................................................................................................................... 85
19. REVISION HISTORY ............................................................................................................................................ 88
P/N: PM2138
3
REV. 0.03, JAN. 30, 2015
PRELIMINARY
MX25R6435F
Wide Vcc Range 64M-BIT [x 1/x 2/x 4] CMOS MXSMIO® (SERIAL MULTI I/O)
FLASH MEMORY
1. FEATURES
GENERAL
• Supports Serial Peripheral Interface -- Mode 0 and Mode 3
• 67,108,864 x 1 bit structure or 33,554,432 x 2 bits (two I/O mode) structure or 16,777,216 x 4 bits (four I/O
mode) structure
• Equal Sectors with 4K byte each or Equal Blocks with 32K/64K byte each
- Any Block can be erased individually
• Single Power Supply Operation
- 1.7 to 3.6 volt for read, erase, and program operations
• Latch-up protected to 100mA from -1V to Vcc +1V
• Low Vcc write inhibit is from 1.1V to 1.5V
PERFORMANCE
• High Performance
- Fast read
- 1 I/O: 70MHz with 8 dummy cycles
- 2 I/O: 60MHz with 4 dummy cycles, equivalent to 120MHz
- 4 I/O: 60MHz with 2+4 dummy cycles, equivalent to 240MHz
- Fast program and erase time
- 8/16/32/64 byte Wrap-Around Burst Read Mode
• Low Power Consumption
• Typical 100,000 erase/program cycles
• 20 years data retention
SOFTWARE FEATURES
• Input Data Format
- 1-byte Command code
• Advanced Security Features
- Block lock protection
The BP0-BP3 status bit defines the size of the area to be software protection against program and erase
instructions
• Additional 8K bits secured OTP
- Features unique identifier.
- Factory locked identifiable and customer lockable
• Auto Erase and Auto Program Algorithm
- Automatically erases and verifies data at selected sector or block
- Automatically programs and verifies data at selected page by an internal algorithm that automatically times the
program pulse widths (Any page to be programed should have page in the erased state first)
• Status Register Feature
• Command Reset
• Program/Erase Suspend and Program/Erase Resume
• Electronic Identification
- JEDEC 1-byte manufacturer ID and 2-byte device ID
- RES command for 1-byte Device ID
- REMS command for 1-byte manufacturer ID and 1-byte device ID
• Support Serial Flash Discoverable Parameters (SFDP) mode
P/N: PM2138
4
REV. 0.03, JAN. 30, 2015
PRELIMINARY
MX25R6435F
HARDWARE FEATURES
• SCLK Input
- Serial clock input
• SI/SIO0
- Serial Data Input or Serial Data Input/Output for 2 x I/O read mode and 4 x I/O read mode
• SO/SIO1
- Serial Data Output or Serial Data Input/Output for 2 x I/O read mode and 4 x I/O read mode
• WP#/SIO2
- Hardware write protection or serial data Input/Output for 4 x I/O read mode
• RESET#/SIO3
- Hardware Reset pin or Serial input & Output for 4 x I/O read mode
• PACKAGE
- 8-pin SOP (200mil)
- 8-land WSON (6x5mm)
- 8-land USON (4x4mm)
- WLCSP
- All devices are RoHS Compliant and Halogen-free
P/N: PM2138
5
REV. 0.03, JAN. 30, 2015
PRELIMINARY
MX25R6435F
2. GENERAL DESCRIPTION
MX25R6435F is 64Mb bits serial Flash memory, which is configured as 8,388,608 x 8 internally. When it is in four I/
O mode, the structure becomes 16,777,216 bits x 4 or 33,554,432 bits x 2. MX25R6435F feature a serial peripheral
interface and software protocol allowing operation on a simple 3-wire bus while it is in single I/O mode. The three
bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial access to the
device is enabled by CS# input.
When it is in two I/O read mode, the SI pin and SO pin become SIO0 pin and SIO1 pin for address/dummy bits
input and data output. When it is in four I/O read mode, the SI pin, SO pin, WP# pin and Reset# pin become SIO0
pin, SIO1 pin, SIO2 pin and SIO3 pin for address/dummy bits input and data output.
The MX25R6435F MXSMIO® (Serial Multi I/O) provides sequential read operation on whole chip.
After program/erase command is issued, auto program/ erase algorithms which program/ erase and verify the
specified page or sector/block locations will be executed. Program command is executed on byte basis, or page (256
bytes) basis, or word basis for erase command is executed on sector (4K-byte) or block (32K-byte), or block (64K-byte),
or whole chip basis.
To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read
command can be issued to detect completion status of a program or erase operation via WIP bit.
Advanced security features enhance the protection and security functions, please see security features section for
more details.
The MX25R6435F utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after
100,000 program and erase cycles.
P/N: PM2138
6
REV. 0.03, JAN. 30, 2015
PRELIMINARY
MX25R6435F
Table 1. Additional Feature
Protection and Security
MX25R6435F
Flexible Block Protection (BP0-BP3)
V
8K-bit security OTP
V
Fast Read
Performance
I/O
Dummy Cycle
Frequency
P/N: PM2138
Low Power Mode
(Configuration Register-2 bit1= 0)
High Performance Mode
(Configuration Register-2 bit1= 1)
1 I/O
1I/2O
2 I/O
1I/4O
4 I/O
1 I/O
1I/2O
2 I/O
1I/4O
4 I/O
8
8
4
8
6
8
8
4
8
6
33MHz
8MHz
8MHz
8MHz
8MHz
70MHz
60MHz
60MHz
60MHz
60MHz
7
REV. 0.03, JAN. 30, 2015
PRELIMINARY
MX25R6435F
3. PIN CONFIGURATIONS
4. PIN DESCRIPTION
8-PIN SOP (200mil)
CS#
SO/SIO1
WP#/SIO2
GND
SYMBOL
CS#
1
2
3
4
8
7
6
5
DESCRIPTION
Chip Select
Serial Data Input (for 1 x I/O)/ Serial
SI/SIO0
Data Input & Output (for 4xI/O read
mode)
Serial Data Output (for 1 x I/O)/ Serial
SO/SIO1
Data Input & Output (for 4xI/O read
mode)
SCLK
Clock Input
Write Protection Active Low or Serial
WP#/SIO2 Data Input & Output (for 4xI/O read
mode)
Hardware Reset Pin Active low or
RESET#/SIO3 Serial Data Input & Output (for 4xI/O
read mode)
VCC
+ 1.7V ~ 3.6V Power Supply
GND
Ground
VCC
RESET#/SIO3
SCLK
SI/SIO0
8-LAND WSON (6x5mm), USON (4x4mm)
CS#
SO/SIO1
WP#/SIO2
GND
1
2
3
4
8
7
6
5
VCC
RESET#/SIO3
SCLK
SI/SIO0
Note:
1. RESET# and WP# with internal pull high circuit.
P/N: PM2138
8
REV. 0.03, JAN. 30, 2015
PRELIMINARY
MX25R6435F
5. BLOCK DIAGRAM
X-Decoder
Address
Generator
SI/SIO0
SO/SIO1
SIO2 *
SIO3 *
WP# *
HOLD# *
RESET# *
CS#
SCLK
Memory Array
Y-Decoder
Data
Register
Sense
Amplifier
SRAM
Buffer
Mode
Logic
State
Machine
HV
Generator
Clock Generator
Output
Buffer
* Depends on part number options.
P/N: PM2138
9
REV. 0.03, JAN. 30, 2015
PRELIMINARY
MX25R6435F
6. DATA PROTECTION
During power transition, there may be some false system level signals which result in inadvertent erasure or
programming. The device is designed to protect itself from these accidental write cycles.
The state machine will be reset as standby mode automatically during power up. In addition, the control register
architecture of the device constrains that the memory contents can only be changed after specific command
sequences have completed successfully.
In the following, there are several features to protect the system from the accidental write cycles during VCC powerup and power-down or from system noise.
•
Power-on reset: to avoid sudden power switch by system power supply transition, the power-on reset may
protect the Flash.
• Valid command length checking: The command length will be checked whether it is at byte base and completed
on byte boundary.
• Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before
issuing other commands to change data.
•
Deep Power Down Mode: By entering deep power down mode, the flash device is under protected from writing
all commands except toggling the CS#. For more detail please see "9-25. Deep Power-down (DP)".
•
Advanced Security Features: there are some protection and security features which protect content from
inadvertent write and hostile access.
I. Block lock protection
- The Software Protected Mode (SPM) use (BP3, BP2, BP1, BP0) bits to allow part of memory to be protected
as read only. The protected area definition is shown as "Table 2. Protected Area Sizes", the protected areas are
more flexible which may protect various area by setting value of BP0-BP3 bits.
- The Hardware Proteced Mode (HPM) use WP#/SIO2 to protect the (BP3, BP2, BP1, BP0) bits and Status
Register Write Protect (SRWD) bit. If the system goes into four I/O mode, the feature of HPM will be disabled.
P/N: PM2138
10
REV. 0.03, JAN. 30, 2015
PRELIMINARY
MX25R6435F
Table 2. Protected Area Sizes
Protected Area Sizes (TB bit = 0)
Status bit
BP3
BP2
BP1
BP0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
Protected Area Sizes (TB bit = 1)
Status bit
BP3
BP2
BP1
BP0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
Protect Level
64Mb
0 (none)
1 (1block, block 127th)
2 (2blocks, block 126th-127th)
3 (4blocks, block 124th-127th)
4 (8blocks, block 120th-127th)
5 (16blocks, block 112th-127th)
6 (32blocks, block 96th-127th)
7 (64blocks, block 64th-127th)
8 (128blocks, protect all)
9 (128blocks, protect all)
10 (128blocks, protect all)
11 (128blocks, protect all)
12 (128blocks, protect all)
13 (128blocks, protect all)
14 (128blocks, protect all)
15 (128blocks, protect all)
Protect Level
64Mb
0 (none)
1 (1block, block 0th)
2 (2blocks, block 0th-1st)
3 (4blocks, block 0th-3rd)
4 (8blocks, block 0th-7th)
5 (16blocks, block 0th-15th)
6 (32blocks, block 0th-31st)
7 (64blocks, block 0th-63rd)
8 (128blocks, protect all)
9 (128blocks, protect all)
10 (128blocks, protect all)
11 (128blocks, protect all)
12 (128blocks, protect all)
13 (128blocks, protect all)
14 (128blocks, protect all)
15 (128blocks, protect all)
Note: The device is ready to accept a Chip Erase instruction if, and only if, all Block Protect (BP3, BP2, BP1,
BP0) are 0.
P/N: PM2138
11
REV. 0.03, JAN. 30, 2015
PRELIMINARY
MX25R6435F
II. Additional 8K-bit secured OTP for unique identifier: to provide 8K-bit One-Time Program area for setting device
unique serial number - Which may be set by factory or system maker.
The 8K-bit secured OTP area is composed of two rows of 4K-bit. Customer could lock the first 4K-bit OTP area
and factory could lock the other.
- Security register bit 0 indicates whether the second 4K-bit is locked by factory or not.
- Customer may lock-down the customer lockable secured OTP by writing WRSCUR(write security register)
command to set customer lock-down bit1 as "1". Please refer to "Table 8. Security Register Definition" for
security register bit definition and "Table 3. 8K-bit Secured OTP Definition" for address range definition.
- To program 8K-bit secured OTP by entering secured OTP mode (with ENSO command), and going through
normal program procedure, and then exiting secured OTP mode by writing EXSO command.
Note: Once lock-down whatever by factory or customer, the corresponding secured area cannot be changed any
more. While in 8K-bit Secured OTP mode, array access is not allowed.
Table 3. 8K-bit Secured OTP Definition
Address range
Size
Customer Lock
Standard Factory Lock
xxx000~xxx1FF
4096-bit
Determined by customer
N/A
xxx200~xxx3FF
4096-bit
N/A
Determined by factory
P/N: PM2138
12
REV. 0.03, JAN. 30, 2015
PRELIMINARY
MX25R6435F
7. MEMORY ORGANIZATION
Table 4. Memory Organization
Block(64K-byte) Block(32K-byte) Sector (4K-byte)
126
252
251
125
250
7F8FFFh
2039
7F7000h
7F7FFFh
…
2032
7F0000h
7F0FFFh
2031
7EF000h
7EFFFFh
…
253
7F8000h
2024
7E8000h
7E8FFFh
2023
7E7000h
7E7FFFh
…
254
2040
2016
7E0000h
7E0FFFh
2015
7DF000h
7DFFFFh
2008
7D8000h
7D8FFFh
2007
7D7000h
7D7FFFh
7D0000h
7D0FFFh
02F000h
02FFFFh
40
028000h
028FFFh
39
027000h
027FFFh
…
127
7FFFFFh
…
255
Address Range
7FF000h
…
2047
∼
2000
1
2
1
0
0
…
…
020000h
020FFFh
31
01F000h
01FFFFh
…
3
32
24
018000h
018FFFh
23
017000h
017FFFh
…
4
16
010000h
010FFFh
15
00F000h
00FFFFh
8
008000h
008FFFh
7
007000h
007FFFh
000000h
000FFFh
…
2
47
…
5
0
P/N: PM2138
13
REV. 0.03, JAN. 30, 2015
PRELIMINARY
MX25R6435F
8. DEVICE OPERATION
1. Before a command is issued, status register should be checked to ensure device is ready for the intended
operation.
2. When incorrect command is inputted to this device, it enters standby mode and remains in standby mode until
next CS# falling edge. In standby mode, SO pin of the device is High-Z.
3. When correct command is inputted to this device, it enters active mode and remains in active mode until next
CS# rising edge.
4. Input data is latched on the rising edge of Serial Clock (SCLK) and data shifts out on the falling edge of SCLK.
The difference of Serial mode 0 and mode 3 is shown as "Figure 1. Serial Modes Supported".
5. For the following instructions: RDID, RDSR, RDCR, RDSCUR, READ, FAST_READ, DREAD, 2READ, 4READ,
QREAD, RDSFDP, RES, REMS, the shifted-in instruction sequence is followed by a data-out sequence. After
any bit of data being shifted out, the CS# can be high. For the following instructions: WREN, WRDI, WRSR, SE,
BE32K, BE, CE, PP, 4PP, DP, ENSO, EXSO, WRSCUR, SUSPEND, RESUME, NOP, RSTEN, RST, the CS#
must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.
6. While a Write Status Register, Program or Erase operation is in progress, access to the memory array is
neglected and will not affect the current operation of Write Status Register, Program, Erase.
Figure 1. Serial Modes Supported
CPOL
CPHA
shift in
(Serial mode 0)
0
0
SCLK
(Serial mode 3)
1
1
SCLK
SI
shift out
MSB
SO
MSB
Note:
CPOL indicates clock polarity of Serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not
transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which Serial mode is
supported.
P/N: PM2138
14
REV. 0.03, JAN. 30, 2015
PRELIMINARY
MX25R6435F
Figure 2. Serial Input Timing
tSHSL
CS#
tCHSL
tSLCH
tCHSH
tSHCH
SCLK
tDVCH
tCHCL
tCHDX
tCLCH
LSB
MSB
SI
High-Z
SO
Figure 3. Output Timing
CS#
tCH
SCLK
tCLQV
tCLQX
tCL
tCLQV
tCLQX
LSB
SO
SI
P/N: PM2138
tSHQZ
ADDR.LSB IN
15
REV. 0.03, JAN. 30, 2015
PRELIMINARY
MX25R6435F
9. COMMAND DESCRIPTION
Table 5. Command Set
Read/Write Array Commands
I/O
1
1
2
2
DREAD
(1I / 2O read
command)
3B (hex)
4
4
4READ
(4 x I/O read)
QREAD
(1I/4O read)
1st byte
03 (hex)
0B (hex)
2READ
(2 x I/O read
command)
BB (hex)
EB (hex)
6B (hex)
2nd byte
ADD1
ADD1
ADD1
ADD1
ADD1
ADD1
3rd byte
ADD2
ADD2
ADD2
ADD2
ADD2
ADD2
4th byte
ADD3
ADD3
ADD3
ADD3
ADD3
ADD3
Action
n bytes read
out until CS#
goes high
Dummy
n bytes read
out until CS#
goes high
Mode
1
4
Command
(byte)
PP
(page program)
1st byte
02 (hex)
Command
(byte)
READ
FAST READ
(normal read) (fast read data)
5th byte
4PP
(quad page
program)
38 (hex)
Dummy
Dummy
Dummy
Dummy
n bytes read
n bytes read Quad I/O read n bytes read
out by 2 x I/O
out by Dual
with 6 dummy out by Quad
output until
until CS# goes Output until
cycles
CS# goes high
high
CS# goes high
1
SE
(sector erase)
20 (hex)
1
1
BE 32K
(block erase
32KB)
52 (hex)
BE
(block erase
64KB)
D8 (hex)
1
1
CE
(chip erase)
RDSFDP
(Read SFDP)
60 or C7 (hex)
5A (hex)
2nd byte
ADD1
ADD1
ADD1
ADD1
ADD1
ADD1
3rd byte
ADD2
ADD2
ADD2
ADD2
ADD2
ADD2
4th byte
ADD3
ADD3
ADD3
ADD3
ADD3
ADD3
5th byte
to program the
selected page
Action
P/N: PM2138
quad input to
to erase the
to erase the
to erase the to erase whole
chip
program the selected sector selected 32KB selected block
selected page
block
16
Dummy
Read SFDP
mode
REV. 0.03, JAN. 30, 2015
PRELIMINARY
MX25R6435F
Register/Setting Commands
Command
(byte)
WREN
(write enable)
WRDI
(write disable)
RDSR
(read status
register)
RDCR (read
configuration
register)
WRSR
(write status
register)
1st byte
06 (hex)
04 (hex)
05 (hex)
15 (hex)
01 (hex)
2nd byte
Values
3rd byte
Values
4th byte
Values
PGM/ERS
Suspend
(Suspends
Program/Erase)
75 or B0 (hex)
5th byte
Action
Command
(byte)
1st byte
sets the (WEL) resets the (WEL)
write enable latch write enable latch
bit
bit
PGM/ERS
Resume
(Resumes
Program/Erase)
7A or 30 (hex)
to read out the
values of the
status register
DP
(Deep power
down)
SBL
(Set Burst Length)
B9 (hex)
C0 (hex)
2nd byte
to read out the
values of the
configuration
register -1 &
configuration
register -2
to write new
values of the
configuration/
status register
program/erase
operation is
interrupted
by suspend
command
Value
3rd byte
4th byte
5th byte
Action
P/N: PM2138
to continue
performing the
suspended
program/erase
sequence
enters deep
power down
mode
to set Burst length
17
REV. 0.03, JAN. 30, 2015
PRELIMINARY
MX25R6435F
ID/Reset Commands
Command
(byte)
1st byte
RDID
RES (read
(read identificelectronic ID)
ation)
9F (hex)
AB (hex)
REMS (read
RDSCUR
WRSCUR
electronic
ENSO (enter EXSO (exit
(read security (write security
manufacturer secured OTP) secured OTP)
register)
register)
& device ID)
90 (hex)
B1 (hex)
C1 (hex)
2B (hex)
2F (hex)
2nd byte
x
x
3rd byte
x
x
4th byte
x
ADD (Note 2)
5th byte
Action
COMMAND
(byte)
1st byte
outputs JEDEC to read out
output the
to enter the
to exit the
to read value to set the lockID: 1-byte
1-byte Device Manufacturer 8K-bit secured 8K-bit secured of security
down bit as
Manufacturer
ID
ID & Device ID OTP mode
OTP mode
register
"1" (once lockID & 2-byte
down, cannot
Device ID
be update)
NOP
RSTEN
(No Operation) (Reset Enable)
00 (hex)
66 (hex)
RST
(Reset
Memory)
99 (hex)
Release Read
Enhanced
FF (hex)
2nd byte
3rd byte
4th byte
5th byte
Action
All these
commands
FFh, 00h, AAh
or 55h will
escape the
performance
mode
(Note 3)
Note 1: ADD=00H will output the manufacturer ID first and ADD=01H will output device ID first.
Note 2: It is not recommended to adopt any other code not in the command definition table, which will potentially enter the hidden mode.
Note 3: Before executing RST command, RSTEN command must be executed. If there is any other command to interfere, the
reset operation will be disabled.
P/N: PM2138
18
REV. 0.03, JAN. 30, 2015
PRELIMINARY
MX25R6435F
9-1. Write Enable (WREN)
The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like PP, 4PP,
SE, BE32K, BE, CE, and WRSR, which are intended to change the device content WEL bit should be set every time
after the WREN instruction setting the WEL bit.
The sequence of issuing WREN instruction is: CS# goes low→sending WREN instruction code→ CS# goes high.
The SIO[3:1] are "don't care" .
Figure 4. Write Enable (WREN) Sequence
CS#
Mode 3
0
1
2
3
4
5
6
7
SCLK
Mode 0
Command
SI
SO
P/N: PM2138
06h
High-Z
19
REV. 0.03, JAN. 30, 2015
PRELIMINARY
MX25R6435F
9-2. Write Disable (WRDI)
The Write Disable (WRDI) instruction is to reset Write Enable Latch (WEL) bit.
The sequence of issuing WRDI instruction is: CS# goes low→sending WRDI instruction code→CS# goes high.
The SIO[3:1] are "don't care".
The WEL bit is reset by following situations:
- Power-up
- Reset# pin driven low
- Completion of Write Disable (WRDI) instruction
- Completion of Write Status Register (WRSR) instruction
- Completion of Page Program (PP) instruction
- Completion of Quad Page Program (4PP) instruction
- Completion of Sector Erase (SE) instruction
- Completion of Block Erase 32KB(BE32K) instruction
- Completion of Block Erase (BE) instruction
- Completion of Chip Erase (CE) instruction
- Program/Erase Suspend
- Completion of Softreset command
- Completion of Write Security Register (WRSCUR) command
Figure 5. Write Disable (WRDI) Sequence
CS#
Mode 3
0
1
2
3
4
5
6
7
SCLK
Mode 0
Command
SI
SO
P/N: PM2138
04h
High-Z
20
REV. 0.03, JAN. 30, 2015
PRELIMINARY
MX25R6435F
9-3. Read Identification (RDID)
The RDID instruction is for reading the manufacturer ID of 1-byte and followed by Device ID of 2-byte. The Macronix
Manufacturer ID and Device ID are listed as "Table 6. ID Definitions".
The sequence of issuing RDID instruction is: CS# goes low→ sending RDID instruction code→24-bits ID data out
on SO→ to end RDID operation can drive CS# to high at any time during data out.
While Program/Erase operation is in progress, it will not decode the RDID instruction, therefore there's no effect on
the cycle of program/erase operation which is currently in progress. When CS# goes high, the device is at standby
stage.
Figure 6. Read Identification (RDID) Sequence
CS#
Mode 3
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18
28 29 30 31
SCLK
Mode 0
Command
SI
9Fh
Manufacturer Identification
SO
High-Z
7
6
5
3
MSB
P/N: PM2138
2
1
Device Identification
0 15 14 13
3
2
1
0
MSB
21
REV. 0.03, JAN. 30, 2015
PRELIMINARY
MX25R6435F
9-4. Read Electronic Signature (RES)
RES instruction is for reading out the old style of 8-bit Electronic Signature, whose values are shown as "Table 6.
ID Definitions". This is not the same as RDID instruction. It is not recommended to use for new design. For new
design, please use RDID instruction.
The SIO[3:1] are "don't care".
The RES instruction is ended by CS# goes high after the ID been read out at least once. The ID outputs repeatedly
if continuously send the additional clock cycles on SCLK while CS# is at low.
Figure 7. Read Electronic Signature (RES) Sequence
CS#
Mode 3
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38
SCLK
Mode 0
Command
SI
ABh
tRES2
3 Dummy Bytes
23 22 21
3
2
1
0
MSB
SO
Electronic Signature Out
High-Z
7
6
5
4
3
2
1
0
MSB
P/N: PM2138
22
REV. 0.03, JAN. 30, 2015
PRELIMINARY
MX25R6435F
9-5. Read Electronic Manufacturer ID & Device ID (REMS)
The REMS instruction is an alternative to the Release from Power-down/Device ID instruction that provides both the
JEDEC assigned manufacturer ID and the specific device ID.
The REMS instruction is very similar to the Release from Power-down/Device ID instruction. The instruction is
initiated by driving the CS# pin low and shift the instruction code "90h" followed by two dummy bytes and one
bytes address (A7~A0). After which, the Manufacturer ID for Macronix (C2h) and the Device ID are shifted out
on the falling edge of SCLK with most significant bit (MSB) first. The Device ID values are listed in "Table 6. ID
Definitions". If the one-byte address is initially set to 01h, then the device ID will be read first and then followed by
the Manufacturer ID. The Manufacturer and Device IDs can be read continuously, alternating from one to the other.
The instruction is completed by driving CS# high.
Figure 8. Read Electronic Manufacturer & Device ID (REMS) Sequence
CS#
SCLK
Mode 3
0
1
2
Mode 0
3
4
5
6
7
8
Command
SI
9 10
2 Dummy Bytes
15 14 13
90h
3
2
1
0
High-Z
SO
CS#
28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
ADD (1)
SI
7
6
5
4
3
2
1
0
Manufacturer ID
SO
7
6
5
4
3
2
1
Device ID
0
7
6
5
4
3
2
MSB
MSB
1
0
7
MSB
Notes:
(1) ADD=00H will output the manufacturer's ID first and ADD=01H will output device ID first.
P/N: PM2138
23
REV. 0.03, JAN. 30, 2015
PRELIMINARY
MX25R6435F
9-6. ID Read
User can execute this ID Read instruction to identify the Device ID and Manufacturer ID. The sequence of issuing
RDID instruction is: CS# goes low→ sending RDID instruction code→24-bits ID data out on SO→ to end RDID
operation can drive CS# to high at any time during data out.
After the command cycle, the device will immediately output data on the falling edge of SCLK. The manufacturer ID,
memory type, and device ID data byte will be output continuously, until the CS# goes high.
While Program/Erase operation is in progress, it will not decode the RDID instruction, therefore there's no effect on
the cycle of program/erase operation which is currently in progress. When CS# goes high, the device is at standby
stage.
Table 6. ID Definitions
Command Type
Command
RDID
9Fh
RES
ABh
REMS
90h
P/N: PM2138
MX25R6435F
Manufactory ID
C2
Manufactory ID
C2
Memory type
28
Electronic ID
17
Device ID
17
24
Memory density
17
REV. 0.03, JAN. 30, 2015
PRELIMINARY
MX25R6435F
9-7. Read Status Register (RDSR)
The RDSR instruction is for reading Status Register Bits. The Read Status Register can be read at any time (even
in program/erase/write status register condition). It is recommended to check the Write in Progress (WIP) bit before
sending a new instruction when a program, erase, or write status register operation is in progress.
The sequence of issuing RDSR instruction is: CS# goes low→ sending RDSR instruction code→ Status Register data
out on SO.
The SIO[3:1] are "don't care".
Figure 9. Read Status Register (RDSR) Sequence
CS#
Mode 3
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
Mode 0
command
05h
SI
SO
High-Z
Status Register Out
7
6
5
4
2
1
0
7
6
5
4
3
2
1
0
7
MSB
MSB
P/N: PM2138
3
Status Register Out
25
REV. 0.03, JAN. 30, 2015
PRELIMINARY
MX25R6435F
9-8. Read Configuration Register (RDCR)
The RDCR instruction is for reading Configuration Register Bits. The Read Configuration Register can be read
at any time (even in program/erase/write configuration register condition). It is recommended to check the Write
in Progress (WIP) bit before sending a new instruction when a program, erase, or write configuration register
operation is in progress.
The sequence of issuing RDCR instruction is: CS# goes low→ sending RDCR instruction code→ Configuration
Register data out on SO.
The SIO[3:1] are don't care.
Figure 10. Read Configuration Register (RDCR) Sequence
CS#
Mode 3
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
Mode 0
command
15h
SI
SO
High-Z
Configuration register-1 Out
Configuration register-2 Out
7
7
6
5
4
2
1
0
6
5
4
3
2
1
0
7
MSB
MSB
P/N: PM2138
3
26
REV. 0.03, JAN. 30, 2015
PRELIMINARY
MX25R6435F
For user to check if Program/Erase operation is finished or not, RDSR instruction flow are shown as follows:
Figure 11. Program/Erase flow with read array data
start
WREN command
RDSR command*
WEL=1?
No
Yes
Program/erase command
Write program data/address
(Write erase address)
RDSR command
WIP=0?
No
Yes
RDSR command
Read WEL=0, BP[3:0], QE,
and SRWD data
Read array data
(same address of PGM/ERS)
Verify OK?
No
Yes
Program/erase successfully
Program/erase
another block?
Program/erase fail
Yes
* Issue RDSR to check BP[3:0].
No
Program/erase completed
P/N: PM2138
27
REV. 0.03, JAN. 30, 2015
PRELIMINARY
MX25R6435F
Figure 12. Program/Erase flow without read array data (read P_FAIL/E_FAIL flag)
start
WREN command
RDSR command*
WEL=1?
No
Yes
Program/erase command
Write program data/address
(Write erase address)
RDSR command
WIP=0?
No
Yes
RDSR command
Read WEL=0, BP[3:0], QE,
and SRWD data
RDSCUR command
Yes
P_FAIL/E_FAIL =1 ?
No
Program/erase fail
Program/erase successfully
Program/erase
another block?
No
Yes
* Issue RDSR to check BP[3:0].
Program/erase completed
P/N: PM2138
28
REV. 0.03, JAN. 30, 2015
PRELIMINARY
MX25R6435F
Status Register
The definition of the status register bits is as below:
WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase/write
status register progress. When WIP bit sets to 1, which means the device is busy in program/erase/write status
register progress. When WIP bit sets to 0, which means the device is not in progress of program/erase/write status
register cycle.
WEL bit. The Write Enable Latch (WEL) bit, a volatile bit, indicates whether the device is set to internal write enable
latch. When WEL bit sets to 1, which means the internal write enable latch is set, the device can accept program/
erase/write status register instruction. When WEL bit sets to 0, which means no internal write enable latch; the
device will not accept program/erase/write status register instruction. The program/erase command will be ignored
if it is applied to a protected memory area. To ensure both WIP bit & WEL bit are both set to 0 and available for next
program/erase/operations, WIP bit needs to be confirm to be 0 before polling WEL bit. After WIP bit confirmed, WEL
bit needs to be confirmed as 0.
BP3, BP2, BP1, BP0 bits. The Block Protect (BP3, BP2, BP1, BP0) bits, non-volatile bits, indicate the protected area (as
defined in "Table 2. Protected Area Sizes") of the device to against the program/erase instruction without hardware
protection mode being set. To write the Block Protect (BP3, BP2, BP1, BP0) bits requires the Write Status Register (WRSR)
instruction to be executed. Those bits define the protected area of the memory to against Page Program (PP), Sector
Erase (SE), Block Erase 32KB(BE32K), Block Erase (BE) and Chip Erase (CE) instructions (only if Block Protect bits
(BP3:BP0) set to 0, the CE instruction can be executed). The BP3, BP2, BP1, BP0 bits are "0" as default, which is unprotected.
QE bit. The Quad Enable (QE) bit, non-volatile bit, while it is "0" (factory default), it performs non-Quad and WP#,
RESET# are enable. While QE is "1", it performs Quad I/O mode and WP#, RESET# are disabled. In the other
word, if the system goes into four I/O mode (QE=1), the feature of HPM and RESET will be disabled.
SRWD bit. The Status Register Write Disable (SRWD) bit, non-volatile bit, is operated together with Write Protection
(WP#/SIO2) pin for providing hardware protection mode. The hardware protection mode requires SRWD sets to 1 and
WP#/SIO2 pin signal is low stage. In the hardware protection mode, the Write Status Register (WRSR) instruction is
no longer accepted for execution and the SRWD bit and Block Protect bits (BP3, BP2, BP1, BP0) are read only. The
SRWD bit defaults to be "0".
Status Register
bit7
SRWD (status
register write
protect)
bit6
QE
(Quad
Enable)
bit5
BP3
(level of
protected
block)
bit4
BP2
(level of
protected
block)
1=Quad
1=status
Enable
register write
(note 1)
(note 1)
0=not Quad
disable
Enable
Non-volatile Non-volatile Non-volatile Non-volatile
bit
bit
bit
bit
Note 1: see the "Table 2. Protected Area Sizes".
P/N: PM2138
bit3
BP1
(level of
protected
block)
bit2
BP0
(level of
protected
block)
(note 1)
(note 1)
Non-volatile
bit
Non-volatile
bit
29
bit1
bit0
WEL
WIP
(write enable
(write in
latch)
progress bit)
1=write
1=write
enable
operation
0=not write 0=not in write
enable
operation
volatile bit
volatile bit
REV. 0.03, JAN. 30, 2015
PRELIMINARY
MX25R6435F
Configuration Register
The Configuration Register is able to change the default status of Flash memory. Flash memory will be configured
after the CR bit is set.
TB bit
The Top/Bottom (TB) bit is a non-volatile OTP bit. The Top/Bottom (TB) bit is used to configure the Block Protect
area by BP bit (BP3, BP2, BP1, BP0), starting from TOP or Bottom of the memory array. The TB bit is defaulted as “0”,
which means Top area protect. When it is set as “1”, the protect area will change to Bottom area of the memory
device. To write the TB bit requires the Write Status Register (WRSR) instruction to be executed.
L/H switch bit
The Low Power / High Performance bit is a volatile bit. User can change the value of L/H switch bit to keep Low
Power mode or High Performance mode. The default value of the L/H switch bit is "0" after power on or reset,
which means that the device is at low power mode.
Configuration Register - 1
bit7
bit6
Reserved
Reserved
Reserved
Reserved
x
x
x
x
x
x
x
x
bit3
TB
(top/bottom
selected)
0=Top area
protect
1=Bottom
area protect
(Default=0)
OTP
bit5
Reserved
bit4
Reserved
bit3
Reserved
bit2
Reserved
Configuration Register - 2
bit7
bit6
Reserved
Reserved
bit5
bit4
bit2
bit1
bit0
Reserved
Reserved
Reserved
x
x
x
x
x
x
bit1
L/H Switch
0 = Low
power mode
(default)
1 = High
performance
mode
Volatile bit
bit0
Reserved
x
x
x
x
x
x
x
x
x
x
x
x
P/N: PM2138
30
x
x
REV. 0.03, JAN. 30, 2015
PRELIMINARY
MX25R6435F
9-9. Write Status Register (WRSR)
The WRSR instruction is for changing the values of Status Register Bits and Configuration Register Bits. Before
sending WRSR instruction, the Write Enable (WREN) instruction must be decoded and executed to set the Write
Enable Latch (WEL) bit in advance. The WRSR instruction can change the value of Block Protect (BP3, BP2,
BP1, BP0) bits to define the protected area of memory (as shown in "Table 2. Protected Area Sizes"). The WRSR
also can set or reset the Quad enable (QE) bit and set or reset the Status Register Write Disable (SRWD) bit in
accordance with Write Protection (WP#/SIO2) pin signal, but has no effect on bit1(WEL) and bit0 (WIP) of the status
register. The WRSR instruction cannot be executed once the Hardware Protected Mode (HPM) is entered.
The sequence of issuing WRSR instruction is: CS# goes low→ sending WRSR instruction code→ Status Register
data on SI→CS# goes high.
The CS# must go high exactly at the 8 bits, 16 bits or 24 bits data boundary; otherwise, the instruction will be
rejected and not executed. The self-timed Write Status Register cycle time (tW) is initiated as soon as Chip Select
(CS#) goes high. The Write in Progress (WIP) bit still can be checked during the Write Status Register cycle is in
progress. The WIP sets 1 during the tW timing, and sets 0 when Write Status Register Cycle is completed, and the
Write Enable Latch (WEL) bit is reset. Please note that there is another parameter, "Write Status Register cycle time
for Mode Changing Switching (tWMS)", which is only for the self-timed of Mode Switching (changing L/H switch bit).
For more detail please check "Table 19. AC Characteristics".
Figure 13. Write Status Register (WRSR) Sequence
CS#
Mode 3
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SCLK
Mode 0
SI
SO
P/N: PM2138
command
01h
High-Z
Configuration
Register -1 In
Status
Register In
7
6
5
4
3
2
1
0 15 14 13 12 11 10 9
Configuration
Register -2 In
8 23 22 21 20 19 18 17 16
MSB
31
REV. 0.03, JAN. 30, 2015
PRELIMINARY
MX25R6435F
Software Protected Mode (SPM):
- When SRWD bit=0, no matter WP#/SIO2 is low or high, the WREN instruction may set the WEL bit and can
change the values of SRWD, BP3, BP2, BP1, BP0. The protected area, which is defined by BP3, BP2, BP1,
BP0, is at software protected mode (SPM).
- When SRWD bit=1 and WP#/SIO2 is high, the WREN instruction may set the WEL bit can change the values
of SRWD, BP3, BP2, BP1, BP0. The protected area, which is defined by BP3, BP2, BP1, BP0, is at software
protected mode (SPM)
Note:
If SRWD bit=1 but WP#/SIO2 is low, it is impossible to write the Status Register even if the WEL bit has previously
been set. It is rejected to write the Status Register and not be executed.
Hardware Protected Mode (HPM):
- When SRWD bit=1, and then WP#/SIO2 is low (or WP#/SIO2 is low before SRWD bit=1), it enters the hardware
protected mode (HPM). The data of the protected area is protected by software protected mode by BP3, BP2,
BP1, BP0 and hardware protected mode by the WP#/SIO2 to against data modification.
Note:
To exit the hardware protected mode requires WP#/SIO2 driving high once the hardware protected mode is entered.
If the WP#/SIO2 pin is permanently connected to high, the hardware protected mode can never be entered; only can
use software protected mode via BP3, BP2, BP1, BP0.
Table 7. Protection Modes
Mode
Software protection
mode (SPM)
Hardware protection
mode (HPM)
Status register condition
WP# and SRWD bit status
Memory
Status register can be written
in (WEL bit is set to "1") and
the SRWD, BP0-BP3
bits can be changed
WP#=1 and SRWD bit=0, or
WP#=0 and SRWD bit=0, or
WP#=1 and SRWD=1
The protected area
cannot
be program or erase.
The SRWD, BP0-BP3 of
status register bits cannot be
changed
WP#=0, SRWD bit=1
The protected area
cannot
be program or erase.
Note:
1. As defined by the values in the Block Protect (BP3, BP2, BP1, BP0) bits of the Status Register, as shown in "Table 2. Protected Area Sizes".
P/N: PM2138
32
REV. 0.03, JAN. 30, 2015
PRELIMINARY
MX25R6435F
Figure 14. WRSR flow
start
WREN command
RDSR command
WEL=1?
No
Yes
WRSR command
Write status register
data
RDSR command
WIP=0?
No
Yes
RDSR command
Read WEL=0, BP[3:0], QE,
and SRWD data
Verify OK?
No
Yes
WRSR successfully
P/N: PM2138
WRSR fail
33
REV. 0.03, JAN. 30, 2015
PRELIMINARY
MX25R6435F
Figure 15. WP# Setup Timing and Hold Timing during WRSR when SRWD=1
WP#
tSHWL
tWHSL
CS#
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCLK
01h
SI
SO
High-Z
Note: WP# must be kept high until the embedded operation finish.
P/N: PM2138
34
REV. 0.03, JAN. 30, 2015
PRELIMINARY
MX25R6435F
9-10. Read Data Bytes (READ)
The read instruction is for reading data out. The address is latched on rising edge of SCLK, and data shifts out on
the falling edge of SCLK at a maximum frequency fR. The first address byte can be at any location. The address
is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can
be read out at a single READ instruction. The address counter rolls over to 0 when the highest address has been
reached.
The sequence of issuing READ instruction is: CS# goes low→sending READ instruction code→ 3-byte address on
SI→ data out on SO→to end READ operation can use CS# to high at any time during data out.
Figure 16. Read Data Bytes (READ) Sequence
CS#
Mode 3
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
Mode 0
SI
command
03h
24-Bit Address
23 22 21
3
2
1
0
MSB
SO
Data Out 1
High-Z
7
6
5
4
3
2
Data Out 2
1
0
7
MSB
P/N: PM2138
35
REV. 0.03, JAN. 30, 2015
PRELIMINARY
MX25R6435F
9-11. Read Data Bytes at Higher Speed (FAST_READ)
The FAST_READ instruction is for quickly reading data out. The address is latched on rising edge of SCLK, and
data of each bit shifts out on the falling edge of SCLK at a maximum frequency fC. The first address byte can be at
any location. The address is automatically increased to the next higher address after each byte data is shifted out,
so the whole memory can be read out at a single FAST_READ instruction. The address counter rolls over to 0 when
the highest address has been reached.
The sequence of issuing FAST_READ instruction is: CS# goes low→ sending FAST_READ instruction code→
3-byte address on SI→1-dummy byte (default) address on SI→ data out on SO→ to end FAST_READ operation
can use CS# to high at any time during data out.
While Program/Erase/Write Status Register cycle is in progress, FAST_READ instruction is rejected without any
impact on the Program/Erase/Write Status Register current cycle.
Figure 17. Read at Higher Speed (FAST_READ) Sequence
CS#
SCLK
Mode 3
0
1
2
Mode 0
3
5
6
7
8
9 10
Command
SI
SO
4
28 29 30 31
24-Bit Address
23 22 21
0Bh
3
2
1
0
High-Z
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
Dummy Cycle
SI
7
6
5
4
3
2
1
0
DATA OUT 2
DATA OUT 1
SO
7
6
5
4
2
1
0
7
MSB
MSB
P/N: PM2138
3
36
6
5
4
3
2
1
0
7
MSB
REV. 0.03, JAN. 30, 2015
PRELIMINARY
MX25R6435F
9-12. Dual Read Mode (DREAD)
The DREAD instruction enable double throughput of Serial Flash in read mode. The address is latched on rising
edge of SCLK, and data of every two bits (interleave on 2 I/O pins) shift out on the falling edge of SCLK at a
maximum frequency fT. The first address byte can be at any location. The address is automatically increased
to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single
DREAD instruction. The address counter rolls over to 0 when the highest address has been reached. Once
writing DREAD instruction, the following data out will perform as 2-bit instead of previous 1-bit.
The sequence of issuing DREAD instruction is: CS# goes low → sending DREAD instruction → 3-byte address
on SI → 8-bit dummy cycle → data out interleave on SO1 & SO0 → to end DREAD operation can use CS# to
high at any time during data out.
While Program/Erase/Write Status Register cycle is in progress, DREAD instruction is rejected without any
impact on the Program/Erase/Write Status Register current cycle.
Figure 18. Dual Read Mode Sequence (Command 3B)
CS#
0
1
2
3
4
5
6
7
8
…
Command
SI/SIO0
SO/SIO1
P/N: PM2138
30 31 32
9
SCLK
3B
…
24 ADD Cycle
A23 A22
…
39 40 41 42 43 44 45
A1 A0
High Impedance
8 dummy
cycle
Data Out
1
Data Out
2
D6 D4 D2 D0 D6 D4
D7 D5 D3 D1 D7 D5
37
REV. 0.03, JAN. 30, 2015
PRELIMINARY
MX25R6435F
9-13. 2 x I/O Read Mode (2READ)
The 2READ instruction enables Double Transfer Rate of Serial Flash in read mode. The address is latched on
rising edge of SCLK, and data of every two bits (interleave on 2 I/O pins) shift out on the falling edge of SCLK at
a maximum frequency fT. The first address byte can be at any location. The address is automatically increased
to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single
2READ instruction. The address counter rolls over to 0 when the highest address has been reached. Once
writing 2READ instruction, the following address/dummy/data out will perform as 2-bit instead of previous 1-bit.
The sequence of issuing 2READ instruction is: CS# goes low→ sending 2READ instruction→ 24-bit address
interleave on SIO1 & SIO0→ 4-bit dummy cycle on SIO1 & SIO0→ data out interleave on SIO1 & SIO0→ to end
2READ operation can use CS# to high at any time during data out.
While Program/Erase/Write Status Register cycle is in progress, 2READ instruction is rejected without any
impact on the Program/Erase/Write Status Register current cycle.
Figure 19. 2 x I/O Read Mode Sequence (Command BB)
CS#
0
1
2
3
4
5
6
7
8
SCLK
…
Command
SI/SIO0
SO/SIO1
18 19 20 21 22 23 24 25 26 27 28 29
9
BB(hex)
High Impedance
12 ADD Cycle
4 dummy
cycle
Data Out
1
Data Out
2
A22 A20
…
A2 A0 P2 P0
D6 D4 D2 D0 D6 D4
A23 A21
…
A3 A1 P3 P1
D7 D5 D3 D1 D7 D5
Note: SI/SIO0 or SO/SIO1 should be kept "0h" or "Fh" in the first two dummy cycles. In other words, P2=P0 or
P3=P1 is necessary.
P/N: PM2138
38
REV. 0.03, JAN. 30, 2015
PRELIMINARY
MX25R6435F
9-14. Quad Read Mode (QREAD)
The QREAD instruction enable quad throughput of Serial Flash in read mode. The address is latched on rising
edge of SCLK, and data of every four bits (interleave on 4 I/O pins) shift out on the falling edge of SCLK at a
maximum frequency fQ. The first address byte can be at any location. The address is automatically increased
to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single
QREAD instruction. The address counter rolls over to 0 when the highest address has been reached. Once
writing QREAD instruction, the following data out will perform as 4-bit instead of previous 1-bit.
The sequence of issuing QREAD instruction is: CS# goes low→ sending QREAD instruction → 3-byte address
on SI → 8-bit dummy cycle → data out interleave on SIO3, SIO2, SIO1 & SIO0→ to end QREAD operation can
use CS# to high at any time during data out.
While Program/Erase/Write Status Register cycle is in progress, QREAD instruction is rejected without any
impact on the Program/Erase/Write Status Register current cycle.
Figure 20. Quad Read Mode Sequence (Command 6B)
CS#
0
1
2
3
4
5
6
7
8
SCLK
…
Command
SI/SIO0
SO/SIO1
SIO2
SIO3
P/N: PM2138
29 30 31 32 33
9
6B
…
24 ADD Cycles
A23 A22
…
High Impedance
38 39 40 41 42
A2 A1 A0
8 dummy cycles
Data Data
Out 1 Out 2
Data
Out 3
D4 D0 D4 D0 D4
D5 D1 D5 D1 D5
High Impedance
D6 D2 D6 D2 D6
High Impedance
D7 D3 D7 D3 D7
39
REV. 0.03, JAN. 30, 2015
PRELIMINARY
MX25R6435F
9-15. 4 x I/O Read Mode (4READ)
The 4READ instruction enable quad throughput of Serial Flash in read mode. A Quad Enable (QE) bit of status
Register must be set to "1" before sending the 4READ instruction. The address is latched on rising edge of SCLK,
and data of every four bits (interleave on 4 I/O pins) shift out on the falling edge of SCLK at a maximum frequency
fQ. The first address byte can be at any location. The address is automatically increased to the next higher address
after each byte data is shifted out, so the whole memory can be read out at a single 4READ instruction. The address
counter rolls over to 0 when the highest address has been reached. Once writing 4READ instruction, the following
address/dummy/data out will perform as 4-bit instead of previous 1-bit.
The sequence of issuing 4READ instruction is: CS# goes low→ sending 4READ instruction→ 24-bit address
interleave on SIO3, SIO2, SIO1 & SIO0→2+4 dummy cycles→data out interleave on SIO3, SIO2, SIO1 & SIO0→ to
end 4READ operation can use CS# to high at any time during data out.
Another sequence of issuing 4READ instruction especially useful in random access is : CS# goes low→sending
4READ instruction→3-bytes address interleave on SIO3, SIO2, SIO1 & SIO0 →performance enhance toggling
bit P[7:0]→ 4 dummy cycles →data out still CS# goes high → CS# goes low (reduce 4 Read instruction) →24-bit
random access address.
In the performance-enhancing mode, P[7:4] must be toggling with P[3:0] ; likewise P[7:0]=A5h, 5Ah, F0h or 0Fh
can make this mode continue and reduce the next 4READ instruction. Once P[7:4] is no longer toggling with P[3:0];
likewise P[7:0]=FFh,00h,AAh or 55h and afterwards CS# is raised and then lowered, the system then will escape
from performance enhance mode and return to normal operation.
While Program/Erase/Write Status Register cycle is in progress, 4READ instruction is rejected without any impact
on the Program/Erase/Write Status Register current cycle.
For the speed of 4READ, please check "Table 1. Additional Feature". Please note that under following conditon in
low power mode, the 4READ oepration can acheive 16MHz:
The 4READ oepation can not cross 4Mb bank boundary as the table below. In other words, to read another bank in
16MHz, request to input a new 4READ command.
BANK (4M bit)
15
14
13
12
11
10
9
8
P/N: PM2138
Address Range
780000h-7FFFFFh
700000h-77FFFFh
680000h-6FFFFFh
600000h-67FFFFh
580000h-5FFFFFh
500000h-57FFFFh
480000h-4FFFFFh
400000h-47FFFFh
BANK (4M bit)
7
6
5
4
3
2
1
0
40
Address Range
380000h-3FFFFFh
300000h-37FFFFh
280000h-2FFFFFh
200000h-27FFFFh
180000h-1FFFFFh
100000h-17FFFFh
080000h-0FFFFFh
000000h-07FFFFh
REV. 0.03, JAN. 30, 2015
PRELIMINARY
MX25R6435F
Figure 21. 4 x I/O Read Mode Sequence
CS#
Mode 3
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
Mode 3
SCLK
Mode 0
Command
EBh
6 ADD Cycles
Performance
enhance
indicator (Note)
4 Dummy
Cycles
Data
Out 1
Data
Out 2
Data
Out 3
A20 A16 A12 A8 A4 A0 P4 P0
D4 D0 D4 D0 D4 D0
SIO1
A21 A17 A13 A9 A5 A1 P5 P1
D5 D1 D5 D1 D5 D1
SIO2
A22 A18 A14 A10 A6 A2 P6 P2
D6 D2 D6 D2 D6 D2
SIO3
A23 A19 A15 A11 A7 A3 P7 P3
D7 D3 D7 D3 D7 D3
SIO0
Mode 0
Note:
1. Hi-impedance is inhibited for the two clock cycles.
2. P7≠P3, P6≠P2, P5≠P1 & P4≠P0 (Toggling) is inhibited.
P/N: PM2138
41
REV. 0.03, JAN. 30, 2015
PRELIMINARY
MX25R6435F
9-16. Burst Read
This device supports Burst Read.
To set the Burst length, following command operation is required
Issuing command: “C0h” in the first Byte (8-clocks), following 4 clocks defining wrap around enable with “0h” and
disable with“1h”.
Next 4 clocks is to define wrap around depth. Definition as following table:
Data
00h
01h
02h
03h
1xh
Wrap Around
Yes
Yes
Yes
Yes
No
Wrap Depth
8-byte
16-byte
32-byte
64-byte
X
The wrap around unit is defined within the 256Byte page, with random initial address. It’s defined as “wrap-around
mode disable” for the default state of the device. To exit wrap around, it is required to issue another “C0” command
in which data=‘1xh”. Otherwise, wrap around status will be retained until power down or reset command. To change
wrap around depth, it is requried to issue another “C0” command in which data=“0xh”. “EBh” supports wrap around
feature after wrap around enable. The device id default without Burst read.
Figure 22. Burst Read
CS#
Mode 3
0
1
2
3
4
5
6
7
8
9
D7
D6
10
11
12
13
14
15
SCLK
Mode 0
SIO
P/N: PM2138
C0h
42
D5
D4
D3
D2
D1
D0
REV. 0.03, JAN. 30, 2015
PRELIMINARY
MX25R6435F
9-17. Performance Enhance Mode
The device could waive the command cycle bits if the two cycle bits after address cycle toggles.
“EBh” command supports enhance mode. The performance enhance mode is not supported in dual I/O mode.
After entering enhance mode, following CS# go high, the device will stay in the read mode and treat CS# go low of
the first clock as address instead of command cycle.
To exit enhance mode, a new fast read command whose first two dummy cycles is not toggle then exit. Or issue
”FFh” command to exit enhance mode.
P/N: PM2138
43
REV. 0.03, JAN. 30, 2015
PRELIMINARY
MX25R6435F
Figure 23. 4 x I/O Read enhance performance Mode Sequence
CS#
Mode 3
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22
n
SCLK
Mode 0
Data
Out 2
Data
Out n
A20 A16 A12 A8 A4 A0 P4 P0
D4 D0 D4 D0
D4 D0
SIO1
A21 A17 A13 A9 A5 A1 P5 P1
D5 D1 D5 D1
D5 D1
SIO2
A22 A18 A14 A10 A6 A2 P6 P2
D6 D2 D6 D2
D6 D2
SIO3
A23 A19 A15 A11 A7 A3 P7 P3
D7 D3 D7 D3
D7 D3
Command
EBh
SIO0
6 ADD Cycles
Performance
enhance
indicator (Note)
4 Dummy
Cycles
Data
Out 1
CS#
n+1
...........
n+7 ...... n+9
........... n+13
...........
Mode 3
SCLK
6 ADD Cycles
Performance
enhance
indicator (Note)
4 Dummy
Cycles
Data
Out 1
Data
Out 2
Data
Out n
SIO0
A20 A16 A12 A8 A4 A0 P4 P0
D4 D0 D4 D0
D4 D0
SIO1
A21 A17 A13 A9 A5 A1 P5 P1
D5 D1 D5 D1
D5 D1
SIO2
A22 A18 A14 A10 A6 A2 P6 P2
D6 D2 D6 D2
D6 D2
SIO3
A23 A19 A15 A11 A7 A3 P7 P3
D7 D3 D7 D3
D7 D3
Mode 0
Note:
1. Performance enhance mode, if P7≠P3 & P6≠P2 & P5≠P1 & P4≠P0 (Toggling), ex: A5, 5A, 0F, if not using
performance enhance recommend to keep 1 or 0 in performance enhance indicator.
2. Reset the performance enhance mode, if P7=P3 or P6=P2 or P5=P1 or P4=P0, ex: AA, 00, FF
P/N: PM2138
44
REV. 0.03, JAN. 30, 2015
PRELIMINARY
MX25R6435F
9-18. Performance Enhance Mode Reset
To conduct the Performance Enhance Mode Reset operation, FFh command code, 8 clocks, should be issued in 1I/
O sequence.
If the system controller is being Reset during operation, the flash device will return to the standard 1 I/O operation.
The SIO[3:1] are "don't care".
Figure 24. Performance Enhance Mode Reset for Fast Read Quad I/O
Mode Bit Reset
for Quad I/O
CS#
Mode 3
SCLK
P/N: PM2138
０ 1
2
3
4
5
6
7
Mode ０
Mode 3
Mode ０
SIO0
FFh
SIO1
Don’t Care
SIO2
Don’t Care
SIO3
Don’t Care
45
REV. 0.03, JAN. 30, 2015
PRELIMINARY
MX25R6435F
9-19. Sector Erase (SE)
The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". The instruction is used
for any 4K-byte sector. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit
before sending the Sector Erase (SE). Any address of the sector (Please refer to "Table 4. Memory Organization")
is a valid address for Sector Erase (SE) instruction. The CS# must go high exactly at the byte boundary (the latest
eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed.
Address bits [Am-A12] (Am is the most significant address) select the sector address.
The sequence of issuing SE instruction is: CS# goes low→ sending SE instruction code→ 3-byte address on SI→
CS# goes high.
The SIO[3:1] are "don't care".
The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked during the Sector Erase cycle is in progress. The WIP sets 1 during the
tSE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If
the sector is protected by BP3, BP2, BP1, BP0 bits, the Sector Erase (SE) instruction will not be executed on the
sector.
Figure 25. Sector Erase (SE) Sequence
CS#
Mode 3
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
Mode 0
SI
24-Bit Address
Command
23 22
20h
2
1
0
MSB
P/N: PM2138
46
REV. 0.03, JAN. 30, 2015
PRELIMINARY
MX25R6435F
9-20. Block Erase (BE32K)
The Block Erase (BE32K) instruction is for erasing the data of the chosen block to be "1". The instruction is used
for 32K-byte block erase operation. A Write Enable (WREN) instruction must be executed to set the Write Enable
Latch (WEL) bit before sending the Block Erase (BE32K). Any address of the block (see "Table 4. Memory
Organization") is a valid address for Block Erase (BE32K) instruction. The CS# must go high exactly at the byte
boundary (the least significant bit of address byte has been latched-in); otherwise, the instruction will be rejected
and not executed.
The sequence of issuing BE32K instruction is: CS# goes low → sending BE32K instruction code → 3-byte
address on SI → CS# goes high.
The SIO[3:1] are don't care.
The self-timed Block Erase Cycle time (tBE32K) is initiated as soon as Chip Select (CS#) goes high. The Write
in Progress (WIP) bit still can be checked while the Sector Erase cycle is in progress. The WIP sets during
the tBE32K timing, and clears when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is
cleared. If the block is protected by BP3~0, the array data will be protected (no change) and the WEL bit still be
reset.
Figure 26. Block Erase 32KB (BE32K) Sequence (Command 52)
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
Command
SI
24 Bit Address
23 22
52h
2
1
0
MSB
P/N: PM2138
47
REV. 0.03, JAN. 30, 2015
PRELIMINARY
MX25R6435F
9-21. Block Erase (BE)
The Block Erase (BE) instruction is for erasing the data of the chosen block to be "1". The instruction is used for
64K-byte block erase operation. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL)
bit before sending the Block Erase (BE). Any address of the block (Please refer to "Table 4. Memory Organization")
is a valid address for Block Erase (BE) instruction. The CS# must go high exactly at the byte boundary (the latest
eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed.
The sequence of issuing BE instruction is: CS# goes low→ sending BE instruction code→ 3-byte address on SI→
CS# goes high.
The SIO[3:1] are "don't care".
The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked during the Block Erase cycle is in progress. The WIP sets 1 during the tBE
timing, and sets 0 when Block Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the block
is protected by BP3, BP2, BP1, BP0 bits, the Block Erase (BE) instruction will not be executed on the block.
Figure 27. Block Erase (BE) Sequence
CS#
Mode 3
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
Mode 0
SI
Command
24-Bit Address
23 22
D8h
2
1
0
MSB
P/N: PM2138
48
REV. 0.03, JAN. 30, 2015
PRELIMINARY
MX25R6435F
9-22. Chip Erase (CE)
The Chip Erase (CE) instruction is for erasing the data of the whole chip to be "1". A Write Enable (WREN)
instruction must execute to set the Write Enable Latch (WEL) bit before sending the Chip Erase (CE). The CS#
must go high exactly at the byte boundary, otherwise the instruction will be rejected and not executed.
The sequence of issuing CE instruction is: CS# goes low→sending CE instruction code→CS# goes high.
The SIO[3:1] are "don't care".
The self-timed Chip Erase Cycle time (tCE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked during the Chip Erase cycle is in progress. The WIP sets 1 during the
tCE timing, and sets 0 when Chip Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the
chip is protected by BP3, BP2, BP1, BP0 bits, the Chip Erase (CE) instruction will not be executed. It will be only
executed when BP3, BP2, BP1, BP0 all set to "0".
Figure 28. Chip Erase (CE) Sequence
CS#
Mode 3
0
1
2
3
4
5
6
7
SCLK
Mode 0
SI
P/N: PM2138
Command
60h or C7h
49
REV. 0.03, JAN. 30, 2015
PRELIMINARY
MX25R6435F
9-23. Page Program (PP)
The Page Program (PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction
must be executed to set the Write Enable Latch (WEL) bit before sending the Page Program (PP). The device
programs only the last 256 data bytes sent to the device. The last address byte (the 8 least significant address
bits, A7-A0) should be set to 0 for 256 bytes page program. If A7-A0 are not all zero, transmitted data that exceed
page length are programmed from the starting address (24-bit address that last 8 bit are all 0) of currently selected
page. If the data bytes sent to the device exceeds 256, the last 256 data byte is programmed at the request page
and previous data will be disregarded. If the data bytes sent to the device has not exceeded 256, the data will be
programmed at the request address of the page. There will be no effort on the other data bytes of the same page.
The sequence of issuing PP instruction is: CS# goes low→ sending PP instruction code→ 3-byte address on SI→ at
least 1-byte on data on SI→ CS# goes high.
The CS# must be kept low during the whole Page Program cycle; The CS# must go high exactly at the byte boundary (the
latest eighth bit of data being latched in), otherwise the instruction will be rejected and will not be executed.
The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked during the Page Program cycle is in progress. The WIP sets 1 during the
tPP timing, and sets 0 when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the
page is protected by BP3, BP2, BP1, BP0 bits, the Page Program (PP) instruction will not be executed.
The SIO[3:1] are "don't care".
P/N: PM2138
50
REV. 0.03, JAN. 30, 2015
PRELIMINARY
MX25R6435F
Figure 29. Page Program (PP) Sequence
CS#
Mode 3
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
1
0
7
6
5
3
2
1
0
2079
2
2078
3
2077
23 22 21
02h
SI
Data Byte 1
24-Bit Address
2076
Command
2075
Mode 0
4
1
0
MSB
MSB
2074
2073
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
2072
CS#
SCLK
Data Byte 2
SI
7
6
MSB
P/N: PM2138
5
4
3
2
Data Byte 3
1
0
7
6
5
4
MSB
3
2
Data Byte 256
1
0
7
6
5
4
3
2
MSB
51
REV. 0.03, JAN. 30, 2015
PRELIMINARY
MX25R6435F
9-24. 4 x I/O Page Program (4PP)
The Quad Page Program (4PP) instruction is for programming the memory to be "0". A Write Enable (WREN)
instruction must execute to set the Write Enable Latch (WEL) bit and Quad Enable (QE) bit must be set to "1" before
sending the Quad Page Program (4PP). The Quad Page Programming takes four pins: SIO0, SIO1, SIO2, and
SIO3 as address and data input, which can improve programmer performance and the effectiveness of application.
The 4PP operation frequency supports as fast as f4PP. The other function descriptions are as same as standard
page program.
The sequence of issuing 4PP instruction is: CS# goes low→ sending 4PP instruction code→ 3-byte address on
SIO[3:0]→ at least 1-byte on data on SIO[3:0]→CS# goes high.
Figure 30. 4 x I/O Page Program (4PP) Sequence
CS#
Mode 3
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21
SCLK
Mode 0
SIO0
P/N: PM2138
Command
38h
6 ADD cycles
Data Data Data Data
Byte 1 Byte 2 Byte 3 Byte 4
A20 A16 A12 A8 A4 A0 D4 D0 D4 D0 D4 D0 D4 D0
SIO1
A21 A17 A13 A9 A5 A1 D5 D1 D5 D1 D5 D1 D5 D1
SIO2
A22 A18 A14 A10 A6 A2 D6 D2 D6 D2 D6 D2 D6 D2
SIO3
A23 A19 A15 A11 A7 A3
52
D7 D3 D7 D3
D7 D3 D7 D3
REV. 0.03, JAN. 30, 2015
PRELIMINARY
MX25R6435F
9-25. Deep Power-down (DP)
The Deep Power-down (DP) instruction is for setting the device on the minimizing the power consumption (to
entering the Deep Power-down mode), the standby current is reduced from ISB1 to ISB2). The Deep Power-down
mode requires the Deep Power-down (DP) instruction to enter, during the Deep Power-down mode, the device is
not active and all Write/Program/Erase instruction are ignored. When CS# goes high, the device is in deep powerdown mode, not standby mode.
The sequence of issuing DP instruction is: CS# goes low→sending DP instruction code→CS# goes high.
The SIO[3:1] are "don't care".
Once the DP instruction is set, all instructions will be ignored except CS# toggling for tRDP timing as "Figure 32.
Release from Deep Power-down (RDP) Sequence". When Power-down, or software reset command the deep
power-down mode automatically stops, and when power-up, the device automatically is in standby mode. For
DP instruction the CS# must go high exactly at the byte boundary (the latest eighth bit of instruction code been
latched-in); otherwise, the instruction will not be executed. As soon as Chip Select (CS#) goes high, a delay of tDP
is required before entering the Deep Power-down mode. In addition, a Deep Power Down Delay time (tDPDD) is
required before release from deep power down once entering deep power down mode.
Figure 31. Deep Power-down (DP) Sequence
CS#
Mode 3
0
1
2
3
4
5
6
tDP
7
SCLK
Mode 0
SI
Command
B9h
Stand-by Mode
Deep Power-down Mode
Figure 32. Release from Deep Power-down (RDP) Sequence
CS#
tCRDP
tRDP
SO/SI
High-Z
Deep Power-down Mode
P/N: PM2138
53
Stand-by Mode
REV. 0.03, JAN. 30, 2015
PRELIMINARY
MX25R6435F
9-26. Enter Secured OTP (ENSO)
The ENSO instruction is for entering the additional 8K-bit secured OTP mode. The additional 8K-bit secured OTP is
independent from main array, which may use to store unique serial number for system identifier. After entering the
Secured OTP mode, and then follow standard read or program procedure to read out the data or update data. The
Secured OTP data cannot be updated again once it is lock-down.
The sequence of issuing ENSO instruction is: CS# goes low→ sending ENSO instruction to enter Secured OTP
mode→ CS# goes high.
The SIO[3:1] are "don't care".
Please note that WRSR/WRSCUR commands are not acceptable during the access of secure OTP region, once
security OTP is lock down, only read related commands are valid.
9-27. Exit Secured OTP (EXSO)
The EXSO instruction is for exiting the additional 8K-bit secured OTP mode.
The sequence of issuing EXSO instruction is: CS# goes low→ sending EXSO instruction to exit Secured OTP
mode→ CS# goes high.
The SIO[3:1] are "don't care".
9-28. Read Security Register (RDSCUR)
The RDSCUR instruction is for reading the value of Security Register bits. The Read Security Register can be read
at any time (even in program/erase/write status register/write security register condition) and continuously.
The sequence of issuing RDSCUR instruction is : CS# goes low→sending RDSCUR instruction→Security Register
data out on SO→ CS# goes high.
The SIO[3:1] are "don't care".
The definition of the Security Register bits is as below:
Secured OTP Indicator bit. The Secured OTP indicator bit shows the chip is locked by factory before ex- factory or
not. When it is "0", it indicates non-factory lock; "1" indicates factory-lock.
Lock-down Secured OTP (LDSO) bit. By writing WRSCUR instruction, the LDSO bit may be set to "1" for
customer lock-down purpose. However, once the bit is set to "1" (lock-down), the LDSO bit and the 1st 4K-bit
Secured OTP area cannot be update any more. While it is in 8K-bit secured OTP mode, main array access is not
allowed.
Program Suspend Status bit. Program Suspend Bit (PSB) indicates the status of Program Suspend operation.
Users may use PSB to identify the state of flash memory. After the flash memory is suspended by Program Suspend
command, PSB is set to "1". PSB is cleared to "0" after program operation resumes.
Erase Suspend Status bit. Erase Suspend Bit (ESB) indicates the status of Erase Suspend operation. Users may
use ESB to identify the state of flash memory. After the flash memory is suspended by Erase Suspend command,
ESB is set to "1". ESB is cleared to "0" after erase operation resumes.
P/N: PM2138
54
REV. 0.03, JAN. 30, 2015
PRELIMINARY
MX25R6435F
Program Fail Flag bit. While a program failure happened, the Program Fail Flag bit would be set. If the program
operation fails on a protected memory region, this bit will also be set. This bit can be the failure indication of one or
more program operations. This fail flag bit will be cleared automatically after the next successful program operation.
Erase Fail Flag bit. While an erase failure happened, the Erase Fail Flag bit would be set. If the erase operation
fails on a protected memory region, this bit will also be set. This bit can be the failure indication of one or more erase
operations. This fail flag bit will be cleared automatically after the next successful erase operation.
Table 8. Security Register Definition
bit7
bit6
bit5
bit4
Reserved
E_FAIL
P_FAIL
Reserved
-
0=normal
Erase
succeed
1=indicate
Erase failed
(default=0)
0=normal
Program
succeed
1=indicate
Program
failed
(default=0)
-
x
Volatile bit
Volatile bit
Volatile bit
Read Only
Read Only
bit3
bit2
bit1
bit0
Secured OTP
LDSO
ESB
PSB
Indicator bit
(lock-down 1st
(Erase
(Program
4K-bit Secured
(2nd 4K-bit
Suspend bit) Suspend bit)
OTP)
Secured OTP)
0 = not
0=Erase
0=Program
0 = nonfactory
lockdown
is not
is not
lock
suspended suspended
1 = lock-down
1 = factory
1= Erase
1= Program
(cannot
lock
suspended suspended
program/erase
(default=0)
(default=0)
OTP)
Volatile bit
Volatile bit
Read Only
Read Only
non-volatile bit non-volatile bit
OTP
Read Only
9-29. Write Security Register (WRSCUR)
The WRSCUR instruction is for changing the values of Security Register Bits. The WREN (Write Enable) instruction
is required before issuing WRSCUR instruction. The WRSCUR instruction may change the values of bit1 (LDSO bit)
for customer to lock-down the 1st 4K-bit Secured OTP area. Once the LDSO bit is set to "1", the 1st 4K-bit Secured
OTP area cannot be updated any more.
The sequence of issuing WRSCUR instruction is :CS# goes low→ sending WRSCUR instruction → CS# goes high.
The SIO[3:1] are "don't care".
The CS# must go high exactly at the boundary; otherwise, the instruction will be rejected and not executed.
P/N: PM2138
55
REV. 0.03, JAN. 30, 2015
PRELIMINARY
MX25R6435F
9-30. Program Suspend and Erase Suspend
The Suspend instruction interrupts a Page Program, Sector Erase, or Block Erase operation to allow access to
the memory array. After the program or erase operation has entered the suspended state, the memory array can
be read except for the page being programmed or the sector or block being erased ("Table 9. Readable Area of
Memory While a Program or Erase Operation is Suspended").
Table 9. Readable Area of Memory While a Program or Erase Operation is Suspended
Suspended Operation
Readable Region of Memory Array
Page Program
All but the Page being programmed
Sector Erase (4KB)
All but the 4KB Sector being erased
Block Erase (32KB)
All but the 32KB Block being erased
Block Erase (64KB)
All but the 64KB Block being erased
When the serial flash receives the Suspend instruction, there is a latency of tPSL or tESL ("Figure 34. Suspend
to Read/Program Latency") before the Write Enable Latch (WEL) bit clears to “0” and the PSB or ESB sets to “1”,
after which the device is ready to accept one of the commands listed in "Table 10. Acceptable Commands During
Program/Erase Suspend after tPSL/tESL" (e.g. FAST READ). Refer to "Table 19. AC Characteristics" for tPSL and
tESL timings. "Table 11. Acceptable Commands During Suspend (tPSL/tESL not required)" lists the commands for
which the tPSL and tESL latencies do not apply. For example, RDSR, RDSCUR, RSTEN, and RST can be issued at
any time after the Suspend instruction.
Security Register bit 2 (PSB) and bit 3 (ESB) can be read to check the suspend status. The PSB (Program Suspend
Bit) sets to “1” when a program operation is suspended. The ESB (Erase Suspend Bit) sets to “1” when an erase
operation is suspended. The PSB or ESB clears to “0” when the program or erase operation is resumed.
Table 10. Acceptable Commands During Program/Erase Suspend after tPSL/tESL
Command Name
Command Code
READ
03h
FAST READ
0Bh
DREAD
3Bh
QREAD
6Bh
2READ
BBh
4READ
EBh
RDSFDP
5Ah
RDID
9Fh
REMS
90h
ENSO
B1h
EXSO
C1h
SBL
C0h
WREN
06h
P/N: PM2138
Suspend Type
Program Suspend
Erase Suspend
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
56
REV. 0.03, JAN. 30, 2015
PRELIMINARY
MX25R6435F
Acceptable Commands During Program/Erase Suspend after tPSL/tESL - Continued
Command Name
Command Code
RESUME
7Ah or 30h
PP
02h
4PP
38h
Suspend Type
Program Suspend
Erase Suspend
•
•
•
•
Table 11. Acceptable Commands During Suspend (tPSL/tESL not required)
Command Name
Command Code
WRDI
04h
RDSR
05h
RDCR
15h
RDSCUR
2Bh
RES
ABh
RSTEN
66h
RST
99h
NOP
00h
Suspend Type
Program Suspend
Erase Suspend
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Figure 33. Resume to Suspend Latency
CS#
Resume Command
tPRS/tERS
Suspend
Command
tPRS: Program Resume to another Suspend
tERS: Erase Resume to another Suspend
P/N: PM2138
57
REV. 0.03, JAN. 30, 2015
PRELIMINARY
MX25R6435F
9-30-1. Erase Suspend to Program
The “Erase Suspend to Program” feature allows Page Programming while an erase operation is suspended. Page
Programming is permitted in any unprotected memory except within the sector of a suspended Sector Erase
operation or within the block of a suspended Block Erase operation. The Write Enable (WREN) instruction must be
issued before any Page Program instruction.
A Page Program operation initiated within a suspended erase cannot itself be suspended and must be allowed to
finish before the suspended erase can be resumed. The Status Register can be polled to determine the status of
the Page Program operation. The WEL and WIP bits of the Status Register will remain “1” while the Page Program
operation is in progress and will both clear to “0” when the Page Program operation completes.
Figure 34. Suspend to Read/Program Latency
CS#
Suspend Command
tPSL/tESL
Read/Program Command
tPSL: Program latency
tESL: Erase latency
Notes:
1. Please note that Program only available after the Erase-Suspend operation
2. To check suspend ready information, please read security register bit2(PSB) and bit3(ESB)
9-31. Program Resume and Erase Resume
The Resume instruction resumes a suspended Page Program, Sector Erase, or Block Erase operation. Before
issuing the Resume instruction to restart a suspended erase operation, make sure that there is no Page Program
operation in progress.
Immediately after the serial flash receives the Resume instruction, the WEL and WIP bits are set to “1” and the PSB
or ESB is cleared to “0”. The program or erase operation will continue until finished ("Figure 35. Resume to Read
Latency") or until another Suspend instruction is received. A resume-to-suspend latency of tPRS or tERS must be
observed before issuing another Suspend instruction ("Figure 33. Resume to Suspend Latency").
Please note that the Resume instruction will be ignored if the serial flash is in “Performance Enhance Mode”. Make
sure the serial flash is not in “Performance Enhance Mode” before issuing the Resume instruction.
Figure 35. Resume to Read Latency
CS#
P/N: PM2138
Resume Command
tSE/tBE/tPP
Read Command
58
REV. 0.03, JAN. 30, 2015
PRELIMINARY
MX25R6435F
9-32. No Operation (NOP)
The "No Operation" command is only able to terminate the Reset Enable (RSTEN) command and will not affect any
other command.
The SIO[3:1] are don't care.
9-33. Software Reset (Reset-Enable (RSTEN) and Reset (RST))
The Software Reset operation combines two instructions: Reset-Enable (RSTEN) command and Reset (RST)
command. It returns the device to a standby mode. All the volatile bits and settings will be cleared then, which
makes the device return to the default status as power on.
To execute Reset command (RST), the Reset-Enable (RSTEN) command must be executed first to perform the
Reset operation. If there is any other command to interrupt after the Reset-Enable command, the Reset-Enable will
be invalid.
The SIO[3:1] are "don't care".
If the Reset command is executed during program or erase operation, the operation will be disabled, the data under
processing could be damaged or lost.
The reset time is different depending on the last operation. Longer latency time is required to recover from a
program operation than from other operations.
P/N: PM2138
59
REV. 0.03, JAN. 30, 2015
PRELIMINARY
MX25R6435F
Figure 36. Software Reset Recovery
Stand-by Mode
66
CS#
99
tReady2
Mode
Note: Refer to "Table 15-2. Reset Timing-(Other Operation)" for tREADY2 data.
Figure 37. Reset Sequence
tSHSL
CS#
SCLK
Mode 3
Mode 3
Mode 0
Mode 0
Command
SIO0
Command
99h
66h
9-34. High Voltage Operation
The flash device supports High Voltage Operation. This opeartion allows user can have better performance in
following operations:
Program/Erase operation.
To enable High Voltage Opeartion, WP#/SIO2 need to apply Vhv during whole operation. If the voltage can not
sustain in Vhv range, the Program/Erase opeation might be failed.
P/N: PM2138
60
REV. 0.03, JAN. 30, 2015
PRELIMINARY
MX25R6435F
9-35. Read SFDP Mode (RDSFDP)
The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the functional
and feature capabilities of serial flash devices in a standard set of internal parameter tables. These parameter tables
can be interrogated by host system software to enable adjustments needed to accommodate divergent features
from multiple vendors. The concept is similar to the one found in the Introduction of JEDEC Standard, JESD68 on
CFI.
The sequence of issuing RDSFDP instruction is same as FAST_READ: CS# goes low→send RDSFDP instruction
(5Ah)→send 3 address bytes on SI pin→send 1 dummy byte on SI pin→read SFDP code on SO→to end RDSFDP
operation can use CS# to high at any time during data out.
SFDP is a JEDEC Standard, JESD216.
Figure 38. Read Serial Flash Discoverable Parameter (RDSFDP) Sequence
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
Command
SI
SO
24 BIT ADDRESS
23 22 21
5Ah
3
2
1
0
High-Z
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
Dummy Cycle
SI
7
6
5
4
3
2
1
0
DATA OUT 2
DATA OUT 1
SO
7
6
5
3
2
1
0
7
MSB
MSB
P/N: PM2138
4
61
6
5
4
3
2
1
0
7
MSB
REV. 0.03, JAN. 30, 2015
PRELIMINARY
MX25R6435F
Table 12. Signature and Parameter Identification Data Values
SFDP Table below is for MX25R6435FM2IL0, MX25R6435FZNIL0, MX25R6435FZAIL0 and MX25R6435FBDIL0
Description
SFDP Signature
Comment
Fixed: 50444653h
Add (h) DW Add Data (h/b) Data
(Byte)
(Bit)
(Note1)
(h)
00h
07:00
53h
53h
01h
15:08
46h
46h
02h
23:16
44h
44h
03h
31:24
50h
50h
SFDP Minor Revision Number
Start from 00h
04h
07:00
00h
00h
SFDP Major Revision Number
Start from 01h
This number is 0-based. Therefore,
0 indicates 1 parameter header.
05h
15:08
01h
01h
06h
23:16
01h
01h
07h
31:24
FFh
FFh
00h: it indicates a JEDEC specified
header.
08h
07:00
00h
00h
Number of Parameter Headers
Unused
ID number (JEDEC)
Parameter Table Minor Revision
Number
Parameter Table Major Revision
Number
Parameter Table Length
(in double word)
Start from 00h
09h
15:08
00h
00h
Start from 01h
0Ah
23:16
01h
01h
How many DWORDs in the
Parameter table
0Bh
31:24
09h
09h
0Ch
07:00
30h
30h
Parameter Table Pointer (PTP)
First address of JEDEC Flash
Parameter table
0Dh
15:08
00h
00h
0Eh
23:16
00h
00h
0Fh
31:24
FFh
FFh
it indicates Macronix manufacturer
ID
10h
07:00
C2h
C2h
Start from 00h
11h
15:08
00h
00h
Start from 01h
12h
23:16
01h
01h
How many DWORDs in the
Parameter table
13h
31:24
04h
04h
14h
07:00
60h
60h
15h
15:08
00h
00h
16h
23:16
00h
00h
17h
31:24
FFh
FFh
Unused
ID number
(Macronix manufacturer ID)
Parameter Table Minor Revision
Number
Parameter Table Major Revision
Number
Parameter Table Length
(in double word)
Parameter Table Pointer (PTP)
First address of Macronix Flash
Parameter table
Unused
P/N: PM2138
62
REV. 0.03, JAN. 30, 2015
PRELIMINARY
MX25R6435F
Table 13. Parameter Table (0): JEDEC Flash Parameter Tables
SFDP Table below is for MX25R6435FM2IL0, MX25R6435FZNIL0, MX25R6435FZAIL0 and MX25R6435FBDIL0
Description
Comment
Block/Sector Erase sizes
00: Reserved, 01: 4KB erase,
10: Reserved,
11: not support 4KB erase
Write Granularity
0: 1Byte, 1: 64Byte or larger
Write Enable Instruction Required 0: not required
for Writing to Volatile Status
1: required 00h to be written to the
Registers
status register
Add (h) DW Add Data (h/b)
(Byte)
(Bit)
(Note1)
31h
(1-1-2) Fast Read (Note2)
0=not support 1=support
Address Bytes Number used in
addressing flash array
Double Transfer Rate (DTR)
Clocking
00: 3Byte only, 01: 3 or 4Byte,
10: 4Byte only, 11: Reserved
01b
02
1b
03
0b
30h
0: use 50h opcode,
1: use 06h opcode
Write Enable Opcode Select for
Note: If target flash status register is
Writing to Volatile Status Registers
nonvolatile, then bits 3 and 4 must
be set to 00b.
Contains 111b and can never be
Unused
changed
4KB Erase Opcode
01:00
0=not support 1=support
32h
Data
(h)
E5h
04
0b
07:05
111b
15:08
20h
16
1b
18:17
00b
19
0b
20
1b
20h
F1h
(1-2-2) Fast Read
0=not support 1=support
(1-4-4) Fast Read
0=not support 1=support
21
1b
(1-1-4) Fast Read
0=not support 1=support
22
1b
23
1b
33h
31:24
FFh
37h:34h
31:00
03FF FFFFh
Unused
Unused
Flash Memory Density
(1-4-4) Fast Read Number of Wait
states (Note3)
(1-4-4) Fast Read Number of
Mode Bits (Note4)
0 0000b: Not supported; 0 0100b: 4
0 0110b: 6; 0 1000b: 8
Mode Bits:
000b: Not supported; 010b: 2 bits
(1-4-4) Fast Read Opcode
(1-1-4) Fast Read Number of Wait
states
(1-1-4) Fast Read Number of
Mode Bits
39h
0 0000b: Not supported; 0 0100b: 4
0 0110b: 6; 0 1000b: 8
Mode Bits:
000b: Not supported; 010b: 2 bits
(1-1-4) Fast Read Opcode
P/N: PM2138
38h
3Ah
3Bh
63
04:00
0 0100b
07:05
010b
15:08
EBh
20:16
0 1000b
23:21
000b
31:24
6Bh
FFh
44h
EBh
08h
6Bh
REV. 0.03, JAN. 30, 2015
PRELIMINARY
MX25R6435F
SFDP Table below is for MX25R6435FM2IL0, MX25R6435FZNIL0, MX25R6435FZAIL0 and MX25R6435FBDIL0
Description
Comment
(1-1-2) Fast Read Number of Wait
states
(1-1-2) Fast Read Number of
Mode Bits
0 0000b: Not supported; 0 0100b: 4
0 0110b: 6; 0 1000b: 8
Mode Bits:
000b: Not supported; 010b: 2 bits
(1-1-2) Fast Read Opcode
(1-2-2) Fast Read Number of Wait
states
(1-2-2) Fast Read Number of
Mode Bits
0 0000b: Not supported; 0 0100b: 4
0 0110b: 6; 0 1000b: 8
Mode Bits:
000b: Not supported; 010b: 2 bits
3Eh
3Fh
0=not support 1=support
Unused
(4-4-4) Fast Read
3Ch
3Dh
(1-2-2) Fast Read Opcode
(2-2-2) Fast Read
Add (h) DW Add Data (h/b)
(Byte)
(Bit)
(Note1)
0=not support 1=support
40h
Unused
04:00
0 1000b
07:05
000b
15:08
3Bh
20:16
0 0100b
23:21
000b
31:24
BBh
00
0b
03:01
111b
04
0b
07:05
111b
Data
(h)
08h
3Bh
04h
BBh
EEh
Unused
43h:41h
31:08
FFh
FFh
Unused
45h:44h
15:00
FFh
FFh
20:16
0 0000b
23:21
000b
47h
31:24
FFh
FFh
49h:48h
15:00
FFh
FFh
20:16
0 0000b
23:21
000b
4Bh
31:24
FFh
FFh
4Ch
07:00
0Ch
0Ch
4Dh
15:08
20h
20h
4Eh
23:16
0Fh
0Fh
4Fh
31:24
52h
52h
50h
07:00
10h
10h
51h
15:08
D8h
D8h
52h
23:16
00h
00h
53h
31:24
FFh
FFh
(2-2-2) Fast Read Number of Wait
states
(2-2-2) Fast Read Number of
Mode Bits
0 0000b: Not supported; 0 0100b: 4
0 0110b: 6; 0 1000b: 8
Mode Bits:
000b: Not supported; 010b: 2 bits
(2-2-2) Fast Read Opcode
Unused
(4-4-4) Fast Read Number of Wait
states
(4-4-4) Fast Read Number of
Mode Bits
0 0000b: Not supported; 0 0100b: 4
0 0110b: 6; 0 1000b: 8
Mode Bits:
000b: Not supported; 010b: 2 bits
(4-4-4) Fast Read Opcode
Sector Type 1 Size
Sector/block size = 2^N bytes (Note5)
0Ch: 4KB; 0Fh: 32KB; 10h: 64KB
Sector Type 1 erase Opcode
Sector Type 2 Size
Sector/block size = 2^N bytes
00h: N/A; 0Fh: 32KB; 10h: 64KB
Sector Type 2 erase Opcode
Sector Type 3 Size
Sector/block size = 2^N bytes
00h: N/A; 0Fh: 32KB; 10h: 64KB
Sector Type 3 erase Opcode
Sector Type 4 Size
00h: N/A, This sector type doesn't
exist
Sector Type 4 erase Opcode
P/N: PM2138
64
46h
4Ah
00h
00h
REV. 0.03, JAN. 30, 2015
PRELIMINARY
MX25R6435F
Table 14. Parameter Table (1): Macronix Flash Parameter Tables
SFDP Table below is for MX25R6435FM2IL0, MX25R6435FZNIL0, MX25R6435FZAIL0 and MX25R6435FBDIL0
Description
Vcc Supply Maximum Voltage
Vcc Supply Minimum Voltage
Add (h) DW Add Data (h/b)
(Byte)
(Bit)
(Note1)
Comment
2000h=2.000V
2700h=2.700V
3600h=3.600V
1650h=1.650V, 1750h=1.750V
2250h=2.250V, 2300h=2.300V
2350h=2.350V, 2650h=2.650V
2700h=2.700V
Data
(h)
61h:60h
07:00
15:08
00h
36h
00h
36h
63h:62h
23:16
31:24
00h
17h
00h
17h
H/W Reset# pin
0=not support 1=support
00
1b
H/W Hold# pin
0=not support 1=support
01
0b
Deep Power Down Mode
0=not support 1=support
02
1b
S/W Reset
0=not support 1=support
03
1b
S/W Reset Opcode
Reset Enable (66h) should be
issued before Reset Opcode
Program Suspend/Resume
0=not support 1=support
12
1b
Erase Suspend/Resume
0=not support 1=support
13
1b
14
1b
15
1b
66h
23:16
C0h
C0h
67h
31:24
64h
64h
65h:64h
Unused
Wrap-Around Read mode
0=not support 1=support
Wrap-Around Read mode Opcode
11:04
1001 1001b
F99Dh
(99h)
Wrap-Around Read data length
08h:support 8B wrap-around read
16h:8B&16B
32h:8B&16B&32B
64h:8B&16B&32B&64B
Individual block lock
0=not support 1=support
00
0b
Individual block lock bit
(Volatile/Nonvolatile)
0=Volatile 1=Nonvolatile
01
1b
09:02
1111 1111b
(FFh)
10
1b
11
1b
Individual block lock Opcode
Individual block lock Volatile
protect bit default protect status
0=protect 1=unprotect
Secured OTP
0=not support 1=support
Read Lock
0=not support 1=support
12
0b
Permanent Lock
0=not support 1=support
13
0b
Unused
15:14
11b
Unused
31:16
FFh
FFh
31:00
FFh
FFh
Unused
6Bh:68h
6Fh:6Ch
CFFEh
MX25R6435FM2IL0-SFDP_2015-01-30,SF10
P/N: PM2138
65
REV. 0.03, JAN. 30, 2015
PRELIMINARY
MX25R6435F
Note 1: h/b is hexadecimal or binary.
Note 2: (x-y-z) means I/O mode nomenclature used to indicate the number of active pins used for the opcode (x),
address (y), and data (z). At the present time, the only valid Read SFDP instruction modes are: (1-1-1), (2-2-2),
and (4-4-4)
Note 3: Wait States is required dummy clock cycles after the address bits or optional mode bits.
Note 4: Mode Bits is optional control bits that follow the address bits. These bits are driven by the system controller
if they are specified. (eg,read performance enhance toggling bits)
Note 5: 4KB=2^0Ch,32KB=2^0Fh,64KB=2^10h
Note 6: All unused and undefined area data is blank FFh for SFDP Tables that are defined in Parameter
Identification Header. All other areas beyond defined SFDP Table are reserved by Macronix.
P/N: PM2138
66
REV. 0.03, JAN. 30, 2015
PRELIMINARY
MX25R6435F
10. RESET
Driving the RESET# pin low for a period of tRLRH or longer will reset the device. After reset cycle, the device is at
the following states:
- Standby mode
- All the volatile bits such as WEL/WIP/SRAM lock bit will return to the default status as power on.
If the device is under programming or erasing, driving the RESET# pin low will also terminate the operation and data
could be lost. During the resetting cycle, the SO data becomes high impedance and the current will be reduced to
minimum.
Figure 39. RESET Timing
CS#
tRHSL
SCLK
tRH tRS
RESET#
tRLRH
tREADY1 / tREADY2
Table 15-1. Reset Timing-(Power On)
Symbol Parameter
tRHSL Reset# high before CS# low
tRS
Reset# setup time
tRH
Reset# hold time
tRLRH Reset# low pulse width
tREADY1 Reset Recovery time
Min.
10
15
15
10
35
Typ.
Max.
Unit
us
ns
ns
us
us
Min.
10
15
15
10
40
35
310
12
25
100
40
Typ.
Max.
Unit
us
ns
ns
us
us
us
us
ms
ms
ms
ms
Table 15-2. Reset Timing-(Other Operation)
Symbol
tRHSL
tRS
tRH
tRLRH
Parameter
Reset# high before CS# low
Reset# setup time
Reset# hold time
Reset# low pulse width
Reset Recovery time (During instruction decoding)
Reset Recovery time (for read operation)
Reset Recovery time (for program operation)
tREADY2 Reset Recovery time(for SE4KB operation)
Reset Recovery time (for BE32K/64K operation)
Reset Recovery time (for Chip Erase operation)
Reset Recovery time (for WRSR operation)
P/N: PM2138
67
REV. 0.03, JAN. 30, 2015
PRELIMINARY
MX25R6435F
11. POWER-ON STATE
The device is at the following states after power-up:
- Standby mode (please note it is not deep power-down mode)
- Write Enable Latch (WEL) bit is reset
The device must not be selected during power-up and power-down stage until the VCC reaches the following levels:
- VCC minimum at power-up stage and then after a delay of tVSL
- GND at power-down
Please note that a pull-up resistor on CS# may ensure a safe and proper power-up/down level.
An internal power-on reset (POR) circuit may protect the device from data corruption and inadvertent data change
during power up state. When VCC is lower than VWI (POR threshold voltage value), the internal logic is reset and
the flash device has no response to any command.
For further protection on the device, if the VCC does not reach the VCC minimum level, the correct operation is not
guaranteed. The write, erase, and program command should be sent after the below time delay:
- tVSL after VCC reached VCC minimum level
The device can accept read command after VCC reached VCC minimum and a time delay of tVSL.
Please refer to the "Figure 46. Power-up Timing".
Note:
- To stabilize the VCC level, the VCC rail decoupled by a suitable capacitor close to package pins is
recommended. (generally around 0.1uF)
- At power-down stage, the VCC drops below VWI level, all operations are disable and device has no response to
any command. The data corruption might occur during this stage if a write, program, erase cycle is in progress.
P/N: PM2138
68
REV. 0.03, JAN. 30, 2015
PRELIMINARY
MX25R6435F
12. ELECTRICAL SPECIFICATIONS
Table 16. Absolute Maximum Ratings
Rating
Value
Ambient Operating Temperature
Industrial grade
-40°C to 85°C
Storage Temperature
-65°C to 150°C
Applied Input Voltage
-0.5V to VCC+0.5V
Applied Output Voltage
-0.5V to VCC+0.5V
VCC to Ground Potential
-0.5V to 4.0V
NOTICE:
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to
the device. This is stress rating only and functional operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended period may affect reliability.
2. Specifications contained within the following tables are subject to change.
3. During voltage transitions, all pins may overshoot to VCC+1.0V or -1.0V for period up to 20ns.
Figure 41. Maximum Positive Overshoot Waveform
Figure 40. Maximum Negative Overshoot Waveform
20ns
0V
VCC+1.0V
-1.0V
VCC
20ns
Table 17. Capacitance
TA = 25°C, f = 1.0 MHz
Symbol Parameter
CIN
COUT
P/N: PM2138
Min.
Typ.
Max.
Unit
Input Capacitance
6
pF
VIN = 0V
Output Capacitance
8
pF
VOUT = 0V
69
Conditions
REV. 0.03, JAN. 30, 2015
PRELIMINARY
MX25R6435F
Figure 42. Input Test Waveforms and Measurement Level
Input timing reference level
0.8VCC
0.7VCC
0.3VCC
0.2VCC
Output timing reference level
AC
Measurement
Level
0.5VCC
Note: Input pulse rise and fall time are <5ns
Figure 43. Output Loading
DEVICE UNDER
TEST
2.7K ohm
CL
6.2K ohm
+3.3V
DIODES=IN3064
OR EQUIVALENT
CL=30pF/15pF Including jig capacitance
P/N: PM2138
70
REV. 0.03, JAN. 30, 2015
PRELIMINARY
MX25R6435F
Table 18. DC Characteristics
Low Power Mode (Configuration Register-2 bit1= 0):
Symbol Parameter
Notes
Min.
Typ.
Max.
Units
Test Conditions
ILI
Input Load Current
1
±2
uA
VCC = VCC Max,
VIN = VCC or GND
ILO
Output Leakage Current
1
±2
uA
VCC = VCC Max,
VOUT = VCC or GND
ISB1
VCC Standby Current
1
12
18
uA
VIN = VCC or GND,
CS# = VCC
ISB2
Deep Power-down
Current
0.2
0.5
uA
6
mA
4
mA
4
mA
4
mA
4
mA
4
mA
1
4
mA
Erase in Progress,
CS#=VCC
1
4
mA
Erase in Progress,
CS#=VCC
7
8
V
-0.5
0.2VCC
V
0.8VCC
VCC+0.4
V
0.2
V
IOL = 100uA
V
IOH = -100uA
ICC1
VCC Read
VIL
VCC Program Current
(PP)
VCC Write Status
Register (WRSR) Current
VCC Sector/Block (64K)
Erase Current
(SE/BE)
VCC Chip Erase Current
(CE)
High Voltage Applied at
WP# pin
Input Low Voltage
VIH
Input High Voltage
VOL
Output Low Voltage
VOH
Output High Voltage
ICC2
ICC3
ICC4
ICC5
Vhv
1
1
VCC-0.2
VIN = VCC or GND,
CS# = VCC
f=16MHz (4x I/O)
SCLK=0.1VCC/0.9VCC,
SO=Open
f=33MHz
SCLK=0.1VCC/0.9VCC,
SO=Open
f=8MHz (2x I/O)
SCLK=0.1VCC/0.9VCC,
SO=Open
f=8MHz (4x I/O)
SCLK=0.1VCC/0.9VCC,
SO=Open
Program in Progress,
CS# = VCC
Program status register in
progress, CS#=VCC
Test Condition, VCC=2.0V
Notes :
1. Typical values at VCC = 3.0V, T = 25°C. These currents are valid for all product versions (package and speeds).
2. Typical value is calculated by simulation.
P/N: PM2138
71
REV. 0.03, JAN. 30, 2015
PRELIMINARY
MX25R6435F
High Performance Mode (Configuration Register-2 bit1= 1):
Symbol Parameter
Notes
Min.
Typ.
Max.
Units Test Conditions
ILI
Input Load Current
1
±2
uA
VCC = VCC Max,
VIN = VCC or GND
ILO
Output Leakage Current
1
±2
uA
VCC = VCC Max,
VOUT = VCC or GND
Iwph
Leakage Current while
WP# at Vhv
30
uA
VCC < 2.1V
ISB1
VCC Standby Current
25
50
uA
VIN = VCC or GND,
CS# = VCC
ISB2
Deep Power-down
Current
0.2
0.5
uA
VIN = VCC or GND,
CS# = VCC
8
mA
12
mA
10
mA
9
12
mA
10
15
mA
10
15
mA
1
10
15
mA
Erase in Progress,
CS#=VCC
1
10
15
mA
Erase in Progress,
CS#=VCC
7
8
V
ICC1
ICC2
ICC3
ICC4
ICC5
VCC Read
VCC Program Current
(PP)
VCC Write Status
Register (WRSR) Current
VCC Sector/Block (64K)
Erase Current
(SE/BE)
VCC Chip Erase Current
(CE)
1
1
1
f=70MHz
SCLK=0.1VCC/0.9VCC,
SO=Open
f=60MHz (2x I/O)
SCLK=0.1VCC/0.9VCC,
SO=Open
f=33MHz (4x I/O)
SCLK=0.1VCC/0.9VCC,
SO=Open
f=60MHz (4x I/O)
SCLK=0.1VCC/0.9VCC,
SO=Open
Program in Progress,
CS# = VCC
Program status register in
progress, CS#=VCC
Vhv
High Voltage Applied at
WP# pin
VIL
Input Low Voltage
-0.5
0.2VCC
V
VIH
Input High Voltage
0.8VCC
VCC+0.4
V
VOL
Output Low Voltage
0.2
V
IOL = 100uA
VOH
Output High Voltage
V
IOH = -100uA
VCC-0.2
Test Condition, VCC=2.0V
Notes :
1. Typical values at VCC = 3.0V, T = 25°C. These currents are valid for all product versions (package and speeds).
2. Typical value is calculated by simulation.
P/N: PM2138
72
REV. 0.03, JAN. 30, 2015
PRELIMINARY
MX25R6435F
Table 19. AC Characteristics
Low Power Mode (Configuration Register-2 bit1= 0):
Symbol
fSCLK
fRSCLK
fTSCLK
f4PP
tCH(1)
tCL(1)
tCLCH(10)
tCHCL(10)
tSLCH
tCHSL
tDVCH
tCHDX
tCHSH
tSHCH
tSHSL
tSHQZ(10)
tCLQV
tCLQX
tLH
tWHSL (3)
tSHWL(3)
tDP
tDPDD
tCRDP
tRDP
tRES2
tW
tWMS
tESL (9)
tPSL (9)
tPRS (4)
tERS (5)
P/N: PM2138
Alt. Parameter
Min.
Clock Frequency for the following instructions:
D.C.
fC FAST_READ, RDSFDP, PP, SE, BE32K, BE, CE, DP,
RES, RDP, WREN, WRDI, RDID, RDSR, WRSR(8)
fR Clock Frequency for READ instructions
fT Clock Frequency for 2READ/DREAD instructions
fQ Clock Frequency for 4READ/QREAD instructions
Clock Frequency for 4PP (Quad page program)
Others (fSCLK)
45%x (1/fSCLK)
tCLH Clock High Time
Normal Read (fRSCLK)
13
Others (fSCLK)
45%x (1/fSCLK)
tCLL Clock Low Time
Normal Read (fRSCLK)
13
Clock Rise Time (peak to peak)
0.1
Clock Fall Time (peak to peak)
0.1
tCSS CS# Active Setup Time (relative to SCLK)
5
CS# Not Active Hold Time (relative to SCLK)
5
tDSU Data In Setup Time
2
tDH Data In Hold Time
3
CS# Active Hold Time (relative to SCLK)
5
CS# Not Active Setup Time (relative to SCLK)
5
Read
5
tCSH CS# Deselect Time
Write/Erase/Program
30
tDIS Output Disable Time
Low to Output Valid Loading: 30pF
tV Clock
Loading: 30pF/15pF
Loading: 15pF
tHO Output Hold Time
0
Low Power Mode switch to High Performance Mode
Time
Write Protect Setup Time
10
Write Protect Hold Time
10
CS# High to Deep Power-down Mode
Delay Time for Release from Deep Power-Down Mode
30
once entering Deep Power-Down Mode
CS# Toggling Time before Release from Deep Power20
Down Mode
Recovery Time for Release from deep power down
35
mode
CS# High to Standby Mode with Electronic Signature
Read
Write Status Register Cycle Time
Write Status Register Cycle Time for Mode Switching
Erase Suspend Latency
Program Suspend Latency
Latency between Program Resume and next Suspend
0.3
Latency between Erase Resume and next Suspend
0.3
73
Typ.(2)
Max.
Unit
33
MHz
33
8
8
33
MHz
MHz
MHz
MHz
ns
ns
ns
ns
V/ns
V/ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
8
8
6
us
10
ns
ns
us
us
ns
us
100
400
30
us
40
20
60
60
ms
us
us
us
us
us
REV. 0.03, JAN. 30, 2015
PRELIMINARY
MX25R6435F
Low Power Mode - Continued:
Symbol
tBP
tPP
tSE
tBE32K
tBE
tCE
P/N: PM2138
Alt. Parameter
Byte-Program
Byte-Program (Applied Vhv at WP# pin)
Page Program Cycle Time
Page Program Cycle Time (Applied Vhv at WP# pin)
Sector Erase Cycle Time
Sector Erase Cycle Time (Applied Vhv at WP# pin)
Block Erase (32KB) Cycle Time
Block Erase (32KB) Cycle Time (Applied Vhv at WP# pin)
Block Erase (64KB) Cycle Time
Block Erase (64KB) Cycle Time (Applied Vhv at WP# pin)
Chip Erase Cycle Time
Chip Erase Cycle Time (Applied Vhv at WP# pin)
74
Min.
Typ.(2)
50
40
4
0.6
200
120
1
0.35
2
0.7
200
50
Max.
125
100
8
1.2
600
360
3
1
6
2.1
600
150
Unit
us
us
ms
ms
ms
ms
s
s
s
s
s
s
REV. 0.03, JAN. 30, 2015
PRELIMINARY
MX25R6435F
High Performance Mode (Configuration Register-2 bit1= 1):
Symbol
Alt. Parameter
fSCLK
fC
fRSCLK
fR
fT
fQ
fTSCLK
f4PP
tCH(1)
tCLH
tCL(1)
tCLL
tCLCH(10)
tCHCL(10)
tSLCH
tCHSL
tDVCH
tCHDX
tCHSH
tSHCH
tCSS
tDSU
tDH
tSHSL
tCSH
tSHQZ(10)
tDIS
tCLQV
tV
tCLQX
tHO
tHL
(3)
tWHSL
tSHWL (3)
tDP
tDPDD
tCRDP
tRDP
tRES2
tW
tWMS
tESL(9)
tPSL(9)
tPRS (4)
tERS (5)
P/N: PM2138
Min.
Clock Frequency for the following instructions:
FAST_READ, RDSFDP, PP, SE, BE32K, BE, CE, DP,
RES, RDP, WREN, WRDI, RDID, RDSR, WRSR(8)
D.C.
Clock Frequency for READ instructions
Clock Frequency for 2READ/DREAD instructions
Clock Frequency for 4READ/QREAD instructions
Clock Frequency for 4PP (Quad page program)
Others (fSCLK)
45%x (1/fSCLK)
Clock High Time
Normal Read (fRSCLK)
13
Others (fSCLK)
45%x (1/fSCLK)
Clock Low Time
Normal Read (fRSCLK)
13
Clock Rise Time (peak to peak)
0.1
Clock Fall Time (peak to peak)
0.1
CS# Active Setup Time (relative to SCLK)
5
CS# Not Active Hold Time (relative to SCLK)
5
Data In Setup Time
2
Data In Hold Time
3
CS# Active Hold Time (relative to SCLK)
5
CS# Not Active Setup Time (relative to SCLK)
5
Read
5
CS# Deselect Time
Write/Erase/Program
30
Output Disable Time
Clock Low to Output Valid Loading: 30pF
Loading: 30pF/15pF
Loading: 15pF
Output Hold Time
0
High Performance Mode switch to Low Power Mode
Time
Write Protect Setup Time
10
Write Protect Hold Time
10
CS# High to Deep Power-down Mode
Delay Time for Release from Deep Power-Down
30
Mode once entering Deep Power-Down Mode
CS# Toggling Time before Release from Deep
20
Power-Down Mode
Recovery Time for Release from deep power down
45
mode
CS# High to Standby Mode with Electronic Signature
Read
Write Status Register Cycle Time
Write Status Register Cycle Time for Mode Switching
Erase Suspend Latency
Program Suspend Latency
Latency between Program Resume and next
0.3
Suspend
Latency between Erase Resume and next Suspend
0.3
75
Typ.(2)
Max.
Unit
70
MHz
33
60
60
60
MHz
MHz
MHz
MHz
ns
ns
ns
ns
V/ns
V/ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
8
8
6
us
10
ns
ns
us
us
ns
us
30
us
40
20
40
40
ms
us
us
us
100
us
400
us
REV. 0.03, JAN. 30, 2015
PRELIMINARY
MX25R6435F
High Performance Mode - Continued:
Symbol
tBP
tPP
tSE
tBE32K
tBE
tCE
Alt. Parameter
Byte-Program
Byte-Program (Applied Vhv at WP# pin)
Page Program Cycle Time
Page Program Cycle Time (Applied Vhv at WP# pin)
Sector Erase Cycle Time
Sector Erase Cycle Time (Applied Vhv at WP# pin)
Block Erase (32KB) Cycle Time
Block Erase (32KB) Cycle Time (Applied Vhv at WP# pin)
Block Erase (64KB) Cycle Time
Block Erase (64KB) Cycle Time (Applied Vhv at WP# pin)
Chip Erase Cycle Time
Chip Erase Cycle Time (Applied Vhv at WP# pin)
Min.
Typ.(2)
40
40
1.2
0.6
140
120
0.5
0.35
1
0.7
80
50
Max.
100
100
2.4
1.2
420
360
1.5
1
3
2.1
240
150
Unit
us
us
ms
ms
ms
ms
s
s
s
s
s
s
Notes:
1. tCH + tCL must be greater than or equal to 1/ Frequency.
2. Typical values given for TA=25°C. Not 100% tested.
3. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.
4. For tPRS, Min. time is needed to issue next program suspend command. However, a period of time equal to/or
longer than typ. timing is also required to complete the program progress.
5. For tRES, Min. timing is needed to issue next erase suspend command. However, a period of time equal to/or
longer than typ. timing is also required to complete the erase progress.
6. If the address range is within 4Mb, the 4READ/QREAD clock rate could achieve to 16MHz for 4READ/QREAD
operation. If user wants to keep 4READ/QREAD at 16MHz for address range that is more than 4Mb, it is
necessary to re-issue 4READ/QREAD command again after each 4Mb boundary.
7. Test condition is shown as "Figure 42. Input Test Waveforms and Measurement Level", "Figure 43. Output
Loading".
8. WRSR speed max. is 33MHz when issuing WRSR for performance mode switch no matter High Performance
Mode to Low Power Mode or Low Power Mode to High Performance Mode.
9. Latency time is required to complete Erase/Program Suspend operation until WIP bit is "0".
10. The value guaranteed by characterization, not 100% tested in production.
P/N: PM2138
76
REV. 0.03, JAN. 30, 2015
PRELIMINARY
MX25R6435F
13. OPERATING CONDITIONS
At Device Power-Up and Power-Down
AC timing illustrated in "Figure 44. AC Timing at Device Power-Up" and "Figure 45. Power-Down Sequence" are
for the supply voltages and the control signals at device power-up and power-down. If the timing in the figures is
ignored, the device will not operate correctly.
During power-up and power-down, CS# needs to follow the voltage applied on VCC to keep the device not to be
selected. The CS# can be driven low when VCC reach Vcc(min.) and wait a period of tVSL.
Figure 44. AC Timing at Device Power-Up
VCC
VCC(min)
GND
tVR
tSHSL
CS#
tSLCH
tCHSL
tCHSH
tSHCH
SCLK
tDVCH
tCHCL
tCHDX
LSB IN
MSB IN
SI
High Impedance
SO
Symbol
tVR
tCLCH
Parameter
VCC Rise Time
Notes
1
Min.
20
Max.
500000
Unit
us/V
Notes :
1. Sampled, not 100% tested.
2. For AC spec tCHSL, tSLCH, tDVCH, tCHDX, tSHSL, tCHSH, tSHCH, tCHCL, tCLCH in the figure, please refer to
"Table 19. AC Characteristics".
P/N: PM2138
77
REV. 0.03, JAN. 30, 2015
PRELIMINARY
MX25R6435F
Figure 45. Power-Down Sequence
During power-down, CS# needs to follow the voltage drop on VCC to avoid mis-operation.
VCC
CS#
SCLK
P/N: PM2138
78
REV. 0.03, JAN. 30, 2015
PRELIMINARY
MX25R6435F
Figure 46. Power-up Timing
VCC
VCC(max)
Chip Selection is Not Allowed
VCC(min)
tVSL
Device is fully accessible
VWI
time
Note: VCC (max.) is 3.6V and VCC (min.) is 1.7V.
Table 20. Power-Up Timing and VWI Threshold
Symbol
tVSL(1)
VWI(1)
Parameter
VCC(min) to CS# low (VCC Rise Time)
Command Inhibit Voltage
Min.
800
1.1
Max.
1.5
Unit
us
V
Note: 1. These parameters are characterized only.
P/N: PM2138
79
REV. 0.03, JAN. 30, 2015
PRELIMINARY
MX25R6435F
Figure 47. Power Up/Down and Voltage Drop
For Power-down to Power-up operation, the VCC of flash device must below VPWD for at least tPWD timing.
Please check the table below for more detail.
VCC
VCC (max.)
Chip Select is not allowed
VCC (min.)
tVSL
Full Device
Access
Allowed
VPWD (max.)
tPWD
Time
Table 21. Power-Up/Down Voltage and Timing
Symbol Parameter
tVSL
VCC(min.) to device operation
VWI
Write Inhibit Voltage
VPWD
tPWD
tVR
VCC
Min.
800
1.1
Deep Power Mode
others
The minimum duration for ensuring initialization will occur
VCC Rise Time
VCC Power Supply
VCC voltage needed to below VPWD for ensuring
initialization will occur
300
20
1.7
Max.
1.5
0.4
0.9
500000
3.6
Unit
us
V
V
V
us
us/V
V
Note: These parameters are characterized only.
13-1. Initial Delivery State
The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status
Register contains 00h (all Status Register bits are 0).
P/N: PM2138
80
REV. 0.03, JAN. 30, 2015
PRELIMINARY
MX25R6435F
14. ERASE AND PROGRAMMING PERFORMANCE
Low Power Mode (Configuration Register-2 bit1= 0):
PARAMETER
Min.
Typ. (1)
Write Status Register Cycle Time
Max. (2)
Unit
40
ms
Sector Erase Cycle Time (4KB)
200
600
ms
Sector Erase Cycle Time (4KB) (Applied Vhv at WP# pin)
120
360
ms
2
6
s
Block Erase Cycle Time (64KB) (Applied Vhv at WP# pin)
0.7
2.1
s
Chip Erase Cycle Time
200
600
s
Chip Erase Cycle Time (Applied Vhv at WP# pin)
50
150
s
125
us
100
us
8
ms
1.2
ms
Block Erase Cycle Time (64KB)
(4)
Byte Program Time
50
Byte Program Time (Applied Vhv at WP# pin)
40
(4)
Page Program Time
4
Page Program Time (Applied Vhv at WP# pin)
0.6
Erase/Program Cycle
100,000
cycles
High Performance Mode (Configuration Register-2 bit1= 1):
PARAMETER
Min.
Typ. (1)
Write Status Register Cycle Time
Max. (2)
Unit
40
ms
Sector Erase Cycle Time (4KB)
140
420
ms
Sector Erase Cycle Time (4KB) (Applied Vhv at WP# pin)
120
360
ms
1
3
s
Block Erase Cycle Time (64KB) (Applied Vhv at WP# pin)
0.7
2.1
s
Chip Erase Cycle Time
80
240
s
Chip Erase Cycle Time (Applied Vhv at WP# pin)
50
150
s
100
us
100
us
2.4
ms
1.2
ms
Block Erase Cycle Time (64KB)
(4)
Byte Program Time
40
Byte Program Time (Applied Vhv at WP# pin)
40
Page Program Time
1.2
Page Program Time (Applied Vhv at WP# pin)
(4)
0.6
Erase/Program Cycle
100,000
cycles
Note:
1. Typical erase assumes the following conditions: 25°C, 3.0V, and all zero pattern.
2. Under worst conditions of 85°C and 1.7V.
3. System-level overhead is the time required to execute the first-bus-cycle sequence for the programming
command.
4. Typical program assumes the following conditions: 25°C, 3.0V, and checkerboard pattern.
P/N: PM2138
81
REV. 0.03, JAN. 30, 2015
PRELIMINARY
MX25R6435F
15. LATCH-UP CHARACTERISTICS
Min.
Max.
Input Voltage with respect to GND on all power pins, SI, CS#
-1.0V
2 VCCmax
Input Voltage with respect to GND on SO
-1.0V
VCC + 1.0V
-100mA
+100mA
Current
Includes all pins except VCC. Test conditions: VCC = 1.8V, one pin at a time.
P/N: PM2138
82
REV. 0.03, JAN. 30, 2015
PRELIMINARY
MX25R6435F
16. ORDERING INFORMATION
PART NO.
TEMPERATURE
PACKAGE
8-SOP
(200mil)
FEATURE
Low Power Mode support,
RESET# support
MX25R6435FM2IL0
-40°C~85°C
MX25R6435FZNIL0
-40°C~85°C
8-WSON
(6x5mm)
Low Power Mode support,
RESET# support
MX25R6435FZAIL0
-40°C~85°C
8-USON
(4x4mm)
Low Power Mode support,
RESET# support
MX25R6435FBDIL0
-40°C~85°C
22-Ball
WLCSP
Low Power Mode support,
RESET# support
P/N: PM2138
83
Remark
REV. 0.03, JAN. 30, 2015
PRELIMINARY
MX25R6435F
17. PART NAME DESCRIPTION
MX 25
R
6435F ZN
I
L0
OPTION:
L0: With Low Power Mode
TEMPERATURE RANGE:
I: Industrial (-40°C to 85°C)
PACKAGE:
M2: 8-SOP(200mil)
ZN: 8-WSON
ZA: 8-USON (4x4mm)
BD: 22-Ball WLCSP
DENSITY & MODE:
6435F: 64Mb
TYPE:
R: Wide Vcc Range (1.7V~3.6V)
DEVICE:
25: Serial Flash
P/N: PM2138
84
REV. 0.03, JAN. 30, 2015
PRELIMINARY
MX25R6435F
18. PACKAGE INFORMATION
P/N: PM2138
85
REV. 0.03, JAN. 30, 2015
PRELIMINARY
MX25R6435F
P/N: PM2138
86
REV. 0.03, JAN. 30, 2015
PRELIMINARY
MX25R6435F
P/N: PM2138
87
REV. 0.03, JAN. 30, 2015
PRELIMINARY
MX25R6435F
19. REVISION HISTORY
Revision No. Description
0.01
1. Modified Voltage in Feature page
2. Modified secured OTP description
3. Added 24bits as data boundary
4. Modified description of Performance Enhance Mode Reset
5. Added Note of Suspend to Read/Program Latency figure
6. Modifed AC value, tCHSH, tSHCH, tESL, tPSL, tPRS, tERS,
tWMS, tDPDD
7. Removed WLCSP pacakge
8. Added tCRDP and f4PP, and modified RDP figure
9. Modified Note of SFDP Table
10. Removed description of 32K byte block, and
Deep Power Down in RES section
11. Added note for WRSR speed
12. Added VPWD value in Deep Power Mode
13. Added 4x4mm 8USON package.
14. Removed "E7" command.
Page
Date
P4
OCT/16/2014
P4,7,12,18,52,53
P30
P44
P55
P30,51,70-72
0.02
P5,8,82-83,87 JAN/09/2015
P12,53-54
P55-58
P61-64,82-83
P62
P70-75,
P70,73,80
P72,74
P72,74-75
P7,30,70-74,80
P26
P31,52,53-54,59
P9
P82
All
JAN/30/2015
All
P83,84
0.03
P/N: PM2138
1. Added 16-Ball WLCSP package.
2. Revised Security OTP function.
3. Updated suspend/resume descriptions.
4. Updated part name.
5. Update SFDP table.
6. Updated parameters for DC/AC Characteristics,
added Vhv spec in Low Power Mode,
deleted tRES1 and revised tCH/tCL formula.
7. Added notes 9-10 of tESL/tPSL, tCLCH/tCHCL/tSHQZ
8. Revised the Configuration Register-2 bit 1 L/H Switch values.
9. Added RDCR content.
10. Content modification.
11. Updated BLOCK DIAGRAM.
12. Updated the ORDERING INFORMATION content.
1. Added description of 32K byte block
2. Revised status from "Advanced Information" to "Preliminary"
3. Modified WLCSP package description
88
P5,8,78,79
P50,51,70,71
P63
P6,22
P71-72
P76
P5,8,78-79,82
P41-42,54
REV. 0.03, JAN. 30, 2015
MX25R6435F
Except for customized products which have been expressly identified in the applicable agreement, Macronix's products
are designed, developed, and/or manufactured for ordinary business, industrial, personal, and/or household applications
only, and not for use in any applications which may, directly or indirectly, cause death, personal injury, or severe property
damages. In the event Macronix products are used in contradicted to their target usage above, the buyer shall take any
and all actions to ensure said Macronix's product qualified for its actual use in accordance with the applicable laws and
regulations; and Macronix as well as it’s suppliers and/or distributors shall be released from any and all liability arisen
therefrom.
Copyright© Macronix International Co., Ltd. 2014~2015. All rights reserved, including the trademarks and tradename
thereof, such as Macronix, MXIC, MXIC Logo, MX Logo, Integrated Solutions Provider, NBit, Nbit, NBiit, Macronix NBit,
eLiteFlash, HybridNVM, HybridFlash, XtraROM, Phines, KH Logo, BE-SONOS, KSMC, Kingtech, MXSMIO, Macronix
vEE, Macronix MAP, Rich Au­dio, Rich Book, Rich TV, and FitCAM. The names and brands of third party referred thereto (if
any) are for identification purposes only.
For the contact and order information, please visit Macronix’s Web site at: http://www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.
89