Hitachi HD4074618FS 4-bit single-chip microcomputer Datasheet

HD404618 Series
4-Bit Single-Chip Microcomputer
Rev. 6.0
Sept. 1998
Description
The HD404618 Series is designed with the powerful and efficient architecture of the HMCS400 family.
The MCU incorporates a high-precision dual-tone multifrequency (DTMF) circuit, LCD driver/controller,
voltage comparator, and 32-kHz watch oscillator circuit.
The HD404618 Series includes five chips: the HD404612 with 2-kword ROM; the HD404614 with 4kword ROM; the HD404616 with 6-kword ROM; the HD404618 with 8-kword ROM; the HD4074618
with 8-kword PROM.
The HD4074618, incorporating PROM, is a ZTAT microcomputer that can dramatically shorten system
development periods and smooth the process from debugging to mass production.
ZTAT™ : Zero Turn Around time ZTAT is a trademark of Hitachi Ltd.
Features
•
•
•
•
•
•
•
•
•
•
•
2048-word × 10-bit ROM (HD404612)
4096-word × 10-bit ROM (HD404614)
6144-word × 10-bit ROM (HD404616)
8192-word × 10-bit ROM (HD404618, HD4074618)
1184-digit × 4-bit RAM
30 I/O pins
 10 high-current output pins
 CMOS I/O pin circuit configuration
 Input/output pull-up MOS can be selected by software
On-chip DTMF generator
LCD controller/driver (32 segments × 4 commons)
Three timer/counters
Clock-synchronous 8-bit serial interface
Six interrupt sources
 Two by external sources
 Four by internal sources
HD404618 Series
• Subroutine stack up to 16 levels, including interrupts
• Instruction cycle time
 10 µs (fOSC = 400 kHz)
 5 µs (fOSC = 800 kHz)
• Four low-power dissipation modes
 Stop mode
 Standby mode
 Watch mode
 Subactive mode
• Built-in oscillator
 Crystal or ceramic oscillator (an external clock also possible)
• Voltage comparator (2 channels)
• Two operating modes
 MCU mode
 PROM mode (HD4074618)
• Package
 80-pin plastic flat package
(FP-80B) (FP-80A)
 80-pin plastic thin flat package (TFP-80)
Ordering Information
Type
Product Name
Model Name
ROM (Word)
Package
Mask ROM
HD404612
HD404612FS
2,048
FP-80B
HD404614
HD404616
HD404618
ZTAT
2
HD4074618
HD404612H
FP-80A
HD404612TF
TFP-80
HD404614FS
4,096
FP-80B
HD404614H
FP-80A
HD404614TF
TFP-80
HD404616FS
6,144
FP-80B
HD404616H
FP-80A
HD404616TF
TFP-80
HD404618FS
8,192
FP-80B
HD404618H
FP-80A
HD404618TF
TFP-80
HD4074618FS
8,192
FP-80B
HD4074618H
FP-80A
HD4074618TF
TFP-80
HD404618 Series
COM1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
D1
D0
RESET
OSC2
OSC1
VCC
VTref
TONER
TONEC
V3
V2
V1
COM4
COM3
COM2
Pin Arrangement
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
FP-80B
R2 0
R2 1
R2 2
R2 3
R3 0
TIMO/R3 1
INT0 /R3 2
INT1 /R3 3
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
D2
D3
D4
D5
D6
D7
D8
D9
D10
VC ref /D11
COMP0/D 12
COMP1/D 13
TEST
X1
X2
GND
SCK/R0 0
SI/R01
SO/R02
R03
R10
R11
R12
R13
61
62
63
64
65
66
67
68
69
71
70
73
72
74
75
76
77
78
1
60
2
59
3
4
58
57
5
56
6
55
7
54
8
53
9
10
52
51
FP-80A
TFP-80
11
12
50
49
40
39
38
37
36
35
34
33
32
30
31
41
28
29
20
27
43
42
26
44
18
19
25
45
17
24
46
16
23
47
15
22
48
14
21
13
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
R1 2
R1 3
R2 0
R2 1
R2 2
R2 3
R3 0
TIMO/R31
INT0 /R32
INT1 /R33
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
D4
D5
D6
D7
D8
D9
D10
VCref /D11
COMP0/D 12
COMP1/D 13
TEST
X1
X2
GND
SCK/R0 0
SI/R0 1
SO/R0 2
R0 3
R1 0
R1 1
79
80
D3
D2
D1
D0
RESET
OSC2
OSC1
VCC
VTref
TONER
TONEC
V3
V2
V1
COM4
COM3
COM2
COM1
SEG32
SEG31
(top view)
(top view)
3
HD404618 Series
Pin Description
Pin Number
Pin Number
FP-80B
FP-80A,
TFP-80
Pin Name
I/O
FP-80B
FP-80A,
TFP-80
Pin Name
I/O
1
79
D2
I/O
33
31
SEG1
O
2
80
D3
I/O
34
32
SEG2
O
3
1
D4
I/O
35
33
SEG3
O
4
2
D5
I/O
36
34
SEG4
O
5
3
D6
I/O
37
35
SEG5
O
6
4
D7
I/O
38
36
SEG6
O
7
5
D8
I/O
39
37
SEG7
O
8
6
D9
I/O
40
38
SEG8
O
9
7
D10
I
41
39
SEG9
O
10
8
D11/VCref
I
42
40
SEG10
O
11
9
D12/COMP0
I
43
41
SEG11
O
12
10
D13/COMP1
I
44
42
SEG12
O
13
11
TEST
I
45
43
SEG13
O
14
12
X1
I
46
44
SEG14
O
15
13
X2
O
47
45
SEG15
O
16
14
GND
48
46
SEG16
O
17
15
R0 0/SCK
I/O
49
47
SEG17
O
18
16
R0 1/SI
I/O
50
48
SEG18
O
19
17
R0 2/SO
I/O
51
49
SEG19
O
20
18
R0 3
I/O
52
50
SEG20
O
21
19
R1 0
I/O
53
51
SEG21
O
22
20
R1 1
I/O
54
52
SEG22
O
23
21
R1 2
I/O
55
53
SEG23
O
24
22
R1 3
I/O
56
54
SEG24
O
25
23
R2 0
I/O
57
55
SEG25
O
26
24
R2 1
I/O
58
56
SEG26
O
27
25
R2 2
I/O
59
57
SEG27
O
28
26
R2 3
I/O
60
58
SEG28
O
29
27
R3 0
I/O
61
59
SEG29
O
30
28
R3 1/TIMO
I/O
62
60
SEG30
O
31
29
R3 2/INT0
I/O
63
61
SEG31
O
32
30
R3 3/INT1
I/O
64
62
SEG32
O
4
HD404618 Series
Pin Number
Pin Number
FP-80B
FP-80A,
TFP-80
Pin Name
I/O
FP-80B
FP-80A,
TFP-80
Pin Name
I/O
65
63
COM1
O
73
71
TONER
O
66
64
COM2
O
74
72
VT ref
67
65
COM3
O
75
73
VCC
68
66
COM4
O
76
74
OSC 1
I
69
67
V1
77
75
OSC 2
O
70
68
V2
78
76
RESET
I
71
69
V3
79
77
D0
I/O
72
70
TONEC
80
78
D1
I/O
O
Note: I/O: Input/output pin, I: Input pin, O: Output pin
Pin Functions
Power Supply
VCC: Apply power voltage to this pin.
GND: Connect to ground.
TEST: Used for test purposes only. Connect it to VCC.
RESET: Resets the MCU.
Oscillators
OSC 1, OSC2 : Used as pins for the internal oscillator circuit. They can be connected to a ceramic
resonator, or OSC1 can be connected to an external oscillator circuit.
X1, X2: Used for a 32.768-kHz crystal oscillator that acts as a clock.
Ports
D 0–D 13 (D Port): Input/output port addressable by individual bits. D0–D 9 are I/O pins and D10–D 13 are
input pins. D0–D 9 are high current output pins (15 mA, max.). D11–D 13 are also available as voltage
comparators.
R0–R3 (R Ports): Input/output ports addressable in 4-bit units. R00, R01, R02, R31, R32, and R3 3, are
multiplexed with SCK, SI, SO, TIMO, INT0, and INT 1, respectively.
5
HD404618 Series
Interrupts
INT0, INT1: Input external interrupts to the MCU. INT1 is also used as an external event input for timer B.
INT 0 and INT1 are multiplexed with R32 and R33, respectively.
Serial Communications Interface
SCK: Input/output serial clock pin multiplexed with R0 0.
SI: Serial receive data input pin multiplexed with R01.
SO: Serial transmit data output pin multiplexed with R02.
Timers
TIMO: Outputs a variable-duty square wave. It is multiplexed with R31.
LCD Driver/Controller
V1, V2, V3: Power supply pins for the LCD driver. Internal resistors provide the voltage level for each pin.
The voltage condition is V CC ≥ V1 ≥ V2 ≥ V3 ≥ GND.
COM1–COM4: Common signal output pins for LCD display.
SEG1–SEG32: Segment signal output pins for LCD display.
DTMF Generator
TONER, TONEC, VT ref: DTMF signal pins. TONER and TONEC transmit signals for row and column,
respectively. VTref is a reference voltage for DTMF signals. Apply condition VCC ≥ VTref ≥ GND to VTref.
Voltage Comparator
COMP0, COMP1, VC ref: COMP0 and COMP1 are analog inputs for the voltage comparator. VCref is a
reference voltage pin that inputs the threshold voltage of the analog input pin.
6
HD404618 Series
VCC
GND
OSC 1
OSC 2
X1
X2
RESET
TEST
Block Diagram
System control circuit
External
interrupt
control
circuit
RAM
(1,184 × 4 bits)
D port
INT0
INT1
W (2 bits)
Timer A
X (4 bits)
Comparator
VTref
TONER
TONEC
DTMF
generation
circuit
ALU
CPU
R0 port
VCref
COMP0
COMP1
SPY (4 bits)
Internal data bus
Serial
interface
Internal address bus
SI
SO
SCK
Internal data bus
Y (4 bits)
R00
R01
R02
R03
R1 port
SPX (4 bits)
Timer C
R10
R11
R12
R13
R2 port
TIMO
R20
R21
R22
R23
R3 port
Timer B
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
R30
R31
R32
R33
High
current
pins
CA
ST
(1 bit) (1 bit)
A (4 bits)
V1
V2
V3
COM1
COM2
COM3
COM4
SEG1
SEG2
SEG3
SEG31
SEG32
B (4 bits)
LCD
controller/
driver
circuit
SP (10 bits)
Instruction
decoder
PC (14 bits)
ROM
(2,048 × 10 bits)
(4,096 × 10 bits)
(6,144 × 10 bits)
(8,192 × 10 bits)
: Data bus
: Signal lines
7
HD404618 Series
Memory Map
ROM Memory Map
The ROM memory map is shown in figure 1, and the ROM is described below.
0
$0000
Vector address
15
$000F
16
$0010
Zero-page subroutine
(64 words)
$003F
63
64
$0040
Pattern
(4096 words)
4095
$0FFF
4096
$1000
Program*
8191
$1FFF
8192
$2000
Not used
16383
0
1
2
3
JMPL instruction
(jump to reset routine)
4
5
6
7
8
9
JMPL instruction
(jump to INT1 routine)
10
11
12
13
14
15
JMPL instruction
(jump to INT0 routine)
JMPL instruction
(jump to timer A routine)
JMPL instruction
(jump to timer B routine)
JMPL instruction
(jump to timer C routine)
JMPL instruction
(jump to serial routine)
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
$000A
$000B
$000C
$000D
$000E
$000F
Note: * HD404612: 2048 words
HD404614: 4096 words
HD404616: 6144 words
HD404618, HD4074618: 8192 words
$3FFF
Figure 1 ROM Memory Map
Vector Address Area ($0000–$000F): Reserved for JMPL instructions that branch to the start addresses
of the reset and interrupt routines. After an MCU reset or interrupt execution, the program starts from the
vector address.
Zero-Page Subroutine Area ($0000–$003F): Reserved for subroutines. The program branches to a
subroutine in this area in response to the CAL instruction.
Pattern Area ($0000–$0FFF): Contains ROM data that can be referenced with the P instruction.
Program Area ($0000–$07FF (HD404612), $0000–$0FFF (HD404614), $0000–$17FF (HD404616),
$0000–$1FFF (HD404618, HD4074618)): Used for program coding.
8
HD404618 Series
RAM Memory Map
The MCU contains a 1,184-digit × 4-bit RAM area consisting of a data area and a stack area. In addition,
interrupt control bits and special registers are mapped onto the same RAM memory space outside this area.
The RAM memory map is shown in figure 2, and described below.
Interrupt Control Bits Area ($000–$003): Used for interrupt control bits and the bit register (figure 3).
The register flag area consists of LSON, WDON, TGSP, and DTON flags. Both areas can be accessed
only by RAM bit manipulation instructions. In addition, note that the interrupt request flag cannot be set
by software, the RSP bit is used only to reset the stack pointer. Limitations on using the instructions are
shown in figure 4.
Register Flag Area ($020–$023): Consist of the LSON, WDON, TGSP, and DTON flags which are bit
registers accessible by RAM bit manipulation instructions.
The WDON flag can only be set, only by the SEM/SEMD instruction.
The TGSP flag can be set and reset by the SEM/SEMD and REM/REMD instructions.
The DTON flag can be set, reset, and tested by the SEM/SEMD, REM/REMD, and TMD instructions.
Note that the DTON flag is active only in subactive mode, and is normally reset in active mode.
Special Function Registers Area ($004–$01F, $024–$03F): Used as mode or data registers for serial
interface, timer/counters, LCD, and DTMF, and as data control registers for I/O ports. These registers are
classified into three types: write-only, read-only, and read/write as shown in figure 2.
The SEM/REM and SEMD/REMD instructions can be used for the LCD control register (LCR), but RAM
bit manipulation instructions cannot be used for other registers.
LCD Data Area ($050–$06F): Used for storing LCD data which is automatically output to LCD segments
as display data. Data 1 lights the corresponding LCD segment; data 0 extinguishes it. This area can be
used as data area.
Data Area ($040–$2CF, $100–$2CF; Bank 0, 1): The memory registers (MR), which consist of 16 digits
($040–$04F), can be accessed by the LAMR and XMRA instructions (see figure 5). In the 464 digits from
$100–$2CF, a bank can be selected by the V register (see section on V register).
Stack Area ($3C0–$3FF): Used for saving the contents of the program counter (PC), status flag (ST),
and carry flag (CA) at subroutine call (CAL or CALL instruction) and interrupt processing. This area can
be used as a 16-level nesting subroutine stack in which one level requires four digits. The data to be saved
and the save conditions are shown in figure 5.
The program counter is restored by either the RTN or RTNI instruction, but the status and carry flags can
only be restored by the RTNI instruction. Any unused space in this area is used for data storage.
9
HD404618 Series
0
$000
RAM-mapped registers
63
64
80
112
Memory registers (MR)
LCD display area (32 digits)
$03F
$040
$050
$070
Data (144 digits)
$100
Data (464 digits × 2) *
V = 0 (bank 0)
V = 1 (bank 1)
Not used
$3BF
$3C0
Stack (64 digits)
$3FF
1023
5
6
7
8
9
10
$2CF
959
960
0
1
2
3
4
11
12
13
14
15
16
17
18
19
20
$000
$001
$002
Interrupt control bits area
Port mode register A
Serial mode register
(PMRA)
(SMR)
W
W
Serial data register lower (SRL) R/W
Serial data register upper (SRU) R/W
Timer mode register A
(TMA) W
Timer mode register B
(TMB) W
Timer B
(TCBL/TLRL)
(TCBU/TLRU)
Miscellaneous register
(MIS)
Timer mode register C
(TMC)
32
(LCR)
(LMR)
$008
$009
R/W
R/W
$00A
$00B
W
W
$00C
$00D
Timer C
(TCCL/TCRL) R/W
(TCCU/TCRU) R/W
TG mode register
(TGM) W
W
TG control register
(TGC)
Port mode register B
(PMRB) W
LCD control register
LCD mode register
Not used
$003
$004
$005
$006
$007
W
W
$00E
$00F
$010
$011
$012
$013
$014
$020
Register flag area
$023
35
Not used
$100
Data (464 digits)
V = 0 (bank 0)
48
49
50
51
$030
$031
(DCR2)
(DCR3)
W
W
W
W
Port R0 DCR
Port R1 DCR
(DCR0)
(DCR1)
Port R2 DCR
Port R3 DCR
Data (464 digits)
V = 1 (bank 1)
$032
$033
Not used
$2CF
Note: Do not use any area labelled “Not used”
* The data area has two banks:
V = 0 (bank 0) and V = 1 (bank 1)
R: Read only
W: Write only
R/W: Read/write
59
60
61
Port D 0 –D 3 DCR
(DCRB)
W
Port D 4 –D 7 DCR
(DCRC)
W
W
$03B
$03C
$03D
63
V register
R/W
$03F
Port D 8 –D 9 DCR
(DCRD)
Not used
10
Timer counter B, lower
(TCBL)
R
Timer load register B, lower
(TLRL)
W $00A
11
Timer counter B, upper
(TCBU)
R
Timer load register B, upper
(TLRU)
W
14
Timer counter C, lower
(TCCL)
R
Timer load register C, lower
(TCRL)
W $00E
15
Timer counter C, upper
(TCCU)
R
Timer load register C, upper
(TCRU)
W $00F
Figure 2 RAM Memory Map
10
(V-REG)
$00B
HD404618 Series
Bit 3
Bit 2
Bit 1
Bit 0
0
IM0
(IM of INT0 )
IF0
(IF of INT0 )
RSP
(Reset SP bit)
1
IMTA
(IM of timer A)
IFTA
(IF of timer A)
IM1
(IM of INT1 )
IF1
(IF of INT1 )
$001
2
IMTC
(IM of timer C)
IFTC
(IF of timer C)
IMTB
(IM of timer B)
IFTB
(IF of timer B)
$002
3
Not used
Not used
IMS
(IM of serial)
IFS
(IF of serial)
$003
32
DTON
Direct transfer on flag
TGSP
(Tone generator
speed flag)
WDON
(Watchdog on flag)
LSON
(Low speed on flag)
$020
IE
(Interrupt enable flag) $000
$021
Not Used
$023
35
IF:
IM:
IE:
SP:
Note:
Interrupt request flag
Interrupt mask
Interrupt enable flag
Stack pointer
Bits in the interrupt control bits area and register flag area are set by the SEM or SEMD
instruction, reset by the REM or REMD instruction, and tested by the TM or TMD instruction.
Other instructions have no effect.
Figure 3 Configuration of Interrupt Control Bits and Register Flag Areas
IF
RSP
WDON
TGSP
DTON
SEM/SEMD
Not executed
Not executed
Allowed
Allowed
Not executed in active mode
Used in subactive mode
REM/REMD
Allowed
Allowed
Not executed
Allowed
TM/TMD
Allowed
Inhibited
Inhibited
Inhibited
Allowed
Allowed
Note: WDON is always reset in active mode.
DTON is always reset in active mode.
If the TM or TMD instruction is executed for the inhibited bits or non-existing bits,
the value in ST becomes invalid.
Figure 4 Usage Limitations of RAM Bit Manipulation Instructions
11
HD404618 Series
Memory registers
64
65
66
67
68
69
MR (0)
MR (1)
$040
MR (2)
MR (3)
$042
MR (4)
$044
$045
Stack area
960
$041
$043
Level 16
Level 15
Level 14
Level 13
70
$046
Level 11
Level 10
71
MR (7)
$047
Level 9
72
MR (8)
MR (9)
$048
Level 8
73
$049
74
MR (10)
$04A
75
$04B
76
MR (11)
MR (12)
Level 7
Level 6
Level 5
$04C
Level 4
77
MR (13)
$04D
Level 3
78
MR (14)
MR (15)
$04E
Level 2
Level 1
$04F 1023
PC13 –PC0 : Program counter
ST: Status flag
CA: Carry flag
Level 12
MR (5)
MR (6)
79
$3C0
$3FF
Bit 3
Bit 2
Bit 1
Bit 0
1020
ST
PC13
PC12
PC11
$3FC
1021
PC10
PC 9
PC 8
PC 7
$3FD
1022
CA
PC 6
PC 5
PC 4
$3FE
1023
PC 3
PC 2
PC 1
PC 0
$3FF
Figure 5 Configuration of Memory Registers and Stack Area, and Stack Position
12
HD404618 Series
Functional Description
Registers and Flags
The MCU has ten registers and two flags for CPU operations. They are illustrated in figure 6 and described
below.
3
0
A
Accumulator
3
0
B
B register
0
V
1
V register
0
W
3
W register
0
X
3
X register
0
Y
3
Y register
0
SPX
3
SPX register
0
SPY
SPY register
0
CA
Carry flag
0
ST
13
Status flag
0
PC
Program counter
9
1
5
1
1
1
0
SP
Stack pointer
Figure 6 Registers and Flags
Accumulator (A), B Register (B): Four-bit registers used to hold results from the arithmetic logic unit
(ALU) and transfer data between memory, I/O, and other registers.
13
HD404618 Series
V Register (V): Used for RAM address expansion and selecting the bank of RAM addresses $100–$2CF
(464 digits). Thus, when accessing locations $100–$2CF, specify the value of the V register (V = $0 for
bank 0, V = $1 for bank 1). Locations $000–$0FF and $3C0–$3FF can be accessed independent of the V
register. The V register is located at RAM address $03F.
W Register (W), X Register (X), Y Register (Y): Two-bit (W) and four-bit (X and Y) registers used for
indirect RAM addressing. The Y register is also used for D-port addressing.
SPX Register (SPX), SPY Register (SPY): Four-bit registers used to supplement the X and Y registers.
Carry Flag (CA): One-bit flag that stores any ALU overflow generated by an arithmetic operation. CA is
affected by the SEC, REC, ROTL, and ROTR instructions. During an interrupt, a carry is pushed onto the
stack and popped from the stack by the RTNI instruction–but not by the RTN instruction.
Status Flag (ST): One-bit flag that latches any overflow generated by an arithmetic or compare
instruction, not-zero decision from the ALU, or result of a bit test. ST is used as a branch condition of the
BR, BRL, CAL, or CALL instruction. The contents of ST remain unchanged until the next arithmetic,
compare, or bit test instruction is executed, but become 1 after the BR, BRL, CAL, or CALL instruction is
read, regardless of whether the instruction is executed or skipped. During an interrupt, the contents of ST
are pushed onto the stack and popped from the stack by the RTNI instruction, but not by the RTN
instruction.
Program Counter (PC): A 14-bit counter that points to the ROM address of the instruction being
executed.
Stack Pointer (SP): Ten-bit pointer that contains the address of the stack area to be used next. The SP is
initialized to $3FF by MCU reset, is decremented by 4 when data is pushed onto the stack, and is
incremented by 4 when data is popped from the stack. Since the top four bits of the SP are fixed at 1111, a
stack of up to 16 levels can be used.
The SP can also be initialized to $3FF in another way: by resetting the RSP bit with the REM or REMD
instruction.
14
HD404618 Series
Reset
The MCU is reset by inputting a high-level voltage to the RESET pin. At power-on or when stop mode is
cancelled, RESET must be high for at least one tRC to enable the oscillator to stabilize.
During operation, RESET must be high for at least two instruction cycles.
I/O pins go to high-impedance at power-on.
Initial values after MCU reset are shown in table 1.
Table 1 Initial Values After MCU Reset
Item
Abbr.
Initial Value Contents
Program counter
(PC)
$0000
Indicates program execution
point from start address of ROM
area
Status flag
(ST)
1
Enables conditional branching
Stack pointer
(SP)
$3FF
Stack level 0
V register (bank register)
(V)
0
Bank 0 (memory)
Interrupt flags/mask Interrupt enable flag
(IE)
0
Inhibits all interrupts
Interrupt request flag
(IF)
0
Indicates there is no interrupt
request
Interrupt mask
(IM)
1
Prevents (masks) interrupt
request
Port data register
(PDR)
All bits 1
Enables output at level 1
Data control register
(DCR)
All bits 0
Turns output buffer off (to high
impedance)
Port mode register A
(PMRA)
0000
Refer to description of port mode
register A
Port mode register B
(PMRB)
0000
Refer to description of port mode
register B
Timer mode register A
(TMA)
0000
Refer to description of timer
mode register A
Timer mode register B
(TMB)
0000
Refer to description of timer
mode register B
Timer mode register C
(TMC)
0000
Refer to description of timer
mode register C
Serial mode register
(SMR)
0000
Refer to description of serial
mode register
Prescaler S
$000
—
Prescaler W
$00
—
$00
—
I/O
Timer/
counters, serial
interface
Timer counter A
(TCA)
15
HD404618 Series
Table 1 Initial Values After MCU Reset (cont)
Item
Timer/
counters, serial
interface
Abbr.
Initial Value Contents
Timer counter B
(TCB)
$00
—
Timer counter C
(TCC)
$00
—
Timer load register B
(TLR)
$00
—
Timer load register C
(TCR)
$00
—
000
—
Octal counter
LCD
DTMF generator
Bit registers
LCD control register
(LCR)
000
Refer to description of LCD
control register
LCD mode register
(LMR)
0000
Refer to description of LCD duty
cycle/clock control
Tone generator control (TGC)
register
000
Refer to description of tone
generator control register
Tone generator mode
register
(TGM)
0000
Refer to description of generator
mode register
Low speed on flag
(LSON)
0
Refer to description of operating
modes
Watchdog timer on flag (WDON) 0
Refer to description of timer C
Tone generator speed
flag
(TGSP)
0
Refer to description of DTMF
generation circuit
Direct transfer on flag
(DTON)
0
Refer to description of operating
modes
(MIS)
000
—
Miscellaneous
register
Item
Abbr.
Carry flag
(CA)
Accumulator
(A)
B register
(B)
W register
(W)
X/SPX register
(X/SPX)
Y/SPY register
(Y/SPY)
Serial data register
(SR)
RAM
16
Status after Cancellation of
Stop Mode by MCU Reset
Status after Cancellation of All
Other Modes by MCU Reset
Pre-MCU-reset values are not
guaranteed; values must be
initialized by program
Pre-MCU-reset values are not
guaranteed; values must be
initialized by program
Pre-MCU-reset (pre-STOPinstruction) values are retained
HD404618 Series
Interrupts
The MCU has six interrupt sources: two external signals (INT0 and INT1), three timer/counters (timers A,
B, and C), and serial interface (serial).
An interrupt request flag (IF), interrupt mask (IM), and vector address are provided for each interrupt
source, and an interrupt enable flag (IE) controls the entire interrupt process.
Interrupt Control Bits and Interrupt Servicing: Locations $000 through $003 in RAM space are
reserved for interrupt control bits which can be accessed by RAM bit manipulation instructions.
The interrupt request flag (IF) cannot be set by software. MCU reset initializes the interrupt enable flag
(IE) and the IF to 0 and the interrupt mask (IM) to 1.
Figure 7 is a block diagram of the interrupt control circuit. Table 2 lists interrupt priorities and vector
addresses, and table 3 lists the interrupt processing conditions for the six interrupt sources.
An interrupt request occurs when the IF is set to 1 and IM to 0. If the IE is 1 at that point, the interrupt is
processed. A priority programmable logic array (PLA) generates the vector address assigned to that
interrupt source.
Figure 8 shows the interrupt processing sequence, and figure 9 shows an interrupt processing flowchart.
After an interrupt is acknowledged, the previous instruction is completed in the first cycle. The IE is reset
in the second cycle, the carry flag, status flag, and program counter values are pushed onto the stack during
the second and third cycles, and the program jumps to the vector address to execute the instruction in the
third cycle.
Program the JMPL instruction at each vector address to branch the program to the start address of the
interrupt program, and reset the IF by a software instruction within the interrupt program.
17
HD404618 Series
$ 000,0
Sequence control
• Push PC/CA/ST
• Reset IE
• Jump to vector
address
IE
$ 000,2
IF0
$ 000,3
IM0
Vector
address
Priority control logic
$ 001,0
IF1
$ 001,1
IM1
$ 001,2
IFTA
$ 001,3
IMTA
$ 002,0
IFTB
$ 002,1
IMTB
$ 002,2
IFTC
$ 002,3
IMTC
$ 003,0
IFS
$ 003,1
IMS
Note: $m, n is at RAM address $m, bit number n.
Figure 7 Block Diagram of Interrupt Control Circuit
Table 2 Vector Addresses and Interrupt Priorities
Reset/Interrupt
Priority
RESET
Vector Address
$0000
INT0
1
$0002
INT1
2
$0004
Timer A
3
$0006
Timer B
4
$0008
Timer C
5
$000A
Serial
6
$000C
18
HD404618 Series
Table 3 Interrupt Processing and Activation Conditions
Interrupt Source
Interrupt
Control Bit INT0
INT1
Timer A
Timer B
Timer C
Serial
IE
1
1
1
1
1
1
IF0·IM0
1
0
0
0
0
0
IF1·IM1
*
1
0
0
0
0
IFTA·IMTA
*
*
1
0
0
0
IFTB·IMTB
*
*
*
1
0
0
IFTC·IMTC
*
*
*
*
1
0
IFS·IMS
*
*
*
*
*
1
Note: Bits marked by * can be either 0 or 1. Their values have no effect on operation.
Instruction cycles
1
2
3
4
5
6
Instruction
execution*
Interrupt
acceptance
Stacking
IE reset
Vector address
generation
Execution of JMPL
instruction at vector address
Note: * The stack is accessed and the IE reset after the instruction
is executed, even if it is a two-cycle instruction.
Execution of
instruction at
start address
of interrupt
routine
Figure 8 Interrupt Processing Sequence
19
HD404618 Series
Power
on
RESET = 1 ?
Yes
No
Interrupt
request ?
Yes
No
No
IE = 1?
Yes
Reset MCU
Accept interrupt
Execute instruction
IE ←0
Stack ← (PC)
Stack ← (CA)
Stack ← (ST)
PC ←(PC) + 1
PC← $0002
Yes
INT0
interrupt ?
No
PC← $0004
Yes
INT1
interrupt ?
No
PC← $0006
Yes
Timer A
interrupt ?
No
PC← $0008
Yes
Timer B
interrupt ?
No
PC ← $000A
Yes
Timer C
interrupt ?
No
PC ← $000C
Figure 9 Interrupt Processing Flowchart
20
(serial interrupt)
HD404618 Series
Interrupt Enable Flag (IE: $000, Bit 0): Controls the entire interrupt process. It is reset by the interrupt
processing and set by the RTNI instruction, as shown in table 4.
Table 4 Interrupt Enable Flag
IE
Interrupt Enabled/Disabled
0
Disabled
1
Enabled
External Interrupts (INT0, INT1): Specified by port mode register A (PMRA: $004).
The INT1 input can be used as a clock signal input to timer B. Timer B increments at each falling edge of
the INT1 input. When using INT1 as a timer B external event input, external interrupt mask IM1 must be
set to prevent the INT1 interrupt request from being accepted (see table 6).
To detect the edge of INT 0 or INT1, more than two instruction cycle times are required (2tcyc or 2tsubcyc).
External Interrupt Request Flags (IF0: $000, Bit 2; IF1: $001, Bit 0): Set at the falling edge of the
INT 0 and INT1 inputs as shown in table 5.
Table 5 External Interrupt Request Flags
IF0, IF1
Interrupt Request
0
No
1
Yes
External Interrupt Masks (IM0: $000, Bit 3; IM1: $001, Bit 1): Prevent (mask) interrupt requests
caused by the corresponding external interrupt request flags, as shown in table 6.
Table 6 External Interrupt Masks
IM0, IM1
Interrupt Request
0
Enabled
1
Disabled (masked)
Timer A Interrupt Request Flag (IFTA: $001, Bit 2): Set by overflow output from timer A as shown in
table 7.
Table 7 Timer A Interrupt Request Flag
IFTA
Interrupt Request
0
No
1
Yes
21
HD404618 Series
Timer A Interrupt Mask (IMTA: $001, Bit 3): Prevents (masks) an interrupt request caused by the timer
A interrupt request flag, as shown in table 8.
Table 8 Timer A Interrupt Mask
IMTA
Interrupt Request
0
Enabled
1
Disabled (masked)
Timer B Interrupt Request Flag (IFTB: $002, Bit 0): Set by overflow output from timer B as shown in
table 9.
Table 9 Timer B Interrupt Request Flag
IFTB
Interrupt Request
0
No
1
Yes
Timer B Interrupt Mask (IMTB: $002, Bit 1): Prevents (masks) an interrupt request caused by the
timer B interrupt request flag, as shown in table 10.
Table 10 Timer B Interrupt Mask
IMTB
Interrupt Request
0
Enabled
1
Disabled (masked)
Timer C Interrupt Request Flag (IFTC: $002, Bit 2): Set by overflow output from timer C as shown in
table 11.
Table 11 Timer C Interrupt Request Flag
IFTC
Interrupt Request
0
No
1
Yes
Timer C Interrupt Mask (IMTC: $002, Bit 3): Prevents (masks) an interrupt request caused by the timer
C interrupt request flag, as shown in table 12.
22
HD404618 Series
Table 12 Timer C Interrupt Mask
IMTC
Interrupt Request
0
Enabled
1
Disabled (masked)
Serial Interrupt Request Flag (IFS: $003,Bit 0): Set when the octal counter counts the eighth transmit
clock signal or when data transmit is discontinued by resetting the octal counter, as shown in table 13.
Table 13 Serial Interrupt Request Flag
IFS
Interrupt Request
0
No
1
Yes
Serial Interrupt Mask (IMS: $003, Bit 1): Prevents (masks) an interrupt request caused by the serial
interrupt request flag, as shown intable 14.
Table 14 Serial Interrupt Mask
IMS
Interrupt Request
0
Enabled
1
Disabled (masked)
23
HD404618 Series
Operating Modes
The MCU has five operating modes that are specified by how the clock is used. The functions available in
each mode are listed in table 15, and operations are shown in table 16. Transitions between operating
modes are shown in figure 10. Table 17 provides additional information for table 15.
Table 15 Functions Available in Each Operating Mode
Mode Name
Active
Standby
Stop
Watch
Subactive*4
Reset
cancellation,
interrupt
request
SBY
instruction
TMA3 = 0,
STOP
instruction
TMA3 = 1,
STOP
instruction
INT0 or timer
A interrupt
request from
watch mode
System
oscillator
Operating
Operating
Stopped
Stopped
Stopped
Subsystem
oscillator
Operating
Operating
Operating*1
Operating
Operating
Instruction
execution
(øCPU)
Operating
Stopped
Stopped
Stopped
Operating
Peripheral
Operating
function
interrupt(øPER)
Operating
Stopped
Stopped
Operating
Clock function Operating
interrupt (øCLK )
Operating
Stopped
Operating*2
Operating*2
RAM
Operating
Retained
Retained
Retained
Operating
Registers/
flags
Operating
Retained
Reset
Retained
Operating
I/O
Operating
Retained
High
Retained*3
3
impedance*
Activation
method
Status
Cancellation
method
Notes: 1.
2.
3.
4.
5.
24
Operating*3
RESET input, RESET input, RESET input RESET input, RESET input,
STOP/SBY
interrupt
INT0 or timer STOP/SBY
instruction
instruction
request
A interrupt
request
To reduce current dissipation, stop all oscillation in external circuits.
Refer to the Interrupt Frame section for details.
Refer to table 17.
Subactive mode is an optional function, specify it on the function option list.
In the watch and subactive modes, the MCU requires a 32.768-kHz crystal oscillator.
HD404618 Series
System Clock (øCPU )
Non-time-base peripheral function clock (ø PER)
Operating
Operating
Stopped
Active mode
Standby mode
Subactive mode
Stopped
—
Watch mode (TMA3 = 1)
Stop mode (TMA3 = 0)
Table 16 Operations in Low-Power Dissipation Modes
Function
Stop Mode
Watch Mode*3
Standby Mode
Subactive Mode*2, 3
CPU
Reset
Retained
Retained
OP
RAM
Retained
Retained
Retained
OP
Timer A
Reset
OP
OP
OP
Timer B
Reset
Stopped
OP
OP
Timer C
Reset
Stopped
OP
OP
4
Serial interface
Reset
Stopped*
OP
OP
LCD
Reset
OP
OP
OP
DTMF
Reset
Reset
Stopped
Reset
Retained
Retained
OP
I/O
Reset*
1
Notes: OP indicates operating.
1. Output pins are at high impedance.
2. Subactive mode is an optional function specified on the function option list.
3. In the watch and subactive modes, the MCU requires a 32.768 kHz crystal oscillator.
4. Transmission/reception is activated if a clock is input in external clock mode. (However,
interrupts stop.)
25
HD404618 Series
Reset
Standby mode
Active mode
Stop mode
(TMA3 = 0)
f OSC :
fX:
ø CPU:
ø CLK :
ø PER:
Operating
Operating
Stopped
f cyc
f cyc
f OSC :
fX:
ø CPU:
ø CLK :
ø PER:
SBY (standby)
Interrupt
Timers A, B, C,
Serial,
INT0 , INT 1
Operating
Operating
f cyc
f cyc
f cyc
(TMA3 = 0)
STOP
f OSC :
fX:
ø CPU:
ø CLK :
ø PER:
Stopped
Operating
Stopped
Stopped
Stopped
Watch mode
(TMA3 = 1)
f OSC :
fX:
ø CPU:
ø CLK :
ø PER:
f OSC :
fX:
f cyc :
f SUB :
ø CPU :
ø CLK :
ø PER :
LSON:
DTON:
Operating
Operating
Stopped
f SUB
f cyc
SBY (standby)
Interrupt
Timers A, B, C,
Serial,
INT0 , INT 1
f OSC :
fX:
ø CPU:
ø CLK :
ø PER:
(TMA3 = 1, LSON = 0)
Operating
Operating
f cyc
f SUB
f cyc
STOP
INT0 ,
Timer A * 1
f OSC :
fX:
ø CPU:
ø CLK :
ø PER:
Stopped
Operating
Stopped
f SUB
Stopped
*3
*2
Main oscillation frequency
Subactive mode
Suboscillation frequency
STOP
(TMA3 = 1, LSON = 1)
for time-base
INT0 ,
f
:
Stopped
f OSC : Stopped
*
1
OSC
f OSC /4
Timer A
fX:
Operating
fX:
Operating
f X /8
ø
:
f
ø
:
Stopped
SUB
CPU
CPU
System clock
STOP/SBY
ø
:
f
ø
:
f SUB
SUB
CLK
CLK
Clock for time-base
(LSON = 1) * 4
ø
:
f
ø
:
Stopped
SUB
PER
PER
Clock for other
peripheral functions
Low speed on flag
Notes: 1. Time-base interrupt
Direct transfer on flag
2. STOP/SBY (DTON = 1, LSON = 0)
3. STOP/SBY (DTON = 0, LSON = 0)
4. DTON is not affected
Figure 10 MCU Status Transitions
Table 17 I/O Status in Low-Power Dissipation Modes
Output
Input
Standby Mode, Watch Mode
Stop Mode
Active Mode, Subactive Mode
D0–D 9
Retained
High impedance
Input enabled
D10–D 13
—
—
Input enabled
R0–R3
Retained
High impedance
Input enabled
26
HD404618 Series
Active Mode: The MCU operates according to the clock generated by the system oscillators OSC1 and
OSC2.
Standby Mode: The MCU enters standby mode when the SBY instruction is executed from active mode.
In this mode, the oscillators, interrupts, timer/counters, and serial interface continue to operate, but all
instruction execution-related clocks stop. The stopping of these clocks stops the CPU, retaining all RAM
and register contents and maintaining the current I/O pin status.
Standby mode is terminated by a RESET input or an interrupt request. If it is terminated by RESET input,
the MCU is reset as well. After an interrupt request, the MCU enters active mode and resumes, executing
the next instruction after the SBY instruction. If the interrupt enable flag is 1, that interrupt is then
processed; if it is 0, the interrupt request is left pending and normal instruction execution continues. A
flowchart of operation in standby mode is shown in figure 11.
27
HD404618 Series
Standby
Watch
Oscillator: Active
Peripheral clocks:
Active
All other clocks:
Stopped
Oscillator: Stopped
Sub-oscillator: Active
Peripheral clocks: Stopped
All other clocks: Stopped
RESET
=1?
No
Yes
No
IF0 =
1?
Yes
IM0 =
0?
Yes
No
No
IF1 =
1?
Yes
IM1 =
0?
Yes
No
No
IFTA =
1?
Yes
IMTA =
0?
No
Yes
(SBY only)
No
IFTB =
1?
Yes
IMTB =
No
0?
Yes
(SBY only)
No
IFTC =
1?
Yes
IMTC =
No
0?
Yes
(SBY only)
IFS = No
1?
Yes
IMS =
0?
(SBY only)
No
Yes
Restart
processor clocks
Restart
processor clocks
Execute
next instruction
(active mode)
No
IF = 1,
IM = 0, and
IE = 1 ?
Yes
Reset MCU
Execute
next instruction
Accept
interrupt
Figure 11 MCU Operation Flowchart in Watch and Standby Modes
Stop Mode: The MCU enters stop mode if the STOP instruction is executed in active mode when TMA3 =
0. In this mode, the system oscillator stops, which stops all MCU functions as well.
Stop mode is terminated by a RESET input as shown in figure 12. RESET must be high for at least one tRC
to stabilize oscillation (refer to the AC Characteristics section). When the MCU restarts after stop mode is
cancelled, all RAM contents are retained, but the accuracy of the contents of the accumulator, B register, W
register, X/SPX register, Y/SPY register, carry flag, and serial data register cannot be guaranteed.
28
,
HD404618 Series
Stop mode
Oscillator
Internal clock
RESET
t res
t res> t RC (stabilization time)
STOP instruction execution
Figure 12 Timing of Stop Mode Cancellation
Watch Mode: The MCU enters watch mode if the STOP instruction is executed in active mode when
TMA3 = 1, or if the STOP or SBY instruc-tion is executed in subactive mode.
Watch mode is terminated by a RESET input or a timer-A/INT0 interrupt request. For details of RESET
input, refer to the Stop Mode section. When terminated by a timer-A/INT0 interrupt request, the MCU
enters active mode if LSON is 0, or subactive mode if LSON is 1. After an interrupt request is generated,
the time required to enter active mode is tRC for a timer A interrupt, and TX (where T + tRC < TX < 2T + tRC)
for an INT0 interrupt, as shown in figure 13.
Operation during mode transition is the same as that at standby mode cancellation (figure 12).
Oscillation
stabilization period
Active mode
Watch mode
Active mode
Interrupt strobe
INT0
Interrupt request
generation
T
(During the transition
from watch mode to
active mode only)
T
t RC
Tx
T = 2 × tRC: Interrupt frame length
tRC: Oscillation stabilization period
Figure 13 Interrupt Frame
Subactive Mode: The CPU operates with a clock generated by the X1 and X2 oscillation circuits.
Functions that can operate in subactive mode are listed in table 16. When the STOP or SBY instruction is
executed in subactive mode, the MCU enters either watch or active mode, depending on the statuses of
29
HD404618 Series
LSON and DTON. The DTON flag can only be set in subactive mode; it is automatically reset after a
transition to active mode.
Subactive mode is an optional function that the user must specify on the function option list.
Interrupt Frame: In watch and subactive modes, ØCLK is supplied for timer A and the INT0 circuit.
Prescaler W and timer A operate as time bases to generate interrupt frame timing. Three interrupt frame
cycles (T) can be selected by the settings of the miscellaneous register, as shown in figure 14.
In watch and subactive modes, timer A and INT0 interrupts are generated in synchronism with the interrupt
frame. An interrupt request is generated at the interrupt strobe timing, except when the MCU enters active
mode from watch mode. The INT0 falling edge is acknowledged regardless of the interrupt frame, but the
interrupt is executed simultaneously with the next interrupt strobe. Timer A generates an overflow and
interrupt request at the timing of an interrupt strobe.
MIS: $00C
MIS2
MIS1
MIS
MIS0
T
*1
t RC
Bit 1
Bit 0
0
0
0.24414 ms
*1
0.12207 ms
0.24414 ms *2
t RC selection
0
1
15.625 ms
7.8125 ms
Refer to
table 20
1
0
62.5 ms
31.25 ms
1
1
Not used
Oscillation circuit
condition
External clock input
400/800-kHz
ceramic oscillator
—
Notes: 1. The value of t RC applies only when using a 32.768-kHz oscillator.
2. Only direct transfer.
Figure 14 Miscellaneous Register
Direct Transfer: By controlling the DTON, the MCU would be placed directly from subactive to active
mode. The detailed procedure is as follows:
• Set the DTON flag in subactive mode while LSON = 0.
• Execute the STOP or SBY instruction.
• After the oscillation stabilization time (a fixed value), the MCU will move automatically from subactive
to active mode.
Note that DTON ($020, bit 3) is valid only in subactive mode. When the MCU is in active mode, this flag
is always at reset.
The transition time (tD) from subactive to active mode is tRC < tD < T + tRC.
30
HD404618 Series
STOP/SBY
execution Internal
execution
time (< T)
Subactive mode
Oscillation
stabilization
time
Active mode
(LSON = 0, DTON = 1)
Interrupt
strobe
Direct transfer
timing
T
t RC
T: Interrupt frame length
t RC : Oscillation stabilization period
Figure 15 Direct Transfer Timing
MCU Operating Sequence: The MCU operates in the sequence shown in figures 16 to 18. It is reset by
an asynchronous RESET input, regardless of its state.
The low-power mode operation sequence is shown in figure 18. With the IE flag cleared and an interrupt
flag set together with its interrupt mask cleared, if a STOP/SBY instruction is executed, the instruction is
cancelled (regarded as an NOP) and the following instruction is executed. Before executing a STOP/SBY
instruction, make sure all interrupt flags are cleared or all interrupts are masked.
Power on
RESET = 1 ?
Yes
Reset
MCU
No
MCU
operation
cycle
Figure 16 MCU Operating Sequence (power on)
31
HD404618 Series
MCU operation
cycle
IF = 1 ?
No
Instruction
execution
Yes
SBY/STOP
instruction ?
Yes
No
IM = 0 and
IE = 1 ?
Yes
IE ← 0 ;
Stack ← (PC),
(CA),
(ST)
No
Low-power mode
operation cycle
IF: Interrupt request flag
IM: Interrupt mask
IE: Interrupt enable flag
PC ← next
location
PC ← vector
address
PC: Program counter
CA: Carry flag
ST: Status flag
Figure 17 MCU Operating Sequence (MCU operation cycle)
32
HD404618 Series
Low-power mode
operation cycle
IF = 1
IM = 0 ?
No
Yes
Standby/watch
mode
No
Stop mode
IF = 1
IM = 0 ?
Yes
Hardware NOP
execution
Hardware NOP
execution
PC ← next
Iocation
PC ← next
Iocation
Instruction
execution
MCU operation
cycle
For IF and IM operation, refer to figure 12.
Figure 18 MCU Operating Sequence (low-power mode operation)
Notes on Use:
• In subactive mode, the timer A interrupt request or the external interrupt request (INT 0) occurs in
synchronism with the interrupt strobe.
If the STOP or SBY instruction is executed at the same time with the interrupt strobe, these interrupt
requests will be cancelled and the corresponding interrupt request flags (IFTA, IF0) will not be set.
In subactive mode, do not use the STOP or SBY instruction at the time of the interrupt strobe.
33
HD404618 Series
• When the MCU is in watch mode or subactive mode, if the high level period before the falling edge of
INT 0 is shorter than the interrupt frame, INT 0 is not detected. Also, if the low level period after the
falling edge of INT 0 is shorter than the interrupt frame, INT 0 is not detected.
Edge detection is shown in figure 19. The level of the INT 0 signal is sampled by a sampling clock.
When this sampled value changes to low from high, a falling edge is detected.
In figure 20, the level of the INT0 signal is sampled by an interrupt frame. In (a) the sampled value is
low at point A, and also low at point B. Therefore, a falling edge is not detected. In (b), the sampled
value is high at point A, and also high at point B. A falling edge is not detected in this case either.
• When the MCU is in watch mode or subactive mode, keep the high level and low level period of INT 0
longer than interrupt frame.
INT0
Sampling
High
Low
Low
Figure 19 Edge Detection
INT0
INT0
Interrupt
frame
Interrupt
frame
A: Low
B: Low
(a) High level period
Figure 20 Sampling Example
34
A: High
B: High
(b) Low level period
HD404618 Series
Internal Oscillator Circuit
,
'
&
%
$
./0'()!"+$*#,
Figure 21 shows a block diagram of the internal oscillator circuit. A ceramic oscillator can be connected to
OSC1 and OSC2, and a 32.768-kHz crystal oscillator can be connected to X1 and X2. The system oscillator
can also be operated by an external clock.
OSC1
System
oscillator
f OSC
Subsystem
oscillator
fX
Divider
(1/4)
Timing
generator
f cyc
Divider
(1/8)
Timing
generator
f SUB
Mode
control
circuit
OSC2
X1
X2
System clock
(ø CPU )
System clock
(ø PER )
Timer-base
clock (ø CLK )
Figure 21 Internal Oscillator Circuit
D0
COMP1/D13
RESET
OSC 2
TEST
X1
X2
OSC 1
V CC
GND
VT ref
SCK/R0 0
GND
Figure 22 Layout of Crystal and Ceramic Oscillators
35
HD404618 Series
Table 18 Oscillator Circuit Examples
Circuit Configuration
External clock operation
(OSC1, OSC 2)
Circuit Constants
External
oscillator
OSC 1
Open
OSC 2
Ceramic oscillator
(OSC1, OSC 2)
Ceramic oscillator: CSB400P22,
CSB400P (Murata)
Rf = 1 MΩ ± 20%
C1 = C2 = 220 pF ± 5%
Ceramic oscillator: CSB800J122,
CSB800J(Murata)
Rf = 1 MΩ ± 20%
C1 = C2 = 220 pF ± 5%
C1
OSC1
Ceramic
Rf
OSC2
C2
GND
Crystal oscillator
Crystal: 32.768 kHz: MX38T
(Nippon Denpa Kogyo)
Rs = 14 kΩ
C0 = 1.5 pF
C1 = 20 pF ± 20%
C2 = 20 pF ± 20%
C1
X1
Crystal
X2
C2
GND
L
CS RS
C0
Notes: 1. The circuit constants given above are recommended values provided by the oscillator
manufacturer. Since they may be affected by stray capacitances from the oscillator or board,
consult the crystal or ceramic oscillator manufacturer to determine the actual circuit parameters
required.
2. Wiring between the OSC1/OSC2 pins (X1, X2 pins) and other elements must be as short as
possible, and must not cross other wiring. Refer to the recommended layout of the crystal and
ceramic oscillator in figure 22.
3. If a 32.768-kHz crystal oscillator is not used, fix the X1 pin to VCC and leave the X2 pin open.
36
HD404618 Series
Input/Output
The MCU provides 26 input/output pins and 4 input pins, including 10 high-current pins (15 mA, max.). A
program-controlled pull-up MOS transistor is provided for each input/output pin.
The output buffer is turned on and off by the data control register (DCR) during input through an
input/output pin.
I/O pin circuit types are shown in table 19.
D Ports (D 0–D13): Consist of ten 1-bit input/output pins and four input pins. Pins D0–D9 are high-current
I/O pins (15 mA, max.). The sum current of the pins can go up to 100 mA. These pins are set by the SED
and SEDD instructions, reset by the RED and REDD instructions, and tested by the TD and TDD
instructions. Output data is stored in the port data register.
The on/off status of the output buffer is controlled by D port data control registers (DCRB, DCRC, and
DCRD) that are mapped to the memory address area. Pins D10–D13 are input-only pins.
Two operating modes are available to pins D 12 and D13: digital input mode and analog input mode. The
operating modes are set by bits 0 and 1 of port mode register B (PMRB). In the digital input mode, these
pins can be used as input pins with the same input characteristics as the I/O pins. In the analog input mode,
the result of a comparison with the reference voltage can be read as input data. The reference voltage is
input by the D11/VCref pin.
R Ports: Consist of sixteen 4-bit I/O ports. Data is input to these ports by the LAR and LBR instructions
and output from them by the LRA and LRB instructions.
The on/off status of the output buffers of the R ports are controlled by R port data control registers (DCR0–
DCR3) that are mapped to memory addresses.
Pins R00, R01, and R0 2 are multiplexed with pins SCK, SI, and SO, respectively.
Pins R31, R32, and R3 3 are multiplexed with TIMO, INT0, and INT 1, respectively. Refer to figure 24.
Pull-Up MOS Transistor Control: A program-controlled pull-up MOS transistor is provided for each
input/output pin.
The on/off status of all these transistors is controlled by bit 3 of port mode register B (PMRB), and the
on/off status of an individual transistor can also be controlled by the port data register (PDR) of the
corresponding pin. This enables on/off control of each individual pin. Refer to table 20.
The on/off status of each transistor and the peripheral function mode of each pin can be set independently.
How to Deal with Unused I/O Pins: I/O pins that are not needed by the user system must be connected to
VCC to prevent LSI malfunctions due to noise. These pins must either be pulled up to VCC by their pull-up
transistors or by resistors of about 100 kΩ.
37
HD404618 Series
Table 19 Circuit Configurations of I/O Pins
I/O Pin Type
Common I/O pin
(with pull-up MOS
transistor)
Circuit
Applicable Pins
VCC
Pull-up control signal
VCC
DCR
Output data
PDR
D0–D 9
R0 0–R0 3
R1 0–R1 3
R2 0–R2 3
R3 0–R3 3
Input data
Input control signal
SCK
VCC
Pull-up control signal
VCC
DCR
Output data
SCK (internal)
SCK
Output pin (with
pull-up MOS
transistor)
SO, TIMO
VCC
Pull-up control signal
VCC
DCR
Output data
Input pin
SO or TIMO
INT0 , INT1
SI
VCC
PDR
Pull-up control signal
Input data
Input control signal
Input control
VCref
+
–
Input data
Analog input
Mode select signal
Note: Refer to table 20, note 3 concerning R0 2/SO.
38
D10
D11/VCref
D12/COMP0
D13/COMP1
(multiplexed with
analog inputs)
HD404618 Series
Pin
Internal bus
MPX
Comparator
+
–
VC ref
Mode
register
Figure 23 Configuration of D12 and D13
39
HD404618 Series
Serial mode register: $005 (SMR)
SMR
3
2
1
0
Bit 3
Port
selection
0
R0 0
1
SCK
R0 0 /SCK pin mode selection
Port mode register A: $004 (PMRA)
3
2
1
0
R0 2
R01
R3 2
R3 3
PMRA
Port
selection
Bit 3
0
R3 3
1
INT1
PMRA
Bit 2
/SO pin mode selection
/SI pin mode selection
/INT0 pin mode selection
/INT1 pin mode selection
Port
selection
0
R3 2
1
INT0
PMRA
Bit 1
0
1
Port
selection
PMRA
Bit 0
Port
selection
R01
0
R0 2
SI
1
SO
Port mode register B: $012 (PMRB)
3
2
1
0
D12 /COMP0 pin mode selection
D13 /COMP1 pin mode selection
R3 1 /TIMO pin mode selection
Pull-up MOS on/off selection
PMRB
Bit 3
Pull-up
MOS
on/off
0
Off
0
1
On
1
PMRB
Bit 2
Port
selection
PMRB
Bit 1
R3 1
0
D13
0
D12
TIMO
1
COMP1
1
COMP0
Port
selection
PMRB
Figure 24 I/O Switching Mode Registers
40
Bit 0
Port
selection
HD404618 Series
Table 20 Programmable I/O Circuits
PMRB Bit 3 (PMRB3)
0
DCR
0
PDR
0
1
0
1
0
1
0
1
PMOS (A)
—
—
—
On
—
—
—
On
NMOS (B)
—
—
On
—
—
—
On
—
—
—
—
—
—
On
—
On
CMOS Buffer
Pull-up MOS Transistor
1
1
0
1
Notes: 1. —: Off
2. Various I/O methods can be selected by different combinations of settings of the above mode
registers (PMRB3, DCR, PDR).
3. The PMOS (A) transistor of the R1 2/SO pin can be turned off by setting bit 2 of the miscellaneous
register (MIS) to 1.
MIS
Bit 2
R0 2/SO Pin
PMOS (A)
0
On
1
Off
4. The relationships between DCRs and pins are as shown below.
DCR
Bit 3
Bit 2
Bit 1
Bit 0
DCR0
R0 3
R0 2
R0 1
R0 0
DCR1
R1 3
R1 2
R1 1
R1 0
DCR2
R2 3
R2 2
R2 1
R2 0
DCR3
R3 3
R3 2
R3 1
R3 0
DCRB
D3
D2
D1
D0
DCRC
D7
D6
D5
D4
DCRD
—
—
D9
D8
41
HD404618 Series
VCC
PMRB3
VCC
Pull-up
MOS
transistor
PMOS (A)
DCR
NMOS (B)
PDR
Input data
Input control signal
Figure 25 I/O Buffer Configuration
42
HD404618 Series
Timers
The MCU has two prescalers (S and W) and three timer/counters (A, B, and C). Figures 26, 27 and 28
show their diagrams.
Prescaler S: Eleven-bit counter that inputs the system clock signal. After being initialized to $000 by
MCU reset, prescaler S divides the system clock. Prescaler S keeps counting, except at MCU reset and in
the stop and watch modes. Of the prescaler S outputs, timer A input clock, timer B input clock, timer C
input clock, and serial interface transmit clock are selected by timer mode register A (TMA), timer mode
register B (TMB), timer mode register C (TMC), and the serial mode register (SMR), respectively.
Prescaler W: Five-bit counter that inputs the X1 input clock signal divided by eight. Prescaler W output
can be selected as a timer A input clock by timer mode register A (TMA).
Timer A: Eight-bit timer that can be used as a clock time-base (figure 26). It is initialized to $00 and
incremented at each clock input. If an input clock is applied to timer A after it has reached $FF, an
overflow that sets the timer A interrupt request flag (IFTA: $001, bit 2) is generated, and timer A restarts
from $00.
Timer A is used to generate regular interrupts (every 256 clocks) for measuring times between events. It
can also be used as a clock time-base when bit 3 of timer mode register A (TMA) is set to 1. The timer is
driven by the 32-kHz oscillator clock frequency divided by prescaler W, and the clock input to timer A is
controlled by TMA. In this case, prescaler W and timer A can be initialized to $00 by software.
(tsubcyc)
1/4
1/2
fSUB
2 fSUB
Timer A interrupt
request flag
(IFTA)
Prescaler W
(PSW)
÷2
÷8
÷ 16
÷ 32
32.768-kHz
oscillator
1/2 tsubcyc
Clock
Timer
counter A
(TCA) Overflow
System
clock
ø PER
÷2
÷4
÷8
÷ 32
÷ 128
÷ 512
÷ 1024
÷ 2048
Selector
Internal data bus
Selector
Selector
Prescaler S (PSS)
3
Timer mode
register A
(TMA)
Figure 26 Timer A Block Diagram
43
HD404618 Series
Timer B (TCBL and TLRL: $00A, TCBU and TLRU: $00B): Eight-bit write-only timer load register
(TLRL and TLRU) and read-only timer counter (TCBL and TCBU) located at the same addresses. The
eight-bit configuration consists of lower and upper 4-bit digits located at sequential addresses. A block
diagram of timer B is shown in figure 27.
Timer counter B is initialized by writing to timer load register B (TLR). In this case, the lower digit must
be written to first. The contents of TLR are loaded into the timer counter at the same time the upper digit is
written to, initializing the timer counter. TLR is initialized to $00 by MCU reset.
The count of timer B is obtained by reading timer counter B. In this case, the upper digit must be read first;
the count is latched when the upper digit is read.
An auto-reload function, input clock source, and prescaler division ratio of timer B depend on the state of
timer mode register B (TMB). When an external event input is used as the input clock source of TMB, the
R3 3/INT 1 pin must be set to INT 1 by setting port mode register A (PMRA: $004).
Timer B is initialized to the value set in TMB by software, and is then incremented by one each clock
input. If an input is applied to timer B after it has reached $FF, an overflow is generated. In this case, if
the auto-reload function is enabled, timer B is initialized to its initial value; if auto-reload is disabled, the
timer is initialized to $00. The overflow sets the timer B interrupt request flag (IFTB: $002, bit 0).
44
HD404618 Series
Timer B interrupt
request flag
(IFTB)
Timer counter register BU (TCBU)
Timer counter
register BL
(TCBL)
Clock
f
System cyc/fSUB
clock (t /t
cyc subcyc)
÷ 2048
INT1
÷2
÷4
÷8
÷ 32
÷ 128
÷ 512
Selector
Timer load
register BU
(TLRU)
Prescaler S (PSS)
Free-running
control
Timer load
register BL
(TLRL)
Internal data bus
Timer counter B
(TCB)
Overflow
3
Timer mode
register B
(TMB)
Figure 27 Timer B Block Diagram
Timer C (TCCL and TCRL: $00E, TCCU and TCRU: $00F): Eight-bit write-only timer load register
(TCRL and TCRU) and read-only timer counter (TCCL and TCCU) located at the same addresses. The
eight-bit configuration consists of lower and upper 4-bit digits located at sequential addresses. The
operation of timer C is basically the same as that of timer B.
The auto-reload function and prescaler division ratio of timer C depend on the state of timer mode register
C (TMC). Timer C is initialized to the value set in TMC by software, and is then incremented by one at
each clock input. If an input is applied to timer C after it has reached $FF, an overflow is generated. In
this case, if the auto-reload function is enabled, timer C is initialized to its initial value; if auto-reload is
disabled, the timer is initialized to $00. The overflow sets the timer C interrupt request flag (IFTC: $002,
bit 2).
Timer C also functions as a watchdog timer. If a program routine runs out of control and an overflow is
generated while the watchdog on (WDON) flag is set, the MCU is reset. This error can be detected by
having the program control timer C reset before timer C reaches $FF.
The WDON can only have 1 written to it ; it is cleared to 0 only by MCU reset.
Timer Mode Register A (TMA: $008): Four-bit write-only register that controls timer A as shown in
table 21.
45
HD404618 Series
System
reset signal
Watchdog on
flag (WDON)
TIMO
Timer C interrupt
request flag
(IFTC)
Watchdog timer
control logic
Timer output
control logic
Timer counter register CU (TCCU)
Clock
Timer counter C
(TCC)
System fcyc/fSUB
clock (t /t
cyc subcyc)
÷2
÷4
÷8
÷32
÷128
÷512
÷1024
÷2048
Selector
Prescaler S (PSS)
Overflow
Timer load
register CU
(TCRU)
Free-running
/Reload control
Timer load
register CL
(TCRL)
3
Timer mode
register C
(TMC)
Figure 28 Timer C Block Diagram
46
Internal data bus
Timer counter
register CL
(TCCL)
HD404618 Series
Table 21 Timer Mode Register A
TMA
Bit 3
Bit 2
Bit 1
Bit 0
Source Prescaler, Input Clock Period,
Operating Mode
0
0
0
0
PSS, 2048 tcyc
1
PSS, 1024 tcyc
0
PSS, 512 tcyc
1
PSS, 128 tcyc
0
PSS, 32 tcyc
1
PSS, 8 tcyc
0
PSS, 4 tcyc
1
PSS, 2 tcyc
0
PSW, 32 t subcyc
1
PSW, 16 t subcyc
0
PSW, 8 t subcyc
1
PSW, 2 t subcyc
0
PSW, 1/2 tsubcyc
1
Not used
0
PSW, TCA reset
1
1
0
1
1
0
0
1
1
0
1
Timer A mode
Time-base mode
1
Notes: 1. t subcyc = 244.14 µs (when 32.768-kHz crystal oscillator is used)
2. Timer counter overflow output period(s) = input clock period(s) × 256
3. If PSW or TCA reset is selected while the LCD is operating, LCD operation halts (power switch
goes off).
When LCD is connected for display, the PSW and TCA reset periods must be set in the program
to the minimum.
4. In time base mode, the timer counter overflow output cycle must be greater than half of the
interrupt frame period (T/2 = tRC).
If 1/2 tsubcyc is selected, t RC must be 7.8125 ms ((MIS1, MIS0) = (0, 1), see figure 14).
5. The division ratio must not be modified during time-base mode operation, otherwise an overflow
cycle error will occur.
47
HD404618 Series
T × (TCR + 1)
TMC3 = 0
T × 256
T
TMC3 = 1
T × (256 – TCR)
T: Period of clock input to the counter (table 23)
TCR: Value of timer load register C (0–255)
Note: This waveform is always fixed low
when TCR = $FF.
Figure 29 Variable-Duty Pulse Output Waveform
Timer Mode Register B (TMB: $009): Four-bit write-only register that selects the auto-reload function,
the prescaler division ratio, and input clock source as shown in table 22. Timer mode register B is
initialized to $0 by MCU reset.
Writing to this register is valid from the second instruction execution cycle. Timer B initialization set by
writing to TMB must be done after a mode change becomes valid.
Table 22 Timer Mode Register B
TMB
Bit 3
Auto-Reload Function
0
Disabled
1
Enabled
TMB
Bit 2
Bit 1
Bit 0
Prescaler Division Ratio, Clock Input Source
0
0
0
÷ 2048
0
0
1
÷ 512
0
1
0
÷ 128
0
1
1
÷ 32
1
0
0
÷8
1
0
1
÷4
1
1
0
÷2
1
1
1
INT1 (external event input)
48
HD404618 Series
Timer Mode Register C (TMC: $00D): Four-bit write-only register that selects the auto-reload function
and prescaler division ratio as shown in table 23. Timer mode register C is initialized to $0 by MCU reset.
Writing to this register is valid from the second instruction execution cycle. Timer C initialization set by
writing to TMC must be done after a mode change becomes valid.
Table 23 Timer Mode Register C
TMC
Bit 3
Auto-Reload Function
0
Disabled
1
Enabled
TMC
Bit 2
Bit 1
Bit 0
Prescaler Division Ratio, Clock Input Source
0
0
0
÷ 2048
0
0
1
÷ 1024
0
1
0
÷ 512
0
1
1
÷ 128
1
0
0
÷ 32
1
0
1
÷8
1
1
0
÷4
1
1
1
÷2
49
HD404618 Series
Note on Use
When using the timer output as PWM output, note the following point. From the update of the timer write
register untill the occurrence of the overflow interrupt, the PWM output differs from the period and duty
settings, as shown in table 24. The PWM output should therefore not be used until after the overflow
interrupt following the update of the timer write register. After the overflow, the PWM output will have the
set period and duty cycle.
Table 24 PWM Output Following Update of Timer Write Register
PWM Output
Mode
Timer Load Register is Updated during
High PWM Output
Timer load
register
updated to
value N
Free running
Timer Load Register is Updated during
Low PWM Output
Timer load
register
updated to
value N
Interrupt
request
T × (255 – N) T × (N + 1)
Interrupt
request
T × (N' + 1)
T × (255 – N)
Timer load
register
updated to
value N
Reload
T
Interrupt
request
T × (255 – N)
T
Timer load
register
updated to
value N
Interrupt
request
T
T × (255 – N)
50
T × (N + 1)
T
HD404618 Series
Serial Interface
The MCU has a clock-synchronous serial interface which transmits and receives 8-bit data.
The serial interface consists of a serial data register (SR), serial mode register (SMR), port mode register A
(PMRA), octal counter, and multiplexers (see figure 30). The R0 0/SCK pin and the transmit clock are
controlled by writing to the SMR. The transmit clock shifts the contents of the SR, which can be read and
written to by software.
The serial interface is activated by the STS instruction. The octal counter is reset to 000 by this instruction,
starts counting at the falling edge of the transmit clock (SCK), and it increments at the rising edge of the
clock. A serial interrupt request flag is set when the eighth transmit clock signal is input (the serial
interface is reset) or when serial transmission is discontinued (the octal counter is reset).
Octal
counter (OC)
SO
I/O
control
logic
Serial interrupt
request flag
(IFS)
SCK
I/O
control
logic
SI
Clock
Selector
1/2
Transfer
control
signal
Internal data bus
Serial data
register (SR)
Selector
÷2
÷8
÷ 32
÷ 128
÷ 512
÷ 2048
3
System
clock
fcyc/fsub
Prescaler S (PSS)
(tcyc/tsubcyc)
Serial mode
register
(SMR)
Port mode
register A
(PMRA)
Figure 30 Serial Interface Block Diagram
Serial Mode Register (SMR: $005): Four-bit write-only register that controls the R00/SCK pin, prescaler
division ratio, and transmit clock source (table 25 and figure 31). Writing to this register initializes the
serial interface.
51
HD404618 Series
A write signal input to the serial mode register discontinues the input of the transmit clock to the serial data
register and octal counter. Therefore, if a write is performed during data transmission, the octal counter is
reset to 000 to stop transmission, and at the same time, the serial interrupt request flag is set.
Write operations are valid from the second instruction execution cycle, so the STS instruction must be
executed after at least two cycles have been executed. The serial mode register is initialized to $0 by MCU
reset.
Table 25 Serial Mode Register
SMR
Bit 3
R0 0/SCK Pin
0
R0 0 port input/output pin
1
SCK input/output pin
SMR
Transmit Clock
Bit 2
Bit 1
Bit 0
R0 0/SCK Pin
Clock Source
Prescaler
Division Ratio
System Clock
Division Ratio
0
0
0
SCK output
Prescaler
÷ 2048
÷ 4096
0
0
1
SCK output
Prescaler
÷ 512
÷ 1024
0
1
0
SCK output
Prescaler
÷ 128
÷ 256
0
1
1
SCK output
Prescaler
÷ 32
÷ 64
1
0
0
SCK output
Prescaler
÷8
÷ 16
1
0
1
SCK output
Prescaler
÷2
÷4
1
1
0
SCK output
System clock
—
÷1
1
1
1
SCK input
External clock
—
—
PMRA: $004
PMRA3 PMRA2 PMRA1 PMRA0
SMR: $005
SMR3
SMR2
SMR1
SMR0
Transmit clock selection
R0 0 /SCK pin mode selection
R02 /SO pin mode selection
R01 /SI pin mode selection
Figure 31 Configurations and Functions of the Mode Registers
52
HD404618 Series
Serial Data Register (SRL: $006, SRU: $007): Eight-bit read/write register separated into upper and
lower digits located at sequential addresses.
Data in this register is output from the SO pin, LSB first, in synchronism with the falling edge of the
transmit clock, and data is input LSB first through the SI pin at the rising edge of the transmit clock.
Input/output timing is shown in figure 32.
Data cannot be read or written during serial data transmission. If a read/write occurs during transmission,
the accuracy of the resultant data cannot be guaranteed.
Transmit
clock
1
Serial
output
data
2
3
4
5
LSB
6
7
8
MSB
Serial input
data
latch timing
Figure 32 Serial Interface Timing
Selecting and Changing Operating Mode: Table 26 lists the serial interface operating modes. To select
an operating mode, use one of these combinations of PMR and SMR settings; to change the operating
mode, always initialize the serial interface internally by writing to the SMR.
Table 26 Serial Interface Operating Modes
SMR
PMRA
Bit 3
Bit 1
Bit 0
Operating Mode
1
0
0
Continuous clock output mode
1
0
1
Transmit mode
1
1
0
Receive mode
1
1
1
Transmit/receive mode
Serial Interface Operation: Three operating modes are provided for the serial interface; transitions
between them are shown in figure 33.
In STS waiting state, the serial interface is initialized and the transmit clock is ignored. If the STS
instruction is then executed, the serial interface enters transmit clock wait state.
In transmit clock wait state, input of the transmit clock increments the octal counter, shifts the serial clock
register, and activates serial transmission. However, note that if clock output mode is selected, the transmit
clock is continuously output but data is not transmitted.
53
HD404618 Series
During transmission, the input of eight clocks or the execution of the STS instruction sets the octal counter
to 000, and the serial interface enters transmit clock wait state. If the state changes from transmit to another
state, the serial interrupt request flag is set by the octal counter reaching 000.
STS instruction wait state
ST
S
SM
R
ins
tru
cti
on
ite
wr )
R
1
←
SM
al
S
rn
(IF
te
(in
s
ck 1)
clo ←
it S
m IF
ns (
tra )
8 ock
cl
wr
i te
octal counter = 000
transmit clock disabled
Transmit clock
Transmit clock wait state
Transfer state
8 transmit clocks (external clock)
(octal counter = 000)
STS instruction
(octal counter ≠ 000)
(IFS ← 1)
Figure 33 Serial Interface Mode Transitions
In this state, if the internal clock has been selected, the transmit clock is output in answer to the execution
of the STS instruction, but serial transmission is inhibited after the eighth clock is output.
If port mode register A (PMRA) is written to in transmit clock wait state or during transmission, the serial
mode register (SMR) must be written to, to initialize the serial interface. The serial interface then enters
STS wait state.
If the serial interface shifts from transfer state to another state, the octal counter returns to 000, setting the
serial interrupt request flag.
Transmit Clock Error Detection: The serial interface will malfunction if a spurious pulse caused by
external noise conflicts with a normal transmit clock during transmission. A transmit clock error of this
type can be detected as shown in figure 34.
If more than eight transmit clocks are input in transmit clock wait state, the serial interface state changes to
transfer, transmit clock wait, then back to transfer.
If the serial interface is set to STS wait state by writing data to the SMR after the serial interrupt request
flag has been reset, the flag is set again.
54
HD404618 Series
Transmission completion
(IFS ←1)
Interrupts
inhibited
IFS ← 0
SMR write
IFS = 1 ?
Yes
Transmit clock
error processing
No
Normal termination
Figure 34 Transmit Clock Error Detection
Note on Use: The serial interrupt request flag might not be set if the status is changed from transfer by the
execution of an SMR write or STS instruction during the first period that the transmit clock is low. To
prevent this, program a check that the SCK pin is at 1 (by executing an input instruction for the R1 port)
before the execution of an SMR write or STS instruction, to ensure that the serial interrupt request flag is
set.
55
HD404618 Series
Liquid Crystal Display (LCD)
The MCU has an LCD controller and driver which drive 4 common signal pins and 32 segment signal pins.
The controller consists of a RAM area in which display data is stored, a display control register (LCR), and
a duty/clock control register (LMR), as shown in figure 37.
Four duties and the LCD clock are program-controllable, and a built-in dual-port RAM ensures that display
data can be automatically transmitted to the segment signal pins without program intervention. If a 32-kHz
oscillation clock is selected as the LCD clock source, the LCD can be used even in watch mode, in which
the system clock stops.
V CC
Power switch
V1
V2
V3
COM1
LCD
common
driver
LCD
power
control
circuit
COM2
COM3
COM4
LCD
clock
Display on/off
GND
SEG1
1 2
LCD
control
register
(LCR: $013)
SEG2
$050
Display
area
(Dual-port
RAM)
LCD
segment
driver
LCD duty/clock $06F
control
register
(LMR: $014)
2
2
SEG32
RAM area
Duty cycle selection
Clock selection
LCD
clock
3
LCD: Liquid crystal display
Divided system clock
output (CL1–CL3)
1 Divided 32-kHz clock
output (CL0)
Figure 35 Liquid Crystal Display Block Diagram
LCD Data Area and Segment Data ($050– $06F): Figure 36 shows the configuration of LCD RAM
area. Each bit of the storage area corresponds to one of four types of duties. If data is written to an area
corresponding to a certain duty cycle, it is automatically output to the corresponding segments as display
data.
56
HD404618 Series
Bit 3
Bit 2
Bit 1
Bit 0
Bit 3
Bit 2
Bit 1
Bit 0
80
SEG1
SEG1
SEG1
SEG1
$050
96
SEG17
SEG17
SEG17
SEG17
$060
81
SEG2
SEG2
SEG2
SEG2
$051
97
SEG18
SEG18
SEG18
SEG18
$061
82
SEG3
SEG3
SEG3
SEG3
$052
98
SEG19
SEG19
SEG19
SEG19
$062
83
SEG4
SEG4
SEG4
SEG4
$053
99
SEG20
SEG20
SEG20
SEG20
$063
84
SEG5
SEG5
SEG5
SEG5
$054
100
SEG21
SEG21
SEG21
SEG21
$064
85
SEG6
SEG6
SEG6
SEG6
$055
101
SEG22
SEG22
SEG22
SEG22
$065
86
SEG7
SEG7
SEG7
SEG7
$056
102
SEG23
SEG23
SEG23
SEG23
$066
87
SEG8
SEG8
SEG8
SEG8
$057
103
SEG24
SEG24
SEG24
SEG24
$067
88
SEG9
SEG9
SEG9
SEG9
$058
104
SEG25
SEG25
SEG25
SEG25
$068
89
SEG10
SEG10
SEG10
SEG10
$059
105
SEG26
SEG26
SEG26
SEG26
$069
90
SEG11
SEG11
SEG11
SEG11
$05A
106
SEG27
SEG27
SEG27
SEG27
$06A
91
SEG12
SEG12
SEG12
SEG12
$05B
107
SEG28
SEG28
SEG28
SEG28
$06B
92
SEG13
SEG13
SEG13
SEG13
$05C
108
SEG29
SEG29
SEG29
SEG29
$06C
93
SEG14
SEG14
SEG14
SEG14
$05D
109
SEG30
SEG30
SEG30
SEG30
$06D
94
SEG15
SEG15
SEG15
SEG15
$05E
110
SEG31
SEG31
SEG31
SEG31
$06E
95
SEG16
SEG16
SEG16
SEG16
$05F
111
SEG32
SEG32
SEG32
SEG32
$06F
COM4
COM3
COM2
COM1
COM4
COM3
COM2
COM1
Figure 36 Configuration of LCD RAM Area
LCD Control Register (LCR: $013): Three-bit write-only register which controls LCD blanking, the
turning on and off of the LCD’s power supply division resistor, and display in watch and subactive modes
(see table 27).
• Blank/display
Blank: Segment signals are turned off regardless of LCD RAM data setting.
Display: LCD RAM data is output as segment signals.
• Power switch on/off
Off: The power switch is off.
On: The power switch is on and V1 is VCC.
• Watch/subactive mode display
Off: In watch and subactive modes, all common and segment pins are grounded and the liquid crystal
power switch is turned off.
On: In watch and subactive modes, LCD RAM data is output as segment signals.
57
HD404618 Series
Table 27 LCD Control Register
LCR
LCR
LCR
Bit 2
Display in
Watch Mode or
Subactive Mode Bit 1
Power Switch
On/Off
Bit 0
Blank/Display
0
Off
0
Off
0
Blank
1
On
1
On
1
Display
Note: When using an LCD in watch mode or subactive mode, use the divided output of a 32-kHz oscillator
as the LCD clock and set bit 2 of the LCR to 1. If using the divided output of the system clock as the
LCD clock, always set bit 2 of the LCR to 0.
LCD Duty/Clock Control Register (LMR: $014): Four-bit write-only register which selects the display
duty and LCD clock source, as shown in table 28.
Table 28 LCD Duty/Clock Control Register
LMR
Bit 3
Bit 2
Bit 1
Bit 0
Duty Selection/Input Clock Selection
—
—
0
0
1/4 duty cycle
—
—
0
1
1/3 duty cycle
—
—
1
0
1/2 duty cycle
—
—
1
1
Static
0
0
—
—
CL0 (32.768/64 kHz when using 32.768-kHz oscillator)
0
1
—
—
CL1 (fcyc/256)
1
0
—
—
CL2 (fcyc/2048)
1
1
—
—
CL3 (refer to table 29)
Note: fcyc is the divided system clock output.
58
HD404618 Series
LCD control register: $013 (LCR)
2
1
0
Blank/display
Power switch on/off
Display on/off in watch mode
(not used)
LCD duty/clock control register: $014 (LMR)
3
2
1
0
Duty cycle
Input clock
Figure 37 LCD Control and LCD Mode Registers
59
HD404618 Series
Table 29 LCD Frame Periods for Different Duties
Static Duty
LMR
Instruction
cycle time
Bit 3
0
Bit 2
0
Bit 3
0
Bit 2
1
Bit 3
1
Bit 2
0
Bit 3
1
CL0
CL1
CL2
CL3*
10 µs
512 Hz
390.6 Hz
48.8 Hz
24.4 Hz/64 Hz
5 µs
512 Hz
781.2 Hz
97.6 Hz
48.8 Hz/64 Hz
1/2 Duty
LMR
Instruction
cycle time
Bit 3
0
Bit 2
0
Bit 3
0
Bit 2
1
Bit 3
1
Bit 2
0
Bit 3
1
CL0
CL1
CL2
CL3*
10 µs
256 Hz
195.3 Hz
24.4 Hz
12.2 Hz/32 Hz
5 µs
256 Hz
390.6 Hz
48.8 Hz
24.4 Hz/32 Hz
1/3 Duty
LMR
Instruction
cycle time
Bit 3
0
Bit 2
0
Bit 3
0
Bit 2
1
Bit 3
1
Bit 2
0
Bit 3
1
CL0
CL1
CL2
CL3*
10 µs
170.6 Hz
130.2 Hz
16.3 Hz
8.1 Hz/21.3 Hz
5 µs
170.6 Hz
260.4 Hz
32.6 Hz
16.2 Hz/21.3 Hz
1/4 Duty
LMR
Instruction
cycle time
Bit 3
0
Bit 2
0
Bit 3
0
Bit 2
1
Bit 3
1
Bit 2
0
Bit 3
1
CL0
CL1
CL2
CL3*
10 µs
128 Hz
97.7 Hz
12.2 Hz
6.1 Hz/16 Hz
5 µs
128 Hz
195.4 Hz
24.4 Hz
12.2 Hz/16 Hz
Bit 2
1
Bit 2
1
Bit 2
1
Bit 2
1
Note: * The division ratio depends on the value of bit 3 of timer mode register A (TMA3): The first value is
for TMA3 = 0 and the second is for TMA3 = 1.
When TMA3 = 0, CL3 = f cyc × duty cycle/4096.
When TMA3 = 1, CL3 = 32.768 kHz × duty cycle/512
60
HD404618 Series
Large Liquid-Crystal Panel Drive and VLCD : To drive a large-capacity LCD, decrease the resistance of
the built-in division resistors by attaching external resistors in parallel, as shown in figure 38.
The size of these resistors cannot be simply calculated from the LCD load capacitance because the matrix
configuration of the LCD complicates the paths of charge/discharge currents flowing through the
capacitors. The resistance will also vary with lighting conditions. This size must be determined by trial
and error, taking into account the power dissipation of the device using the LCD, but a resistance of 1 to 10
kΩ would usually be suitable. (Another effective method is to attach capacitors of 0.1 to 0.3 µF.)
Always turn off the power switch (set bit 1 of the LCR to 0) before changing the liquid crystal drive
voltage (VLCD).
VCC (V1 )
VCC (V1 )
R
R
C
V2
V2
R
R
V3
C
V3
C
R
C = 0.1 to 0.3 µF
R
GND
GND
VCC
VCC
VLCD
COM1
.
V1
SEG1
V2
to
V3
SEG32
GND
4-digit LCD
with sign
32
Static drive
VCC
VCC
VCC
VLCD
COM1
COM2
2
.
V1
SEG1
V2
to
V3
SEG32
GND
8-digit LCD
32
1/2 duty cycle, 1/2 bias drive
3
10-digit LCD
VCC COM1
to
. with sign
COM3
V
1
VLCD
V2
SEG1
to
V3
GND SEG32
32
1/3 duty cycle, 1/3 bias drive
VCC
VCC
VCC ≥ V LCD ≥ GND
VLCD
COM1
to
COM4
4
V1
V2
SEG1
to
V3
GND SEG32
.
16-digit LCD
32
1/4 duty cycle, 1/3 bias drive
Figure 38 LCD Connection Examples
61
HD404618 Series
DTMF Generation Circuit
The MCU has a dual-tone multifrequency (DTMF) generation circuit.
The DTMF signal consists of two sine waves to access the switching system.
Figure 39 shows the DTMF keypad and frequencies. Pressing a key generates a tone corresponding to its
frequency. Figure 40 shows a block diagram of the DTMF circuit.
The MCU uses an oscillation frequency reduced to 400 kHz, an eighth of the conventionally used
frequency, for low-power consumption. This, however, causes a potential frequency deviation. The MCU
provides transformed programmable dividers in addition to sine wave counters and a control register to
reduce frequency deviation.
1
2
3
A
R1 (697 Hz)
4
5
6
B
R2 (770 Hz)
7
8
9
C
R3 (852 Hz)
*
0
#
D
R4 (941 Hz)
C1 (1209 Hz)
C2 (1336 Hz)
C3 (1477 Hz)
C4 (1633 Hz)
The DTMF generation circuit is controlled by the following three registers.
Figure 39 DTMF Keypad and Frequencies
62
HD404618 Series
400 kHz (selected at TGSP reset)
800 kHz
Transformed
programmable
divider
Sine wave
counter D/A
TONER
Feedback
TGSP
flag
DTMF
register
VTref
Transformed
programmable
divider
Sine wave
counter D/A
TONEC
Feedback
Figure 40 DTMF Circuit Block Diagram
Tone Generator Mode Register (TGM: $010): Four-bit write-only register which controls output
frequencies (see table 30). It is cleared to $0 by MCU reset.
Table 30 Tone Generator Mode Register
TGM
Bit 3
Bit 2
Option
(TONER output
is not affected)
Bit 1
Bit 0
Output Frequencies
0
0
f R1 (697 Hz)
0
1
f R2 (770 Hz)
1
0
f R3 (852 Hz)
1
1
f R4 (941 Hz)
0
0
Option
(TONEC output is not affected)
f C1 (1,209 Hz)
0
1
f C2 (1,336 Hz)
1
0
f C3 (1,477 Hz)
1
1
f C4 (1,633 Hz)
Output through
TONER pin
Output through
TONEC pin
Tone Generator Control Register (TGC: $011): Three-bit write-only register which controls the start
and stop of DTMF signal output (see table 31). It is cleared to $0 by MCU reset.
63
HD404618 Series
Table 31 Tone Generator Control Register
TGC
Bit 1
DTMF Enable Bit
0
DTMF disabled
1
DTMF enabled
TGC
Bit 2
TONER Output Control (row)
0
Stopped
1
TONER output (active)
TGC
Bit 3
TONEC Output Control (column)
0
Stopped
1
TONEC output (active)
Tone Generator Speed Flag (TGSP: $020,Bit 2): One-bit register which can be set and reset by the
SEM/REM and SEMD/REMD instructions. The DTMF generation circuit generates output frequencies
with a 400-kHz clock (table 30). With an 800-kHz clock, the DTMF generation circuit generates these
same frequencies by pulling the TGSP flag high.
DTMF Output: The sine waves of the row-group and column-group are individually converted from
digital to analog in the D/A conversion circuit, which provides high-precision ladder resistance. The
DTMF output pins, TONER and TONEC, transmit the sine waves of the row-group and column-group,
respectively. Figure 41 shows thetone output equivalent circuit. Figure 42 shows the output waveform.
One cycle of this wave consists of 32 time slots, making the output waveform stable with little distortion.
Table 32 lists the frequency deviation of the MCU from standard DTMF signals.
Switch control
VT ref
GND
TONER
TONEC
Figure 41 Tone Output Equivalent Circuit
64
HD404618 Series
VT ref
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
GND
Time slots
Figure 42 Waveform of Tone Output
Table 32 Frequency Deviation of the MCU from Standard DTMF Signals
Standard
DTMF (Hz)
MCU (Hz)
Deviation from
Standard (%)
R1
697
694.44
–0.37
R2
770
769.23
–0.10
R3
852
851.06
–0.11
R4
941
938.97
–0.22
C1
1,209
1,212.12
0.26
C2
1,336
1,333.33
–0.20
C3
1,477
1,481.48
0.30
C4
1,633
1,639.34
0.39
Note: This frequency deviation value does not include the frequency deviation due to the oscillator
element. Also note that in this case the ratio of the high level and low level widths in the oscillator
waveform due to the oscillator element will be 50% : 50%.
65
HD404618 Series
Programmable ROM
The HD4074618 is a ZTAT microcomputer with built-in PROM that can be programmed in PROM
mode.
PROM Mode Pin Description
Pin Number
MCU Mode
FP-80A,
FP-80B TFP-80
Pin Name
Pin
I/O Name
I/O
FP-80A, Pin Name
FP-80B TFP-80
I/O
Pin
Name I/O
1
79
D2
I/O O2
I/O
28
26
R2 3
I/O
A12
I
2
80
D3
I/O O3
I/O
29
27
R3 0
I/O
A13
I
3
1
D4
I/O O4
I/O
30
28
R3 1/TIMO I/O
A14
I
4
2
D5
I/O O5
I/O
31
29
R3 2/INT0
I/O
CE
I
5
3
D6
I/O O6
I/O
32
30
R3 3/INT1
I/O
OE
I
6
4
D7
I/O O7
I/O
33
31
SEG1
O
7
5
D8
I/O
34
32
SEG2
O
8
6
D9
I/O
35
33
SEG3
O
9
7
D10
I
VPP
36
34
SEG4
O
10
8
D11/VCref
I
A9
I
37
35
SEG5
O
11
9
D12/COMP0
I
M0
I
38
36
SEG6
O
12
10
D13/COMP1
I
M1
I
39
37
SEG7
O
13
11
TEST
I
TEST
I
40
38
SEG8
O
14
12
X1
I
GND
41
39
SEG9
O
15
13
X2
O
42
40
SEG10
O
16
14
GND
43
41
SEG11
O
17
15
R0 0/SCK
I/O A1
I
44
42
SEG12
O
18
16
R0 1/SI
I/O A2
I
45
43
SEG13
O
19
17
R0 2/SO
I/O A3
I
46
44
SEG14
O
20
18
R0 3
I/O A4
I
47
45
SEG15
O
21
19
R1 0
I/O A5
I
48
46
SEG16
O
22
20
R1 1
I/O A6
I
49
47
SEG17
O
23
21
R1 2
I/O A7
I
50
48
SEG18
O
24
22
R1 3
I/O A8
I
51
49
SEG19
O
25
23
R2 0
I/O A0
I
52
50
SEG20
O
26
24
R2 1
I/O A10
I
53
51
SEG21
O
27
25
R2 2
I/O A11
I
54
52
SEG22
O
66
PROM Mode
GND
Pin Number
MCU Mode
PROM
Mode
HD404618 Series
Pin Number
MCU Mode
PROM Mode
FP-80A,
FP-80B TFP-80
Pin Name
Pin
I/O Name
55
53
SEG23
O
68
66
COM4
56
54
SEG24
O
69
67
V1
57
55
SEG25
O
70
68
V2
58
56
SEG26
O
71
69
V3
59
57
SEG27
O
72
70
TONEC O
60
58
SEG28
O
73
71
TONER O
61
59
SEG29
O
74
72
VT ref
VCC
62
60
SEG30
O
75
73
VCC
VCC
63
61
SEG31
O
76
74
OSC 1
I
64
62
SEG32
O
77
75
OSC 2
O
65
63
COM1
O
78
76
RESET I
66
64
COM2
O
79
77
D0
I/O O0
I/O
67
65
COM3
O
80
78
D1
I/O O1
I/O
I/O
Pin Number
MCU Mode
FP-80A,
FP-80B TFP-80
Pin
Name
PROM Mode
Pin
I/O Name
I/O
O
VCC
VCC
RESET
I
67
HD404618 Series
Programming the Built-in PROM
The MCU’s built-in PROM is programmed in PROM mode which is set by pulling TEST, M0, and M1 low,
and RESET high, as shown in figure 43. In PROM mode, the MCU does not operate, but it can be
programmed in the same way as any other commercial 27256 EPROM using a standard PROM
programmer and a 80-to-28-pin socket adaptor. Recommended PROM programmers and socket adapters
are listed in table 34.
Since an HMCS400-series instruction is ten bits long, the HMCS400-series MCU has a built-in conversion
circuit to enable use of a general-purpose PROM programmer. This circuit splits each instruction into a
lower 5 bits and an upper 5 bits that are read from or written to consecutive addresse. This means that if,
for example, 8 kwords of built-in PROM are to be programmed by a general-purpose PROM programmer,
a 16-kbyte address space ($0000–$3FFF) must be specified.
Programming and Verification: The built-in PROM of the MCU can be programmed at high-speed
programming sequence without risk of voltage stress or damage to data reliability.
For details of PROM programming, refer to the notes on PROM Programming section.
Warnings
1. Always specify addresses $0000 to $3FFF when programming with a PROM programmer. If address
$4000 or higher is accessed, the PROM may not be programmed or verified correctly. Set all data in
unused addresses to $FF.
Note that the plastic-package version cannot be erased and reprogrammed.
2. Make sure that the PROM programmer, socket adapter, and LSI are aligned correctly (their pin 1
positions match), otherwise overcurrents may damage the LSI. Before starting programming, make
sure that the LSI is firmly fixed in the socket adapter and the socket adapter is firmly fixed onto the
programmer.
3. PROM programmers have two voltages (Vpp): 12.5 V and 21 V. Remember that ZTAT devices
require a VPP of 12.5 V—the 21-V setting will damage them. 12.5 V is the Intel’s 27256 setting.
Table 33 PROM Mode Selection
Pin
Mode
CE
OE
VPP
O0–O7
Programming
Low
High
VPP
Data input
Verification
High
Low
VPP
Data output
Programming inhibition
High
High
VPP
High impedance
68
HD404618 Series
Table 34 Recommended PROM Programmers and Socket Adapters
PROM Programmer
Socket Adapter
Manufacturer
Model Name
Manufacturer
Model Name
Package
DATA I/O Corp.
121B
29B
Hitachi
HS460ESF01H
FP-80B
HS460ESH01H
FP-80A
HS461EST01H
TFP-80
HS460ESF01H
FP-80B
HS460ESH01H
FP-80A
HS461EST01H
TFP-80
AVAL Corp.
PKW-1000
Hitachi
VCC
VCC
VCC
RESET
TEST
M0
M1
VPP
D10 /VPP
O0–O7
Data
O0 to O7
A0–A 14
Address
A0 to A14
VCC
OSC1
VTref
V3
OE
OE
CE
CE
X1
GND
Figure 43 Connections for PROM Mode
69
HD404618 Series
Addressing Modes
RAM Addressing Modes
The MCU has three RAM addressing modes, as shown in figure 44 and described below.
Register Indirect Addressing Mode: The contents of the W, X, and Y registers (10 bits in total) are used
as a RAM address.
Direct Addressing Mode: A direct addressing instruction consists of two words. The first word contains
the opcode, and the contents of the second word (10 bits) are used as a RAM address.
Memory Register Addressing Mode: The memory registers (MR), consisting of 16 digits from $040 to
$04F, are accessed with the LAMR and XMRA instructions.
W register
W1 W0
RAM address
X register
X3
X2
X1
Y register
X0
Y3
Y2
Y1
Y0
AP9 AP8 AP7 AP6 AP5 AP4 AP3 AP2 AP1 AP0
Register Indirect Addressing
1st word of instruction
Opcode
2nd word of instruction
d
RAM address
9
d8
d7
d6
d5
d4
d3
d2
d1
d0
AP9 AP8 AP7 AP6 AP5 AP4 AP3 AP2 AP1 AP0
Direct Addressing
Instruction
Opcode
0
RAM address
0
0
1
0
m1
m0
0
AP9 AP8 AP7 AP6 AP5 AP4 AP3 AP2 AP1 AP0
Memory Register Addressing
Figure 44 RAM Addressing Modes
70
m3 m2
HD404618 Series
ROM Addressing Modes and the P Instruction
The MCU has four ROM addressing modes, as shown in figure 45 and described below.
Direct Addressing Mode: A program can branch to any address in the ROM memory space by executing
the JMPL, BRL, or CALL instruction. Each of these instructions replaces the 14 program counter bits
(PC 13–PC0) with 14-bit immediate data.
Current Page Addressing Mode: The MCU has 32 pages of ROM with 256 words per page. A program
can branch to any address in the current page by executing the BR instruction. This instruction replaces the
eight low-order bits of the program counter (PC7–PC0) with eight-bit immediate data. If the BR instruction
is on a page boundary (address 256n + 255), executing that instruction transfers the PC contents to the next
physical page, as shown in figure 46. This means that the execution of the BR instruction on a page
boundary will make the program branch to the next page.
Note that the HMCS400-series cross macro-assembler has an automatic paging feature for ROM pages.
Zero-Page Addressing Mode: A program can branch to the zero-page subroutine area located at $000–
$003F by executing the CAL instruction. When the CAL instruction is executed, 6 bits of immediate data
are placed in the six low-order bits of the program counter (PC5–PC0), and 0s are placed in the eight highorder bits (PC13–PC6).
Table Data Addressing Mode: A program can branch to an address determined by the contents of fourbit immediate data, the accumulator, and the B register by executing the TBR instruction.
P Instruction: ROM data addressed in table data addressing mode can be referenced with the P instruction
as shown in figure 47. If bit 8 of the ROM data is 1, eight bits of ROM data are written to the accumulator
and the B register. If bit 9 is 1, eight bits of ROM data are written to the R1 and R2 port output registers.
If both bits 8 and 9 are 1, ROM data is written to the accumulator and the B register, and also to the R1 and
R2 port output registers at the same time.
The P instruction has no effect on the program counter.
71
HD404618 Series
1st word of instruction
[JMPL]
[BRL]
[CALL]
Opcode
p3
Program counter
2nd word of instruction
p2
p1
p0
d9
d8
d7
d6
d5
d4
d3
d2
d1
d0
PC13 PC12 PC11 PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0
Direct Addressing
Instruction
[BR]
Program counter
Opcode
b6
b7
b5
b4
b3
b2
b1
b0
PC13 PC12 PC11 PC10 PC 9 PC 8 PC7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0
Current Page Addressing
Instruction
[CAL]
0
Program counter
0
0
a5
Opcode
0
0
0
0
a4
a3
a2
a1
a0
0
PC13 PC12 PC11 PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0
Zero Page Addressing
Instruction
[TBR]
Opcode
P3
P2
P1
P0
B register
B3
0
Program counter
B0
A3
A2
A1
A0
0
PC13 PC12 PC11 PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0
Table Data Addressing
Figure 45 ROM Addressing Modes
72
B2 B1
Accumulator
HD404618 Series
256 (n – 1) + 255
BR AAA
256 n
AAA NOP
BR AAA
BR BBB
256 n + 254
256 n + 255
256 (n + 1)
BBB NOP
Figure 46 Page Boundary between BR Instruction and Branch Destination
73
HD404618 Series
Instruction
[P]
p3
Opcode
p2
p1
p0
B register
B3
0
B2 B1
Accumulator
B0
A3
A2
A1
A0
0
Referred ROM address RA13 RA12 RA11 RA10 RA 9 RA 8 RA 7 RA 6 RA 5 RA 4 RA 3 RA 2 RA 1 RA 0
Address Specification
ROM data
RO9 RO8 RO7 RO6 RO5 RO4 RO3 RO2 RO1 RO0
Accumulator, B register
ROM data
B3
B2
B1
B0
A3 A
A1
A
0
If RO 8 = 1
RO9 RO8 RO7 RO6 RO5 RO4 RO3 RO2 RO1 RO0
Output registers R1, R2
R23 R22 R21 R20 R13 R12 R11 R10
Pattern Output
Figure 47 P Instruction
74
2
If RO 9 = 1
HD404618 Series
Absolute Maximum Ratings
Item
Symbol
Value
Unit
Supply voltage
VCC
–0.3 to +7.0
V
Programming voltage
VPP
–0.3 to +14.0
V
Pin voltage
VT
–0.3 to (VCC + 0.3)
V
Total permissible input current
∑IO
100
mA
2
Total permissible output current
–∑IO
50
mA
3
Maximum input current
IO
4
mA
4, 5
30
mA
4, 6
7, 8
Maximum output current
–I O
4
mA
Operating temperature
Topr
–20 to +75
°C
Storage temperature
Tstg
–55 to +125
°C
Notes
1
Notes: Permanent damage may occur if these absolute maximum ratings are exceeded. Normal operation
must be under the conditions stated in the electrical characteristics tables. If these conditions are
exceeded, the LSI may malfunction or its reliability may be affected.
1. D10 (VPP) of the HD4074618.
2. Total permissible input current is the total of input currents simultaneously flowing in from all the
I/O pins to GND.
3. Total permissible output current is the total of output currents simultaneously flowing out from V CC
to all I/O pins.
4. The maximum input current is the maximum current flowing from any I/O pin to ground.
5. Applies to R0–R3
6. Applies to D 0–D 9
7. The maximum output current is the maximum current flowing from V CC to any I/O pin.
8. Applies to D 0–D 9, R0–R3
75
HD404618 Series
Electrical Characteristics (Please inquire about the characteristics of HD404612,
HD404614, HD404616, and HD404618 at VCC = 2.2 V)
DC Characteristics (HD404612, HD404614, HD404616, HD404618: VC C = 2.7 V to 6.0 V;
HD4074618: V CC = 3.0 V to 5.5 V, GND = 0.0 V, Ta = –20 to +75°C, unless otherwise specified)
Max
Test
Unit Condition
0.9V CC
VCC + 0.3
V
OSC 1
VCC – 0.3
VCC + 0.3
V
SI
0.9V CC
VCC + 0.3
V
RESET, SCK,
INT0, INT1
–0.3
0.1V CC
V
OSC 1
–0.3
0.3
V
SI
–0.3
0.1V CC
V
VCC – 1.0
Item
Symbol
Pin(s)
Min
Input high
voltage
VIH
RESET, SCK,
INT0, INT1
Input low
voltage
VIL
Output high
voltage
VOH
SCK, TIMO, SO
Output low
voltage
VOL
SCK, TIMO, SO
I/O leakage
current
|IIL|
RESET, SCK,
INT0, INT1, SI,
SO, TIMO, OSC1
Stop mode
retaining
voltage
VSTOP
VCC
Typ
Notes
External clock
operation
External clock
operation
V
–I OH = 0.5 mA
0.4
V
I OL = 0.4 mA
1
µA
Vin = 0 to VCC 1
V
No 32-kHz
oscillator
2
7
Current
I CC1
dissipation in
VCC
400
1000
µA
VCC = 3 V
2
f OSC = 400 kHz
active mode
I CC2
VCC
500
1500
µA
VCC = 3 V
3
DTMF: active
f OSC = 400 kHz
I CC3
VCC
1
2
mA
4
VCC = 3 V
f OSC = 400 kHz
D12, D13
analog input
mode
I SBY
Current
dissipation in
standby
mode
VCC
200
500
µA
VCC = 3 V
5
LCD on
f OSC = 400 kHz
Current
I STOP
dissipation in
stop mode
VCC
1
10
µA
VCC = 3 V
No 32-kHz
oscillator
76
HD404618 Series
Item
Symbol
Pin(s)
Current
dissipation in
subactive
mode
I SUB
VCC
Min
Typ
Max
Test
Unit Condition
50
100
µA
35
70
µA
VCC = 3 V
LCD on
6
I WTC1
Current
dissipation in
watch mode
(1)
VCC
5
15
µA
VCC = 3 V
LCD off
I WTC2
Current
dissipation in
watch mode
(2)
VCC
15
35
µA
VCC = 3 V
LCD on
—
VCC – 1.2
V
Comparator
input
reference
voltage
scope
VC ref
VC ref
0
Notes
Notes: 1. Output buffer current is excluded.
2. I CC is the source current when no I/O current is flowing while the MCU is in reset state.
Test conditions:
MCU: Reset
Pins: RESET, TEST at V CC
3. I SBY is the source current when no I/O current is flowing while the MCU timer is in operation.
Test conditions:
D12, D13 in digital input mode
DTMF in operation (excludes current flowing from VTref to GND)
4. Pins D 12 and D 13 are in analog input mode and I/O current is not flowing.
Test conditions:
VC ref/D11 , COMP0/D12 , COMP1/D13 at GND
DTMF stopped
5. Timer is in operation and I/O current is not flowing.
Test conditions:
MCU:
I/O in reset state
Serial interface stopped
D12, D13 in digital input mode
DTMF stopped
Stanby mode
Pins :
RESET at GND
TEST at V CC
6. Applies only to HD404612, HD404614, HD404616, and HD404618.
7. RAM data retention.
77
HD404618 Series
I/O Characteristics for Standard Pins (HD404612, HD404614, HD404616, HD404618: VCC = 2.7 V to
6.0 V; HD4074618: V CC = 3.0 V to 5.5 V, GND = 0.0 V, Ta = –20 to +75°C, unless otherwise specified)
Item
Symbol Pin(s)
Min
Typ
Max
Input high
voltage
VIH
Input low
voltage
Output high
voltage
D10–D 13 ,
R0– R3
0.7V CC
—
VCC + 0.3
V
VIL
D10–D 13 ,
R0–R3
–0.3
—
0.3V CC
V
VOH
R0–R3
VCC – 1.0 —
—
–I OH = 0.5 mA
V
Pull-up MOS –I PU
current
R0–R3
5
90
VCC = 3 V,
µA
Output low
voltage
VOL
R0–R3
—
—
0.4
I OL = 0.4 mA
V
I/O leakage
current
|IIL|
D11 to D13 ,
R0 to R3
—
—
1
HD404612,
HD404614
HD404616,
HD404618:
Vin = 0 V to VCC
µA
1
D10
—
—
20
HD4074618:
Vin = 0 V to VCC
µA
2
40
Test Conditions
Unit Notes
Vin = 0 V
Input high
voltage
VIHA
D12, D13
VC ref+
0.1
(analog
compare mode)
—
—
V
Input low
voltage
VILA
D12, D13
—
(analog
compare mode)
—
VC ref – 0.1
V
Note:
78
1. Output buffer current is excluded.
2. The Max value for the HD404618, HD404616, HD404614, and HD404612 is 1µA.
HD404618 Series
I/O Characteristics for High-Current Pins (HD404612, HD404614, HD404616, HD404618: VCC = 2.7
V to 6.0 V; HD4074618: VCC = 3.0 V to 5.5 V, GND = 0 V, T a = –20 to +75°C, unless otherwise
specified)
Item
Symbol
Pin(s)
Min
Typ
Max
Input high
voltage
VIH
D0–D 9
0.7V CC
—
VCC + 0.3
V
Input low
voltage
VIL
D0–D 9
–0.3
—
0.3V CC
V
Output high
voltage
VOH
D0–D 9
VCC – 1.0 —
Pull-up MOS
current
–I PU
D0–D 9
5
40
Output low
voltage
VOL
D0–D 9
—
I/O leakage
current
|IIL|
D0–D 9
Test Conditions Unit Notes
–I OH = 0.5 mA
V
90
VCC = 3 V,
Vin = 0 V
µA
—
2.0
I OL = 15 mA
V
VCC = 4.5 V to 6 V
—
—
0.4
I OL = 0.4 mA
V
—
—
1
Vin = 0 to VCC
µA
1
Note: 1. Output buffer current is excluded.
LCD Circuit Characteristics (HD404612, HD404614, HD404616, HD404618: V CC = 2.7 V to 6.0 V;
HD4074618: VCC = 3.0 V to 5.5 V, GND = 0 V, Ta = –20 to +75°C, unless otherwise specified)
Item
Symbol
Pin(s)
Min
Typ
Max
Test Condition
Unit
Notes
Segment driver
voltage drop
Vds
SEG1–
SEG32
—
—
0.6
I d = 3 µA
V
1
Common driver
voltage drop
Vdc
COM1–
COM4
—
—
0.3
I d = 3 µA
V
1
LCD power
supply division
resistor
RWell
100
300
900
Between V 1 and GND
kΩ
LCD voltage
VLCD
2.7
—
VCC
HD404612, HD404614,
HD404616, HD404618
V
2
3.0
—
VCC
HD4074618
V
2
V1
Notes: 1. VDS and VDC are the voltage drops from power supply pins V1, V2, and V 3, and GND to each
segment pin and each common pin.
2. When VLCD is supplied from an external source, the following relations must be retained:
VCC ≥ V 1 ≥ V 2 ≥ V 3 ≥ GND
79
HD404618 Series
DTMF Characteristics (HD404612, HD404614, HD404616, HD404618: VCC = 2.7 V to 6.0 V;
HD4074618: VCC = 3.0 V to 5.5 V, GND = 0 V, Ta = –20 to +75°C, unless otherwise specified)
Item
Symbol
Pin(s)
Min
Typ
Max
Test Conditions
Unit
Notes
Tone output
voltage (1)
VOR
TONER
500
660
—
VT ref – GND = 2.0 V,
RL = 100 kΩ
mVrms
1
Tone output
voltage (2)
VOC
TONEC
520
690
—
VT ref – GND = 2.0 V,
RL = 100 kΩ
mVrms
1
Tone output
distortion
%DIS
—
3
7
Short circuit between
TONER and TONEC,
RL = 100 kΩ
%
2
Tone output
ratio
dBCR
—
2.5
—
Short circuit between
TONER and TONEC,
RL = 100 kΩ
dB
2
Notes: 1. See figure 48.
2. See figure 49.
80
HD404618 Series
AC Characteristics (HD404612, HD404614, HD404616, HD404618: VC C = 2.7 V to 6.0 V;
HD4074618: VCC = 3.0 V to 5.5 V, GND = 0 V, Ta = –20 to +75°C, unless otherwise specified)
Item
Symbol
Pin(s)
Min
Typ
Max
Test Condition
Unit
Clock
oscillation
frequency
f OSC
OSC 1,
OSC 2
—
400
—
1/4 division
kHz
—
800
—
kHz
—
32.768
—
kHz
—
10
—
f OSC / fCP = 400 kHz µs
—
5
—
f OSC / fCP = 800 kHz µs
—
—
7.5
f OSC = 400 kHz
ms
1
—
—
7.5
f OSC = 800 kHz
ms
1
X1, X2
—
—
3
Ta = –10 to +60°C
s
2
OSC 1
—
400
—
kHz
—
800
—
kHz
1100
—
—
f CP = 400 kHz
ns
3
550
—
—
f CP = 800 kHz
ns
3
1100
—
—
f CP = 400 kHz
ns
3
550
—
—
f CP = 800 kHz
ns
3
—
—
150
f CP = 400 kHz
ns
3
—
—
75
f CP = 800 kHz
ns
3
—
—
150
f CP = 400 kHz
ns
3
—
—
75
f CP = 800 kHz
ns
3
X1, X2
Instruction
cycle time
Oscillator
stabilization
time
External
clock
frequency
External
clock high
width
External
clock low
width
External
clock rise
time
t cyc
t RC
f CP
t CPH
t CPL
t CPr
External
t CPf
clock fall time
OSC 1,
OSC 2
OSC 1
OSC 1
OSC 1
OSC 1
Notes
INT0 high
width
t IH
INT0
2
—
—
t cyc /
t subcyc
4, 6
INT0 low
width
t IL
INT0
2
—
—
t cyc /
t subcyc
4, 6
INT1 high
width
t IH
INT1
2
—
—
t cyc
4
81
HD404618 Series
Item
Symbol
Pin(s)
Min
Typ
Max
INT1 low
width
t IL
INT1
2
—
RESET high
width
t RSTH
RESET
2
Input
capacitance
Cin
D10
All pins
except D 10
RESET fall
time
t RSTf
Analog
comparator
stabilization
time
t CSTB
D12, D13
Test Condition
Unit
Notes
—
t cyc
4
—
—
t cyc
5
—
—
90
HD4074618:
f = 1 MHz,
Vin = 0 V
pF
8
—
—
15
f = 1 MHz,
Vin = 0 V
pF
—
—
20
ms
5
—
—
2
t cyc
7
(analog input
mode)
Notes: 1. The oscillation stabilization time is the period required for the oscillator to stabilize after V CC
reaches 2.7 V (3.0 V for HD4074618) at power-on or after RESET input goes high after stop
mode is cancelled. At power-on or when stop mode is cancelled, RESET must remain high for
at least tRC to ensure the oscillation stabilization time. Since tRC depends on the ceramic
oscillator’s circuit constant and stray capacitance, contact the manufacturer when designing a
reset circuit.
2. The oscillation stabilization time is the period required for the oscillator to stabilize after V CC
reaches 2.7 V (3.0 V for HD4074618) at power-on. The oscillation stabilization time (t RC) must be
ensured. If using a crystal oscillator, contact the manufacturer to determine what oscillation
stabilization time is required, since it depends on the circuit constants and stray capacitances.
3. See figure 50.
4. See figure 51. The unit t cyc applies when the MCU is in standby mode or active mode.
5. See figure 52.
6. The unit t subcyc applies when the MCU is in watch mode or subactive mode.
t subcyc = 244.14 µs (32.768-kHz crystal oscillator)
7. The analog comparator stabilization time is the period required for the oscillator to stabilize and
for correct data to be read after D12 /D13 is input to enter analog input mode.
8. The Max value for the HD404618, HD404616, HD404614, and HD404612 is 15pF.
82
HD404618 Series
Serial Interface Timing Characteristics (HD404612, HD404614, HD404616, HD404618: VCC = 2.7 V
to 6.0 V; HD4074618: VCC = 3.0 V to 5.5 V, GND = 0 V, Ta = –20 to +75°C, unless otherwise specified)
During Transmit Clock Output
Item
Symbol
Pin(s)
Min
Typ
Max
Test Condition Unit
Notes
Transmit clock
cycle time
t Scyc
SCK
1
—
—
Load shown in
figure 54
t cyc /tsubcyc 1, 3
Transmit clock
high width
t SCKH
SCK
0.5
—
—
Load shown in
figure 54
t Scyc
1
Transmit clock
low width
t SCKL
SCK
0.5
—
—
Load shown in
figure 54
t Scyc
1
Transmit clock
rise time
t SCKr
SCK
—
—
200
Load shown in
figure 54
ns
1
Transmit clock
fall time
t SCKf
SCK
—
—
200
Load shown in
figure 54
ns
1
Serial output
data delay time
t DSO
SO
—
—
500
Load shown in
figure 54
ns
1
Serial input data t SSI
setup time
SI
300
—
—
ns
1
Serial input data t HSI
hold time
SI
300
—
—
ns
1
83
HD404618 Series
During Transmit Clock Input
Item
Symbol
Pin(s)
Min
Typ
Max
Transmit clock
cycle time
t Scyc
SCK
1
—
—
t cyc /tsubcyc 1, 3
Transmit clock
high width
t SCKH
SCK
0.5
—
—
t Scyc
1
Transmit clock
low width
t SCKL
SCK
0.5
—
—
t Scyc
1
Transmit clock
rise time
t SCKr
SCK
—
—
200
ns
1
Transmit clock
fall time
t SCKf
SCK
—
—
200
ns
1
Serial output
data delay time
t DSO
SO
—
—
500
ns
1
Serial input data t SSI
setup time
SI
300
—
—
ns
1
Serial input data t HSI
hold time
SI
300
—
—
ns
1
Transmit clock
completion
detect time
SCK
1
—
—
t cyc /tsubcyc 1, 2, 3
t SCKHD
Test Condition Unit
Load shown in
figure 54
Notes
Notes: 1. See figure 53.
2. The transmit clock completion detect time is the high level period after eight transmit clock
pulses have been input. The serial interrupt request flag is not set if the next transmit clock is
input before the transmit clock completion detect time has passed.
3. The unit t subcyc applies when the MCU is in subactive mode.
t subcyc = 244.14 µs (32.768-kHz crystal oscillator)
RL = 100 kΩ
TONEC
TONER
RL = 100 kΩ
Figure 48 Tone Output Load Circuit
84
HD404618 Series
R L = 100 k Ω
TONEC
TONER
Figure 49 Distortion and dBCR Load Circuit
1/fCP
VCC – 0.3 V
OSC1
t CPH
0.3 V
t CPL
t CPr
t CPf
Figure 50 Oscillator Timing
0.9VCC
INT0 , INT1
tIH
0.1VCC
tIL
Figure 51 Interrupt Timing
0.9VCC
RESET
0.1VCC
t RSTH
t RSTf
Figure 52 Reset Timing
After 8 transmit clock
pulses are input
t Scyc
t SCKf
SCK
VCC – 1.0 V (0.9VCC )*
0.4 V (0.1VCC)*
t SCKHD
t SCKr
t SCKL
tSCKH
t DSO
SO
VCC – 0.5 V
0.4 V
t SSI
SI
t HSI
0.9V CC
0.1VCC
Note: * VCC – 1.0 V and 0.4 V are the threshold voltages for transmit clock output.
0.9VCC and 0.1VCC are threshold voltages for transmit clock input.
Figure 53 Serial Interface Timing
85
HD404618 Series
VCC
R L = 2.6 k Ω
Test
point
C
30 pF
R
1S2074 H
or equivalent
12 kΩ
Figure 54 Timing Load Circuit
86
HD404618 Series
Notes on ROM Out
Please pay attention to the following items regarding ROM out.
On ROM out, fill the ROM area indicated below with 1s to create the same data size as a 8-kword version
(HD404618). An 8-kword data size is required to change ROM data to mask manufac turing data since the
program used is for a 8-kword version.
This limitation applies when using an EPROM or a data base.
$0000
$0000
Vector
address
Vector
address
Zero-page
subroutine
(64 words)
Zero-page
subroutine
(64 words)
Pattern &
program
(2,048 words)
Zero-page
subroutine
(64 words)
$003F
$0040
Pattern &
program
(4,096 words)
$0FFF
$1000
$07FF
$0800
Vector
address
$000F
$0010
$003F
$0040
$003F
$0040
Not used
$1FFF
$0000
$000F
$0010
$000F
$0010
ROM 6-kword version:
HD404616
Address $1800–$1FFF
ROM 4-kword version:
HD404614
Address $1000–$1FFF
ROM 2-kword version:
HD404612
Address $0800–$1FFF
Pattern &
program
(6,144 words)
$17FF
$1800
Not used
$1FFF
Not used
$1FFF
Fill this area with 1s
87
HD404618 Series
HD404612, HD404614, HD404616, HD404618 Option List
Please check off the appropriate applications and
enter the necessary information.
Date of order
/
/
Customer
Department
ROM code name
1. ROM Size
HD404612
2-kword
HD404614
4-kword
HD404616
6-kword
HD404618
8-kword
LSI number
(to be filled in
by HITACHI)
2. Optional Functions
*
With 32-kHz CPU operation, with time-base for clock
*
Without 32-kHz CPU operation, with time-base for clock
Without 32-kHz CPU operation, without time-base
Note: * Options marked with an asterisk require a subsystem
crystal oscillator
5. ROM Code Media
Please specify the first type below (the upper bits and lower bits are mixed together), when using the
EPROM on-package microcomputer type (including ZTAT™ version).
EPROM: The upper bits and lower bits are mixed together. The upper five bits and lower five bits are
programmed to the same EPROM in alternating order (i.e., LULULU...).
EPROM: The upper bits and lower bits are separated. The upper five bits and lower five bits are
programmed to different EPROMS.
6. System oscillator (OSC1 and OSC2)
Ceramic oscillator
f=
MHz
External clock
f=
MHz
7. Stop Mode
Used
Not used
8. Package
FP-80A
FP-80B
TFP-80
88
HD404618 Series
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,
copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party’s rights, including
intellectual property rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly
for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable
failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other
consequential damage due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor
products.
Hitachi, Ltd.
Semiconductor & Integrated Circuits.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109
URL
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: http:semiconductor.hitachi.com/
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Asia (HongKong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm
Japan
: http://www.hitachi.co.jp/Sicd/indx.htm
For further information write to:
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(America) Inc.
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Fax: <1>(408) 433-0223
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Germany
Tel: <49> (89) 9 9180-0
Fax: <49> (89) 9 29 30 00
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Tel: <886> (2) 2718-3666
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Copyright © Hitachi, Ltd., 1998. All rights reserved. Printed in Japan.
89