ALSC AS7C4098-12TI 5v/3.3v 256k x 16 cmos sram Datasheet

AS7C4098
AS7C34098
January 2005
®
5V/3.3V 256K × 16 CMOS SRAM
Features
• AS7C4098 (5V version)
• AS7C34098 (3.3V version)
• Industrial and commercial temperature
• Organization: 262,144 words × 16 bits
• Center power and ground pins
• High speed
• Low power consumption: STANDBY
- 110 mW (AS7C4098)/max CMOS
- 72 mW (AS7C34098)/max CMOS
• Individual byte read/write controls
• Easy memory expansion with CE, OE inputs
• TTL- and CMOS-compatible, three-state I/O
• 44-pin JEDEC standard packages
- 10/12/15/20 ns address access time
- 5/6/7/8 ns output enable access time
- 400-mil SOJ
- TSOP 2
• Low power consumption: ACTIVE
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 100 mA
- 1375 mW (AS7C4098)/max @ 12 ns
- 576 mW (AS7C34098)/max @ 10 ns
Logic block diagram
1024 × 256 × 16
Array
(4,194,304)
I/O
buffer
A0
A1
A2
A3
A4
CE
I/O1
I/O2
I/O3
I/O4
VCC
GND
I/O5
I/O6
I/O7
I/O8
WE
A5
A6
A7
A8
A9
GND
Control circuit
Column decoder
A5
A9
A10
A11
A14
A15
A16
A17
WE
UB
OE
LB
CE
44-pin (400 mil) SOJ
TSOP2
VCC
Row Decoder
A0
A1
A2
A3
A4
A6
A7
A8
A12
A13
I/O1–I/O8
I/O9–I/O16
Pin arrangement for SOJ and TSOP 2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A17
A16
A15
OE
UB
LB
I/O16
I/O15
I/O14
I/O13
GND
VCC
I/O12
I/O11
I/O10
I/O9
NC
A14
A13
A12
A11
A10
Selection guide
–10
–12
–15
–20
Unit
Maximum address access time
10
12
15
20
ns
Maximum output enable access time
5
6
7
8
ns
AS7C4098
–
250
220
180
mA
AS7C34098
160
130
110
100
mA
AS7C4098
–
20
20
20
mA
AS7C34098
20
20
20
20
mA
Maximum operating current
Maximum CMOS standby current
1/13/05; v.1.9
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AS7C4098
AS7C34098
®
Functional description
The AS7C4098 and AS7C34098 are high-performance CMOS 4,194,304-bit Static Random Access Memory (SRAM) devices
organized as 262,144 words × 16 bits. They are designed for memory applications where fast data access, low power, and
simple interfacing are desired.
Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 5/6/7/8 ns are
ideal for high-performance applications. The chip enable input CE permits easy memory expansion with multiple-bank
memory systems.
When CE is High the device enters standby mode. The standard AS7C4098/AS7C34098 is guaranteed not to exceed 110/
72mW power consumption in CMOS standby mode. A write cycle is accomplished by asserting write enable (WE) and chip
enable (CE). Data on the input pins I/O1–I/O16 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To
avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or
write enable (WE).
A read cycle is accomplished by asserting output enable (OE) and chip enable (CE), with write enable (WE) High. The chip
drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or
write enable is active, output drivers stay in high-impedance mode.
These devices provide multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to
be written and read. LB controls the lower bits, I/O1–I/O8, and UB controls the higher bits, I/O9–I/O16.
All chip inputs and outputs are TTL- and CMOS-compatible, and operation is from either a single 5V (AS7C4098) or 3.3V
(AS7C34098) supply. Both devices are available in the JEDEC standard 400-mL, 44-pin SOJ and TSOP 2 packages.
Absolute maximum ratings
Parameter
Device
Symbol
Min
Max
Unit
AS7C4098
Vt1
–0.50
+7.0
V
AS7C34098
Vt1
–0.50
+5.0
V
Voltage on any pin relative to GND
Vt2
–0.50
VCC +0.50
V
Power dissipation
PD
–
1.5
W
Storage temperature
Tstg
–65
+150
°C
Ambient temperature with VCC applied
Tbias
–55
+125
°C
DC current into outputs (low)
IOUT
–
±20
mA
Voltage on VCC relative to GND
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Truth table
CE
WE
OE
LB
UB
I/O1–I/O8
I/O9–I/O16
Mode
H
X
X
X
X
High Z
High Z
Standby (ISB, ISB1)
L
H
H
X
X
L
X
X
H
H
High Z
High Z
Output disable (ICC)
L
H
DOUT
High Z
H
L
High Z
DOUT
L
L
DOUT
DOUT
L
H
DIN
High Z
H
L
High Z
DIN
L
L
DIN
DIN
L
L
H
L
L
X
Read (ICC)
Write (ICC)
Key: X = Don’t care, L = Low, H = High.
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AS7C4098
AS7C34098
®
Recommended operating conditions
Parameter
Symbol
Max
Unit
AS7C4098
VCC (12/15/20)
4.5
5.0
5.5
V
AS7C34098
VCC (10)
3.15
3.3
3.6
V
AS7C34098
VCC (12/15/20)
3.0
3.3
3.6
V
AS7C4098
VIH
2.2
–
VCC + 0.5
V
AS7C34098
VIH
2.0
–
VCC + 0.5
V
VIL1
–0.5
–
0.8
V
commercial
TA
0
–
70
°C
industrial
TA
–40
–
85
°C
Supply voltage
Input voltage
Ambient operating temperature
Min Typical
1 VIL min = –1.0V for pulse width less than 5ns.
DC operating characteristics (over the operating range)1
–10
Parameter
Symbol
Input leakage
current
|ILI|
VCC = Max
VIN = GND to VCC
Output leakage
current
|ILO|
VCC = Max
CE = VIH or OE = VIH
or WE = VIL
VI/O = GND to VCC
Operating
power supply
current
ICC
VCC = Max
Min cycle, 100% duty
CE = VIL, IOUT = 0mA
ISB
VCC = Max
CE = VIH, f = Max
Standby power
supply current
Output voltage
ISB1
Test conditions
–12
–15
–20
Min Max Min Max Min Max Min Max Unit
AS7C4098/
–
1
–
1
–
1
–
1
µA
–
1
–
1
–
1
–
1
µA
AS7C4098
–
–
–
250
–
220
–
180 mA
AS7C34098
–
160
–
130
–
110
–
100 mA
AS7C4098
–
–
–
60
–
60
–
60
mA
AS7C34098
–
60
–
60
–
60
–
60
mA
VCC = Max
AS7C4098
CE ≥ VCC – 0.2V, VIN ≥ VCC
– 0.2V or VIN ≤ 0.2V, f = 0 AS7C34098
–
–
–
20
–
20
–
20
mA
–
20
–
20
–
20
–
20
mA
–
0.4
–
0.4
–
0.4
–
0.4
V
–
2.4
–
2.4
–
2.4
–
V
AS7C34098
AS7C4098/
AS7C34098
VOL
IOL = 8 mA, VCC = Min
AS7C4098/
VOH
IOH = –4 mA, VCC = Min
AS7C34098 2.4
Capacitance (f = 1MHz, Ta = 25° C, VCC = NOMINAL)2
Parameter
Symbol
Signals
Test conditions
Max
Unit
Input capacitance
CIN
A, CE, WE, OE, UB, LB
VIN = 0V
6
pF
I/O capacitance
CI/O
I/O
VIN = VOUT = 0V
8
pF
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AS7C4098
AS7C34098
®
Read cycle (over the operating range)3,9
–10
Parameter
–12
–15
–20
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Unit Notes
Read cycle time
tRC
10
–
12
–
15
–
20
–
ns
Address access time
tAA
–
10
–
12
–
15
–
20
ns
Chip enable (CE) access time
tACE
–
10
–
12
–
15
–
20
ns
Output enable (OE) access time
tOE
–
5
–
6
–
7
–
8
ns
Output hold from address change
tOH
3
–
3
–
3
–
3
–
ns
5
CE Low to output in low Z
tCLZ
0
–
3
–
0
–
0
–
ns
4, 5
CE High to output in higfch Z
tCHZ
–
5
–
6
–
7
–
9
ns
4, 5
OE Low to output in low Z
tOLZ
0
–
0
–
0
–
0
–
ns
4, 5
OE High to output in high Z
tOHZ
–
5
–
6
–
7
–
9
ns
4, 5
LB, UB access time
tBA
–
5
–
6
–
7
–
8
ns
LB, UB Low to output in low Z
tBLZ
0
–
0
–
0
–
0
–
ns
LB, UB High to output in high Z
tBHZ
–
5
–
6
–
7
–
9
ns
Power up time
tPU
0
–
0
–
0
–
0
–
ns
5
Power down time
tPD
–
10
–
12
–
15
–
20
ns
5
Key to switching waveforms
Rising input
Falling input
Undefined/don’t care
Read waveform 1 (address controlled)6,7,9
tRC
Address
tOH
DataOUT
1/13/05; v.1.9
tAA
Previous data valid
tOH
Data valid
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AS7C4098
AS7C34098
®
Read waveform 2 (CE, OE, UB, LB controlled)6,8,9
tRC
Address
tAA
OE
tOHZ
tOE
tOLZ
tOH
CE
tACE
tLZ
tCHZ
LB, UB
tBA
tBLZ
tBHZ
DataOUT
Data valid
Write cycle (over the operating range)11
–10
Parameter
Symbol Min
–12
–15
–20
Max
Min
Max
Min
Max
Min
Max
Unit
Note
Write cycle time
tWC
10
–
12
–
15
–
20
–
ns
Chip enable (CE) to write end
tCW
7
–
8
–
10
–
12
–
ns
Address setup to write end
tAW
7
–
8
–
10
–
12
–
ns
Address setup time
tAS
0
–
0
–
0
–
0
–
ns
Write pulse width (OE = High)
tWP1
7
–
8
–
10
–
12
–
ns
Write pulse width (OE = Low)
tWP2
10
–
12
–
15
–
20
–
ns
Write recovery time
tWR
0
–
0
–
0
–
0
–
ns
Address hold from end of write
tAH
0
–
0
–
0
–
0
–
ns
Data valid to write end
tDW
5
–
6
7
–
9
–
ns
Data hold time
tDH
0
–
0
–
0
–
0
–
ns
4, 5
Write enable to output in High-Z
tWZ
0
5
0
6
0
7
0
9
ns
4, 5
Output active from write end
tOW
3
–
3
–
3
–
3
–
ns
4, 5
Byte enable Low to write end
tBW
7
–
8
–
10
–
12
–
ns
4, 5
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AS7C4098
AS7C34098
®
Write waveform 1(WE controlled)10,11
tWC
tAH
tWR
Address
tCW
CE
tBW
LB, UB
tAW
tAS
tWP
WE
tDW
DataIN
Data valid
tWZ
DataOUT
tDH
tOW
Data undefined
High Z
Write waveform 2 (CE controlled)10,11
tWC
tAH
tWR
Address
tAS
CE
tCW
tAW
tBW
LB, UB
tWP
WE
tDW
DataIN
DataOUT
1/13/05; v.1.9
tCLZ
High Z
tWZ
Data undefined
Alliance Semiconductor
tDH
Data valid
tOW
High Z
P. 6 of 10
AS7C4098
AS7C34098
®
Write waveform 3 10,11
tWC
tAH
tWR
Address
tAS
tCW
CE
tAW
tBW
LB, UB
tWP
WE
tDW
DataIN
Data valid
tDH
tWZ
DataOUT
Data undefined
High Z
High Z
AC test conditions
-
Output load: see Figure B or Figure C.
Input pulse level: GND to 3.0V. See Figure A.
Input rise and fall times: 2 ns. See Figure A.
Input and output timing reference levels: 1.5V.
Thevenin equivalent: D
OUT
+5V
DOUT
+3.0V
GND
90%
90%
10%
10%
2 ns
Figure A: Input pulse
255Ω
480Ω
C13
GND
Figure B: 5V Output load
168Ω
+1.728V (5V and 3.3V)
+3.3V
DOUT
350Ω
320Ω
C13
GND
Figure C: 3.3V Output load
Notes
1
2
3
4
5
6
7
8
9
10
11
12
13
During VCC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification.
This parameter is sampled, but not 100% tested.
For test conditions, see AC Test Conditions, Figures A, B, C.
tCLZ and tCHZ are specified with CL = 5pF as in Figure C. Transition is measured ±500mV from steady-state voltage.
This parameter is guaranteed, but not tested.
WE is High for read cycle.
CE and OE are Low for read cycle.
Address valid prior to or coincident with CE transition Low.
All read cycle timings are referenced from the last valid address to the first transitioning address.
CE or WE must be High during address transitions. Either CE or WE asserting high terminates a write cycle.
All write cycle timings are referenced from the last valid address to the first transitioning address.
Not applicable.
C = 30pF, except on High Z and Low Z parameters, where C = 5pF.
1/13/05; v.1.9
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AS7C4098
AS7C34098
®
Typical DC and AC characteristics12
1.2
ICC
1.0
Normalized ICC, ISB
0.8
0.6
ISB
0.4
0.2
0.8
0.6
ISB
0.4
0.0
–55
MAX
Normalized access time
1.4
Ta = 25° C
1.3
1.2
1.1
1.0
0.9
0.8
MIN
NOMINAL
Supply voltage (V)
Output source current IOH
vs. output voltage VOH
140
120
Ta = 25° C
80
60
40
20
Output voltage (V)
VCC
5
1
0.2
0.04
–10
35
80
125
Ambient temperature (°C)
–55
–10
35
80
125
Ambient temperature (°C)
Normalized supply current ICC
vs. cycle frequency 1/tRC, 1/tWC
1.4
1.2
1.2
1.1
1.0
0.9
VCC = VCC(NOMINAL)
Ta = 25° C
1.0
0.8
0.6
0.4
0.2
0.0
–10
35
80
125
Ambient temperature (°C)
Output sink current IOL
vs. output voltage VOL
120
VCC = VCC(NOMINAL)
100
Ta = 25° C
80
60
40
0
25
50
75
Cycle frequency (MHz)
100
Typical access time change ∆tAA
vs. output capacitive loading
35
30
VCC = VCC(NOMINAL)
25
20
15
10
5
20
0
0
1/13/05; v.1.9
1.3
VCC = VCC(NOMINAL)
25
VCC = VCC(NOMINAL)
140
VCC = VCC(NOMINAL)PL
100
1.4
0.8
–55
MAX
625
Normalized access time tAA
vs. ambient temperature Ta
1.5
Output sink current (mA)
Normalized access time
NOMINAL
Supply voltage (V)
Normalized access time tAA
vs. supply voltage VCC
1.5
Output source current (mA)
1.0
0.2
0.0
MIN
0
ICC
Normalized ICC
Normalized ICC, ISB
1.2
Normalized supply current ISB1
vs. ambient temperature Ta
Normalized ISB1 (log scale)
1.4
Normalized supply current ICC, ISB
vs. ambient temperature Ta
Change in tAA (ns)
1.4
Normalized supply current ICC, ISB
vs. supply voltage VCC
0
0
Output voltage (V)
Alliance Semiconductor
VCC
0
250
500
750
Capacitance (pF)
1000
P. 8 of 10
AS7C4098
AS7C34098
®
Package dimensions
c
44 434241403938373635343332313029282726252423
e He
44-pin TSOP 2
1 2 3 4 5 6 7 8 9 101112131415161718 19202122
d
A2
A
A1
l
0–5°
E
b
e
E1E2
Pin 1
c
B
A
A1
1/13/05; v.1.9
A
A1
A2
B
b
c
D
E
E1
E2
e
44-pin SOJ 400 mils
Min(mils) Max(mils)
0.128
0.148
0.025
0.105
0.115
0.026
0.032
0.015
0.020
0.007
0.013
1.120
1.130
0.370 NOM
0.395
0.405
0.435
0.445
0.050 NOM
D
44-pin SOJ
b
A
A1
A2
b
c
d
e
He
E
l
44-pin TSOP 2
Min (mm) Max (mm)
1.2
0.05
0.15
0.95
1.05
0.30
0.45
0.21
0.12
18.31
18.52
10.06
10.26
11.68
11.94
0.80 (typical)
0.40
0.60
Seating
Plane
A2
E
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AS7C4098
AS7C34098
®
Ordering Codes
Package
SOJ
TSOP 2
Version
10 ns
12 ns
15 ns
20 ns
5V commercial
NA
AS7C4098-12JC
AS7C4098-15JC
AS7C4098-20JC
5V industrial
NA
AS7C4098-12JI
AS7C4098-15JI
AS7C4098-20JI
3.3V commercial
AS7C34098-10JC
AS7C34098-12JC
AS7C34098-15JC
AS7C34098-20JC
3.3V industrial
NA
AS7C34098-12JI
AS7C34098-15JI
AS7C34098-20JI
5V commercial
NA
AS7C4098-12TC
AS7C4098-15TC
AS7C4098-20TC
5V industrial
NA
AS7C4098-12TI
AS7C4098-15TI
AS7C4098-20TI
3.3V commercial
AS7C34098-10TC
AS7C34098-12TC
AS7C34098-15TC
AS7C34098-20TC
3.3V industrial
NA
AS7C34098-12TI
AS7C34098-15TI
AS7C34098-20TI
Note:
Add suffix “N” to the above part number for lead free devices, Ex. AS7C4098-12JCN
Part numbering system
AS7C
X
SRAM prefix
Voltage:
Blank: 5V CMOS
3: 3.3V CMOS
1/13/05; v.1.9
4098
–XX
Device Access
number time
J or T
Packages:
J: SOJ 400 mil
T: TSOP 2
Alliance Semiconductor
X
N
Temperature ranges:
C: Commercial, 0°C to 70°C Lead free device
I: Industrial, –40°C to 85°C
P. 10 of 10
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