HI-8045 CMOS High Voltage Display Driver March 2007 GENERAL DESCRIPTION APPLICATIONS S80 S79 S78 S77 S76 S75 S74 S73 S72 S71 S70 S69 S68 S67 S66 S65 S64 S63 S62 S61 S60 S59 S58 S57 S56 N/C VSS CS CL LD DIN BPOSC N/C N/C BPIN N/C CONVOUT VDD DOUT 85 CONVOSC VEE T1 T2 BP S1 S2 S3 S4 S5 S6 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 HI-8045PQ 80 - SEGMENT 100 - PIN PLASTIC QUAD FLAT PACK 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 S55 S54 S53 S52 S51 S50 S49 S48 S47 S46 S45 S44 S43 S42 S41 S40 S39 S38 S37 S36 S35 S34 S33 S32 S31 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 N/C The die is metal mask programmable to provide for various package and/or cascade tap options. Consult your Holt Sales representative to explore the possibilities. PIN CONFIGURATION (Top View) 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 The HI-8045 and the HI-80XX series of display drivers all control segment information in the same way. Data is serially clocked into the device and the data for all segment outputs are latched in parallel when the Load input transitions from high to low. With the Data Out from the shift register available, devices may be cascaded to obtain more segment outputs. The shift register is 85 bits long. ! Dichroic Liquid Crystal Displays ! Standard Liquid Crystal Displays ! MEMS Drivers 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 The HI-8045 high voltage display driver is a low cost plastic, 80-segment version of the Holt HI-8040 display driver series. The 20 mil package lead pitch allows the maximum number of display driver segments in the smallest space. An optional voltage converter can generate the negative display drive voltage. Test inputs facilitate opens and shorts testing. The backplane frequency is checked and, as long as power is available, the segments are shut "Off" if the frequency becomes too low. FEATURES ! 4 MHz serial input data rate FUNCTIONAL BLOCK DIAGRAM ! 80 segment outputs DIN CL Þ Þ ! Test pins allow hardware all "ON", all "OFF" or alternating CS Þ ! Monitors backplane oscillation and forces all segments to "OFF" condition if below 10Hz LD ! Negative voltage converter available on-chip BPOSC BPIN ! Cascadable ! 5 Volt inputs translated to 35 Volts DATA IN 85 Stage Shift Register CLK LE Þ Þ Þ ! CMOS low power ! Industrial and JEDEC processing available Oscillator Divider Vo l t a g e Tr a n s l a t o r DOUT 85 Þ 80 Bit Latch Vo l t a g e Tr a n s l a t o r s H i g h Vo l t a g e Drivers H i g h Vo l t a g e B u ff e r Þ BP (DS8045, Rev. E) HOLT INTEGRATED CIRCUITS www.holtic.com 80 SEGMENTS 03/07 HI-8045 FUNCTIONAL DESCRIPTION INPUT LOGIC DOUT CS must be held low to enter data into the shift register. The data is clocked on the negative edge of CL. LD is normally held low and only pulsed high when new data is ready for display. When LD is high the latch is transparent. All four logic inputs are TTL compatible. A logic "1" at DIN that is eventually latched to the segment drivers will cause the segment to be at the opposite voltage level of the BP pin (out of phase). The DOUT pin is available from segment 85 for cascading devices to drive more segments and for verifying the data integrity. However only the first 80 output segments are available to the user. This output can drive 2 TTL loads. It changes on the positive edge of CL. BPOSC and BPIN The user can either make an oscillator to create the backplane frequency or drive an external clock into BPIN leaving BPOSC open. To make an oscillator, pins BPOSC and BPIN must be connected together and the appropriate R and C combination applied (See Figure 1). If the oscillator is used, the backplane frequency is approximately 1 fBP = (for R = 180KW & C = 220pF, fBP » 100Hz). 256 RC VEE & NEGATIVE VOLTAGE CONVERTER VEE may be externally driven to a maximum -30V. Alternatively, there is a voltage converter that will provide -21.4 volts (See Figure 2). If the converter pins are left open circuit, an on-chip sense resistor will cause shut down of all current consumption associated with the converter. The converter will survive a shorted segment condition and continue to maintain VEE at -20 volts. AUTOMATIC SEGMENTS OFF The internal backplane signal is tested continuously to be at least 10Hz. If the detector senses f<10Hz, then the segments are forced to the same voltage as the backplane (all segments in "OFF" state). However, the detector is only functional while VDD is above the minimum operating voltage specification. TEST INPUTS The test functions available are: T2 0 0 1 1 T1 0 1 0 1 Display Normal All Off All On Alternating On/Off Segments The test inputs must be tied to the appropriate logic level for correct circuit operation. VDD R 330KW C R CONVOSC RSENSE ÷ 256 Control VDD Q R VSS IN5818, IN5819 CONVOUT BPIN C OSC VDD 330µH VSS BPOSC TO BACKPLANE TRANSLATOR AND DRIVER VEE 10µF VSS Figure 1. INTERNAL OSCILLATOR CIRCUIT Figure 2. OPTIONAL VOLTAGE CONVERTER HOLT INTEGRATED CIRCUITS 2 HI-8045 LD CL CS DIN BP CS CL LD CS CL LD CS CL LD DIN DO DIN DO DIN DO BPIN BP BPIN BP BPIN BP 1MW 1MW 1500pF 1µF 1µF R C BPOSC BPOSC V os BPOSC 1MW 1MW SEGMENTS SEGMENTS BACK PLANE SEGMENTS SEG n Figure 3. RC OSCILLATOR AND CASCADED DEVICES CL INPUT 1µF 1µF 360pF Figure 4. OFFSET MEASUREMENT tCL tCW DIN INPUT tDS tDH CS INPUT tCSS tLCS tCSL tCSH LD INPUT tCDO DOUT OUTPUT tLS VALID Figure 5. TIMING DIAGRAM HOLT INTEGRATED CIRCUITS 3 tLW HI-8045 ABSOLUTE MAXIMUM RATINGS Voltages referenced to VSS = 0V Supply Voltage VDD........................ 0V to 7V VEE................VDD-35V to 0V Voltage at any input, except BPIN....-0.3 to VDD+0.3V Voltage at BPIN input.................VDD-35 to VDD+0.3V DC Current any input pin...................................10 mA Power Dissipation......................................................300 mW Operating Temperature Range - Industrial.......-40° to +85°C Operating Temperature Range - Hi-Temp........-55° to +125°C Storage Temperature Range............................-65° to +150°C NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS VDD = 5V ±5%, VEE = -21.5V, VSS = 0V, TA = Operating temperature range (unless otherwise specified). PARAMETER Operating Voltage Supply Current: SYMBOL (Converter Off, fBP = 100Hz) Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage Input Current Input Capacitance (excluding BPIN) (excluding BPIN) (BPIN) (BPIN) (Guaranteed, not tested) Segment Output Impedance Backplane Output Impedance Data Out Current: Source Current Sink Current Voltage Converter: @ No Load (VDD - VSS = 5V, TA = 25°C) @ 0.1mA Load @ 10KW Load Offset Voltage (Guaranteed, not tested) VDD IDD IEE VIL VIH VILX VIHX IIN CI RSEG RBP IDOH IDOL VEEC IDD VEEC VOS CONDITION MIN TYP 3.0 Static, No Load Static, No Load 300 0 2 VEE 0.8 VDD VIN = 0 to 5V IL = 10µA IL = 10µA VOH = 4.5 VOL = 0.4 See Fig. 2 See Fig. 2 See Fig. 2 See Fig. 4 3.2 -22 -21.5 MAX UNITS 7.0 600 120 0.8 VDD 0.6 VDD VDD 100 5 15,000 600 -3.0 25 V µA µA V V V V nA pF W W mA mA V mA V mV MAX UNITS 170 ns ns ns ns ns ns ns ns ns ns ns ns ns -21 1.8 -20 AC ELECTRICAL CHARACTERISTICS VDD = 5V , VEE = -21.5V, VSS = 0V, TA = Operating temperature range (unless otherwise specified). PARAMETER Clock Period Clock Pulse Width Data In - Setup Data In - Hold Chip Select - Setup to Clock Chip Select - Hold to Clock Load - Setup to Clock Chip Select - Setup to Load Load Pulse Width Chip Select - Hold to Load Data Out Valid, from Clock non-cascaded cascaded non-cascaded cascaded SYMBOL VDD MIN tCL tCL tCW tCW tDS tDH tCSS tCSH tLS tCSL tLW tLCS tCDO 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 250 500 125 250 80 80 100 120 120 0 130 120 HOLT INTEGRATED CIRCUITS 4 TYP HI-8045 ORDERING INFORMATION HI - 8045PQ xx PART NUMBER TEMPERATURE RANGE FLOW BURN IN LEAD FINISH Blank -40°C TO +85°C I No Tin / Lead (Sn / Pb) Solder F -40°C TO +85°C I No 100% Matte Tin (Pb-free, RoHS compliant) T -55°C TO +125°C T No Tin / Lead (Sn / Pb) Solder TF -55°C TO +125°C T No 100% Matte Tin (Pb-free, RoHS compliant) PART NUMBER PACKAGE DESCRIPTION HI-8045PQ 100-PIN PLASTIC QUAD FLAT PACK, PQFP (100PQS) S80 S79 S78 S77 S76 S75 S74 S73 S72 S71 S70 S69 S68 S67 S66 S65 S64 S63 S62 S61 S60 S59 S58 S57 S56 PIN ASSIGNMENTS HI-8045PQ 80 - SEGMENT 100 - PIN PLASTIC QUAD FLAT PACK 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 N/C N/C VSS CS CL LD DIN BPOSC N/C N/C BPIN N/C CONVOUT VDD DOUT 85 CONVOSC VEE T1 T2 BP S1 S2 S3 S4 S5 S6 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 Pin 1 HOLT INTEGRATED CIRCUITS 5 S55 S54 S53 S52 S51 S50 S49 S48 S47 S46 S45 S44 S43 S42 S41 S40 S39 S38 S37 S36 S35 S34 S33 S32 S31 HI-8045 PACKAGE DIMENSIONS inches (millimeters) 100-PIN PLASTIC QUAD FLAT PACK (PQFP) Package Type: 100PQS .0197 BSC (0.50) .630 BSC SQ (16.0) .551 BSC SQ (14.0) .009 ± .002 (.22 ± .05) .024 ± .006 (.60 ± .15) .039 typ (1.0) See Detail A .059 ± .004 (1.50 ± .10) .008 min (0.20) .008 R max (0.20) .055 ± .002 (1.40 ± .05) BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) 0° £ Q £ 7° .003 R min (0.08) HOLT INTEGRATED CIRCUITS 6 Detail A