Estek K24C64WIRG-A Available in space-saving 8-lead pdip, 8-lead sop, and 8-lead tssop package Datasheet

24C32 / 24C64
Features
¡Wide Voltage Operation
¡1 MHz (5V), 400 kHz (1.8V, 2.5V, 2.7V) Compatibility
¡Write Protect Pin for Hardware Data Protection
¡32-byte Page (32K, 64K) Write Modes
¡Partial Page Writes Allowed
¡Self-timed Write Cycle (5 ms max)
¡High-reliability
- VCC = 1.8V to 5.5V
¡Operating Ambient Temperature: -40。C to +85。C
¡Internally Organized:
- 24C32, 4096 X 8 (32K bits)
- 24C64, 8192 X 8 (64K bits)
- Endurance: 1 Million Write Cycles
¡Two-wire Serial Interface
¡Schmitt Trigger, Filtered Inputs for Noise Suppression
¡Bidirectional Data Transfer Protocol
- Data Retention: 100 Years
¡8-lead PDIP, 8-lead SOP and 8-lead TSSOP Packages
¡Die Sales: Wafer Form, Waffle Pack
General Description
The
24C32/ 24C64 provides 32,768/65,536 bits of serial electrically erasable and programmable read-only memory
(EEPROM) organized as 4096/8192 words of 8 bits each. The device is optimized for use in many industrial and
commercial applications where low-power and low-voltage operation are essential. The
24C32/ 24C64 is available in
space-saving 8-lead PDIP, 8-lead SOP, and 8-lead TSSOP packages and is accessed via a two-wire serial interface.
Pin Configuration
8-lead PDIP
8-lead SOP
8-lead TSSOP
A0
1
8
V CC
A0
1
8
VCC
A0
1
8
VCC
A1
2
7
WP
A1
2
7
WP
A1
2
7
WP
A2
3
6
SCL
A2
3
6
SCL
A2
3
6
SCL
GND
4
5
SDA
GND
4
5
SDA
GND
4
5
SDA
Pin Descriptions
¡Table 1: Pin Configuration
Pin Designation
Type
Name and Functions
A0 - A2
I
Address Inputs
SDA
I/O & Open-drain
Serial Data
SCL
I
Serial Clock Input
WP
I
Write Protect
GND
P
Ground
VCC
P
Power Supply
BEIJING ESTEK ELECTRONICS CO.,LTD
1
E
24C32 / 24C64
Block Diagram
VCC
GND
WP
SCL
START STOP
LOGIC
SDA
EN
SERIAL CONTROL
LOGIC
HIGH VOLTAGE
PUMP/TIMING
LOAD
COMP
DATA RECOVERY
DEVICE ADDRESS
COMPARATOR
INC
A1
DATA WORD
ADDRESS COUNTER
A2
Y DECODER
DIN
X DECODER
LOAD
A0
EEPROM
SERIAL MUX
DOUT/ACKNOWLEDGE
DOUT
BEIJING ESTEK ELECTRONICS CO.,LTD
2
24C32 / 24C64
Pin Descriptions
DEVICE/PAGE ADDRESSES (A2, A1 and A0): The A2, A1 and A0 pins are device address inputs that are hard
wired for the
24C32/ 24C64. Eight 32K/64K devices may be addressed on a single bus system (device addressing is
discussed in detail under the Device Addressing section).
SERIAL DATA (SDA): The SDA pin is bi-directional for serial data transfer. This pin is open-drain driven and may be
wire-ORed with any number of other open-drain or open- collector devices.
SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative
edge clock data out of each device.
WRITE PROTECT (WP): The
24C32/ 24C64 has a Write Protect pin that provides hardware data protection. The
Write Protect pin allows normal read/write operations when connected to ground (GND). When the Write Protect pin is
connected to V CC , the write protection feature is enabled and operates as shown in the following Table 2.
¡Table 2: Write Protect
WP Pin Status
At VCC
At GND
Part of the Array Protected
24C32
24C64
Full (32K) Array
Full (64K) Array
Normal Read / Write Operations
Memory Organization
24C32, 32K SERIAL EEPROM: Internally organized with 128 pages of 32 bytes each, the 32K requires an 12-bit
data word address for random word addressing.
24C64, 64K SERIAL EEPROM: Internally organized with 256 pages of 32 bytes each, the 64K requires a 13-bit
data word address for random word address
BEIJING ESTEK ELECTRONICS CO.,LTD
3
24C32 / 24C64
Device Operation
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA
pin may change only during SCL low time periods (see to Figure 1 on page 4). Data changes during SCL high periods
will indicate a start or stop condition as defined below.
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any other
command (see to Figure 2 on page 4).
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop
command will place the EEPROM in a standby power mode (see Figure 2 on page 4).
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The
EEPROM sends a "0" to acknowledge that it has received each word. This happens during the ninth clock cycle.
STANDBY MODE: The
24C32/ 24C64 features a low-power standby mode which is enabled: (a) upon power-up and
(b) after the receipt of the STOP bit and the completion of any internal operations
MEMORY RESET: After an interruption in protocol, power loss or system reset, any two-wire part can be reset by
following these steps:
1.
Clock up to 9 cycles.
2.
Look for SDA high in each cycle while SCL is high.
3.
Create a start condition.
¡Figure 1: Data Validity
SDA
SCL
DATA STABLE
DATA STABLE
DATA
CHANGE
¡Figure 2: Start and Stop Definition
SDA
SCL
START
STOP
BEIJING ESTEK ELECTRONICS CO.,LTD
4
24C32 / 24C64
¡Figure 3: Output Acknowledge
1
SCL
8
9
DATA IN
DATA OUT
START
ACKNOWLEDGE
Device Addressing
The 32K and 64K EEPROM devices all require an 8-bit device address word following a start condition to enable the
chip for a read or write operation (see to Figure 4 on page 7).
The device address word consists of a mandatory "1", "0" sequence for the first four most significant bits as shown.
This is common to all the Serial EEPROM devices.
The next 3 bits are the A2, A1 and A0 device address bits for the 32K/64K EEPROM. These 3 bits must compare to
their corresponding hardwired input pins.
The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is high
and a write operation is initiated if this bit is low.
Upon a compare of the device address, the EEPROM will output a "0". If a compare is not made, the chip will return to a
standby state.
BEIJING ESTEK ELECTRONICS CO.,LTD
5
EE
24C32 / 24C64
Write Operations
BYTE WRITE: A write operation requires two 8-bit data word address following the device address word and
acknowledgment. Upon receipt of this address, the EEPROM will again respond with a "0" and then clock in the first 8bit data word. Following receipt of the 8-bit data word, the EEPROM will output a "0" and the addressing device, such
as a microcontroller, must terminate the write sequence with a stop condition. At this time the EEPROM enters an
internally timed write cycle, tWR, to the nonvolatile memory. All inputs are disabled during this write cycle and the
EEPROM will not respond until the write is complete (see Figure 5 on page 7).
PAGE WRITE: The 32K/64K EEPROM is capable of an 32-byte page write.
A page write is initiated the same as a byte write, but the microcontroller does not send a stop condition after the first
data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can
transmit up to 31 (32K, 64K) more data words. The EEPROM will respond with a "0" after each data word received. The
microcontroller must terminate the page write sequence with a stop condition (see Figure 6 on page 7).
The data word address lower five (32K, 64K) bits are internally incremented following the receipt of each data word.
The higher data word address bits are not incremented, retaining the memory page row location. When the word
address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same
page. If more than 32 (32K, 64K) data words are transmitted to the EEPROM, the data word address will "roll over" and
previous data will be overwritten.
ACKNOWLEDGE POLLING: Once the internally timed write cycle has started and the EEPROM inputs are disabled,
acknowledge polling can be initiated. This involves sending a start condition followed by the device address word. The
read/write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPROM
respond with a "0", allowing the read or write sequence to continue.
Read Operations
Read operations are initiated the same way as write operations with the exception that the read/write select bit in the
device address word is set to "1". There are three read operations: current address read, random address read and
sequential read.
CURRENT ADDRESS READ: The internal data word address counter maintains the last address accessed during
the last read or write operation, incremented by one. This address stays valid between operations as long as the chip
power is maintained. The address "roll over" during read is from the last byte of the last memory page to the first byte
of the first page. The address "roll over" during write is from the last byte of the current page to the first byte of the
same page.
Once the device address with the read/write select bit set to "1" is clocked in and acknowledged by the EEPROM, the
current address data word is serially clocked out. The microcontroller does not respond with an input "0" but does
generate a following stop condition (see Figure 7 on page 8).
BEIJING ESTEK ELECTRONICS CO.,LTD
6
24C32 / 24C64
E
Read Operations
RANDOM READ: A random read requires a "dummy" byte write sequence to load in the data word address. Once the
device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller
must generate another start condition. The microcontroller now initiates a current address read by sending a device
address with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the
data word. The microcontroller does not respond with a "0" but does generate a following stop condition (see Figure 8
on page 8).
SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a random address read. After
the microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives an
acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When
the memory address limit is reached, the data word address will "roll over" and the sequential read will continue. The
sequential read operation is terminated when the microcontroller does not respond with a "0" but does generate a
following stop condition (see Figure 9 on page 8).
¡Figure 4: Device Address
32K/64K
1
0
1
0
A2
A1
A0
MSB
R/W
LSB
¡Figure 5: Byte Write
W
S
R
T
I
A
DEVICE
T
R
ADDRESS
E
T
FIRST WORD SECOND WORD
ADDRESS
ADDRESS
S
T
O
P
DATA
SDA LINE
M
S
B
L R AM
S / CS
BWK B
L AM
SCS
B KB
LA
SC
BK
A
C
K
¡Figure 6: Page Write
S
T
A
R DEVICE
T ADDRESS
W
R
I
T
E
FIRST WORD SECOND WORD
ADDRESS
ADDRESS
DATA( n )
S
T
O
P
DATA( n+x )
DATA( n+1 )
SDA LINE
M
S
B
L R AM
S / CS
BWK B
L AM
SCS
B KB
L
S
B
A
C
K
A
C
K
A
C
K
A
C
K
BEIJING ESTEK ELECTRONICS CO.,LTD
7
24C32 / 24C64
¡Figure 7: Current Address Read
S
T
A
R DEVICE
T ADDRESS
R
E
A
D
S
T
O
P
DATA
SDA LINE
M
S
B
N
O
L RA
S/C
BWK
A
C
K
¡Figure 8: Random Read
W
S
R
T
I
A
R DEVICE T 1st, 2nd WORD
T ADDRESS E ADDRESS(n)
S
T
A
R DEVICE
T ADDRESS
R
E
A
D
S
T
O
P
DATA( n )
SDA LINE
M
S
B
A M
C S
K B
L RA
S/C
BWK
N
O
LRA
S /C
BWK
A
C
K
DUMMY WRITE
¡Figure 9: Sequential Read
R
E
DEVICE A
ADDRESS D
DATA( n+1 )
DATA( n )
S
T
O
P
DATA( n+x )
DATA( n+2 )
SDA LINE
RA
/C
WK
A
C
K
A
C
K
A
C
K
N
O
A
C
K
BEIJING ESTEK ELECTRONICS CO.,LTD
8
24C32 / 24C64
Electrical Characteristics
¡Absolute Maximum Stress Ratings
¡Comments
Stresses above those listed under "Absolute Maximum Ratings"
DC Supply Voltage . . . . . . . . . . . . . . . . .-0.3V to +6.5V
may cause permanent damage to this device. These are stress
ratings only. Functional operation of this device at these or any
Input / Output Voltage . . . . . . . .GND-0.3V to VCC+0.3V
other conditions above those indicated in the operational sections
Operating Ambient Temperature . . . . . -40。C to +85。C
of this specification is not implied or intended. Exposure to the
absolute maximum rating conditions for extended periods may
Storage Temperature . . . . . . . . . . . . -65。C to +150。C
affect device reliability.
DC Electrical Characteristics
= -40 。C to +85 。C, VCC = +1.8V to +5.5V (unless otherwise noted)
¡Applicable over recommended operating range from: T
A
Symbol
Min.
Typ.
Max.
Unit
Supply Voltage
Parameter
VCC
1.8
-
5.5
V
Condition
Supply Current VCC = 5.0V
ICC1
-
0.4
1.0
mA
READ at 100 kHz
Supply Current VCC = 5.0V
ICC2
-
2.0
3.0
mA
WRITE at 100 kHz
Standby Current
ISB
-
-
1.0
A
VIN = VCC or GND
Input Leakage Current
ILI
-
-
3.0
A
VIN = VCC or GND
Output Leakage Current
ILO
-
0.05
3.0
A
VOUT = VCC or GND
Input Low Level
VIL
-0.6
-
VCC X 0.3
V
Input High Level
VIH
VCC X 0.7
-
VCC + 0.5
V
Output Low Level VCC =5.0V
VOL3
-
-
0.4
V
IOL = 3.0 mA
Output Low Level VCC =3.0V
VOL2
-
-
0.4
V
IOL = 2.1 mA
Output Low Level VCC =1.8V
VOL1
-
-
0.2
V
IOL = 0.15 mA
Pin Capacitance
¡Applicable over recommended operating range from T
A
Parameter
= 25 。C, f = 1.0 MHz, VCC = +1.8V
Symbol
Min.
Typ.
Input/Output Capacitance (SDA)
CI/O
-
-
Max.
8
Unit
pF
VI/O = 0V
Condition
Input Capacitance (A0, A1, A2,
SCL)
CIN
-
-
6
pF
VIN = 0V
BEIJING ESTEK ELECTRONICS CO.,LTD
9
24C32 / 24C64
AC Electrical Characteristics
¡Applicable over recommended operating range from T
A
= -40。C to +85。C, VCC = +1.8V to +5.5V, CL = 1 TTL Gate and
100 pF (unless otherwise noted)
Parameter
Symbol
1.8-volt
5.0-volt
Min.
Typ.
Max.
Min.
Typ.
Max.
Units
Clock Frequency, SCL
fSCL
-
-
400
-
-
1000
kHz
Clock Pulse Width Low
tLOW
1.2
-
-
0.6
-
-
s
Clock Pulse Width High
tHIGH
0.6
-
-
0.4
-
-
s
Noise Suppression Time
tI
-
-
50
-
-
40
s
Clock Low to Data Out Valid
tAA
0.05
-
0.9
0.05
-
0.55
s
Time the bus must be free before
a new transmission can start
tBUF
1.2
-
-
0.5
-
-
s
tHD.STA
0.6
-
-
0.25
-
-
s
Start Setup Time
tSU.STA
0.6
-
-
0.25
-
-
s
Data In Hold Time
tHD.DAT
0
-
-
0
-
-
s
Data In Setup Time
tSU.DAT
100
-
-
100
-
-
ns
Inputs Rise Time(1)
tR
-
-
0.3
-
-
0.3
s
Start Hold Time
Inputs Fall Time(1)
Stop Setup Time
Data Out Hold Time
Write Cycle Time
。
5.0V, 25 C, Byte Mode
tF
-
-
300
-
-
100
ns
tSU.STO
0.6
-
-
0.25
-
-
s
tDH
50
-
-
50
-
-
ns
tWR
-
-
5
-
-
5
ms
Endurance
1M
-
-
-
-
-
Write Cycles
Note
1. This parameter is characterized and is not 100% tested.
2. AC measurement conditions:
RL (connects to VCC): 1.3 k
(2.5V, 5V), 10 k
(1.8V)
Input pulse voltages: 0.3 VCC to 0.7 VCC
Input rise and fall time:
50 ns
Input and output timing reference voltages: 0.5 VCC
The value of RL should be concerned according to the actual loading
on the user's system.
BEIJING ESTEK ELECTRONICS CO.,LTD
10
24C32 / 24C64
Bus Timing
¡Figure 10: SCL: Serial Clock, SDA: Serial Data I/O
tHIGH
tF
tLOW
tR
tLOW
SCL
tSU.STA
tHD.STA
tHD.DAT
tSU.DAT
tSU.STO
SDA_IN
tAA
tDH
tBUF
SDA_OUT
Write Cycle Timing
¡Figure 11: SCL: Serial Clock, SDA: Serial Data I/O
SCL
SDA
8th BIT
ACK
tWR(1)
STOP
CONDITION
START
CONDITION
Note
1. The write cycle time tWR is the time from a valid stop condition
of a write sequence to the end of the internal clear/write cycle.
BEIJING ESTEK ELECTRONICS CO.,LTD
11
24C32 / 24C64
Ordering Information
Code Number
Part Number
1.Prefix
K
24
XXX
X
1
2
3
4
4.Design Option
2.Series Name
24: Two-wire (I2C) Interface
3.EEPROM Density
C32=32K bits
C64=64K bits
o=
X
X
X
X
5
6
7
8
6. Temperature Range
。
。
。
。
I = Ind Temp(-40 C-85 C)
。
。
C = Com Temp(0 C-70 C)
(Blank)
5.Package Type
D = DIP
-
E = Exp Temp(-40 C-125 C)
-
X
9
8.Plating Technology
Blank = Standard SnPb plating
G = ECOPACK(RoHS compliant)
9.Operating Voltage
7.Pack Type
S=2.7~5.5
R = TSSOP
T = Tube
A=1.8~5.5
W = Wafer/die
R = Tape & Reel
S = SOP
Product Datasheet Change Notice
Datasheet Revision History
Version
Content
Date
1.0
Datasheet
Mar., 2007
BEIJING ESTEK ELECTRONICS CO.,LTD
12
Similar pages