Mitel MT8804 Cmos 8 x 4 analog switch array Datasheet

CMOS MT8804A
8 x 4 Analog Switch Array

Features
ISSUE 2
•
Microprocessor compatible control inputs
•
On chip control memory and address decoding
•
Row addressing
•
Master reset
•
32 crosspoint switches in 8 x 4 array
•
5.0V to 15.0V operation
•
Low crosstalk between switches
•
Low on resistance: 90Ω (typ.) at 13V
•
Matched switch characteristics
•
Switches frequencies up to 40MHz
Ordering Information
MT8804AC
24 Pin Ceramic DIP
MT8804AE
24 Pin Plastic DIP
MT8804AP
28 Pin PLCC
-40° to 85°C
Description
The MT8804A is a CMOS/LSI 8 x 4 Analog Switch
Array incorporating control memory (32 bits), decoder and digital logic level converters. This circuit has
digitally controlled analog switches having very low
“ON“ resistance and very low “OFF” leakage current.
Switches will operate with analog signals at
frequencies to 40 MHz and up to 15.0Vp-p. A
“HIGH“ on the Master Reset input switches all
channels “OFF“ and clears the memory. This device
is ideal for crosspoint switching applications.
Applications
•
PABX and key sytems
•
Data acquisition systems
•
Test equipment/instrumentation
•
Analog/digital multiplexers
AE
D0 D1 D2 D3
1
VDD
VEE
VSS
1
8 x 4
3 to 8
Decoder
Latches
Switch
Array
A2
8
••••••••••••••••
A0
A1
October 1989
Li I/O
(i=0-7)
32
•••••••••••••••••••
MR
Ji I/O (i=0-3)
Figure 1 - Functional Block Diagram
3-3
CMOS
NC
L0
L1
L2
VDD
L3
L4
MT8804A
VDD
L3
L4
L5
L6
L7
MR
AE
A2
A1
A0
VEE
4
3
2
1
28
27
26
24
23
22
21
20
19
18
17
16
15
14
13
NC
D0
J0
D1
J1
D2
J2
5
6
7
8
9
10
11
•
12
13
14
15
16
17
18
1
2
3
4
5
6
7
8
9
10
11
12
25
24
23
22
21
20
19
L5
L6
L7
MR
AE
A2
NC
D3
J3
VSS
VEE
A0
A1
NC
L2
L1
L0
D0
J0
D1
J1
D2
J2
D3
J3
VSS
28 PIN PLCC
24 PIN CERDIP/PLASTIC DIP
Figure 2 - Pin Connections
Pin Description
Pin #*
Name
Description
1-3
L2-L0
L2-L0 Analog Lines (Inputs/Outputs): these are connected to the L2-L0 columns of the
switch array.
4
D0
D0 Data (Input): Active High.
5
J0
J0 Analog Junctor (Input/Output): this is connected to the J0 row of the switch array.
6
DI
DI Data (Input). Active High.
7
J1
J1 Analog Junctor (Input/Output): this is connected to the J1 row of the switch array.
8
D2
D2 Data (Input): Active High.
9
J2
J2 Analog Junctor (Input/Output): this is connected to the J2 row of the switch array.
10
D3
D3 Data (Input): Active High.
11
J3
J3 Analog Junctor (Input/Output): this is connected to the J3 row of the switch array.
12
VSS
Digital Ground Reference.
13
VEE
Negative Power Supply.
14-16
A0-A2
17
AE
Address Enable/Strobe (Input): enables function selected by address and data. Address
must be stable before AE goes high and D0-D3 must be stable on the falling edge of the
AE. Active High.
18
MR
Master RESET (Input): this is used to turn off all switches. Active High.
19-23
L7-L3
24
VDD
A0-A2 Address Lines (Inputs).
L7-L3 Analog Lines (Inputs/Outputs): these are connected to the L7-L3 columns of the
switch array.
Positive Power Supply.
* Plastic DIP and CERDIP only
3-4
CMOS
MT8804A
Functional Description
The MT8804A is a CMOS/LSI 8 X 4 Analog Switch
Array incorporating an 8 X 4 analog switch array,
address decoder, control memory, and digital logic
level converter.
The analog switch array is arranged in 8 rows and 4
columns. The row input/outputs are referred to as
Lines (L0-L7) and the column input/outputs as
Junctors (J0-J3). The crosspoint analog switches
interconnect the lines and junctors when turned “ON”
and provide a high degree of isolation when turned
“OFF”. Interchannel crosstalk is minimal despite the
high density of the analog switch array. The control
memory of the MT8804A can be treated as an 8
word by 4 bit random access memory. The 8 words
are selected by the ADDRESS (A0-A2) inputs
through the on chip address decoder. Data is
presented to the memory via the four DATA inputs
(D0-D3). This data is asynchronously written into the
control memory whenever the ADDRESS ENABLE
(AE) input is HIGH. A HIGH level written into a
memory cell turns the corresponding crosspoint
switch “ON” while a LOW level causes the crosspoint
to turn “OFF”.
Only the crosspoint switches corresponding to the
addressed memory word are affected when data is
written into the memory. The remaining switches
retain their previous states. By establishing
appropriate patterns in the control memory, any
combination of lines and junctors may be
interconnected. A HIGH level on the MASTER
RESET (MR) input returns all memory locations to a
LOW level and turns all crosspoint switches “OFF”
effectively isolating the lines from the junctors. The
digital logic level converters allow the digital input
levels to differ from limits of the analog levels
switched through the array. For example, with
Figure 3 - On Resistance vs. Temperature
(Input Signal Voltage=Supply Voltage/2)
VDD=5V, V SS=0V and VEE=-6V, the control inputs
can be driven by a 5V system while the analog
voltages through the crosspoint switches can swing
from +5V to -6V.
Figure 4 - On Resistance vs. Input Signal Voltage
8x8 Analog/Digital Switch
Two MT8804s configured as shown, implement
an 8 x 8 analog/digital switch. The switch capacity
can be expanded to an M x N array of inputs/
outputs. Expansion in the M dimension is as
shown with the MT8804A lines (L0-L7)
commoned. Expansion in the N dimension is
accomplished by replicating the circuit shown and
connecting the MT8804A junctors (J0-J3) in
common. The address and data control inputs of
the MT8804A’s can be connected in common for
any size and switch provided that the address
enable (AE) inputs are driven individually. A
particular signal path is connected by setting up
the appropriate signals or the address and data
lines and taking the corresponding address
enable input high. The master reset (MR), when
taken high, disconnects all signal paths.
Figure 5 - 8 x 8 Analog/Digital Switch
3-5
MT8804A
CMOS
Absolute Maximum Ratings* - Voltages are with respect to VEE unless otherwise stated.
Parameter
Symbol
Min
Max
Units
VDD-VSS
VDD-VEE
VSS-VEE
-0.3
-0.3
-0.3
16
16
16
V
V
V
1
Supply Voltage
2
Analog Input Voltage
VINA
VEE-0.3
VDD+0.3
V
3
Digital Input Voltage
VIN
VSS-0.3
VDD+0.3
V
4
Current on any Logic Pin
10
mA
5
Storage Temperature
+150
°C
6
Package Power Dissipation
0.6
1.2
W
W
I
-65
TS
PLASTIC DIP
CERDIP
PD
PD
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Recommended Operating Conditions - Voltages are with respect to VEE unless otherwise stated.
Characteristics
Sym
Min
Typ
Max
Units
TO
-40
25
85
°C
VDD-V SS
VDD-V EE
VSS-VEE
5
5
0
5
10
5
15
15
10
V
V
V
1
Operating Temperature
2
Supply Voltage
3
Analog Input Voltage
VINA
VEE
VDD
V
4
Digital Input Voltage
VIN
VSS
VDD
V
DC Electrical Characteristics† Characteristics
Test Conditions
Voltages are with respect to VEE=VSS=0V.
Sym
Min
Typ‡
Max
Units
Test Conditions
1
Quiescent Supply Current
IDD
1
100
µA
VDD=15V. All digital inputs at
VIN=VSS or VDD
2
Off-state Leakage Current
(Any line to any junctor)
IOFF
±0.1
±500
nA
VDD=13V, Switch is ‘Off’
IVJi - VLjI = VDD - VEE
3
Input Logic “0” level
VIL
3.0
1.5
V
V
VDD =10V
VDD=5V
VINA=VDD through 1kΩ
4
Input Logic “1” level
VIH
V
V
VDD =10V
VDD=5V
VINA=VDD through 1kΩ
5
Maximum current through
Crosspoint Switch
IMAX
7.0
3.5
±8.0
mA
VDD=13V
† DC Electrical Characteristics are at ambient temperature (25°C).
‡ Typical figures are for design aid only; not guaranteed and not subject to production testing.
DC Electrical Characteristics- Switch Resistance - VDC is the external DC offset applied at the analog I/O pins.
Characteristics
1 On-state
VDD=13V
Resistance VDD=10V
VDD= 5V
2 Difference in on-state
resistance between
two switches
VDD=13V
VDD=10V
3-6
Sym
R ON
∆RON
25°C
70°C
85°C
Units
Test Conditions
Min
Typ
Max
Typ
Typ
60
90
105
290
108
160
650
105
120
320
110
125
325
Ω
Ω
Ω
VSS=VEE=0V,VDC=VDD/2,
IVJi - VLjI = 0.6V
20
30
20
30
Ω
Ω
VSS=VEE=0V,VDC=VDD/2,
IVJi - VLjI = 0.6V
20
30
CMOS
MT8804A
AC Electrical Characteristics† - Crosspoint Performance -VDC is the external DC offset applied at the analog
I/O pins. Voltages are with respect to VDD=10V, VSS=V EE=0V unless otherwise stated.
1
2
3
4
5
6
7
Characteristics
Sym
Switch Line Capacitance
Switch Junctor Capacitance
Feedthrough Capacitance
Frequency Response
Channel “ON”
20LOG(VOUT / VINA) = -3dB
Total Harmonic Distortion
VDD=15V/VDC=7.5V
VDD=10V/VDC=5V
VDD=5V/VDC=2.5V
Feedthrough
Channel “OFF”
Feed.=20LOG (VOUT / VINA)
Crosstalk between any two
channels for switches Li - Ji and
Lj - Jj.
CIS
COS
CI
F3dB
Min
Typ‡
Max
Units
5
20
0.2
40
pF
pF
pF
MHz
FDT
0.1
0.2
1.0
-50
%
%
%
dB
Xtalk
-40
dB
-90
dB
THD
Li - Ji is “ON“
Lj - Jj is “OFF“
Test Conditions
Switch is “ON”; VDC=5V,
VINA=5Vpp sinewave
f= 1kHz; RL = 1kΩ
Switch is “ON”; VEE=VSS=0V
VINA=5Vpp sinewave
f= 1kHz;
RL = 10kΩ
All Switches “OFF”; VINA=
5Vpp sinewave f= 1MHz;
RL= 1kΩ. VDC=5V
VINA=2Vpp sinewave
f= 1.0MHz; RL = 600Ω.
VINA=2Vpp sinewave
f= 3.4kHz; RL = 600Ω.
VDC = 5V
8
Xtalk=20LOG (VJj/VLi).
Propagation delay through
switch
10
tPS
ns
CL=50pF
† AC Electrical Characteristics are at ambient temperature (25°C).
‡ Typical figures are for design aid only; not guaranteed and not subject to production testing.
AC Electrical Characteristics† - Control and I/O Timings- Voltages are with respect
to VSS=VEE=0V unless
otherwise stated.
Characteristics
Sym
1
2
Digital Input Capacitance
Setup Time D0-D3 to AE
CDI
tDS
3
Hold Time D0-D3 to AE
tDH
4
Setup Time Address to AE
tAS
5
Hold Time Address to AE
tAH
6
AE Pulse Width
tAEW
7
AE to Switch Status Delay
tPAE
8
DATA to Switch Status Delay
9
MR to Switch Status Delay
tPLH
tPHL
tMR
tMRR
Min
Typ‡
Max
Units
300
900
400
1000
400
600
350
750
pF
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
150
200
120
300
0
50
120
300
100
250
200
650
250
650
250
500
200
500
Test Conditions
VDD=10V
VDD=10V
VDD=5V
VDD=10V
VDD=5V
VDD=10V
VDD=5V
VDD=10V
VDD=5V
VDD=10V
VDD=5V
VDD=10V
VDD=5V
VDD=10V
VDD=5V
VDD=10V
VDD=5V
VDD=10V
VDD=5V
See Note 1
See Note 1
See Note 2
† AC Electrical Characteristics are at ambient temperature (25°C).
‡ Typical figures are for design aid only; not guaranteed and not subject to production testing.
Note 1 R L = 10kΩ, C L=50pF
Note 2 R L = 1kΩ, C L =50pF
Digital Input rise time (tr) and fall time (tf) = 5ns.
3-7
MT8804A
CMOS
50%
MR
50%
tAEW
AE
50%
50%
50%
tAS
ADDRESS
50%
50%
tAH
D0-D3
50%
tDS
SWITCH
50%
tDH
ON
OFF
tPLH /tPHL
tPAE
tMRR
tMR
tPLH/tPHL
Figure 6 - Control Memory Timing Diagram
Input Data To Control
Memory
Junctors Connected To
Addressed Line
Memory
Reset
MR
Address
Enable
AE
A2
A1
A0
D3
D2
D1
D0
1
X
X
X
X
ALL
X
X
X
X
0
0
X
X
X
NONE
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
L0
L0
L0
L0
L0
L0
L0
L0
L0
L0
L0
L0
L0
L0
L0
L0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
L1
0
0
0
0
•
•
•
•
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
+
Address
Addressed
Line
J2
J1
J0
All Switches "OFF"
No Change of State
•
•
•
•
•
•
•
•
+
+
+
+
+
+
+
+
•
•
•
•
+
+
+
+
•
•
•
•
+
+
+
+
•
•
+
+
•
•
+
+
•
•
+
+
•
•
+
+
•
+
•
+
•
+
•
+
•
+
•
+
•
+
•
+
0
1
0
0
1
L1
1
1
1
1
+
+
+
0
1
0
1
0
L2
0
0
0
0
•
•
•
•
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
+
0
1
0
1
0
L2
1
1
1
1
+
+
+
0
1
0
1
1
L3
0
0
0
0
•
•
•
•
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
+
0
1
0
1
1
L3
1
1
1
1
+
+
+
0
1
1
0
0
L4
0
0
0
0
•
•
•
•
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
+
0
1
1
0
0
L4
1
1
1
1
+
+
+
0
1
1
0
1
L5
0
0
0
0
•
•
•
•
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
+
0
1
1
0
1
L5
1
1
1
1
+
+
+
0
1
1
1
0
L6
0
0
0
0
•
•
•
•
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
+
0
1
1
1
0
L6
1
1
1
1
+
+
+
0
1
1
1
1
L7
0
0
0
0
•
•
•
•
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
0
1
1
1
1
L7
1
1
1
1
+
+
+
+
Table 1 - Address Decode Truth Table
NOTES:
3-8
J3
0 - Low Logic Level
1 - High Logic Level
X - Don’t Care Condition
+ - Indicates Connection Between Junctor and Addressed Line
• - Indicates No Connection Between Junctor and Addressed Line