IDT IDT8N3S271 Fourth generation femtoclock Datasheet

IDT8N3S271
LVPECL Frequency-Programmable
Crystal Oscillator
DATA SHEET
General Description
Features
The IDT8N3S271 is a Frequency-Programmable Crystal Oscillator
with very flexible frequency programming capabilities. The device
uses IDT’s fourth generation FemtoClock® NG technology for an
optimum of high clock frequency and low phase noise performance.
The device accepts 2.5V or 3.3V supply and is packaged in a small,
lead-free (RoHS 6) 6-lead ceramic 5mm x 7mm x 1.55mm package.
•
•
Fourth generation FemtoClock® NG technology
•
•
•
Frequency programming resolution is 218Hz and better
•
RMS phase jitter @ 156.25MHz (12kHz - 20MHz): 0.24ps
(typical), integer PLL feedback configuration
•
RMS phase jitter @ 156.25MHz (1kHz - 40MHz): 0.27ps (typical),
integer PLL feedback configuration
•
•
•
2.5V or 3.3V supply
The device can be factory programmed to any frequency in the range
from 15.476MHz to 866.67MHz and from 975MHz to 1,300MHz and
supports a very high degree of frequency precision of 218Hz or
better. The extended temperature range supports wireless
infrastructure, telecommunication and networking end equipment
requirements.
Factory-programmable clock output frequency from 15.476MHz to
866.67MHz and from 975MHz to 1,300MHz
One 2.5V or 3.3V LVPECL clock output
Output enable control (positive polarity), LVCMOS/LVTTL
compatible
-40°C to 85°C ambient operating temperature
Available in a lead-free (RoHS 6) 6-pin ceramic package
Block Diagram
Pin Assignment
÷P
OSC
PFD
&
LPF
FemtoClock® NG
VCO
1950-2600MHz
Q
nQ
÷N
fXTAL
2
÷MINT, MFRAC
7
25
DNU
1
6
VCC
OE
2
5
nQ
VEE
3
4
Q
IDT8N3S271
6-lead ceramic 5mm x 7mm x 1.55mm
package body
CD Package
Top View
Configuration Register (ROM)
OE
Pullup
IDT8N3S271CCD
REVISION A DECEMBER 17, 2012
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©2012 Integrated Device Technology, Inc.
IDT8N3S271 Data Sheet
LVPECL FREQUENCY-PROGRAMMABLE CRYSTAL OSCILLATOR
Pin Description and Characteristic Tables
Table 1. Pin Descriptions
Number
Name
Type
Description
1
DNU
2
OE
Input
3
VEE
Power
Negative power supply.
4, 5
Q, nQ
Output
Differential clock output. LVPECL interface levels.
6
VCC
Power
Positive power supply.
Do not use (factory use only).
Pullup
Output enable pin. See Table 3A for function. LVCMOS/LVTTL interface levels.
NOTE: Pullup refers to internal input resistor. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
Test Conditions
CIN
Input Capacitance
RPULLUP
Input Pullup Resistor
OE
Minimum
Typical
Maximum
Units
5.5
pF
50
k
Function Tables
Table 3A. OE Configuration
Input
OE
0
1 (default)
Output Enable
Outputs Q, nQ are in high-impedance state.
Outputs are enabled.
NOTE: OE is an asynchronous control.
Table 3B. Output Frequency Range
15.476MHz to 866.67MHz
975MHz to 1,300MHz
NOTE: Supported output frequency range. The output frequency can be programmed to any frequency in this range and to a precision of
218Hz or better.
IDT8N3S271CCD REVISION A DECEMBER 17, 2012
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©2012 Integrated Device Technology, Inc.
IDT8N3S271 Data Sheet
LVPECL FREQUENCY-PROGRAMMABLE CRYSTAL OSCILLATOR
Principles of Operation
18-bit fractional portion (MFRAC) and provides the means for
high-resolution frequency generation. The output frequency fOUT is
calculated by:
The block diagram consists of the internal 3rd overtone crystal and
oscillator which provide the reference clock fXTAL of either
114.285MHz or 100MHz. The PLL includes the FemtoClock NG VCO
along with the Pre-divider (P), the feedback divider (M) and the post
divider (N). The P, M, and N dividers determine the output frequency
based on the fXTAL reference. The feedback divider is fractional
supporting a huge number of output frequencies. The configuration
of the feedback divider to integer-only values results in an improved
output phase noise characteristics at the expense of the range of
output frequencies. Internal registers are used to hold one factory
pre-set P, M, and N configuration setting. The P, M, and N frequency
configuration supports an output frequency range from 15.476MHz to
866.67MHz and from 975MHz to 1,300MHz.
1
+ 0.5f OUT = f XTAL  ------------  MINT + MFRAC
-----------------------------------PN
18
2
Frequency Configuration
An order code is assigned to each frequency configuration
programmed by the factory (default frequencies). For more
information on the available default frequencies and order codes,
please see the Ordering Information section in this document. For
available order codes, see the FemtoClock NG Ceramic-Package XO
and VCXO Ordering Product Information document.
The devices use the fractional feedback divider with a delta-sigma
modulator for noise shaping and robust frequency synthesis
capability. The relatively high reference frequency minimizes phase
noise generated by frequency multiplication and allows more efficient
shaping of noise by the delta-sigma modulator.
For more information on programming capabilities of the device for
custom frequency and pull-range configurations, see the FemtoClock
NG Ceramic 5x7 Module Programming Guide.
The output frequency is determined by the 2-bit pre-divider (P), the
feedback divider (M) and the 7-bit post divider (N). The feedback
divider (M) consists of both a 7-bit integer portion (MINT) and an
IDT8N3S271CCD REVISION A DECEMBER 17, 2012
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©2012 Integrated Device Technology, Inc.
IDT8N3S271 Data Sheet
LVPECL FREQUENCY-PROGRAMMABLE CRYSTAL OSCILLATOR
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum
Ratings may cause permanent damage to the device. These ratings
are stress specifications only. Functional operation of product at
these conditions or any conditions beyond those listed in the DC
Characteristics or AC Characteristics is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect
product reliability.
Item
Rating
Supply Voltage, VCC
3.63V
Inputs, VI
-0.5V to VCC + 0.5V
Outputs, IO 
Continuous Current
Surge Current
50mA
100mA
Package Thermal Impedance, JA
49.4C/W (0 mps)
Storage Temperature, TSTG
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
VCC
Power Supply Voltage
IEE
Power Supply Current
Test Conditions
Minimum
Typical
Maximum
Units
3.135
3.3
3.465
V
123
148
mA

Table 4B. Power Supply DC Characteristics, VCC = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
VCC
Power Supply Voltage
IEE
Power Supply Current
Test Conditions
Minimum
Typical
Maximum
Units
2.375
2.5
2.625
V
119
143
mA

Table 4C. LVPECL DC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
VOH
Output High Voltage; NOTE 1
VOL
Output Low Voltage; NOTE 1
VSWING
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
Typical
Maximum
Units
VCC – 1.4
VCC – 0.8
V
VCC – 2.0
VCC – 1.6
V
0.6
1.0
V
Maximum
Units
NOTE 1: Outputs terminated with 50 to VCC – 2V.
Table 4D. LVPECL DC Characteristics, VCC = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
VOH
Output High Voltage; NOTE 1
VCC – 1.4
VCC – 0.8
V
VOL
Output Low Voltage; NOTE 1
VCC – 2.0
VCC – 1.5
V
VSWING
Peak-to-Peak Output Voltage Swing
0.4
1.0
V
NOTE 1: Outputs terminated with 50 to VCC – 2V.
IDT8N3S271CCD REVISION A DECEMBER 17, 2012
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©2012 Integrated Device Technology, Inc.
IDT8N3S271 Data Sheet
LVPECL FREQUENCY-PROGRAMMABLE CRYSTAL OSCILLATOR
Table 4E. LVCMOS/LVTTL DC Characteristic, VCC = 3.3V ± 5% or 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
VIH
Input High Voltage
VIL
Input Low Voltage
IIH
Input High Current
OE
VCC = VIN = 3.465V or 2.625V
IIL
Input Low Current
OE
VCC = 3.465V or 2.625V, VIN = 0V
IDT8N3S271CCD REVISION A DECEMBER 17, 2012
Test Conditions
Minimum
VCC = 3.3V
Maximum
Units
2
VCC + 0.3
V
VCC = 2.5V
1.7
VCC + 0.3
V
VCC = VIN = 3.465V
-0.3
0.8
V
VCC = VIN = 2.5V
-0.3
0.7
V
10
µA
5
-150
Typical
µA
©2012 Integrated Device Technology, Inc.
IDT8N3S271 Data Sheet
LVPECL FREQUENCY-PROGRAMMABLE CRYSTAL OSCILLATOR
AC Electrical Characteristics
Table 5. AC Characteristics, VCC = 3.3V ± 5% or 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
fOUT
Output Frequency Q, nQ
fI
Initial Accuracy
fS
Temperature Stability
fA
fT
Aging
Total Stability
tjit(cc)
Cycle-to-Cycle Jitter; NOTE 1
tjit(per)
RMS Period Jitter; NOTE 1
RMS Phase Jitter (Random);
Fractional PLL feedback and
fXTAL = 100MHz (2xxx order codes)
tjit(Ø)
RMS Phase Jitter (Random);
Integer PLL feedback and
fXTAL = 100MHz (1xxx order codes)
RMS Phase Jitter (Random)
Fractional PLL feedback and
fXTAL = 114.285MHz (0xxx order codes)
Test Conditions
Minimum
Maximum
Units
15.476
Typical
866.67
MHz
975
1,300
MHz
Measured @ 25°C
±10
ppm
Option code = A or B
±100
ppm
Option code = E or F
±50
ppm
Option code = K or L
±20
ppm
Frequency drift over 10 year life
±3
ppm
Frequency drift over 15 year life
±5
ppm
Option code A, B (10 year life)
±113
ppm
Option code E, F (10 year life)
±63
ppm
Option code K, L (10 year life)
±33
ppm
30
ps
1.9
2.8
ps
17MHz fOUT 1300MHz,
NOTE 2, 3, 4
0.497
0.882
ps
500MHz fOUT 1300MHz,
NOTE 2, 3, 4
0.232
0.322
ps
125MHz fOUT 500MHz,
NOTE 2, 3, 4
0.250
0.384
ps
17MHz fOUT 125MHz,
NOTE 2, 3, 4
0.275
0.405
ps
fOUT 156.25MHz, NOTE 2, 3, 4
0.242
0.311
ps
fOUT 156.25MHz, NOTE 2, 3, 5
0.275
0.359
ps
17MHz fOUT 1300MHz,
NOTE 2, 3, 4
0.474
0.986
ps
N(100)
Single-side band phase noise, 
100Hz from Carrier
156.25MHz
-92
dBc/Hz
N(1k)
Single-side band phase noise, 
1kHz from Carrier
156.25MHz
-120
dBc/Hz
N(10k)
Single-side band phase noise, 
10kHz from Carrier
156.25MHz
-131
dBc/Hz
N(100k)
Single-side band phase noise, 
100kHz from Carrier
156.25MHz
-138
dBc/Hz
N(1M)
Single-side band phase noise, 
1MHz from Carrier
156.25MHz
-139
dBc/Hz
N(10M)
Single-side band phase noise, 
10MHz from Carrier
156.25MHz
-154
dBc/Hz
t R / tF
Output Rise/Fall Time
20% to 80%
odc
Output Duty Cycle
tSTARTUP
Device startup time after power up
50
450
ps
47
53
%
20
ms
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
IDT8N3S271CCD REVISION A DECEMBER 17, 2012
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©2012 Integrated Device Technology, Inc.
IDT8N3S271 Data Sheet
LVPECL FREQUENCY-PROGRAMMABLE CRYSTAL OSCILLATOR
has been reached under these conditions.
NOTE: XTAL parameters (initial accuracy, temperature stability, aging and total stability) are guaranteed by manufacturing.
NOTE 1: This parameter is defined in accordance with JEDEC standard 65.
NOTE 2: Refer to the phase noise plot.
NOTE 3: Please see the FemtoClockNG® Ceramic 5x7 Modules Programming guide for more information on PLL feedback modes and the
optimum configuration for phase noise. Integer PLL feedback is the default operation for the dddd = 1xxx order codes.
NOTE 4: Integration range: 12kHz - 20MHz.
NOTE 5: Integration range: 1kHz - 40MHz.
IDT8N3S271CCD REVISION A DECEMBER 17, 2012
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©2012 Integrated Device Technology, Inc.
IDT8N3S271 Data Sheet
LVPECL FREQUENCY-PROGRAMMABLE CRYSTAL OSCILLATOR
Noise Power dBc/Hz
Typical Phase Noise at 156.25MHz (12kHz - 20MHz)
Offset Frequency (Hz)
IDT8N3S271CCD REVISION A DECEMBER 17, 2012
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©2012 Integrated Device Technology, Inc.
IDT8N3S271 Data Sheet
LVPECL FREQUENCY-PROGRAMMABLE CRYSTAL OSCILLATOR
Parameter Measurement Information
2V
2V
VCC
Qx
SCOPE
VCC
Qx
SCOPE
nQx
nQx
VEE
VEE
-1.3V±0.165V
-0.5V± 0.125V
3.3V LVPECL Output Load Test Circuit
2.5V LVPECL Output Load Test Circuit
Noise Power
Phase Noise Plot
nQ
80%
80%
VSW I N G
Q
20%
20%
tF
tR
Offset Frequency
f1
f2
RMS Phase Jitter =
1
* Area Under Curve Defined by the Offset Frequency Markers
2* *ƒ
RMS Phase Jitter
Output Rise/Fall Time
nQ
nQ
Q
Q
t PW
➤
odc =
PERIOD
t PW
tcycle n
➤
t
➤
tcycle n+1
➤
tjit(cc) = |tcycle n – tcycle n+1|
1000 Cycles
x 100%
t PERIOD
Output Duty Cycle/Pulse Width/Period
IDT8N3S271CCD REVISION A DECEMBER 17, 2012
Cycle-to-Cycle Jitter
9
©2012 Integrated Device Technology, Inc.
IDT8N3S271 Data Sheet
LVPECL FREQUENCY-PROGRAMMABLE CRYSTAL OSCILLATOR
Parameter Measurement Information, continued
VOH
VREF
VOL
1σ contains 68.26% of all measurements
2σ contains 95.4% of all measurements
3σ contains 99.73% of all measurements
4σ contains 99.99366% of all measurements
6σ contains (100-1.973x10-7)% of all measurements
Histogram
Reference Point
Mean Period
(Trigger Edge)
(First edge after trigger)
RMS Period Jitter
Applications Information
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
transmission lines. Matched impedance techniques should be used
to maximize operating frequency and minimize signal distortion.
Figures 1A and 1B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and clock
component process variations.
The differential outputs are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50
R3
125Ω
3.3V
3.3V
Zo = 50Ω
3.3V
R4
125Ω
3.3V
3.3V
+
Zo = 50Ω
+
_
LVPECL
Input
Zo = 50Ω
R1
50Ω
_
LVPECL
R2
50Ω
R1
84Ω
VCC - 2V
RTT =
1
* Zo
((VOH + VOL) / (VCC – 2)) – 2
Input
Zo = 50Ω
R2
84Ω
RTT
Figure 1A. 3.3V LVPECL Output Termination
IDT8N3S271CCD REVISION A DECEMBER 17, 2012
Figure 1B. 3.3V LVPECL Output Termination
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©2012 Integrated Device Technology, Inc.
IDT8N3S271 Data Sheet
LVPECL FREQUENCY-PROGRAMMABLE CRYSTAL OSCILLATOR
Termination for 2.5V LVPECL Outputs
level. The R3 in Figure 2B can be eliminated and the termination is
shown in Figure 2C.
Figure 2A and Figure 2B show examples of termination for 2.5V
LVPECL driver. These terminations are equivalent to terminating 50
to VCC – 2V. For VCC = 2.5V, the VCC – 2V is very close to ground
2.5V
VCC = 2.5V
2.5V
2.5V
VCC = 2.5V
R1
250Ω
50Ω
R3
250Ω
+
50Ω
+
50Ω
–
50Ω
2.5V LVPECL Driver
–
R1
50Ω
2.5V LVPECL Driver
R2
62.5Ω
R2
50Ω
R4
62.5Ω
R3
18Ω
Figure 2A. 2.5V LVPECL Driver Termination Example
Figure 2B. 2.5V LVPECL Driver Termination Example
2.5V
VCC = 2.5V
50Ω
+
50Ω
–
2.5V LVPECL Driver
R1
50Ω
R2
50Ω
Figure 2C. 2.5V LVPECL Driver Termination Example
IDT8N3S271CCD REVISION A DECEMBER 17, 2012
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©2012 Integrated Device Technology, Inc.
IDT8N3S271 Data Sheet
LVPECL FREQUENCY-PROGRAMMABLE CRYSTAL OSCILLATOR
Schematic Layout
Figure 3 shows an example IDT8N3S271 application schematic. The
schematic example focuses on functional connections and is
intended as an example only and may not represent the exact user
configuration. Refer to the pin description and functional tables in the
datasheet to ensure the logic control inputs are properly set. For
example OE can be configured from an FPGA instead of set with
pullup and pulldown resistors as shown.
capacitor on the VCC pin must be placed on the device side with direct
return to the ground plane though vias. The remaining filter
components can be on the opposite side of the PCB.
Power supply filter component recommendations are a general
guideline to be used for reducing external noise from coupling into
the devices. The filter performance is designed for a wide range of
noise frequencies. This low-pass filter starts to attenuate noise at
approximately 10kHz. If a specific frequency noise component is
known, such as switching power supplies frequencies, it is
recommended that component values be adjusted and if required,
additional filtering be added. Additionally, good general design
practices for power plane voltage stability suggests adding bulk
capacitance in the local area of all devices.
As with any high speed analog circuitry, the power supply pins are
vulnerable to random noise, so to achieve optimum jitter performance
isolation of the VCC pin from power supply is required. In order to
achieve the best possible filtering, it is recommended that the
placement of the filter components be on the device side of the PCB
as close to the power pins as possible. If space is limited, the 0.1µF
Logic Control Input Examples
Set Logic
Input to '1'
VCC
RU1
1K
Set Logic
Input to '0'
VCC
RU2
Not Install
To Logic
Input
pins
RD1
Not Install
To Logic
Input
pins
RD2
1K
3.3V
U1
OE
2
3
DNU VCC
OE
Q
VEE
nQ
6
4
5
C3
0.1uF
1
BLM18BB221SN1
C4
10uF
1
FB1
2
VCC
C5
0.1uF
Place 0.1uF bypass cap
directly adjacent to
the VCC pin.
Zo = 50 Ohm
+
Zo = 50 Ohm
-
R2
50
R1
50
+3.3V PECL Receiv er
R3
50
For AC termination options consult the IDT Applications Note
"Termination - LVPECL"
Figure 3. IDT8N3S271 Schematic Example
IDT8N3S271CCD REVISION A DECEMBER 17, 2012
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©2012 Integrated Device Technology, Inc.
IDT8N3S271 Data Sheet
LVPECL FREQUENCY-PROGRAMMABLE CRYSTAL OSCILLATOR
Power Considerations
This section provides information on power dissipation and junction temperature for the IDT8N3S271. 
Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the IDT8N3S271 is the sum of the core power plus the output power dissipated due to the loading. 
The following is the power dissipation for VCC = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating output power dissipated due to the loading.
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 148mA = 512.82mW
•
Power (outputs)MAX = 34.2mW/Loaded Output pair
Total Power_MAX (3.465V, with all outputs switching) = 512.82mW + 32mW = 544.82mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 49.4°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.545W * 49.4°C/W = 111.9°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 6. Thermal Resistance JA for 6 Lead Ceramic VFQFN, Forced Convection
JA by Velocity
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
IDT8N3S271CCD REVISION A DECEMBER 17, 2012
0
1
2
49.4°C/W
44.2°C/W
42.1°C/W
13
©2012 Integrated Device Technology, Inc.
IDT8N3S271 Data Sheet
LVPECL FREQUENCY-PROGRAMMABLE CRYSTAL OSCILLATOR
3. Calculations and Equations.
The purpose of this section is to calculate the power dissipation for the LVPECL output pair.
LVPECL output driver circuit and termination are shown in Figure 4.
VCC
Q1
VOUT
RL
50Ω
VCC - 2V
Figure 4. LVPECL Driver Circuit and Termination
To calculate power dissipation per output pair due to the loading, use the following equations which assume a 50 load, and a termination
voltage of VCC – 2V.
•
For logic high, VOUT = VOH_MAX = VCC_MAX – 0.8V
(VCC_MAX – VOH_MAX) = 0.8V
•
For logic low, VOUT = VOL_MAX = VCC_MAX – 1.6V
(VCC_MAX – VOL_MAX) = 1.6V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOH_MAX) = [(2V – (VCC_MAX – VOH_MAX))/RL] * (VCC_MAX – VOH_MAX) =
[(2V – 0.8V)/50] * 0.8V = 19.2mW
Pd_L = [(VOL_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOL_MAX) = [(2V – (VCC_MAX – VOL_MAX))/RL] * (VCC_MAX – VOL_MAX) =
[(2V – 1.6V)/50] * 1.6V = 12.8mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 32mW
IDT8N3S271CCD REVISION A DECEMBER 17, 2012
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©2012 Integrated Device Technology, Inc.
IDT8N3S271 Data Sheet
LVPECL FREQUENCY-PROGRAMMABLE CRYSTAL OSCILLATOR
Reliability Information
Table 7. JA vs. Air Flow Table for a 6-lead Ceramic 5mm x 7mm Package
JA vs. Air Flow
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
0
1
2
49.4°C/W
44.2°C/W
42.1°C/W
Transistor Count
The transistor count for IDT8N3S271 is: 47,511
IDT8N3S271CCD REVISION A DECEMBER 17, 2012
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©2012 Integrated Device Technology, Inc.
IDT8N3S271 Data Sheet
LVPECL FREQUENCY-PROGRAMMABLE CRYSTAL OSCILLATOR
Package Outline and Package Dimensions
IDT8N3S271CCD REVISION A DECEMBER 17, 2012
16
©2012 Integrated Device Technology, Inc.
IDT8N3S271 Data Sheet
LVPECL FREQUENCY-PROGRAMMABLE CRYSTAL OSCILLATOR
Ordering Information for FemtoClock NG Ceramic-Package XO and VCXO Products
The programmable VCXO and XO devices support a variety of
devices options such as the output type, number of default frequencies, internal crystal frequency, power supply voltage, ambient
temperature range and the frequency accuracy. The device options,
default frequencies and default VCXO pull range must be specified at
the time of order and are programmed by IDT before the shipment.
The table below specifies the available order codes, including the
device options and default frequency configurations. Example part
number: the order code 8N3QV01FG-0001CDI specifies a
programmable, quad default-frequency VCXO with a voltage supply
of 2.5V, a LVPECL output, a 50ppm crystal frequency accuracy,
contains a 114.285MHz internal crystal as frequency source,
industrial temperature range, a lead-free (6/6 RoHS) 6-lead ceramic
5mm x 7mm x 1.55mm package and is factory-programmed to the
default frequencies of 100MHz, 122.88MHz, 125MHz and
156.25MHz and to the VCXO pull range of min. 100ppm.
Other default frequencies and order codes are available from IDT on
request. For more information on available default frequencies, see
the FemtoClock NG Ceramic-Package XO and VCXO Ordering
Product Information document.
Part/Order Numbers
8N X
X
XXX X X - dddd XX X
X
Shipping Package
8: Tape & Reel
(no letter): Tray
FemtoClock NG
Ambient Temperature Range
“I”: Industrial: (TA = -40°C to 85°C)
(no letter) : (TA = 0°C to 70°C)
I/O Identifier
0: LVCMOS
3: LVPECL
4: LVDS
Package Code
CD: Lead-Free, 6/10-lead ceramic 5mm x 7mm x 1.55mm
Number of Default Frequencies
S: 1: Single
D: 2: Dual
Q: 4: Quad
Part Number
Function
#pins
OE fct. at
pin
001
XO
10
OE@2
003
XO
10
OE@1
V01
VCXO
10
OE@2
V03
VCXO
10
OE@1
V75
VCXO
6
OE@2
V76
VCXO
6
nOE@2
V85
VCXO
6
—
085
XO
6
OE@1
270
XO
6
OE@1
271
XO
6
OE@2
272
XO
6
nOE@2
273
XO
6
nOE@1
IDT8N3S271CCD REVISION A DECEMBER 17, 2012
Default-Frequency and VCXO Pull Range
See document FemtoClock NG Ceramic-Package XO and VCXO
Ordering Product Information.
dddd
fXTAL (MHz)
PLL Feedback
Use for
0000 to 0999
114.285
Fractional
VCXO, XO
Integer
XO
Fractional
XO
1000 to 1999
2000 to 2999
100.000
Last digit = L: configuration pre-programmed and not changeable
Die Revision
C
Option Code (Supply Voltage and Frequency-Stability)
A: VCC = 3.3V±5%, ±100ppm
B: VCC = 2.5V±5%, ±100ppm
E: VCC = 3.3V±5%, ±50ppm
F: VCC = 2.5V±5%, ±50ppm
K: VCC = 3.3V±5%, ±20ppm
L: VCC = 2.5V±5%, ±20ppm
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©2012 Integrated Device Technology, Inc.
IDT8N3S271 Data Sheet
LVPECL FREQUENCY-PROGRAMMABLE CRYSTAL OSCILLATOR
Table 8. Device Marking
Marking
Industrial Temperature Range (TA = -40°C to 85°C)
Commercial Temperature Range (TA = 0°C to 70°C)
IDT8N3S271yC-
ddddCDI
IDT8N3S271yC-
ddddCD
y = Option Code, dddd=Default-Frequency and VCXO Pull Range
IDT8N3S271CCD REVISION A DECEMBER 17, 2012
18
©2012 Integrated Device Technology, Inc.
IDT8N3S271 Data Sheet
LVPECL FREQUENCY-PROGRAMMABLE CRYSTAL OSCILLATOR
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[email protected]
+480-763-2056
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including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not
guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the
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Copyright 2012. All rights reserved.