Holt HI-3182PSI-N Arinc 429 differential line driver Datasheet

HI-3182PSx-N, HI-3184PSx-N
HI-3185PSx-N
May 2008
ARINC 429 Differential Line Driver
GENERAL DESCRIPTION
PIN CONFIGURATION
The HI-3182, HI-3184 and HI-3185 bus interface products are
silicon gate CMOS devices designed as a line driver in accordance with the ARINC 429 bus specifications. In addition to
being functional upgrades of Holt's HI-8382 product, they are
also alternate sources for a variety of similar line driver products
from other manufacturers.
14 V1
VREF 1
13 CLOCK
N/C (See Note) 2
12 DATA (B)
SYNC 3
11 CB
DATA (A) 4
Inputs are provided for clocking and synchronization. These
signals are AND'd with the DATA inputs to enhance system
performance and allow the HI-318X series of products to be
used in a variety of applications. Both logic and synchronization
inputs feature built-in 2,000V minimum ESD input protection as
well as TTL and CMOS compatibility.
(Top View)
10 BOUT
CA 5
9 +V
AOUT 6
8 GND
-V 7
HI-3184PSx-N & HI-3185PSx-N
The differential outputs of the HI-318X series of products are
programmable to either the high speed or low speed ARINC 429
output rise and fall time specifications through the use of two
external capacitors. The output voltage swing is also adjustable
by the application of an external voltage to the VREF input. A
37.5 ohm resistor is in series with each ARINC output. In
addition the HI-3182 and HI-3184 products also have a fuse in
series with each output.
14-PIN PLASTIC NARROW SMALL OUTLINE (SOIC)
The HI-318X series of line drivers are intended for use where
logic signals must be converted to ARINC 429 levels such as
when using an ASIC, the HI-8584/HI-3282/HI-8282A
ARINC 429 Serial Transmitter/Dual Receivers, the HI-6010
ARINC 429 Transmitter/Receiver or the HI-8783 ARINC
Interface Device. Holt products are readily available for both
industrial and military applications. Please contact the Holt
Sales Department for additional information.
FUNCTION
Note: Pin 2 not internally connected
(See Page 5 for HI-3182PSx-N package pin configurations)
+
_
FEATURES
ARINC 429 DIFFERENTIAL LINE DRIVER
! Low power CMOS
TRUTH TABLE
! TTL and CMOS compatible inputs
! Programmable output voltage swing
! Adjustable ARINC rise and fall times
SYNC CLOCK DATA(A) DATA(B) AOUT
BOUT COMMENTS
! Operates at data rates up to 100 Kbits
X
L
X
X
0V
0V
NULL
! Overvoltage protection
L
X
X
X
0V
0V
NULL
! Industrial and Military temperature ranges
H
H
L
L
0V
0V
NULL
H
H
L
H
-VREF
+VREF
LOW
H
H
H
L
+VREF
-VREF
HIGH
H
H
H
H
0V
0V
NULL
(DS3182N Rev. C)
HOLT INTEGRATED CIRCUITS
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05/08
HI-3182PSx-N, HI-3184PSx-N, HI-3185PSx-N
FUNCTIONAL DESCRIPTION
The SYNC and CLOCK inputs establish data synchronization
utilizing two AND gates, one for each data input (figure 2).
Each logic input is TTL/CMOS compatible.
The Vref pin has an internal pull-up resistor to V+, allowing the
use of a simple external zener diode to set the reference
voltage.
Figure 1 illustrates a typical ARINC 429 bus application.
Three power supplies are necessary to operate the HI-318X;
typically +15V, -15V and +5V. The chip also works with ±12V
supplies. The +5V supply can also provide a reference
voltage that determines the output voltage swing. The
differential output voltage swing will equal 2VREF. If a value of
VREF other than +5V is needed, a separate +5V power supply
is required for pin V1.
POWER SUPPLY SEQUENCING
The power supplies should be controlled to prevent large
currents during supply turn-on and turn-off. The
recommended sequence is +V followed by V1, always
ensuring that +V is the most positive supply. The -V supply is
not critical and can be asserted at any time.
With the DATA (A) input at a logic high and DATA (B) input at a
logic low, AOUT will switch to the +VREF rail and BOUT will
switch to the -VREF rail (ARINC HIGH state). With both data
input signals at a logic low state, the outputs will both switch to
0V (ARINC NULL state).
The driver output impedance, ROUT, is nominally 75 ohms.
The rise and fall times of the outputs can be calibrated through
the selection of two external capacitor values that are
connected to the CA and CB input pins. Typical values for
high-speed operation (100KBPS) are CA = CB = 75pF and for
low-speed operation (12.5 to 14KBPS) CA = CB = 500pF.
+5V
VREF
DATA (A)
VREF
+V
V1
SYNC
CLOCK
INPUTS
AOUT
+V
TO ARINC BUS
-V
DATA (B)
CA
The CA and CB pins swing between +5V and ground allowing
the switching of capacitor values with an external singlesupply analog switch.
The ARINC outputs of the HI-3182 and HI-3184 are protected
by internal fuses capable of sinking between 800 - 900 mA for
short periods of time (125ms).
+15V
CB
GND
BOUT
-15V
Figure 1. ARINC 429 BUS APPLICATION
A OUT
CA
DATA (A)
LEVEL SHIFTER
AND SLOPE
CONTROL (A)
CLOCK
24.5W
13W
FA
OUTPUT
DRIVER (A)
CL
SYNC
LEVEL SHIFTER
AND SLOPE
CONTROL (B)
DATA (B)
V1
24.5W
13W
FB
OUTPUT
DRIVER (B)
CURRENT
REGULATOR
Shorted on
HI-3185PSx-N
GND
-V
B OUT
CB
Figure 2. FUNCTIONAL BLOCK DIAGRAM
HOLT INTEGRATED CIRCUITS
2
RL
HI-3182PSx-N, HI-3184PSx-N, HI-3185PSx-N
PIN DESCRIPTIONS
SYMBOL
FUNCTION
DESCRIPTION
VREF
ANALOG
SYNC
INPUT
Synchronizes data inputs
DATA (A)
INPUT
Data input terminal A
Connection for DATA (A) slew-rate capacitor
Ref. voltage used to determine output voltage swing. Pin sources current to allow use of a zener reference.
CA
INPUT
AOUT
OUTPUT
ARINC output terminal A
-V
POWER
-12V to -15V
GND
POWER
0.0V
+V
POWER
+12V to +15V
BOUT
OUTPUT
ARINC output terminal B
CB
INPUT
Connection for DATA (B) slew-rate capacitor
DATA (B)
INPUT
Data input terminal B
CLOCK
INPUT
V1
POWER
Synchronizes data inputs
+5V ±5%
ABSOLUTE MAXIMUM RATINGS
All Voltages referenced to GND, TA = Operating Temperature Range (unless otherwise specified)
PARAMETER
Differential Voltage
Supply Voltage
Voltage Reference
Input Voltage Range
SYMBOL
VDIF
CONDITIONS
For ARINC 429
For Applications other than ARINC
See Note: 1
Output Overvoltage Protection
See Note: 2
Storage Temperature Range
TA
TSTG
Lead Temperature
Junction Temperature
UNIT
40
V
+10.8 to +16.5
-10.8 to -16.5
+5 ±5%
+7
V
V
V
+5 ±5%
1.5 to 6
6
6
V
V
> GND -0.3
< V1 +0.3
V
V
VIN
Output Short-Circuit Duration
Operating Temperature Range
MAXIMUM
Voltage between +V and -V terminals
+V
-V
V1
VREF
OPERATING RANGE
High-temp & Military
Industrial
-55 to +125
-40 to +85
°C
°C
Ceramic & Plastic
-65 to +150
°C
Soldering, 10 seconds
TJ
+275
°C
+175
°C
Note 1. Heatsinking may be required for continuous Output Short Circuit operation at +125°C and for 100KBPS (high speed) data rate
operation at +125°C. Under either of these conditions the HI-318xPSx product with the Enhanced SOIC (ESOIC) package should
be selected (see Data Sheet for HI-3182PSx, HI-3184PSx and HI-3185PSx).
Note 2. The fuses used for Output Overvoltage Protection may be blown by the presence of a voltage at either output that is greater
than ±12.0V with respect to GND. (HI-3182PSx-N and HI-3184PSx-N only)
NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings
only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
HOLT INTEGRATED CIRCUITS
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HI-3182PSx-N, HI-3184PSx-N, HI-3185PSx-N
DC ELECTRICAL CHARACTERISTICS
+V = +15V, -V = -15V, V1 = VREF = +5.0V, TA = Operating Temperature Range (unless otherwise specified).
PARAMETER
SYMBOL
Output Voltage High (Output to Ground)
ICCOP (+V)
ICCOP (-V)
ICCOP (V1)
ICCOP (VREF)
ISC (+V)
ISC (-V)
IOHSC
IOLSC
IIH
IIL
VIH
VIL
VOH
Output Voltage Low (Output to Ground)
Supply Current +V (Operating)
Supply Current -V (Operating)
Supply Current V1 (Operating)
Reference Pin Current VREF (Operating)
Supply Current +V (During Short Circuit Test)
Supply Current -V (During Short Circuit Test)
Output Short Circuit Current (Output High)
Output Short Circuit Current (Output Low)
Input Current (Input High)
Input Current (Input Low)
Input Voltage High
Input Voltage Low
Output Voltage Null
Input Capacitance
CONDITION
No Load
MIN
TYP
(0 - 100KBPS)
No Load
(0 - 100KBPS)
No Load
(0 - 100KBPS)
No Load, VREF = 5V (0 - 100KBPS)
Short to Ground
(See Note: 1)
Short to Ground
(See Note: 1)
Short to Ground
VMIN=0 (See Note: 2)
VMIN=0 (See Note: 2)
Short to Ground
MAX UNITS
+16
-16
-1.0
mA
mA
-0.4
500
µA
-0.15
mA
150
mA
-150
mA
-80
+80
mA
mA
1.0
-1.0
µA
µA
2.0
V
0.5
V
No Load
(0 -100KBPS)
+VREF
-.25
+VREF
+.25
V
VOL
No Load
(0 -100KBPS)
-VREF
-.25
-VREF
+.25
V
VNULL
CIN
No Load
(0-100KBPS)
-250
+250
mV
15
See Note 1
pF
Note 1. Not tested, but characterized at initial device design and after major process and/or design change which affects this parameter.
Note 2. Interchangeability of force and sense is acceptable.
AC ELECTRICAL CHARACTERISTICS
+V = +15V, -V = -15V, V1 = VREF = +5.0V, TA = Operating Temperature Range (unless otherwise specified).
PARAMETER
SYMBOL
CONDITION
MIN
TYP
MAX UNITS
Rise Time ( A OUT , B OUT )
tR
C A = C B = 75pF
See Figure 3.
1.0
2.0
µs
Fall Time ( A OUT , B OUT )
tF
C A = C B = 75pF
See Figure 3.
1.0
2.0
µs
Propagtion Delay Input to Output
t PLH
C A = C B = 75pF
See Figure 3.
3.0
µs
Propagtion Delay Input to Output
t PHL
C A = C B = 75pF
See Figure 3.
3.0
µs
DATA (B) 0V
VREF
AOUT 0V
2.0V
0.5V
50%
DATA (A) 0V
50%
2.0V
0.5V
ADJUST
BY CA
+4.75V to +5.25V
ADJUST
BY CA
-VREF
t PHL
+VREF
BOUT 0V
-VREF
50%
50%
t PLH
-4.75V to -5.25V
ADJUST
BY CB
-4.75V to -5.25V
2VREF
tR
+4.75V to +5.25V
ADJUST
BY CB
HIGH
DIFFERENTIAL
OUTPUT 0V
+9.5V to +10.5V
NULL
(AOUT - BOUT)
NOTE: OUTPUTS UNLOADED
tF
-2VREF
LOW
Figure 3. SWITCHING WAVEFORMS
HOLT INTEGRATED CIRCUITS
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-9.5V to -10.5V
HI-3182PSx-N, HI-3184PSx-N, HI-3185PSx-N
ADDITIONAL PIN CONFIGURATIONS (See page 1 for 14-Pin Narrow Small Outline SOIC)
HI-3182PSx-N
VREF - 1
16 - V1
GND (See Note) - 2
15 - N/C
SYNC - 3
14 - CLOCK
DATA(A) - 4
13 - DATA(B)
CA - 5
12 - CB
AOUT - 6
11 - BOUT
-V - 7
10 - N/C
GND - 8
9 - +V
Note: Pin 2 may be left floating
16 - PIN PLASTIC WIDE SMALL OUTLINE (SOIC)
ORDERING INFORMATION
HI - 318xPS x x - N
PART
NUMBER
Blank
F
PART
NUMBER
PACKAGE
DESCRIPTION
Tin / Lead (Sn / Pb) Solder
100% Matte Tin (Pb-free RoHS compliant)
TEMPERATURE
RANGE
FLOW
BURN
IN
I
-40°C TO +85°C
I
No
T
-55°C TO +125°C
T
No
OUTPUT SERIES
RESISTANCE FUSE
PART
NUMBER
PACKAGE
DESCRIPTION
3182PS
16 PIN PLASTIC WIDE SMALL OUTLINE SOIC (16HW)
37.5 Ohms
Yes
3184PS
14 PIN PLASTIC NARROW SMALL OUTLINE SOIC (14HN)
37.5 Ohms
Yes
3185PS
14 PIN PLASTIC NARROW SMALL OUTLINE SOIC (14HN)
37.5 Ohms
No
HOLT INTEGRATED CIRCUITS
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HI-3182PSx-N, HI-3184PSx-N, HI-3185PSx-N
REVISION HISTORY
Revision
Date
DS3182N, Rev. C 05/01/08
Page Description of Change
1
1
1
1
2-5
2
3
3
5
6
7
Date was “March 2007”, is “May 2008”. Footer was “Rev. B”, is “Rev. C” and was
“03/07”, is “05/08”
Added “HI-3184PSx-N” to the document title and in the Pin Configuration.
“HI-3182” in first sentence of the first paragraph of the GENERAL DESCRIPTION
changed to “HI-3182, HI-3184”.
“HI-3182 product also has” in the last sentence of the third paragraph of the
GENERAL DESCRIPTION changed to “and HI-3184 products also have”.
“HI-3182PSx-N” added to header.
“HI-3182,” in the sixth paragraph of the FUNCTIONAL DESCRIPTION changed
to “HI-3182 and HI-3184”.
Clarified Note 1 to read ”Heatsinking may be required for continuous Output
Short Circuit operation at +125°C and for 100KBPS (high speed) data rate
operation at +125°C. Under either of these conditions the HI-318xPSx product
with the Enhanced SOIC (ESOIC) package should be selected (see Data
Sheet for HI-3182PSx, HI-3184PSx and HI-3185PSx).”
“HI-3182” in Note 2. changed to “HI-3182PSx-N and HI-3184PSx-N”.
Added “HI-3184PS” to ORDERING INFORMATION table.
Added “REVISION HISTORY” table.
Renumbered old page”6” as “7”.
HOLT INTEGRATED CIRCUITS
6
HI-318xPSx-N PACKAGE DIMENSIONS
14-PIN PLASTIC SMALL OUTLINE (SOIC) - NB
(Narrow Body)
Package Type: 14HN
.0087 ± .001
(.221 ± .029)
.341 ± .004
(8.65 ± .10)
.236 ± .008
(5.99 ± .20)
inches (millimeters)
.153 ± .003
(3.87 ± .06)
Top View
See Detail A
.0165 ± .003
(.419 ± .089)
.055 ± .005
(1.397 ± .13)
.050 BSC
(1.27)
0°° to 8°°
.007 ± .003
(.175 ± .07)
.033 ± .017
(.838 ± .43)
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
Detail A
16-PIN PLASTIC SMALL OUTLINE (SOIC) - WB
(Wide Body)
Package Type: 16HW
.0105 ± .0015
(.2667 ± .0381)
.405 ± .008
(10.287 ± .203)
.4065 ± .0125
(10.325 ± .318)
inches (millimeters)
.295 ± .004
(7.493 ± .102)
Top View
Detail A
.090 ± .010
(2.286 ± .254)
.050
BSC
(1.27)
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
.0165 ± .0035
(.4191 ± .0889)
0°° to 8°°
.0025 ± .0015
(.0635 ± .04)
.033 ± .017
(.838 ± .43)
HOLT INTEGRATED CIRCUITS
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Detail A
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